ARMInstrFormats.td revision 9d63d90de5e57ad96f467b270544443a9284eb2b
1//===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// ARM Instruction Format Definitions. 13// 14 15// Format specifies the encoding used by the instruction. This is part of the 16// ad-hoc solution used to emit machine instruction encodings by our machine 17// code emitter. 18class Format<bits<6> val> { 19 bits<6> Value = val; 20} 21 22def Pseudo : Format<0>; 23def MulFrm : Format<1>; 24def BrFrm : Format<2>; 25def BrMiscFrm : Format<3>; 26 27def DPFrm : Format<4>; 28def DPSoRegFrm : Format<5>; 29 30def LdFrm : Format<6>; 31def StFrm : Format<7>; 32def LdMiscFrm : Format<8>; 33def StMiscFrm : Format<9>; 34def LdStMulFrm : Format<10>; 35 36def LdStExFrm : Format<11>; 37 38def ArithMiscFrm : Format<12>; 39def SatFrm : Format<13>; 40def ExtFrm : Format<14>; 41 42def VFPUnaryFrm : Format<15>; 43def VFPBinaryFrm : Format<16>; 44def VFPConv1Frm : Format<17>; 45def VFPConv2Frm : Format<18>; 46def VFPConv3Frm : Format<19>; 47def VFPConv4Frm : Format<20>; 48def VFPConv5Frm : Format<21>; 49def VFPLdStFrm : Format<22>; 50def VFPLdStMulFrm : Format<23>; 51def VFPMiscFrm : Format<24>; 52 53def ThumbFrm : Format<25>; 54def MiscFrm : Format<26>; 55 56def NGetLnFrm : Format<27>; 57def NSetLnFrm : Format<28>; 58def NDupFrm : Format<29>; 59def NLdStFrm : Format<30>; 60def N1RegModImmFrm: Format<31>; 61def N2RegFrm : Format<32>; 62def NVCVTFrm : Format<33>; 63def NVDupLnFrm : Format<34>; 64def N2RegVShLFrm : Format<35>; 65def N2RegVShRFrm : Format<36>; 66def N3RegFrm : Format<37>; 67def N3RegVShFrm : Format<38>; 68def NVExtFrm : Format<39>; 69def NVMulSLFrm : Format<40>; 70def NVTBLFrm : Format<41>; 71 72// Misc flags. 73 74// The instruction has an Rn register operand. 75// UnaryDP - Indicates this is a unary data processing instruction, i.e. 76// it doesn't have a Rn operand. 77class UnaryDP { bit isUnaryDataProc = 1; } 78 79// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 80// a 16-bit Thumb instruction if certain conditions are met. 81class Xform16Bit { bit canXformTo16Bit = 1; } 82 83//===----------------------------------------------------------------------===// 84// ARM Instruction flags. These need to match ARMBaseInstrInfo.h. 85// 86 87// Addressing mode. 88class AddrMode<bits<5> val> { 89 bits<5> Value = val; 90} 91def AddrModeNone : AddrMode<0>; 92def AddrMode1 : AddrMode<1>; 93def AddrMode2 : AddrMode<2>; 94def AddrMode3 : AddrMode<3>; 95def AddrMode4 : AddrMode<4>; 96def AddrMode5 : AddrMode<5>; 97def AddrMode6 : AddrMode<6>; 98def AddrModeT1_1 : AddrMode<7>; 99def AddrModeT1_2 : AddrMode<8>; 100def AddrModeT1_4 : AddrMode<9>; 101def AddrModeT1_s : AddrMode<10>; 102def AddrModeT2_i12 : AddrMode<11>; 103def AddrModeT2_i8 : AddrMode<12>; 104def AddrModeT2_so : AddrMode<13>; 105def AddrModeT2_pc : AddrMode<14>; 106def AddrModeT2_i8s4 : AddrMode<15>; 107def AddrMode_i12 : AddrMode<16>; 108 109// Instruction size. 110class SizeFlagVal<bits<3> val> { 111 bits<3> Value = val; 112} 113def SizeInvalid : SizeFlagVal<0>; // Unset. 114def SizeSpecial : SizeFlagVal<1>; // Pseudo or special. 115def Size8Bytes : SizeFlagVal<2>; 116def Size4Bytes : SizeFlagVal<3>; 117def Size2Bytes : SizeFlagVal<4>; 118 119// Load / store index mode. 120class IndexMode<bits<2> val> { 121 bits<2> Value = val; 122} 123def IndexModeNone : IndexMode<0>; 124def IndexModePre : IndexMode<1>; 125def IndexModePost : IndexMode<2>; 126def IndexModeUpd : IndexMode<3>; 127 128// Instruction execution domain. 129class Domain<bits<2> val> { 130 bits<2> Value = val; 131} 132def GenericDomain : Domain<0>; 133def VFPDomain : Domain<1>; // Instructions in VFP domain only 134def NeonDomain : Domain<2>; // Instructions in Neon domain only 135def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 136 137//===----------------------------------------------------------------------===// 138// ARM special operands. 139// 140 141def CondCodeOperand : AsmOperandClass { 142 let Name = "CondCode"; 143 let SuperClasses = []; 144} 145 146// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 147// register whose default is 0 (no register). 148def pred : PredicateOperand<OtherVT, (ops i32imm, CCR), 149 (ops (i32 14), (i32 zero_reg))> { 150 let PrintMethod = "printPredicateOperand"; 151 let ParserMatchClass = CondCodeOperand; 152} 153 154// Conditional code result for instructions whose 's' bit is set, e.g. subs. 155def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 156 let EncoderMethod = "getCCOutOpValue"; 157 let PrintMethod = "printSBitModifierOperand"; 158} 159 160// Same as cc_out except it defaults to setting CPSR. 161def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 162 let EncoderMethod = "getCCOutOpValue"; 163 let PrintMethod = "printSBitModifierOperand"; 164} 165 166// ARM special operands for disassembly only. 167// 168def setend_op : Operand<i32> { 169 let PrintMethod = "printSetendOperand"; 170} 171 172def cps_opt : Operand<i32> { 173 let PrintMethod = "printCPSOptionOperand"; 174} 175 176def msr_mask : Operand<i32> { 177 let PrintMethod = "printMSRMaskOperand"; 178} 179 180// A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0. 181// The neg_zero operand translates -0 to -1, -1 to -2, ..., etc. 182def neg_zero : Operand<i32> { 183 let PrintMethod = "printNegZeroOperand"; 184} 185 186//===----------------------------------------------------------------------===// 187// ARM Instruction templates. 188// 189 190class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im, 191 Format f, Domain d, string cstr, InstrItinClass itin> 192 : Instruction { 193 let Namespace = "ARM"; 194 195 AddrMode AM = am; 196 SizeFlagVal SZ = sz; 197 IndexMode IM = im; 198 bits<2> IndexModeBits = IM.Value; 199 Format F = f; 200 bits<6> Form = F.Value; 201 Domain D = d; 202 bit isUnaryDataProc = 0; 203 bit canXformTo16Bit = 0; 204 205 // If this is a pseudo instruction, mark it isCodeGenOnly. 206 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 207 208 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h. 209 let TSFlags{4-0} = AM.Value; 210 let TSFlags{7-5} = SZ.Value; 211 let TSFlags{9-8} = IndexModeBits; 212 let TSFlags{15-10} = Form; 213 let TSFlags{16} = isUnaryDataProc; 214 let TSFlags{17} = canXformTo16Bit; 215 let TSFlags{19-18} = D.Value; 216 217 let Constraints = cstr; 218 let Itinerary = itin; 219} 220 221class Encoding { 222 field bits<32> Inst; 223} 224 225class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, 226 Format f, Domain d, string cstr, InstrItinClass itin> 227 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding; 228 229// This Encoding-less class is used by Thumb1 to specify the encoding bits later 230// on by adding flavors to specific instructions. 231class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im, 232 Format f, Domain d, string cstr, InstrItinClass itin> 233 : InstTemplate<am, sz, im, f, d, cstr, itin>; 234 235class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern> 236 // FIXME: This really should derive from InstTemplate instead, as pseudos 237 // don't need encoding information. TableGen doesn't like that 238 // currently. Need to figure out why and fix it. 239 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain, 240 "", itin> { 241 let OutOperandList = oops; 242 let InOperandList = iops; 243 let Pattern = pattern; 244} 245 246// PseudoInst that's ARM-mode only. 247class ARMPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin, 248 list<dag> pattern> 249 : PseudoInst<oops, iops, itin, pattern> { 250 let SZ = sz; 251 list<Predicate> Predicates = [IsARM]; 252} 253 254// PseudoInst that's Thumb-mode only. 255class tPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin, 256 list<dag> pattern> 257 : PseudoInst<oops, iops, itin, pattern> { 258 let SZ = sz; 259 list<Predicate> Predicates = [IsThumb]; 260} 261 262// Almost all ARM instructions are predicable. 263class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 264 IndexMode im, Format f, InstrItinClass itin, 265 string opc, string asm, string cstr, 266 list<dag> pattern> 267 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 268 bits<4> p; 269 let Inst{31-28} = p; 270 let OutOperandList = oops; 271 let InOperandList = !con(iops, (ins pred:$p)); 272 let AsmString = !strconcat(opc, "${p}", asm); 273 let Pattern = pattern; 274 list<Predicate> Predicates = [IsARM]; 275} 276 277// A few are not predicable 278class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 279 IndexMode im, Format f, InstrItinClass itin, 280 string opc, string asm, string cstr, 281 list<dag> pattern> 282 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 283 let OutOperandList = oops; 284 let InOperandList = iops; 285 let AsmString = !strconcat(opc, asm); 286 let Pattern = pattern; 287 let isPredicable = 0; 288 list<Predicate> Predicates = [IsARM]; 289} 290 291// Same as I except it can optionally modify CPSR. Note it's modeled as an input 292// operand since by default it's a zero register. It will become an implicit def 293// once it's "flipped". 294class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 295 IndexMode im, Format f, InstrItinClass itin, 296 string opc, string asm, string cstr, 297 list<dag> pattern> 298 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 299 bits<4> p; // Predicate operand 300 bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 301 let Inst{31-28} = p; 302 let Inst{20} = s; 303 304 let OutOperandList = oops; 305 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 306 let AsmString = !strconcat(opc, "${s}${p}", asm); 307 let Pattern = pattern; 308 list<Predicate> Predicates = [IsARM]; 309} 310 311// Special cases 312class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 313 IndexMode im, Format f, InstrItinClass itin, 314 string asm, string cstr, list<dag> pattern> 315 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 316 let OutOperandList = oops; 317 let InOperandList = iops; 318 let AsmString = asm; 319 let Pattern = pattern; 320 list<Predicate> Predicates = [IsARM]; 321} 322 323class AI<dag oops, dag iops, Format f, InstrItinClass itin, 324 string opc, string asm, list<dag> pattern> 325 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 326 opc, asm, "", pattern>; 327class AsI<dag oops, dag iops, Format f, InstrItinClass itin, 328 string opc, string asm, list<dag> pattern> 329 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 330 opc, asm, "", pattern>; 331class AXI<dag oops, dag iops, Format f, InstrItinClass itin, 332 string asm, list<dag> pattern> 333 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 334 asm, "", pattern>; 335class AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 336 string opc, string asm, list<dag> pattern> 337 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 338 opc, asm, "", pattern>; 339 340// Ctrl flow instructions 341class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 342 string opc, string asm, list<dag> pattern> 343 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 344 opc, asm, "", pattern> { 345 let Inst{27-24} = opcod; 346} 347class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 348 string asm, list<dag> pattern> 349 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 350 asm, "", pattern> { 351 let Inst{27-24} = opcod; 352} 353 354// BR_JT instructions 355class JTI<dag oops, dag iops, InstrItinClass itin, 356 string asm, list<dag> pattern> 357 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin, 358 asm, "", pattern>; 359 360// Atomic load/store instructions 361class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 362 string opc, string asm, list<dag> pattern> 363 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 364 opc, asm, "", pattern> { 365 bits<4> Rt; 366 bits<4> Rn; 367 let Inst{27-23} = 0b00011; 368 let Inst{22-21} = opcod; 369 let Inst{20} = 1; 370 let Inst{19-16} = Rn; 371 let Inst{15-12} = Rt; 372 let Inst{11-0} = 0b111110011111; 373} 374class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 375 string opc, string asm, list<dag> pattern> 376 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 377 opc, asm, "", pattern> { 378 bits<4> Rd; 379 bits<4> Rt; 380 bits<4> Rn; 381 let Inst{27-23} = 0b00011; 382 let Inst{22-21} = opcod; 383 let Inst{20} = 0; 384 let Inst{19-16} = Rn; 385 let Inst{15-12} = Rd; 386 let Inst{11-4} = 0b11111001; 387 let Inst{3-0} = Rt; 388} 389class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> 390 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> { 391 bits<4> Rt; 392 bits<4> Rt2; 393 bits<4> Rn; 394 let Inst{27-23} = 0b00010; 395 let Inst{22} = b; 396 let Inst{21-20} = 0b00; 397 let Inst{19-16} = Rn; 398 let Inst{15-12} = Rt; 399 let Inst{11-4} = 0b00001001; 400 let Inst{3-0} = Rt2; 401} 402 403// addrmode1 instructions 404class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 405 string opc, string asm, list<dag> pattern> 406 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 407 opc, asm, "", pattern> { 408 let Inst{24-21} = opcod; 409 let Inst{27-26} = 0b00; 410} 411class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 412 string opc, string asm, list<dag> pattern> 413 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 414 opc, asm, "", pattern> { 415 let Inst{24-21} = opcod; 416 let Inst{27-26} = 0b00; 417} 418class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 419 string asm, list<dag> pattern> 420 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 421 asm, "", pattern> { 422 let Inst{24-21} = opcod; 423 let Inst{27-26} = 0b00; 424} 425 426// loads 427 428// LDR/LDRB/STR/STRB/... 429class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am, 430 Format f, InstrItinClass itin, string opc, string asm, 431 list<dag> pattern> 432 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm, 433 "", pattern> { 434 let Inst{27-25} = op; 435 let Inst{24} = 1; // 24 == P 436 // 23 == U 437 let Inst{22} = isByte; 438 let Inst{21} = 0; // 21 == W 439 let Inst{20} = isLd; 440} 441// Indexed load/stores 442class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops, 443 IndexMode im, Format f, InstrItinClass itin, string opc, 444 string asm, string cstr, list<dag> pattern> 445 : I<oops, iops, AddrMode2, Size4Bytes, im, f, itin, 446 opc, asm, cstr, pattern> { 447 bits<4> Rt; 448 let Inst{27-26} = 0b01; 449 let Inst{24} = isPre; // P bit 450 let Inst{22} = isByte; // B bit 451 let Inst{21} = isPre; // W bit 452 let Inst{20} = isLd; // L bit 453 let Inst{15-12} = Rt; 454} 455class AI2stridx<bit isByte, bit isPre, dag oops, dag iops, 456 IndexMode im, Format f, InstrItinClass itin, string opc, 457 string asm, string cstr, list<dag> pattern> 458 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 459 pattern> { 460 // AM2 store w/ two operands: (GPR, am2offset) 461 // {13} 1 == Rm, 0 == imm12 462 // {12} isAdd 463 // {11-0} imm12/Rm 464 bits<14> offset; 465 bits<4> Rn; 466 let Inst{25} = offset{13}; 467 let Inst{23} = offset{12}; 468 let Inst{19-16} = Rn; 469 let Inst{11-0} = offset{11-0}; 470} 471 472// addrmode3 instructions 473class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f, 474 InstrItinClass itin, string opc, string asm, list<dag> pattern> 475 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 476 opc, asm, "", pattern> { 477 bits<14> addr; 478 bits<4> Rt; 479 let Inst{27-25} = 0b000; 480 let Inst{24} = 1; // P bit 481 let Inst{23} = addr{8}; // U bit 482 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 483 let Inst{21} = 0; // W bit 484 let Inst{20} = op20; // L bit 485 let Inst{19-16} = addr{12-9}; // Rn 486 let Inst{15-12} = Rt; // Rt 487 let Inst{11-8} = addr{7-4}; // imm7_4/zero 488 let Inst{7-4} = op; 489 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 490} 491 492class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops, 493 IndexMode im, Format f, InstrItinClass itin, string opc, 494 string asm, string cstr, list<dag> pattern> 495 : I<oops, iops, AddrMode3, Size4Bytes, im, f, itin, 496 opc, asm, cstr, pattern> { 497 bits<4> Rt; 498 let Inst{27-25} = 0b000; 499 let Inst{24} = isPre; // P bit 500 let Inst{21} = isPre; // W bit 501 let Inst{20} = op20; // L bit 502 let Inst{15-12} = Rt; // Rt 503 let Inst{7-4} = op; 504} 505class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops, 506 IndexMode im, Format f, InstrItinClass itin, string opc, 507 string asm, string cstr, list<dag> pattern> 508 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 509 pattern> { 510 // AM3 store w/ two operands: (GPR, am3offset) 511 bits<14> offset; 512 bits<4> Rt; 513 bits<4> Rn; 514 let Inst{27-25} = 0b000; 515 let Inst{23} = offset{8}; 516 let Inst{22} = offset{9}; 517 let Inst{19-16} = Rn; 518 let Inst{15-12} = Rt; // Rt 519 let Inst{11-8} = offset{7-4}; // imm7_4/zero 520 let Inst{7-4} = op; 521 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 522} 523 524// stores 525class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin, 526 string opc, string asm, list<dag> pattern> 527 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 528 opc, asm, "", pattern> { 529 bits<14> addr; 530 bits<4> Rt; 531 let Inst{27-25} = 0b000; 532 let Inst{24} = 1; // P bit 533 let Inst{23} = addr{8}; // U bit 534 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 535 let Inst{21} = 0; // W bit 536 let Inst{20} = 0; // L bit 537 let Inst{19-16} = addr{12-9}; // Rn 538 let Inst{15-12} = Rt; // Rt 539 let Inst{11-8} = addr{7-4}; // imm7_4/zero 540 let Inst{7-4} = op; 541 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 542} 543 544// Pre-indexed stores 545class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin, 546 string opc, string asm, string cstr, list<dag> pattern> 547 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 548 opc, asm, cstr, pattern> { 549 let Inst{4} = 1; 550 let Inst{5} = 1; // H bit 551 let Inst{6} = 0; // S bit 552 let Inst{7} = 1; 553 let Inst{20} = 0; // L bit 554 let Inst{21} = 1; // W bit 555 let Inst{24} = 1; // P bit 556 let Inst{27-25} = 0b000; 557} 558class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin, 559 string opc, string asm, string cstr, list<dag> pattern> 560 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 561 opc, asm, cstr, pattern> { 562 let Inst{4} = 1; 563 let Inst{5} = 1; // H bit 564 let Inst{6} = 1; // S bit 565 let Inst{7} = 1; 566 let Inst{20} = 0; // L bit 567 let Inst{21} = 1; // W bit 568 let Inst{24} = 1; // P bit 569 let Inst{27-25} = 0b000; 570} 571 572// Post-indexed stores 573class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin, 574 string opc, string asm, string cstr, list<dag> pattern> 575 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 576 opc, asm, cstr,pattern> { 577 let Inst{4} = 1; 578 let Inst{5} = 1; // H bit 579 let Inst{6} = 0; // S bit 580 let Inst{7} = 1; 581 let Inst{20} = 0; // L bit 582 let Inst{21} = 0; // W bit 583 let Inst{24} = 0; // P bit 584 let Inst{27-25} = 0b000; 585} 586class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin, 587 string opc, string asm, string cstr, list<dag> pattern> 588 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 589 opc, asm, cstr, pattern> { 590 let Inst{4} = 1; 591 let Inst{5} = 1; // H bit 592 let Inst{6} = 1; // S bit 593 let Inst{7} = 1; 594 let Inst{20} = 0; // L bit 595 let Inst{21} = 0; // W bit 596 let Inst{24} = 0; // P bit 597 let Inst{27-25} = 0b000; 598} 599 600// addrmode4 instructions 601class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 602 string asm, string cstr, list<dag> pattern> 603 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, asm, cstr, pattern> { 604 bits<4> p; 605 bits<16> regs; 606 bits<4> Rn; 607 let Inst{31-28} = p; 608 let Inst{27-25} = 0b100; 609 let Inst{22} = 0; // S bit 610 let Inst{19-16} = Rn; 611 let Inst{15-0} = regs; 612} 613 614// Unsigned multiply, multiply-accumulate instructions. 615class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 616 string opc, string asm, list<dag> pattern> 617 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 618 opc, asm, "", pattern> { 619 let Inst{7-4} = 0b1001; 620 let Inst{20} = 0; // S bit 621 let Inst{27-21} = opcod; 622} 623class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 624 string opc, string asm, list<dag> pattern> 625 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 626 opc, asm, "", pattern> { 627 let Inst{7-4} = 0b1001; 628 let Inst{27-21} = opcod; 629} 630 631// Most significant word multiply 632class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 633 InstrItinClass itin, string opc, string asm, list<dag> pattern> 634 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 635 opc, asm, "", pattern> { 636 bits<4> Rd; 637 bits<4> Rn; 638 bits<4> Rm; 639 let Inst{7-4} = opc7_4; 640 let Inst{20} = 1; 641 let Inst{27-21} = opcod; 642 let Inst{19-16} = Rd; 643 let Inst{11-8} = Rm; 644 let Inst{3-0} = Rn; 645} 646// MSW multiple w/ Ra operand 647class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 648 InstrItinClass itin, string opc, string asm, list<dag> pattern> 649 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> { 650 bits<4> Ra; 651 let Inst{15-12} = Ra; 652} 653 654// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 655class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 656 InstrItinClass itin, string opc, string asm, list<dag> pattern> 657 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 658 opc, asm, "", pattern> { 659 bits<4> Rn; 660 bits<4> Rm; 661 let Inst{4} = 0; 662 let Inst{7} = 1; 663 let Inst{20} = 0; 664 let Inst{27-21} = opcod; 665 let Inst{6-5} = bit6_5; 666 let Inst{11-8} = Rm; 667 let Inst{3-0} = Rn; 668} 669class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 670 InstrItinClass itin, string opc, string asm, list<dag> pattern> 671 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 672 bits<4> Rd; 673 let Inst{19-16} = Rd; 674} 675 676// AMulxyI with Ra operand 677class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 678 InstrItinClass itin, string opc, string asm, list<dag> pattern> 679 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 680 bits<4> Ra; 681 let Inst{15-12} = Ra; 682} 683// SMLAL* 684class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 685 InstrItinClass itin, string opc, string asm, list<dag> pattern> 686 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 687 bits<4> RdLo; 688 bits<4> RdHi; 689 let Inst{19-16} = RdHi; 690 let Inst{15-12} = RdLo; 691} 692 693// Extend instructions. 694class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 695 string opc, string asm, list<dag> pattern> 696 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin, 697 opc, asm, "", pattern> { 698 // All AExtI instructions have Rd and Rm register operands. 699 bits<4> Rd; 700 bits<4> Rm; 701 let Inst{15-12} = Rd; 702 let Inst{3-0} = Rm; 703 let Inst{7-4} = 0b0111; 704 let Inst{9-8} = 0b00; 705 let Inst{27-20} = opcod; 706} 707 708// Misc Arithmetic instructions. 709class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops, 710 InstrItinClass itin, string opc, string asm, list<dag> pattern> 711 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 712 opc, asm, "", pattern> { 713 bits<4> Rd; 714 bits<4> Rm; 715 let Inst{27-20} = opcod; 716 let Inst{19-16} = 0b1111; 717 let Inst{15-12} = Rd; 718 let Inst{11-8} = 0b1111; 719 let Inst{7-4} = opc7_4; 720 let Inst{3-0} = Rm; 721} 722 723// PKH instructions 724class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin, 725 string opc, string asm, list<dag> pattern> 726 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 727 opc, asm, "", pattern> { 728 bits<4> Rd; 729 bits<4> Rn; 730 bits<4> Rm; 731 bits<8> sh; 732 let Inst{27-20} = opcod; 733 let Inst{19-16} = Rn; 734 let Inst{15-12} = Rd; 735 let Inst{11-7} = sh{7-3}; 736 let Inst{6} = tb; 737 let Inst{5-4} = 0b01; 738 let Inst{3-0} = Rm; 739} 740 741//===----------------------------------------------------------------------===// 742 743// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 744class ARMPat<dag pattern, dag result> : Pat<pattern, result> { 745 list<Predicate> Predicates = [IsARM]; 746} 747class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 748 list<Predicate> Predicates = [IsARM, HasV5TE]; 749} 750class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 751 list<Predicate> Predicates = [IsARM, HasV6]; 752} 753 754//===----------------------------------------------------------------------===// 755// Thumb Instruction Format Definitions. 756// 757 758class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 759 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 760 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 761 let OutOperandList = oops; 762 let InOperandList = iops; 763 let AsmString = asm; 764 let Pattern = pattern; 765 list<Predicate> Predicates = [IsThumb]; 766} 767 768// TI - Thumb instruction. 769class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 770 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 771 772// Two-address instructions 773class TIt<dag oops, dag iops, InstrItinClass itin, string asm, 774 list<dag> pattern> 775 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", 776 pattern>; 777 778// tBL, tBX 32-bit instructions 779class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 780 dag oops, dag iops, InstrItinClass itin, string asm, 781 list<dag> pattern> 782 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, 783 Encoding { 784 let Inst{31-27} = opcod1; 785 let Inst{15-14} = opcod2; 786 let Inst{12} = opcod3; 787} 788 789// BR_JT instructions 790class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, 791 list<dag> pattern> 792 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 793 794// Thumb1 only 795class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 796 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 797 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 798 let OutOperandList = oops; 799 let InOperandList = iops; 800 let AsmString = asm; 801 let Pattern = pattern; 802 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 803} 804 805class T1I<dag oops, dag iops, InstrItinClass itin, 806 string asm, list<dag> pattern> 807 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 808class T1Ix2<dag oops, dag iops, InstrItinClass itin, 809 string asm, list<dag> pattern> 810 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 811 812// Two-address instructions 813class T1It<dag oops, dag iops, InstrItinClass itin, 814 string asm, string cstr, list<dag> pattern> 815 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, 816 asm, cstr, pattern>; 817 818// Thumb1 instruction that can either be predicated or set CPSR. 819class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 820 InstrItinClass itin, 821 string opc, string asm, string cstr, list<dag> pattern> 822 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 823 let OutOperandList = !con(oops, (outs s_cc_out:$s)); 824 let InOperandList = !con(iops, (ins pred:$p)); 825 let AsmString = !strconcat(opc, "${s}${p}", asm); 826 let Pattern = pattern; 827 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 828} 829 830class T1sI<dag oops, dag iops, InstrItinClass itin, 831 string opc, string asm, list<dag> pattern> 832 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 833 834// Two-address instructions 835class T1sIt<dag oops, dag iops, InstrItinClass itin, 836 string opc, string asm, list<dag> pattern> 837 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 838 "$Rn = $Rdn", pattern>; 839 840// Thumb1 instruction that can be predicated. 841class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 842 InstrItinClass itin, 843 string opc, string asm, string cstr, list<dag> pattern> 844 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 845 let OutOperandList = oops; 846 let InOperandList = !con(iops, (ins pred:$p)); 847 let AsmString = !strconcat(opc, "${p}", asm); 848 let Pattern = pattern; 849 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 850} 851 852class T1pI<dag oops, dag iops, InstrItinClass itin, 853 string opc, string asm, list<dag> pattern> 854 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 855 856// Two-address instructions 857class T1pIt<dag oops, dag iops, InstrItinClass itin, 858 string opc, string asm, list<dag> pattern> 859 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 860 "$Rn = $Rdn", pattern>; 861 862class T1pIs<dag oops, dag iops, 863 InstrItinClass itin, string opc, string asm, list<dag> pattern> 864 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>; 865 866class Encoding16 : Encoding { 867 let Inst{31-16} = 0x0000; 868} 869 870// A6.2 16-bit Thumb instruction encoding 871class T1Encoding<bits<6> opcode> : Encoding16 { 872 let Inst{15-10} = opcode; 873} 874 875// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 876class T1General<bits<5> opcode> : Encoding16 { 877 let Inst{15-14} = 0b00; 878 let Inst{13-9} = opcode; 879} 880 881// A6.2.2 Data-processing encoding. 882class T1DataProcessing<bits<4> opcode> : Encoding16 { 883 let Inst{15-10} = 0b010000; 884 let Inst{9-6} = opcode; 885} 886 887// A6.2.3 Special data instructions and branch and exchange encoding. 888class T1Special<bits<4> opcode> : Encoding16 { 889 let Inst{15-10} = 0b010001; 890 let Inst{9-6} = opcode; 891} 892 893// A6.2.4 Load/store single data item encoding. 894class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 895 let Inst{15-12} = opA; 896 let Inst{11-9} = opB; 897} 898class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 899 900// Helper classes to encode Thumb1 loads and stores. For immediates, the 901// following bits are used for "opA" (see A6.2.4): 902// 903// 0b0110 => Immediate, 4 bytes 904// 0b1000 => Immediate, 2 bytes 905// 0b0111 => Immediate, 1 byte 906class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am, 907 InstrItinClass itin, string opc, string asm, 908 list<dag> pattern> 909 : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>, 910 T1LoadStore<0b0101, opcode> { 911 bits<3> Rt; 912 bits<8> addr; 913 let Inst{8-6} = addr{5-3}; // Rm 914 let Inst{5-3} = addr{2-0}; // Rn 915 let Inst{2-0} = Rt; 916} 917class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am, 918 InstrItinClass itin, string opc, string asm, 919 list<dag> pattern> 920 : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>, 921 T1LoadStore<opA, {opB,?,?}> { 922 bits<3> Rt; 923 bits<8> addr; 924 let Inst{10-6} = addr{7-3}; // imm5 925 let Inst{5-3} = addr{2-0}; // Rn 926 let Inst{2-0} = Rt; 927} 928 929// A6.2.5 Miscellaneous 16-bit instructions encoding. 930class T1Misc<bits<7> opcode> : Encoding16 { 931 let Inst{15-12} = 0b1011; 932 let Inst{11-5} = opcode; 933} 934 935// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 936class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 937 InstrItinClass itin, 938 string opc, string asm, string cstr, list<dag> pattern> 939 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 940 let OutOperandList = oops; 941 let InOperandList = !con(iops, (ins pred:$p)); 942 let AsmString = !strconcat(opc, "${p}", asm); 943 let Pattern = pattern; 944 list<Predicate> Predicates = [IsThumb2]; 945} 946 947// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an 948// input operand since by default it's a zero register. It will become an 949// implicit def once it's "flipped". 950// 951// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 952// more consistent. 953class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 954 InstrItinClass itin, 955 string opc, string asm, string cstr, list<dag> pattern> 956 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 957 let OutOperandList = oops; 958 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 959 let AsmString = !strconcat(opc, "${s}${p}", asm); 960 let Pattern = pattern; 961 list<Predicate> Predicates = [IsThumb2]; 962} 963 964// Special cases 965class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 966 InstrItinClass itin, 967 string asm, string cstr, list<dag> pattern> 968 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 969 let OutOperandList = oops; 970 let InOperandList = iops; 971 let AsmString = asm; 972 let Pattern = pattern; 973 list<Predicate> Predicates = [IsThumb2]; 974} 975 976class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 977 InstrItinClass itin, 978 string asm, string cstr, list<dag> pattern> 979 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 980 let OutOperandList = oops; 981 let InOperandList = iops; 982 let AsmString = asm; 983 let Pattern = pattern; 984 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 985} 986 987class T2I<dag oops, dag iops, InstrItinClass itin, 988 string opc, string asm, list<dag> pattern> 989 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 990class T2Ii12<dag oops, dag iops, InstrItinClass itin, 991 string opc, string asm, list<dag> pattern> 992 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>; 993class T2Ii8<dag oops, dag iops, InstrItinClass itin, 994 string opc, string asm, list<dag> pattern> 995 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>; 996class T2Iso<dag oops, dag iops, InstrItinClass itin, 997 string opc, string asm, list<dag> pattern> 998 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>; 999class T2Ipc<dag oops, dag iops, InstrItinClass itin, 1000 string opc, string asm, list<dag> pattern> 1001 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>; 1002class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin, 1003 string opc, string asm, list<dag> pattern> 1004 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "", 1005 pattern> { 1006 let Inst{31-27} = 0b11101; 1007 let Inst{26-25} = 0b00; 1008 let Inst{24} = P; 1009 let Inst{23} = ?; // The U bit. 1010 let Inst{22} = 1; 1011 let Inst{21} = W; 1012 let Inst{20} = load; 1013 1014 bits<4> Rt; 1015 bits<4> Rt2; 1016 bits<13> addr; 1017 let Inst{15-12} = Rt{3-0}; 1018 let Inst{11-8} = Rt2{3-0}; 1019 let Inst{19-16} = addr{12-9}; 1020 let Inst{23} = addr{8}; 1021 let Inst{7-0} = addr{7-0}; 1022} 1023 1024class T2sI<dag oops, dag iops, InstrItinClass itin, 1025 string opc, string asm, list<dag> pattern> 1026 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1027 1028class T2XI<dag oops, dag iops, InstrItinClass itin, 1029 string asm, list<dag> pattern> 1030 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 1031class T2JTI<dag oops, dag iops, InstrItinClass itin, 1032 string asm, list<dag> pattern> 1033 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 1034 1035// Two-address instructions 1036class T2XIt<dag oops, dag iops, InstrItinClass itin, 1037 string asm, string cstr, list<dag> pattern> 1038 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>; 1039 1040// T2Iidxldst - Thumb2 indexed load / store instructions. 1041class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre, 1042 dag oops, dag iops, 1043 AddrMode am, IndexMode im, InstrItinClass itin, 1044 string opc, string asm, string cstr, list<dag> pattern> 1045 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> { 1046 let OutOperandList = oops; 1047 let InOperandList = !con(iops, (ins pred:$p)); 1048 let AsmString = !strconcat(opc, "${p}", asm); 1049 let Pattern = pattern; 1050 list<Predicate> Predicates = [IsThumb2]; 1051 let Inst{31-27} = 0b11111; 1052 let Inst{26-25} = 0b00; 1053 let Inst{24} = signed; 1054 let Inst{23} = 0; 1055 let Inst{22-21} = opcod; 1056 let Inst{20} = load; 1057 let Inst{11} = 1; 1058 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1059 let Inst{10} = pre; // The P bit. 1060 let Inst{8} = 1; // The W bit. 1061 1062 bits<9> addr; 1063 let Inst{7-0} = addr{7-0}; 1064 let Inst{9} = addr{8}; // Sign bit 1065 1066 bits<4> Rt; 1067 bits<4> Rn; 1068 let Inst{15-12} = Rt{3-0}; 1069 let Inst{19-16} = Rn{3-0}; 1070} 1071 1072// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1073class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1074 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T]; 1075} 1076 1077// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1078class T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1079 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1080} 1081 1082// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1083class T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1084 list<Predicate> Predicates = [IsThumb2]; 1085} 1086 1087//===----------------------------------------------------------------------===// 1088 1089//===----------------------------------------------------------------------===// 1090// ARM VFP Instruction templates. 1091// 1092 1093// Almost all VFP instructions are predicable. 1094class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1095 IndexMode im, Format f, InstrItinClass itin, 1096 string opc, string asm, string cstr, list<dag> pattern> 1097 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1098 bits<4> p; 1099 let Inst{31-28} = p; 1100 let OutOperandList = oops; 1101 let InOperandList = !con(iops, (ins pred:$p)); 1102 let AsmString = !strconcat(opc, "${p}", asm); 1103 let Pattern = pattern; 1104 list<Predicate> Predicates = [HasVFP2]; 1105} 1106 1107// Special cases 1108class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1109 IndexMode im, Format f, InstrItinClass itin, 1110 string asm, string cstr, list<dag> pattern> 1111 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1112 bits<4> p; 1113 let Inst{31-28} = p; 1114 let OutOperandList = oops; 1115 let InOperandList = iops; 1116 let AsmString = asm; 1117 let Pattern = pattern; 1118 list<Predicate> Predicates = [HasVFP2]; 1119} 1120 1121class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1122 string opc, string asm, list<dag> pattern> 1123 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 1124 opc, asm, "", pattern>; 1125 1126// ARM VFP addrmode5 loads and stores 1127class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1128 InstrItinClass itin, 1129 string opc, string asm, list<dag> pattern> 1130 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1131 VFPLdStFrm, itin, opc, asm, "", pattern> { 1132 // Instruction operands. 1133 bits<5> Dd; 1134 bits<13> addr; 1135 1136 // Encode instruction operands. 1137 let Inst{23} = addr{8}; // U (add = (U == '1')) 1138 let Inst{22} = Dd{4}; 1139 let Inst{19-16} = addr{12-9}; // Rn 1140 let Inst{15-12} = Dd{3-0}; 1141 let Inst{7-0} = addr{7-0}; // imm8 1142 1143 // TODO: Mark the instructions with the appropriate subtarget info. 1144 let Inst{27-24} = opcod1; 1145 let Inst{21-20} = opcod2; 1146 let Inst{11-9} = 0b101; 1147 let Inst{8} = 1; // Double precision 1148 1149 // 64-bit loads & stores operate on both NEON and VFP pipelines. 1150 let D = VFPNeonDomain; 1151} 1152 1153class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1154 InstrItinClass itin, 1155 string opc, string asm, list<dag> pattern> 1156 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1157 VFPLdStFrm, itin, opc, asm, "", pattern> { 1158 // Instruction operands. 1159 bits<5> Sd; 1160 bits<13> addr; 1161 1162 // Encode instruction operands. 1163 let Inst{23} = addr{8}; // U (add = (U == '1')) 1164 let Inst{22} = Sd{0}; 1165 let Inst{19-16} = addr{12-9}; // Rn 1166 let Inst{15-12} = Sd{4-1}; 1167 let Inst{7-0} = addr{7-0}; // imm8 1168 1169 // TODO: Mark the instructions with the appropriate subtarget info. 1170 let Inst{27-24} = opcod1; 1171 let Inst{21-20} = opcod2; 1172 let Inst{11-9} = 0b101; 1173 let Inst{8} = 0; // Single precision 1174} 1175 1176// VFP Load / store multiple pseudo instructions. 1177class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr, 1178 list<dag> pattern> 1179 : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain, 1180 cstr, itin> { 1181 let OutOperandList = oops; 1182 let InOperandList = !con(iops, (ins pred:$p)); 1183 let Pattern = pattern; 1184 list<Predicate> Predicates = [HasVFP2]; 1185} 1186 1187// Load / store multiple 1188class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1189 string asm, string cstr, list<dag> pattern> 1190 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im, 1191 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1192 // Instruction operands. 1193 bits<4> Rn; 1194 bits<13> regs; 1195 1196 // Encode instruction operands. 1197 let Inst{19-16} = Rn; 1198 let Inst{22} = regs{12}; 1199 let Inst{15-12} = regs{11-8}; 1200 let Inst{7-0} = regs{7-0}; 1201 1202 // TODO: Mark the instructions with the appropriate subtarget info. 1203 let Inst{27-25} = 0b110; 1204 let Inst{11-9} = 0b101; 1205 let Inst{8} = 1; // Double precision 1206 1207 // 64-bit loads & stores operate on both NEON and VFP pipelines. 1208 let D = VFPNeonDomain; 1209} 1210 1211class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1212 string asm, string cstr, list<dag> pattern> 1213 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im, 1214 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1215 // Instruction operands. 1216 bits<4> Rn; 1217 bits<13> regs; 1218 1219 // Encode instruction operands. 1220 let Inst{19-16} = Rn; 1221 let Inst{22} = regs{8}; 1222 let Inst{15-12} = regs{12-9}; 1223 let Inst{7-0} = regs{7-0}; 1224 1225 // TODO: Mark the instructions with the appropriate subtarget info. 1226 let Inst{27-25} = 0b110; 1227 let Inst{11-9} = 0b101; 1228 let Inst{8} = 0; // Single precision 1229} 1230 1231// Double precision, unary 1232class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1233 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1234 string asm, list<dag> pattern> 1235 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1236 // Instruction operands. 1237 bits<5> Dd; 1238 bits<5> Dm; 1239 1240 // Encode instruction operands. 1241 let Inst{3-0} = Dm{3-0}; 1242 let Inst{5} = Dm{4}; 1243 let Inst{15-12} = Dd{3-0}; 1244 let Inst{22} = Dd{4}; 1245 1246 let Inst{27-23} = opcod1; 1247 let Inst{21-20} = opcod2; 1248 let Inst{19-16} = opcod3; 1249 let Inst{11-9} = 0b101; 1250 let Inst{8} = 1; // Double precision 1251 let Inst{7-6} = opcod4; 1252 let Inst{4} = opcod5; 1253} 1254 1255// Double precision, binary 1256class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1257 dag iops, InstrItinClass itin, string opc, string asm, 1258 list<dag> pattern> 1259 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1260 // Instruction operands. 1261 bits<5> Dd; 1262 bits<5> Dn; 1263 bits<5> Dm; 1264 1265 // Encode instruction operands. 1266 let Inst{3-0} = Dm{3-0}; 1267 let Inst{5} = Dm{4}; 1268 let Inst{19-16} = Dn{3-0}; 1269 let Inst{7} = Dn{4}; 1270 let Inst{15-12} = Dd{3-0}; 1271 let Inst{22} = Dd{4}; 1272 1273 let Inst{27-23} = opcod1; 1274 let Inst{21-20} = opcod2; 1275 let Inst{11-9} = 0b101; 1276 let Inst{8} = 1; // Double precision 1277 let Inst{6} = op6; 1278 let Inst{4} = op4; 1279} 1280 1281// Single precision, unary 1282class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1283 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1284 string asm, list<dag> pattern> 1285 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1286 // Instruction operands. 1287 bits<5> Sd; 1288 bits<5> Sm; 1289 1290 // Encode instruction operands. 1291 let Inst{3-0} = Sm{4-1}; 1292 let Inst{5} = Sm{0}; 1293 let Inst{15-12} = Sd{4-1}; 1294 let Inst{22} = Sd{0}; 1295 1296 let Inst{27-23} = opcod1; 1297 let Inst{21-20} = opcod2; 1298 let Inst{19-16} = opcod3; 1299 let Inst{11-9} = 0b101; 1300 let Inst{8} = 0; // Single precision 1301 let Inst{7-6} = opcod4; 1302 let Inst{4} = opcod5; 1303} 1304 1305// Single precision unary, if no NEON. Same as ASuI except not available if 1306// NEON is enabled. 1307class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1308 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1309 string asm, list<dag> pattern> 1310 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, 1311 pattern> { 1312 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1313} 1314 1315// Single precision, binary 1316class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1317 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1318 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1319 // Instruction operands. 1320 bits<5> Sd; 1321 bits<5> Sn; 1322 bits<5> Sm; 1323 1324 // Encode instruction operands. 1325 let Inst{3-0} = Sm{4-1}; 1326 let Inst{5} = Sm{0}; 1327 let Inst{19-16} = Sn{4-1}; 1328 let Inst{7} = Sn{0}; 1329 let Inst{15-12} = Sd{4-1}; 1330 let Inst{22} = Sd{0}; 1331 1332 let Inst{27-23} = opcod1; 1333 let Inst{21-20} = opcod2; 1334 let Inst{11-9} = 0b101; 1335 let Inst{8} = 0; // Single precision 1336 let Inst{6} = op6; 1337 let Inst{4} = op4; 1338} 1339 1340// Single precision binary, if no NEON. Same as ASbI except not available if 1341// NEON is enabled. 1342class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1343 dag iops, InstrItinClass itin, string opc, string asm, 1344 list<dag> pattern> 1345 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1346 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1347 1348 // Instruction operands. 1349 bits<5> Sd; 1350 bits<5> Sn; 1351 bits<5> Sm; 1352 1353 // Encode instruction operands. 1354 let Inst{3-0} = Sm{4-1}; 1355 let Inst{5} = Sm{0}; 1356 let Inst{19-16} = Sn{4-1}; 1357 let Inst{7} = Sn{0}; 1358 let Inst{15-12} = Sd{4-1}; 1359 let Inst{22} = Sd{0}; 1360} 1361 1362// VFP conversion instructions 1363class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1364 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1365 list<dag> pattern> 1366 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1367 let Inst{27-23} = opcod1; 1368 let Inst{21-20} = opcod2; 1369 let Inst{19-16} = opcod3; 1370 let Inst{11-8} = opcod4; 1371 let Inst{6} = 1; 1372 let Inst{4} = 0; 1373} 1374 1375// VFP conversion between floating-point and fixed-point 1376class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1377 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1378 list<dag> pattern> 1379 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1380 // size (fixed-point number): sx == 0 ? 16 : 32 1381 let Inst{7} = op5; // sx 1382} 1383 1384// VFP conversion instructions, if no NEON 1385class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1386 dag oops, dag iops, InstrItinClass itin, 1387 string opc, string asm, list<dag> pattern> 1388 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1389 pattern> { 1390 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1391} 1392 1393class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1394 InstrItinClass itin, 1395 string opc, string asm, list<dag> pattern> 1396 : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1397 let Inst{27-20} = opcod1; 1398 let Inst{11-8} = opcod2; 1399 let Inst{4} = 1; 1400} 1401 1402class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1403 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1404 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1405 1406class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1407 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1408 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1409 1410class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1411 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1412 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1413 1414class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1415 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1416 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1417 1418//===----------------------------------------------------------------------===// 1419 1420//===----------------------------------------------------------------------===// 1421// ARM NEON Instruction templates. 1422// 1423 1424class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1425 InstrItinClass itin, string opc, string dt, string asm, string cstr, 1426 list<dag> pattern> 1427 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> { 1428 let OutOperandList = oops; 1429 let InOperandList = !con(iops, (ins pred:$p)); 1430 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1431 let Pattern = pattern; 1432 list<Predicate> Predicates = [HasNEON]; 1433} 1434 1435// Same as NeonI except it does not have a "data type" specifier. 1436class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1437 InstrItinClass itin, string opc, string asm, string cstr, 1438 list<dag> pattern> 1439 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> { 1440 let OutOperandList = oops; 1441 let InOperandList = !con(iops, (ins pred:$p)); 1442 let AsmString = !strconcat(opc, "${p}", "\t", asm); 1443 let Pattern = pattern; 1444 list<Predicate> Predicates = [HasNEON]; 1445} 1446 1447class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1448 dag oops, dag iops, InstrItinClass itin, 1449 string opc, string dt, string asm, string cstr, list<dag> pattern> 1450 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm, 1451 cstr, pattern> { 1452 let Inst{31-24} = 0b11110100; 1453 let Inst{23} = op23; 1454 let Inst{21-20} = op21_20; 1455 let Inst{11-8} = op11_8; 1456 let Inst{7-4} = op7_4; 1457 1458 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; 1459 1460 bits<5> Vd; 1461 bits<6> Rn; 1462 bits<4> Rm; 1463 1464 let Inst{22} = Vd{4}; 1465 let Inst{15-12} = Vd{3-0}; 1466 let Inst{19-16} = Rn{3-0}; 1467 let Inst{3-0} = Rm{3-0}; 1468} 1469 1470class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1471 dag oops, dag iops, InstrItinClass itin, 1472 string opc, string dt, string asm, string cstr, list<dag> pattern> 1473 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc, 1474 dt, asm, cstr, pattern> { 1475 bits<3> lane; 1476} 1477 1478class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr> 1479 : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr, 1480 itin> { 1481 let OutOperandList = oops; 1482 let InOperandList = !con(iops, (ins pred:$p)); 1483 list<Predicate> Predicates = [HasNEON]; 1484} 1485 1486class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr, 1487 list<dag> pattern> 1488 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr, 1489 itin> { 1490 let OutOperandList = oops; 1491 let InOperandList = !con(iops, (ins pred:$p)); 1492 let Pattern = pattern; 1493 list<Predicate> Predicates = [HasNEON]; 1494} 1495 1496class NDataI<dag oops, dag iops, Format f, InstrItinClass itin, 1497 string opc, string dt, string asm, string cstr, list<dag> pattern> 1498 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr, 1499 pattern> { 1500 let Inst{31-25} = 0b1111001; 1501 let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1502} 1503 1504class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin, 1505 string opc, string asm, string cstr, list<dag> pattern> 1506 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm, 1507 cstr, pattern> { 1508 let Inst{31-25} = 0b1111001; 1509} 1510 1511// NEON "one register and a modified immediate" format. 1512class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1513 bit op5, bit op4, 1514 dag oops, dag iops, InstrItinClass itin, 1515 string opc, string dt, string asm, string cstr, 1516 list<dag> pattern> 1517 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> { 1518 let Inst{23} = op23; 1519 let Inst{21-19} = op21_19; 1520 let Inst{11-8} = op11_8; 1521 let Inst{7} = op7; 1522 let Inst{6} = op6; 1523 let Inst{5} = op5; 1524 let Inst{4} = op4; 1525 1526 // Instruction operands. 1527 bits<5> Vd; 1528 bits<13> SIMM; 1529 1530 let Inst{15-12} = Vd{3-0}; 1531 let Inst{22} = Vd{4}; 1532 let Inst{24} = SIMM{7}; 1533 let Inst{18-16} = SIMM{6-4}; 1534 let Inst{3-0} = SIMM{3-0}; 1535} 1536 1537// NEON 2 vector register format. 1538class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1539 bits<5> op11_7, bit op6, bit op4, 1540 dag oops, dag iops, InstrItinClass itin, 1541 string opc, string dt, string asm, string cstr, list<dag> pattern> 1542 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> { 1543 let Inst{24-23} = op24_23; 1544 let Inst{21-20} = op21_20; 1545 let Inst{19-18} = op19_18; 1546 let Inst{17-16} = op17_16; 1547 let Inst{11-7} = op11_7; 1548 let Inst{6} = op6; 1549 let Inst{4} = op4; 1550 1551 // Instruction operands. 1552 bits<5> Vd; 1553 bits<5> Vm; 1554 1555 let Inst{15-12} = Vd{3-0}; 1556 let Inst{22} = Vd{4}; 1557 let Inst{3-0} = Vm{3-0}; 1558 let Inst{5} = Vm{4}; 1559} 1560 1561// Same as N2V except it doesn't have a datatype suffix. 1562class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1563 bits<5> op11_7, bit op6, bit op4, 1564 dag oops, dag iops, InstrItinClass itin, 1565 string opc, string asm, string cstr, list<dag> pattern> 1566 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> { 1567 let Inst{24-23} = op24_23; 1568 let Inst{21-20} = op21_20; 1569 let Inst{19-18} = op19_18; 1570 let Inst{17-16} = op17_16; 1571 let Inst{11-7} = op11_7; 1572 let Inst{6} = op6; 1573 let Inst{4} = op4; 1574 1575 // Instruction operands. 1576 bits<5> Vd; 1577 bits<5> Vm; 1578 1579 let Inst{15-12} = Vd{3-0}; 1580 let Inst{22} = Vd{4}; 1581 let Inst{3-0} = Vm{3-0}; 1582 let Inst{5} = Vm{4}; 1583} 1584 1585// NEON 2 vector register with immediate. 1586class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1587 dag oops, dag iops, Format f, InstrItinClass itin, 1588 string opc, string dt, string asm, string cstr, list<dag> pattern> 1589 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1590 let Inst{24} = op24; 1591 let Inst{23} = op23; 1592 let Inst{11-8} = op11_8; 1593 let Inst{7} = op7; 1594 let Inst{6} = op6; 1595 let Inst{4} = op4; 1596 1597 // Instruction operands. 1598 bits<5> Vd; 1599 bits<5> Vm; 1600 bits<6> SIMM; 1601 1602 let Inst{15-12} = Vd{3-0}; 1603 let Inst{22} = Vd{4}; 1604 let Inst{3-0} = Vm{3-0}; 1605 let Inst{5} = Vm{4}; 1606 let Inst{21-16} = SIMM{5-0}; 1607} 1608 1609// NEON 3 vector register format. 1610class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1611 dag oops, dag iops, Format f, InstrItinClass itin, 1612 string opc, string dt, string asm, string cstr, list<dag> pattern> 1613 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1614 let Inst{24} = op24; 1615 let Inst{23} = op23; 1616 let Inst{21-20} = op21_20; 1617 let Inst{11-8} = op11_8; 1618 let Inst{6} = op6; 1619 let Inst{4} = op4; 1620 1621 // Instruction operands. 1622 bits<5> Vd; 1623 bits<5> Vn; 1624 bits<5> Vm; 1625 1626 let Inst{15-12} = Vd{3-0}; 1627 let Inst{22} = Vd{4}; 1628 let Inst{19-16} = Vn{3-0}; 1629 let Inst{7} = Vn{4}; 1630 let Inst{3-0} = Vm{3-0}; 1631 let Inst{5} = Vm{4}; 1632} 1633 1634// Same as N3V except it doesn't have a data type suffix. 1635class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1636 bit op4, 1637 dag oops, dag iops, Format f, InstrItinClass itin, 1638 string opc, string asm, string cstr, list<dag> pattern> 1639 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> { 1640 let Inst{24} = op24; 1641 let Inst{23} = op23; 1642 let Inst{21-20} = op21_20; 1643 let Inst{11-8} = op11_8; 1644 let Inst{6} = op6; 1645 let Inst{4} = op4; 1646 1647 // Instruction operands. 1648 bits<5> Vd; 1649 bits<5> Vn; 1650 bits<5> Vm; 1651 1652 let Inst{15-12} = Vd{3-0}; 1653 let Inst{22} = Vd{4}; 1654 let Inst{19-16} = Vn{3-0}; 1655 let Inst{7} = Vn{4}; 1656 let Inst{3-0} = Vm{3-0}; 1657 let Inst{5} = Vm{4}; 1658} 1659 1660// NEON VMOVs between scalar and core registers. 1661class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1662 dag oops, dag iops, Format f, InstrItinClass itin, 1663 string opc, string dt, string asm, list<dag> pattern> 1664 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain, 1665 "", itin> { 1666 let Inst{27-20} = opcod1; 1667 let Inst{11-8} = opcod2; 1668 let Inst{6-5} = opcod3; 1669 let Inst{4} = 1; 1670 1671 let OutOperandList = oops; 1672 let InOperandList = !con(iops, (ins pred:$p)); 1673 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1674 let Pattern = pattern; 1675 list<Predicate> Predicates = [HasNEON]; 1676 1677 let PostEncoderMethod = "NEONThumb2DupPostEncoder"; 1678 1679 bits<5> V; 1680 bits<4> R; 1681 bits<4> p; 1682 bits<4> lane; 1683 1684 let Inst{31-28} = p{3-0}; 1685 let Inst{7} = V{4}; 1686 let Inst{19-16} = V{3-0}; 1687 let Inst{15-12} = R{3-0}; 1688} 1689class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1690 dag oops, dag iops, InstrItinClass itin, 1691 string opc, string dt, string asm, list<dag> pattern> 1692 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin, 1693 opc, dt, asm, pattern>; 1694class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1695 dag oops, dag iops, InstrItinClass itin, 1696 string opc, string dt, string asm, list<dag> pattern> 1697 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin, 1698 opc, dt, asm, pattern>; 1699class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1700 dag oops, dag iops, InstrItinClass itin, 1701 string opc, string dt, string asm, list<dag> pattern> 1702 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin, 1703 opc, dt, asm, pattern>; 1704 1705// Vector Duplicate Lane (from scalar to all elements) 1706class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops, 1707 InstrItinClass itin, string opc, string dt, string asm, 1708 list<dag> pattern> 1709 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> { 1710 let Inst{24-23} = 0b11; 1711 let Inst{21-20} = 0b11; 1712 let Inst{19-16} = op19_16; 1713 let Inst{11-7} = 0b11000; 1714 let Inst{6} = op6; 1715 let Inst{4} = 0; 1716 1717 bits<5> Vd; 1718 bits<5> Vm; 1719 bits<4> lane; 1720 1721 let Inst{22} = Vd{4}; 1722 let Inst{15-12} = Vd{3-0}; 1723 let Inst{5} = Vm{4}; 1724 let Inst{3-0} = Vm{3-0}; 1725} 1726 1727// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 1728// for single-precision FP. 1729class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 1730 list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 1731} 1732