ARMInstrFormats.td revision c63e15ebf517f96d2ac3a6b969791bf3f9130964
1//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// ARM Instruction Format Definitions. 13// 14 15// Format specifies the encoding used by the instruction. This is part of the 16// ad-hoc solution used to emit machine instruction encodings by our machine 17// code emitter. 18class Format<bits<5> val> { 19 bits<5> Value = val; 20} 21 22def Pseudo : Format<1>; 23def MulFrm : Format<2>; 24def BrFrm : Format<3>; 25def BrMiscFrm : Format<4>; 26 27def DPFrm : Format<5>; 28def DPSoRegFrm : Format<6>; 29 30def LdFrm : Format<7>; 31def StFrm : Format<8>; 32def LdMiscFrm : Format<9>; 33def StMiscFrm : Format<10>; 34def LdMulFrm : Format<11>; 35def StMulFrm : Format<12>; 36 37def ArithMiscFrm: Format<13>; 38def ExtFrm : Format<14>; 39def VFPFrm : Format<15>; 40def VFPUnaryFrm : Format<16>; 41def VFPBinaryFrm: Format<17>; 42def ThumbFrm : Format<18>; 43 44// Misc flag for data processing instructions that indicates whether 45// the instruction has a Rn register operand. 46class UnaryDP { bit isUnaryDataProc = 1; } 47 48//===----------------------------------------------------------------------===// 49 50// ARM Instruction templates. 51// 52 53class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, 54 Format f, string cstr> 55 : Instruction { 56 field bits<32> Inst; 57 58 let Namespace = "ARM"; 59 60 // TSFlagsFields 61 AddrMode AM = am; 62 bits<4> AddrModeBits = AM.Value; 63 64 SizeFlagVal SZ = sz; 65 bits<3> SizeFlag = SZ.Value; 66 67 IndexMode IM = im; 68 bits<2> IndexModeBits = IM.Value; 69 70 Format F = f; 71 bits<5> Form = F.Value; 72 73 // 74 // Attributes specific to ARM instructions... 75 // 76 bit isUnaryDataProc = 0; 77 78 let Constraints = cstr; 79} 80 81class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern> 82 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> { 83 let OutOperandList = oops; 84 let InOperandList = iops; 85 let AsmString = asm; 86 let Pattern = pattern; 87} 88 89// Almost all ARM instructions are predicable. 90class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 91 IndexMode im, Format f, string opc, string asm, string cstr, 92 list<dag> pattern> 93 : InstARM<am, sz, im, f, cstr> { 94 let OutOperandList = oops; 95 let InOperandList = !con(iops, (ops pred:$p)); 96 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 97 let Pattern = pattern; 98 list<Predicate> Predicates = [IsARM]; 99} 100 101// Same as I except it can optionally modify CPSR. Note it's modeled as 102// an input operand since by default it's a zero register. It will 103// become an implicit def once it's "flipped". 104class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 105 IndexMode im, Format f, string opc, string asm, string cstr, 106 list<dag> pattern> 107 : InstARM<am, sz, im, f, cstr> { 108 let OutOperandList = oops; 109 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); 110 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm)); 111 let Pattern = pattern; 112 list<Predicate> Predicates = [IsARM]; 113} 114 115// Special cases 116class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 117 IndexMode im, Format f, string asm, string cstr, list<dag> pattern> 118 : InstARM<am, sz, im, f, cstr> { 119 let OutOperandList = oops; 120 let InOperandList = iops; 121 let AsmString = asm; 122 let Pattern = pattern; 123 list<Predicate> Predicates = [IsARM]; 124} 125 126class AI<dag oops, dag iops, Format f, string opc, 127 string asm, list<dag> pattern> 128 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, 129 asm, "", pattern>; 130class AsI<dag oops, dag iops, Format f, string opc, 131 string asm, list<dag> pattern> 132 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, 133 asm, "", pattern>; 134class AXI<dag oops, dag iops, Format f, string asm, 135 list<dag> pattern> 136 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, 137 "", pattern>; 138 139// Ctrl flow instructions 140class ABI<bits<4> opcod, dag oops, dag iops, string opc, 141 string asm, list<dag> pattern> 142 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, opc, 143 asm, "", pattern> { 144 let Inst{27-24} = opcod; 145} 146class ABXI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> 147 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, asm, 148 "", pattern> { 149 let Inst{27-24} = opcod; 150} 151class ABXIx2<dag oops, dag iops, string asm, list<dag> pattern> 152 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, asm, 153 "", pattern>; 154 155// BR_JT instructions 156class JTI<dag oops, dag iops, string asm, list<dag> pattern> 157 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, 158 asm, "", pattern>; 159 160// addrmode1 instructions 161class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc, 162 string asm, list<dag> pattern> 163 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc, 164 asm, "", pattern> { 165 let Inst{24-21} = opcod; 166 let Inst{27-26} = {0,0}; 167} 168class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc, 169 string asm, list<dag> pattern> 170 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc, 171 asm, "", pattern> { 172 let Inst{24-21} = opcod; 173 let Inst{27-26} = {0,0}; 174} 175class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm, 176 list<dag> pattern> 177 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm, 178 "", pattern> { 179 let Inst{24-21} = opcod; 180 let Inst{27-26} = {0,0}; 181} 182class AI1x2<dag oops, dag iops, Format f, string opc, 183 string asm, list<dag> pattern> 184 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc, 185 asm, "", pattern>; 186 187 188// addrmode2 loads and stores 189class AI2<dag oops, dag iops, Format f, string opc, 190 string asm, list<dag> pattern> 191 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 192 asm, "", pattern> { 193 let Inst{27-26} = {0,1}; 194} 195 196// loads 197class AI2ldw<dag oops, dag iops, Format f, string opc, 198 string asm, list<dag> pattern> 199 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 200 asm, "", pattern> { 201 let Inst{20} = 1; // L bit 202 let Inst{21} = 0; // W bit 203 let Inst{22} = 0; // B bit 204 let Inst{24} = 1; // P bit 205 let Inst{27-26} = {0,1}; 206} 207class AXI2ldw<dag oops, dag iops, Format f, string asm, 208 list<dag> pattern> 209 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 210 asm, "", pattern> { 211 let Inst{20} = 1; // L bit 212 let Inst{21} = 0; // W bit 213 let Inst{22} = 0; // B bit 214 let Inst{24} = 1; // P bit 215 let Inst{27-26} = {0,1}; 216} 217class AI2ldb<dag oops, dag iops, Format f, string opc, 218 string asm, list<dag> pattern> 219 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 220 asm, "", pattern> { 221 let Inst{20} = 1; // L bit 222 let Inst{21} = 0; // W bit 223 let Inst{22} = 1; // B bit 224 let Inst{24} = 1; // P bit 225 let Inst{27-26} = {0,1}; 226} 227class AXI2ldb<dag oops, dag iops, Format f, string asm, 228 list<dag> pattern> 229 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 230 asm, "", pattern> { 231 let Inst{20} = 1; // L bit 232 let Inst{21} = 0; // W bit 233 let Inst{22} = 1; // B bit 234 let Inst{24} = 1; // P bit 235 let Inst{27-26} = {0,1}; 236} 237 238// stores 239class AI2stw<dag oops, dag iops, Format f, string opc, 240 string asm, list<dag> pattern> 241 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 242 asm, "", pattern> { 243 let Inst{20} = 0; // L bit 244 let Inst{21} = 0; // W bit 245 let Inst{22} = 0; // B bit 246 let Inst{24} = 1; // P bit 247 let Inst{27-26} = {0,1}; 248} 249class AXI2stw<dag oops, dag iops, Format f, string asm, 250 list<dag> pattern> 251 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 252 asm, "", pattern> { 253 let Inst{20} = 0; // L bit 254 let Inst{21} = 0; // W bit 255 let Inst{22} = 0; // B bit 256 let Inst{24} = 1; // P bit 257 let Inst{27-26} = {0,1}; 258} 259class AI2stb<dag oops, dag iops, Format f, string opc, 260 string asm, list<dag> pattern> 261 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 262 asm, "", pattern> { 263 let Inst{20} = 0; // L bit 264 let Inst{21} = 0; // W bit 265 let Inst{22} = 1; // B bit 266 let Inst{24} = 1; // P bit 267 let Inst{27-26} = {0,1}; 268} 269class AXI2stb<dag oops, dag iops, Format f, string asm, 270 list<dag> pattern> 271 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 272 asm, "", pattern> { 273 let Inst{20} = 0; // L bit 274 let Inst{21} = 0; // W bit 275 let Inst{22} = 1; // B bit 276 let Inst{24} = 1; // P bit 277 let Inst{27-26} = {0,1}; 278} 279 280// Pre-indexed loads 281class AI2ldwpr<dag oops, dag iops, Format f, string opc, 282 string asm, string cstr, list<dag> pattern> 283 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 284 asm, cstr, pattern> { 285 let Inst{20} = 1; // L bit 286 let Inst{21} = 1; // W bit 287 let Inst{22} = 0; // B bit 288 let Inst{24} = 1; // P bit 289 let Inst{27-26} = {0,1}; 290} 291class AI2ldbpr<dag oops, dag iops, Format f, string opc, 292 string asm, string cstr, list<dag> pattern> 293 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 294 asm, cstr, pattern> { 295 let Inst{20} = 1; // L bit 296 let Inst{21} = 1; // W bit 297 let Inst{22} = 1; // B bit 298 let Inst{24} = 1; // P bit 299 let Inst{27-26} = {0,1}; 300} 301 302// Pre-indexed stores 303class AI2stwpr<dag oops, dag iops, Format f, string opc, 304 string asm, string cstr, list<dag> pattern> 305 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 306 asm, cstr, pattern> { 307 let Inst{20} = 0; // L bit 308 let Inst{21} = 1; // W bit 309 let Inst{22} = 0; // B bit 310 let Inst{24} = 1; // P bit 311 let Inst{27-26} = {0,1}; 312} 313class AI2stbpr<dag oops, dag iops, Format f, string opc, 314 string asm, string cstr, list<dag> pattern> 315 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 316 asm, cstr, pattern> { 317 let Inst{20} = 0; // L bit 318 let Inst{21} = 1; // W bit 319 let Inst{22} = 1; // B bit 320 let Inst{24} = 1; // P bit 321 let Inst{27-26} = {0,1}; 322} 323 324// Post-indexed loads 325class AI2ldwpo<dag oops, dag iops, Format f, string opc, 326 string asm, string cstr, list<dag> pattern> 327 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 328 asm, cstr,pattern> { 329 let Inst{20} = 1; // L bit 330 let Inst{21} = 0; // W bit 331 let Inst{22} = 0; // B bit 332 let Inst{24} = 0; // P bit 333 let Inst{27-26} = {0,1}; 334} 335class AI2ldbpo<dag oops, dag iops, Format f, string opc, 336 string asm, string cstr, list<dag> pattern> 337 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 338 asm, cstr,pattern> { 339 let Inst{20} = 1; // L bit 340 let Inst{21} = 0; // W bit 341 let Inst{22} = 1; // B bit 342 let Inst{24} = 0; // P bit 343 let Inst{27-26} = {0,1}; 344} 345 346// Post-indexed stores 347class AI2stwpo<dag oops, dag iops, Format f, string opc, 348 string asm, string cstr, list<dag> pattern> 349 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 350 asm, cstr,pattern> { 351 let Inst{20} = 0; // L bit 352 let Inst{21} = 0; // W bit 353 let Inst{22} = 0; // B bit 354 let Inst{24} = 0; // P bit 355 let Inst{27-26} = {0,1}; 356} 357class AI2stbpo<dag oops, dag iops, Format f, string opc, 358 string asm, string cstr, list<dag> pattern> 359 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 360 asm, cstr,pattern> { 361 let Inst{20} = 0; // L bit 362 let Inst{21} = 0; // W bit 363 let Inst{22} = 1; // B bit 364 let Inst{24} = 0; // P bit 365 let Inst{27-26} = {0,1}; 366} 367 368// addrmode3 instructions 369class AI3<dag oops, dag iops, Format f, string opc, 370 string asm, list<dag> pattern> 371 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 372 asm, "", pattern>; 373class AXI3<dag oops, dag iops, Format f, string asm, 374 list<dag> pattern> 375 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm, 376 "", pattern>; 377 378// loads 379class AI3ldh<dag oops, dag iops, Format f, string opc, 380 string asm, list<dag> pattern> 381 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 382 asm, "", pattern> { 383 let Inst{4} = 1; 384 let Inst{5} = 1; // H bit 385 let Inst{6} = 0; // S bit 386 let Inst{7} = 1; 387 let Inst{20} = 1; // L bit 388 let Inst{21} = 0; // W bit 389 let Inst{24} = 1; // P bit 390} 391class AXI3ldh<dag oops, dag iops, Format f, string asm, 392 list<dag> pattern> 393 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 394 asm, "", pattern> { 395 let Inst{4} = 1; 396 let Inst{5} = 1; // H bit 397 let Inst{6} = 0; // S bit 398 let Inst{7} = 1; 399 let Inst{20} = 1; // L bit 400 let Inst{21} = 0; // W bit 401 let Inst{24} = 1; // P bit 402} 403class AI3ldsh<dag oops, dag iops, Format f, string opc, 404 string asm, list<dag> pattern> 405 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 406 asm, "", pattern> { 407 let Inst{4} = 1; 408 let Inst{5} = 1; // H bit 409 let Inst{6} = 1; // S bit 410 let Inst{7} = 1; 411 let Inst{20} = 1; // L bit 412 let Inst{21} = 0; // W bit 413 let Inst{24} = 1; // P bit 414} 415class AXI3ldsh<dag oops, dag iops, Format f, string asm, 416 list<dag> pattern> 417 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 418 asm, "", pattern> { 419 let Inst{4} = 1; 420 let Inst{5} = 1; // H bit 421 let Inst{6} = 1; // S bit 422 let Inst{7} = 1; 423 let Inst{20} = 1; // L bit 424 let Inst{21} = 0; // W bit 425 let Inst{24} = 1; // P bit 426} 427class AI3ldsb<dag oops, dag iops, Format f, string opc, 428 string asm, list<dag> pattern> 429 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 430 asm, "", pattern> { 431 let Inst{4} = 1; 432 let Inst{5} = 0; // H bit 433 let Inst{6} = 1; // S bit 434 let Inst{7} = 1; 435 let Inst{20} = 1; // L bit 436 let Inst{21} = 0; // W bit 437 let Inst{24} = 1; // P bit 438} 439class AXI3ldsb<dag oops, dag iops, Format f, string asm, 440 list<dag> pattern> 441 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 442 asm, "", pattern> { 443 let Inst{4} = 1; 444 let Inst{5} = 0; // H bit 445 let Inst{6} = 1; // S bit 446 let Inst{7} = 1; 447 let Inst{20} = 1; // L bit 448 let Inst{21} = 0; // W bit 449 let Inst{24} = 1; // P bit 450} 451class AI3ldd<dag oops, dag iops, Format f, string opc, 452 string asm, list<dag> pattern> 453 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 454 asm, "", pattern> { 455 let Inst{4} = 1; 456 let Inst{5} = 0; // H bit 457 let Inst{6} = 1; // S bit 458 let Inst{7} = 1; 459 let Inst{20} = 0; // L bit 460 let Inst{21} = 0; // W bit 461 let Inst{24} = 1; // P bit 462} 463 464// stores 465class AI3sth<dag oops, dag iops, Format f, string opc, 466 string asm, list<dag> pattern> 467 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 468 asm, "", pattern> { 469 let Inst{4} = 1; 470 let Inst{5} = 1; // H bit 471 let Inst{6} = 0; // S bit 472 let Inst{7} = 1; 473 let Inst{20} = 0; // L bit 474 let Inst{21} = 0; // W bit 475 let Inst{24} = 1; // P bit 476} 477class AXI3sth<dag oops, dag iops, Format f, string asm, 478 list<dag> pattern> 479 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 480 asm, "", pattern> { 481 let Inst{4} = 1; 482 let Inst{5} = 1; // H bit 483 let Inst{6} = 0; // S bit 484 let Inst{7} = 1; 485 let Inst{20} = 0; // L bit 486 let Inst{21} = 0; // W bit 487 let Inst{24} = 1; // P bit 488} 489class AI3std<dag oops, dag iops, Format f, string opc, 490 string asm, list<dag> pattern> 491 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 492 asm, "", pattern> { 493 let Inst{4} = 1; 494 let Inst{5} = 1; // H bit 495 let Inst{6} = 1; // S bit 496 let Inst{7} = 1; 497 let Inst{20} = 0; // L bit 498 let Inst{21} = 0; // W bit 499 let Inst{24} = 1; // P bit 500} 501 502// Pre-indexed loads 503class AI3ldhpr<dag oops, dag iops, Format f, string opc, 504 string asm, string cstr, list<dag> pattern> 505 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 506 asm, cstr, pattern> { 507 let Inst{4} = 1; 508 let Inst{5} = 1; // H bit 509 let Inst{6} = 0; // S bit 510 let Inst{7} = 1; 511 let Inst{20} = 1; // L bit 512 let Inst{21} = 1; // W bit 513 let Inst{24} = 1; // P bit 514} 515class AI3ldshpr<dag oops, dag iops, Format f, string opc, 516 string asm, string cstr, list<dag> pattern> 517 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 518 asm, cstr, pattern> { 519 let Inst{4} = 1; 520 let Inst{5} = 1; // H bit 521 let Inst{6} = 1; // S bit 522 let Inst{7} = 1; 523 let Inst{20} = 1; // L bit 524 let Inst{21} = 1; // W bit 525 let Inst{24} = 1; // P bit 526} 527class AI3ldsbpr<dag oops, dag iops, Format f, string opc, 528 string asm, string cstr, list<dag> pattern> 529 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 530 asm, cstr, pattern> { 531 let Inst{4} = 1; 532 let Inst{5} = 0; // H bit 533 let Inst{6} = 1; // S bit 534 let Inst{7} = 1; 535 let Inst{20} = 1; // L bit 536 let Inst{21} = 1; // W bit 537 let Inst{24} = 1; // P bit 538} 539 540// Pre-indexed stores 541class AI3sthpr<dag oops, dag iops, Format f, string opc, 542 string asm, string cstr, list<dag> pattern> 543 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 544 asm, cstr, pattern> { 545 let Inst{4} = 1; 546 let Inst{5} = 1; // H bit 547 let Inst{6} = 0; // S bit 548 let Inst{7} = 1; 549 let Inst{20} = 0; // L bit 550 let Inst{21} = 1; // W bit 551 let Inst{24} = 1; // P bit 552} 553 554// Post-indexed loads 555class AI3ldhpo<dag oops, dag iops, Format f, string opc, 556 string asm, string cstr, list<dag> pattern> 557 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 558 asm, cstr,pattern> { 559 let Inst{4} = 1; 560 let Inst{5} = 1; // H bit 561 let Inst{6} = 0; // S bit 562 let Inst{7} = 1; 563 let Inst{20} = 1; // L bit 564 let Inst{21} = 1; // W bit 565 let Inst{24} = 0; // P bit 566} 567class AI3ldshpo<dag oops, dag iops, Format f, string opc, 568 string asm, string cstr, list<dag> pattern> 569 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 570 asm, cstr,pattern> { 571 let Inst{4} = 1; 572 let Inst{5} = 1; // H bit 573 let Inst{6} = 1; // S bit 574 let Inst{7} = 1; 575 let Inst{20} = 1; // L bit 576 let Inst{21} = 1; // W bit 577 let Inst{24} = 0; // P bit 578} 579class AI3ldsbpo<dag oops, dag iops, Format f, string opc, 580 string asm, string cstr, list<dag> pattern> 581 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 582 asm, cstr,pattern> { 583 let Inst{4} = 1; 584 let Inst{5} = 0; // H bit 585 let Inst{6} = 1; // S bit 586 let Inst{7} = 1; 587 let Inst{20} = 1; // L bit 588 let Inst{21} = 1; // W bit 589 let Inst{24} = 0; // P bit 590} 591 592// Post-indexed stores 593class AI3sthpo<dag oops, dag iops, Format f, string opc, 594 string asm, string cstr, list<dag> pattern> 595 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 596 asm, cstr,pattern> { 597 let Inst{4} = 1; 598 let Inst{5} = 1; // H bit 599 let Inst{6} = 0; // S bit 600 let Inst{7} = 1; 601 let Inst{20} = 0; // L bit 602 let Inst{21} = 1; // W bit 603 let Inst{24} = 0; // P bit 604} 605 606 607// addrmode4 instructions 608class AXI4ld<dag oops, dag iops, Format f, string asm, list<dag> pattern> 609 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, 610 "", pattern> { 611 let Inst{20} = 1; // L bit 612 let Inst{22} = 0; // S bit 613 let Inst{27-25} = 0b100; 614} 615class AXI4st<dag oops, dag iops, Format f, string asm, list<dag> pattern> 616 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, 617 "", pattern> { 618 let Inst{20} = 0; // L bit 619 let Inst{22} = 0; // S bit 620 let Inst{27-25} = 0b100; 621} 622 623// Unsigned multiply, multiply-accumulate instructions. 624class AMul1I<bits<7> opcod, dag oops, dag iops, string opc, 625 string asm, list<dag> pattern> 626 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 627 asm, "", pattern> { 628 let Inst{7-4} = 0b1001; 629 let Inst{20} = 0; // S bit 630 let Inst{27-21} = opcod; 631} 632class AsMul1I<bits<7> opcod, dag oops, dag iops, string opc, 633 string asm, list<dag> pattern> 634 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 635 asm, "", pattern> { 636 let Inst{7-4} = 0b1001; 637 let Inst{27-21} = opcod; 638} 639 640// Most significant word multiply 641class AMul2I<bits<7> opcod, dag oops, dag iops, string opc, 642 string asm, list<dag> pattern> 643 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 644 asm, "", pattern> { 645 let Inst{7-4} = 0b1001; 646 let Inst{20} = 1; 647 let Inst{27-21} = opcod; 648} 649 650// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 651class AMulxyI<bits<7> opcod, dag oops, dag iops, string opc, 652 string asm, list<dag> pattern> 653 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 654 asm, "", pattern> { 655 let Inst{4} = 0; 656 let Inst{7} = 1; 657 let Inst{20} = 0; 658 let Inst{27-21} = opcod; 659} 660 661// Extend instructions. 662class AExtI<bits<8> opcod, dag oops, dag iops, string opc, 663 string asm, list<dag> pattern> 664 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, opc, 665 asm, "", pattern> { 666 let Inst{7-4} = 0b0111; 667 let Inst{27-20} = opcod; 668} 669 670// Misc Arithmetic instructions. 671class AMiscA1I<bits<8> opcod, dag oops, dag iops, string opc, 672 string asm, list<dag> pattern> 673 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, opc, 674 asm, "", pattern> { 675 let Inst{27-20} = opcod; 676} 677 678//===----------------------------------------------------------------------===// 679 680// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 681class ARMPat<dag pattern, dag result> : Pat<pattern, result> { 682 list<Predicate> Predicates = [IsARM]; 683} 684class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 685 list<Predicate> Predicates = [IsARM, HasV5TE]; 686} 687class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 688 list<Predicate> Predicates = [IsARM, HasV6]; 689} 690 691//===----------------------------------------------------------------------===// 692// 693// Thumb Instruction Format Definitions. 694// 695 696 697// TI - Thumb instruction. 698 699class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz, 700 string asm, string cstr, list<dag> pattern> 701 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> { 702 let OutOperandList = outs; 703 let InOperandList = ins; 704 let AsmString = asm; 705 let Pattern = pattern; 706 list<Predicate> Predicates = [IsThumb]; 707} 708 709class TI<dag outs, dag ins, string asm, list<dag> pattern> 710 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>; 711class TI1<dag outs, dag ins, string asm, list<dag> pattern> 712 : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>; 713class TI2<dag outs, dag ins, string asm, list<dag> pattern> 714 : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>; 715class TI4<dag outs, dag ins, string asm, list<dag> pattern> 716 : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>; 717class TIs<dag outs, dag ins, string asm, list<dag> pattern> 718 : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>; 719 720// Two-address instructions 721class TIt<dag outs, dag ins, string asm, list<dag> pattern> 722 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>; 723 724// BL, BLX(1) are translated by assembler into two instructions 725class TIx2<dag outs, dag ins, string asm, list<dag> pattern> 726 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>; 727 728// BR_JT instructions 729class TJTI<dag outs, dag ins, string asm, list<dag> pattern> 730 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>; 731 732 733//===----------------------------------------------------------------------===// 734 735//===----------------------------------------------------------------------===// 736// ARM VFP Instruction templates. 737// 738 739// ARM Float Instruction 740class ASI<dag oops, dag iops, string opc, string asm, list<dag> pattern> 741 : AI<oops, iops, VFPFrm, opc, asm, pattern> { 742 // TODO: Mark the instructions with the appropriate subtarget info. 743} 744 745class ASI5<dag oops, dag iops, string opc, string asm, list<dag> pattern> 746 : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 747 VFPFrm, opc, asm, "", pattern> { 748 // TODO: Mark the instructions with the appropriate subtarget info. 749} 750 751// ARM Double Instruction 752class ADI<dag oops, dag iops, string opc, string asm, list<dag> pattern> 753 : AI<oops, iops, VFPFrm, opc, asm, pattern> { 754 // TODO: Mark the instructions with the appropriate subtarget info. 755} 756 757class ADI5<dag oops, dag iops, string opc, string asm, list<dag> pattern> 758 : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 759 VFPFrm, opc, asm, "", pattern> { 760 // TODO: Mark the instructions with the appropriate subtarget info. 761} 762 763// Double precision, unary 764class ADuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops, 765 string opc, string asm, list<dag> pattern> 766 : AI<oops, iops, VFPUnaryFrm, opc, asm, pattern> { 767 let Inst{27-20} = opcod1; 768 let Inst{19-16} = opcod2; 769 let Inst{11-8} = 0b1011; 770 let Inst{7-4} = opcod3; 771} 772 773// Double precision, binary 774class ADbI<bits<8> opcod, dag oops, dag iops, string opc, 775 string asm, list<dag> pattern> 776 : AI<oops, iops, VFPBinaryFrm, opc, asm, pattern> { 777 let Inst{27-20} = opcod; 778 let Inst{11-8} = 0b1011; 779} 780 781// Single precision, unary 782class ASuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops, 783 string opc, string asm, list<dag> pattern> 784 : AI<oops, iops, VFPUnaryFrm, opc, asm, pattern> { 785 // Bits 22 (D bit) and 5 (M bit) will be changed during instruction encoding. 786 let Inst{27-20} = opcod1; 787 let Inst{19-16} = opcod2; 788 let Inst{11-8} = 0b1010; 789 let Inst{7-4} = opcod3; 790} 791 792// Single precision, binary 793class ASbI<bits<8> opcod, dag oops, dag iops, string opc, 794 string asm, list<dag> pattern> 795 : AI<oops, iops, VFPBinaryFrm, opc, asm, pattern> { 796 // Bit 22 (D bit) can be changed during instruction encoding. 797 let Inst{27-20} = opcod; 798 let Inst{11-8} = 0b1010; 799} 800 801// Special cases. 802class AXSI<dag oops, dag iops, string asm, list<dag> pattern> 803 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, 804 VFPFrm, asm, "", pattern> { 805 // TODO: Mark the instructions with the appropriate subtarget info. 806} 807 808class AXSI5<dag oops, dag iops, string asm, list<dag> pattern> 809 : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 810 VFPFrm, asm, "", pattern> { 811 // TODO: Mark the instructions with the appropriate subtarget info. 812} 813 814class AXDI<dag oops, dag iops, string asm, list<dag> pattern> 815 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, 816 VFPFrm, asm, "", pattern> { 817 // TODO: Mark the instructions with the appropriate subtarget info. 818} 819 820class AXDI5<dag oops, dag iops, string asm, list<dag> pattern> 821 : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 822 VFPFrm, asm, "", pattern> { 823 // TODO: Mark the instructions with the appropriate subtarget info. 824} 825 826 827//===----------------------------------------------------------------------===// 828 829 830// ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode. 831class ThumbPat<dag pattern, dag result> : Pat<pattern, result> { 832 list<Predicate> Predicates = [IsThumb]; 833} 834 835class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> { 836 list<Predicate> Predicates = [IsThumb, HasV5T]; 837} 838