ARMInstrFormats.td revision dbb532831985861ebcda6ce79f7de1a3a1ca5f04
1//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// ARM Instruction Format Definitions. 13// 14 15// Format specifies the encoding used by the instruction. This is part of the 16// ad-hoc solution used to emit machine instruction encodings by our machine 17// code emitter. 18class Format<bits<6> val> { 19 bits<6> Value = val; 20} 21 22def Pseudo : Format<0>; 23def MulFrm : Format<1>; 24def BrFrm : Format<2>; 25def BrMiscFrm : Format<3>; 26 27def DPFrm : Format<4>; 28def DPSoRegFrm : Format<5>; 29 30def LdFrm : Format<6>; 31def StFrm : Format<7>; 32def LdMiscFrm : Format<8>; 33def StMiscFrm : Format<9>; 34def LdStMulFrm : Format<10>; 35 36def LdStExFrm : Format<11>; 37 38def ArithMiscFrm : Format<12>; 39def SatFrm : Format<13>; 40def ExtFrm : Format<14>; 41 42def VFPUnaryFrm : Format<15>; 43def VFPBinaryFrm : Format<16>; 44def VFPConv1Frm : Format<17>; 45def VFPConv2Frm : Format<18>; 46def VFPConv3Frm : Format<19>; 47def VFPConv4Frm : Format<20>; 48def VFPConv5Frm : Format<21>; 49def VFPLdStFrm : Format<22>; 50def VFPLdStMulFrm : Format<23>; 51def VFPMiscFrm : Format<24>; 52 53def ThumbFrm : Format<25>; 54def MiscFrm : Format<26>; 55 56def NGetLnFrm : Format<27>; 57def NSetLnFrm : Format<28>; 58def NDupFrm : Format<29>; 59def NLdStFrm : Format<30>; 60def N1RegModImmFrm: Format<31>; 61def N2RegFrm : Format<32>; 62def NVCVTFrm : Format<33>; 63def NVDupLnFrm : Format<34>; 64def N2RegVShLFrm : Format<35>; 65def N2RegVShRFrm : Format<36>; 66def N3RegFrm : Format<37>; 67def N3RegVShFrm : Format<38>; 68def NVExtFrm : Format<39>; 69def NVMulSLFrm : Format<40>; 70def NVTBLFrm : Format<41>; 71 72// Misc flags. 73 74// the instruction has a Rn register operand. 75// UnaryDP - Indicates this is a unary data processing instruction, i.e. 76// it doesn't have a Rn operand. 77class UnaryDP { bit isUnaryDataProc = 1; } 78 79// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 80// a 16-bit Thumb instruction if certain conditions are met. 81class Xform16Bit { bit canXformTo16Bit = 1; } 82 83//===----------------------------------------------------------------------===// 84// ARM Instruction flags. These need to match ARMBaseInstrInfo.h. 85// 86 87// Addressing mode. 88class AddrMode<bits<5> val> { 89 bits<5> Value = val; 90} 91def AddrModeNone : AddrMode<0>; 92def AddrMode1 : AddrMode<1>; 93def AddrMode2 : AddrMode<2>; 94def AddrMode3 : AddrMode<3>; 95def AddrMode4 : AddrMode<4>; 96def AddrMode5 : AddrMode<5>; 97def AddrMode6 : AddrMode<6>; 98def AddrModeT1_1 : AddrMode<7>; 99def AddrModeT1_2 : AddrMode<8>; 100def AddrModeT1_4 : AddrMode<9>; 101def AddrModeT1_s : AddrMode<10>; 102def AddrModeT2_i12 : AddrMode<11>; 103def AddrModeT2_i8 : AddrMode<12>; 104def AddrModeT2_so : AddrMode<13>; 105def AddrModeT2_pc : AddrMode<14>; 106def AddrModeT2_i8s4 : AddrMode<15>; 107def AddrMode_i12 : AddrMode<16>; 108 109// Instruction size. 110class SizeFlagVal<bits<3> val> { 111 bits<3> Value = val; 112} 113def SizeInvalid : SizeFlagVal<0>; // Unset. 114def SizeSpecial : SizeFlagVal<1>; // Pseudo or special. 115def Size8Bytes : SizeFlagVal<2>; 116def Size4Bytes : SizeFlagVal<3>; 117def Size2Bytes : SizeFlagVal<4>; 118 119// Load / store index mode. 120class IndexMode<bits<2> val> { 121 bits<2> Value = val; 122} 123def IndexModeNone : IndexMode<0>; 124def IndexModePre : IndexMode<1>; 125def IndexModePost : IndexMode<2>; 126def IndexModeUpd : IndexMode<3>; 127 128// Instruction execution domain. 129class Domain<bits<2> val> { 130 bits<2> Value = val; 131} 132def GenericDomain : Domain<0>; 133def VFPDomain : Domain<1>; // Instructions in VFP domain only 134def NeonDomain : Domain<2>; // Instructions in Neon domain only 135def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 136 137//===----------------------------------------------------------------------===// 138 139// ARM special operands. 140// 141 142def CondCodeOperand : AsmOperandClass { 143 let Name = "CondCode"; 144 let SuperClasses = []; 145} 146 147// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 148// register whose default is 0 (no register). 149def pred : PredicateOperand<OtherVT, (ops i32imm, CCR), 150 (ops (i32 14), (i32 zero_reg))> { 151 let PrintMethod = "printPredicateOperand"; 152 let ParserMatchClass = CondCodeOperand; 153} 154 155// Conditional code result for instructions whose 's' bit is set, e.g. subs. 156def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 157 string EncoderMethod = "getCCOutOpValue"; 158 let PrintMethod = "printSBitModifierOperand"; 159} 160 161// Same as cc_out except it defaults to setting CPSR. 162def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 163 string EncoderMethod = "getCCOutOpValue"; 164 let PrintMethod = "printSBitModifierOperand"; 165} 166 167// ARM special operands for disassembly only. 168// 169def setend_op : Operand<i32> { 170 let PrintMethod = "printSetendOperand"; 171} 172 173def cps_opt : Operand<i32> { 174 let PrintMethod = "printCPSOptionOperand"; 175} 176 177def msr_mask : Operand<i32> { 178 let PrintMethod = "printMSRMaskOperand"; 179} 180 181// A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0. 182// The neg_zero operand translates -0 to -1, -1 to -2, ..., etc. 183def neg_zero : Operand<i32> { 184 let PrintMethod = "printNegZeroOperand"; 185} 186 187//===----------------------------------------------------------------------===// 188 189// ARM Instruction templates. 190// 191 192class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im, 193 Format f, Domain d, string cstr, InstrItinClass itin> 194 : Instruction { 195 let Namespace = "ARM"; 196 197 AddrMode AM = am; 198 SizeFlagVal SZ = sz; 199 IndexMode IM = im; 200 bits<2> IndexModeBits = IM.Value; 201 Format F = f; 202 bits<6> Form = F.Value; 203 Domain D = d; 204 bit isUnaryDataProc = 0; 205 bit canXformTo16Bit = 0; 206 207 // If this is a pseudo instruction, mark it isCodeGenOnly. 208 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 209 210 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h. 211 let TSFlags{4-0} = AM.Value; 212 let TSFlags{7-5} = SZ.Value; 213 let TSFlags{9-8} = IndexModeBits; 214 let TSFlags{15-10} = Form; 215 let TSFlags{16} = isUnaryDataProc; 216 let TSFlags{17} = canXformTo16Bit; 217 let TSFlags{19-18} = D.Value; 218 219 let Constraints = cstr; 220 let Itinerary = itin; 221} 222 223class Encoding { 224 field bits<32> Inst; 225} 226 227class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, 228 Format f, Domain d, string cstr, InstrItinClass itin> 229 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding; 230 231// This Encoding-less class is used by Thumb1 to specify the encoding bits later 232// on by adding flavors to specific instructions. 233class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im, 234 Format f, Domain d, string cstr, InstrItinClass itin> 235 : InstTemplate<am, sz, im, f, d, cstr, itin>; 236 237class PseudoInst<dag oops, dag iops, InstrItinClass itin, 238 string asm, list<dag> pattern> 239 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain, 240 "", itin> { 241 let OutOperandList = oops; 242 let InOperandList = iops; 243 let AsmString = asm; 244 let Pattern = pattern; 245} 246 247// Almost all ARM instructions are predicable. 248class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 249 IndexMode im, Format f, InstrItinClass itin, 250 string opc, string asm, string cstr, 251 list<dag> pattern> 252 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 253 bits<4> p; 254 let Inst{31-28} = p; 255 let OutOperandList = oops; 256 let InOperandList = !con(iops, (ins pred:$p)); 257 let AsmString = !strconcat(opc, "${p}", asm); 258 let Pattern = pattern; 259 list<Predicate> Predicates = [IsARM]; 260} 261 262// A few are not predicable 263class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 264 IndexMode im, Format f, InstrItinClass itin, 265 string opc, string asm, string cstr, 266 list<dag> pattern> 267 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 268 let OutOperandList = oops; 269 let InOperandList = iops; 270 let AsmString = !strconcat(opc, asm); 271 let Pattern = pattern; 272 let isPredicable = 0; 273 list<Predicate> Predicates = [IsARM]; 274} 275 276// Same as I except it can optionally modify CPSR. Note it's modeled as an input 277// operand since by default it's a zero register. It will become an implicit def 278// once it's "flipped". 279class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 280 IndexMode im, Format f, InstrItinClass itin, 281 string opc, string asm, string cstr, 282 list<dag> pattern> 283 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 284 bits<4> p; // Predicate operand 285 bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 286 let Inst{31-28} = p; 287 let Inst{20} = s; 288 289 let OutOperandList = oops; 290 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 291 let AsmString = !strconcat(opc, "${s}${p}", asm); 292 let Pattern = pattern; 293 list<Predicate> Predicates = [IsARM]; 294} 295 296// Special cases 297class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 298 IndexMode im, Format f, InstrItinClass itin, 299 string asm, string cstr, list<dag> pattern> 300 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 301 let OutOperandList = oops; 302 let InOperandList = iops; 303 let AsmString = asm; 304 let Pattern = pattern; 305 list<Predicate> Predicates = [IsARM]; 306} 307 308class AI<dag oops, dag iops, Format f, InstrItinClass itin, 309 string opc, string asm, list<dag> pattern> 310 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 311 opc, asm, "", pattern>; 312class AsI<dag oops, dag iops, Format f, InstrItinClass itin, 313 string opc, string asm, list<dag> pattern> 314 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 315 opc, asm, "", pattern>; 316class AXI<dag oops, dag iops, Format f, InstrItinClass itin, 317 string asm, list<dag> pattern> 318 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 319 asm, "", pattern>; 320class AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 321 string opc, string asm, list<dag> pattern> 322 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 323 opc, asm, "", pattern>; 324 325// Ctrl flow instructions 326class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 327 string opc, string asm, list<dag> pattern> 328 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 329 opc, asm, "", pattern> { 330 let Inst{27-24} = opcod; 331} 332class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 333 string asm, list<dag> pattern> 334 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin, 335 asm, "", pattern> { 336 let Inst{27-24} = opcod; 337} 338class ABXIx2<dag oops, dag iops, InstrItinClass itin, 339 string asm, list<dag> pattern> 340 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, Pseudo, itin, 341 asm, "", pattern>; 342 343// BR_JT instructions 344class JTI<dag oops, dag iops, InstrItinClass itin, 345 string asm, list<dag> pattern> 346 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin, 347 asm, "", pattern>; 348 349// Atomic load/store instructions 350class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 351 string opc, string asm, list<dag> pattern> 352 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 353 opc, asm, "", pattern> { 354 bits<4> Rt; 355 bits<4> Rn; 356 let Inst{27-23} = 0b00011; 357 let Inst{22-21} = opcod; 358 let Inst{20} = 1; 359 let Inst{19-16} = Rn; 360 let Inst{15-12} = Rt; 361 let Inst{11-0} = 0b111110011111; 362} 363class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 364 string opc, string asm, list<dag> pattern> 365 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, 366 opc, asm, "", pattern> { 367 bits<4> Rd; 368 bits<4> Rt; 369 bits<4> Rn; 370 let Inst{27-23} = 0b00011; 371 let Inst{22-21} = opcod; 372 let Inst{20} = 0; 373 let Inst{19-16} = Rn; 374 let Inst{15-12} = Rd; 375 let Inst{11-4} = 0b11111001; 376 let Inst{3-0} = Rt; 377} 378class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> 379 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> { 380 bits<4> Rt; 381 bits<4> Rt2; 382 bits<4> Rn; 383 let Inst{27-23} = 0b00010; 384 let Inst{22} = b; 385 let Inst{21-20} = 0b00; 386 let Inst{19-16} = Rn; 387 let Inst{15-12} = Rt; 388 let Inst{11-4} = 0b00001001; 389 let Inst{3-0} = Rt2; 390} 391 392// addrmode1 instructions 393class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 394 string opc, string asm, list<dag> pattern> 395 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 396 opc, asm, "", pattern> { 397 let Inst{24-21} = opcod; 398 let Inst{27-26} = 0b00; 399} 400class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 401 string opc, string asm, list<dag> pattern> 402 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 403 opc, asm, "", pattern> { 404 let Inst{24-21} = opcod; 405 let Inst{27-26} = 0b00; 406} 407class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 408 string asm, list<dag> pattern> 409 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, 410 asm, "", pattern> { 411 let Inst{24-21} = opcod; 412 let Inst{27-26} = 0b00; 413} 414class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin, 415 string opc, string asm, list<dag> pattern> 416 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin, 417 opc, asm, "", pattern>; 418 419 420// addrmode2 loads and stores 421class AI2<dag oops, dag iops, Format f, InstrItinClass itin, 422 string opc, string asm, list<dag> pattern> 423 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 424 opc, asm, "", pattern> { 425 let Inst{27-26} = 0b01; 426} 427 428// loads 429 430// LDR/LDRB/STR/STRB 431class AIldst1<bits<3> op, bit opc22, bit isLd, dag oops, dag iops, AddrMode am, 432 Format f, InstrItinClass itin, string opc, string asm, 433 list<dag> pattern> 434 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm, 435 "", pattern> { 436 let Inst{27-25} = op; 437 let Inst{24} = 1; // 24 == P 438 // 23 == U 439 let Inst{22} = opc22; 440 let Inst{21} = 0; // 21 == W 441 let Inst{20} = isLd; 442} 443// LDRH/LDRSB/LDRSH/LDRD 444class AIldr2<bits<4> op, bit opc22, bit opc20, dag oops, dag iops, AddrMode am, 445 Format f, InstrItinClass itin, string opc, string asm, 446 list<dag> pattern> 447 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm, 448 "", pattern> { 449 let Inst{27-25} = 0b000; 450 let Inst{24} = 1; // 24 == P 451 // 23 == U 452 let Inst{22} = opc22; 453 let Inst{21} = 0; // 21 == W 454 let Inst{20} = opc20; 455 456 let Inst{7-4} = op; 457} 458 459 460 461 462class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin, 463 string opc, string asm, list<dag> pattern> 464 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 465 opc, asm, "", pattern> { 466 let Inst{20} = 1; // L bit 467 let Inst{21} = 0; // W bit 468 let Inst{22} = 0; // B bit 469 let Inst{24} = 1; // P bit 470 let Inst{27-26} = 0b01; 471} 472class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin, 473 string asm, list<dag> pattern> 474 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 475 asm, "", pattern> { 476 let Inst{20} = 1; // L bit 477 let Inst{21} = 0; // W bit 478 let Inst{22} = 0; // B bit 479 let Inst{24} = 1; // P bit 480 let Inst{27-26} = 0b01; 481} 482class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin, 483 string opc, string asm, list<dag> pattern> 484 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 485 opc, asm, "", pattern> { 486 let Inst{20} = 1; // L bit 487 let Inst{21} = 0; // W bit 488 let Inst{22} = 1; // B bit 489 let Inst{24} = 1; // P bit 490 let Inst{27-26} = 0b01; 491} 492class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin, 493 string asm, list<dag> pattern> 494 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 495 asm, "", pattern> { 496 let Inst{20} = 1; // L bit 497 let Inst{21} = 0; // W bit 498 let Inst{22} = 1; // B bit 499 let Inst{24} = 1; // P bit 500 let Inst{27-26} = 0b01; 501} 502 503// stores 504class AI2stw<dag oops, dag iops, Format f, InstrItinClass itin, 505 string opc, string asm, list<dag> pattern> 506 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 507 opc, asm, "", pattern> { 508 let Inst{20} = 0; // L bit 509 let Inst{21} = 0; // W bit 510 let Inst{22} = 0; // B bit 511 let Inst{24} = 1; // P bit 512 let Inst{27-26} = 0b01; 513} 514class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin, 515 string asm, list<dag> pattern> 516 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 517 asm, "", pattern> { 518 let Inst{20} = 0; // L bit 519 let Inst{21} = 0; // W bit 520 let Inst{22} = 0; // B bit 521 let Inst{24} = 1; // P bit 522 let Inst{27-26} = 0b01; 523} 524class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin, 525 string opc, string asm, list<dag> pattern> 526 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 527 opc, asm, "", pattern> { 528 let Inst{20} = 0; // L bit 529 let Inst{21} = 0; // W bit 530 let Inst{22} = 1; // B bit 531 let Inst{24} = 1; // P bit 532 let Inst{27-26} = 0b01; 533} 534class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin, 535 string asm, list<dag> pattern> 536 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, 537 asm, "", pattern> { 538 let Inst{20} = 0; // L bit 539 let Inst{21} = 0; // W bit 540 let Inst{22} = 1; // B bit 541 let Inst{24} = 1; // P bit 542 let Inst{27-26} = 0b01; 543} 544 545// Pre-indexed loads 546class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin, 547 string opc, string asm, string cstr, list<dag> pattern> 548 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 549 opc, asm, cstr, pattern> { 550 let Inst{20} = 1; // L bit 551 let Inst{21} = 1; // W bit 552 let Inst{22} = 0; // B bit 553 let Inst{24} = 1; // P bit 554 let Inst{27-26} = 0b01; 555} 556class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin, 557 string opc, string asm, string cstr, list<dag> pattern> 558 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 559 opc, asm, cstr, pattern> { 560 let Inst{20} = 1; // L bit 561 let Inst{21} = 1; // W bit 562 let Inst{22} = 1; // B bit 563 let Inst{24} = 1; // P bit 564 let Inst{27-26} = 0b01; 565} 566 567// Pre-indexed stores 568class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin, 569 string opc, string asm, string cstr, list<dag> pattern> 570 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 571 opc, asm, cstr, pattern> { 572 let Inst{20} = 0; // L bit 573 let Inst{21} = 1; // W bit 574 let Inst{22} = 0; // B bit 575 let Inst{24} = 1; // P bit 576 let Inst{27-26} = 0b01; 577} 578class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin, 579 string opc, string asm, string cstr, list<dag> pattern> 580 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin, 581 opc, asm, cstr, pattern> { 582 let Inst{20} = 0; // L bit 583 let Inst{21} = 1; // W bit 584 let Inst{22} = 1; // B bit 585 let Inst{24} = 1; // P bit 586 let Inst{27-26} = 0b01; 587} 588 589// Post-indexed loads 590class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin, 591 string opc, string asm, string cstr, list<dag> pattern> 592 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 593 opc, asm, cstr,pattern> { 594 let Inst{20} = 1; // L bit 595 let Inst{21} = 0; // W bit 596 let Inst{22} = 0; // B bit 597 let Inst{24} = 0; // P bit 598 let Inst{27-26} = 0b01; 599} 600class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin, 601 string opc, string asm, string cstr, list<dag> pattern> 602 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 603 opc, asm, cstr,pattern> { 604 let Inst{20} = 1; // L bit 605 let Inst{21} = 0; // W bit 606 let Inst{22} = 1; // B bit 607 let Inst{24} = 0; // P bit 608 let Inst{27-26} = 0b01; 609} 610 611// Post-indexed stores 612class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin, 613 string opc, string asm, string cstr, list<dag> pattern> 614 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 615 opc, asm, cstr,pattern> { 616 let Inst{20} = 0; // L bit 617 let Inst{21} = 0; // W bit 618 let Inst{22} = 0; // B bit 619 let Inst{24} = 0; // P bit 620 let Inst{27-26} = 0b01; 621} 622class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin, 623 string opc, string asm, string cstr, list<dag> pattern> 624 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin, 625 opc, asm, cstr,pattern> { 626 let Inst{20} = 0; // L bit 627 let Inst{21} = 0; // W bit 628 let Inst{22} = 1; // B bit 629 let Inst{24} = 0; // P bit 630 let Inst{27-26} = 0b01; 631} 632 633// addrmode3 instructions 634class AI3<dag oops, dag iops, Format f, InstrItinClass itin, 635 string opc, string asm, list<dag> pattern> 636 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 637 opc, asm, "", pattern>; 638class AXI3<dag oops, dag iops, Format f, InstrItinClass itin, 639 string asm, list<dag> pattern> 640 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 641 asm, "", pattern>; 642 643// loads 644class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin, 645 string opc, string asm, list<dag> pattern> 646 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 647 opc, asm, "", pattern> { 648 let Inst{4} = 1; 649 let Inst{5} = 1; // H bit 650 let Inst{6} = 0; // S bit 651 let Inst{7} = 1; 652 let Inst{20} = 1; // L bit 653 let Inst{21} = 0; // W bit 654 let Inst{24} = 1; // P bit 655 let Inst{27-25} = 0b000; 656} 657class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin, 658 string asm, list<dag> pattern> 659 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 660 asm, "", pattern> { 661 let Inst{4} = 1; 662 let Inst{5} = 1; // H bit 663 let Inst{6} = 0; // S bit 664 let Inst{7} = 1; 665 let Inst{20} = 1; // L bit 666 let Inst{21} = 0; // W bit 667 let Inst{24} = 1; // P bit 668} 669class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin, 670 string opc, string asm, list<dag> pattern> 671 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 672 opc, asm, "", pattern> { 673 let Inst{4} = 1; 674 let Inst{5} = 1; // H bit 675 let Inst{6} = 1; // S bit 676 let Inst{7} = 1; 677 let Inst{20} = 1; // L bit 678 let Inst{21} = 0; // W bit 679 let Inst{24} = 1; // P bit 680 let Inst{27-25} = 0b000; 681} 682class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin, 683 string asm, list<dag> pattern> 684 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 685 asm, "", pattern> { 686 let Inst{4} = 1; 687 let Inst{5} = 1; // H bit 688 let Inst{6} = 1; // S bit 689 let Inst{7} = 1; 690 let Inst{20} = 1; // L bit 691 let Inst{21} = 0; // W bit 692 let Inst{24} = 1; // P bit 693} 694class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin, 695 string opc, string asm, list<dag> pattern> 696 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 697 opc, asm, "", pattern> { 698 let Inst{4} = 1; 699 let Inst{5} = 0; // H bit 700 let Inst{6} = 1; // S bit 701 let Inst{7} = 1; 702 let Inst{20} = 1; // L bit 703 let Inst{21} = 0; // W bit 704 let Inst{24} = 1; // P bit 705 let Inst{27-25} = 0b000; 706} 707class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin, 708 string asm, list<dag> pattern> 709 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 710 asm, "", pattern> { 711 let Inst{4} = 1; 712 let Inst{5} = 0; // H bit 713 let Inst{6} = 1; // S bit 714 let Inst{7} = 1; 715 let Inst{20} = 1; // L bit 716 let Inst{21} = 0; // W bit 717 let Inst{24} = 1; // P bit 718} 719class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin, 720 string opc, string asm, list<dag> pattern> 721 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 722 opc, asm, "", pattern> { 723 let Inst{4} = 1; 724 let Inst{5} = 0; // H bit 725 let Inst{6} = 1; // S bit 726 let Inst{7} = 1; 727 let Inst{20} = 0; // L bit 728 let Inst{21} = 0; // W bit 729 let Inst{24} = 1; // P bit 730 let Inst{27-25} = 0b000; 731} 732 733// stores 734class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin, 735 string opc, string asm, list<dag> pattern> 736 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 737 opc, asm, "", pattern> { 738 let Inst{4} = 1; 739 let Inst{5} = 1; // H bit 740 let Inst{6} = 0; // S bit 741 let Inst{7} = 1; 742 let Inst{20} = 0; // L bit 743 let Inst{21} = 0; // W bit 744 let Inst{24} = 1; // P bit 745 let Inst{27-25} = 0b000; 746} 747class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin, 748 string asm, list<dag> pattern> 749 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 750 asm, "", pattern> { 751 let Inst{4} = 1; 752 let Inst{5} = 1; // H bit 753 let Inst{6} = 0; // S bit 754 let Inst{7} = 1; 755 let Inst{20} = 0; // L bit 756 let Inst{21} = 0; // W bit 757 let Inst{24} = 1; // P bit 758} 759class AI3std<dag oops, dag iops, Format f, InstrItinClass itin, 760 string opc, string asm, list<dag> pattern> 761 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, 762 opc, asm, "", pattern> { 763 let Inst{4} = 1; 764 let Inst{5} = 1; // H bit 765 let Inst{6} = 1; // S bit 766 let Inst{7} = 1; 767 let Inst{20} = 0; // L bit 768 let Inst{21} = 0; // W bit 769 let Inst{24} = 1; // P bit 770 let Inst{27-25} = 0b000; 771} 772 773// Pre-indexed loads 774class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin, 775 string opc, string asm, string cstr, list<dag> pattern> 776 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 777 opc, asm, cstr, pattern> { 778 let Inst{4} = 1; 779 let Inst{5} = 1; // H bit 780 let Inst{6} = 0; // S bit 781 let Inst{7} = 1; 782 let Inst{20} = 1; // L bit 783 let Inst{21} = 1; // W bit 784 let Inst{24} = 1; // P bit 785 let Inst{27-25} = 0b000; 786} 787class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin, 788 string opc, string asm, string cstr, list<dag> pattern> 789 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 790 opc, asm, cstr, pattern> { 791 let Inst{4} = 1; 792 let Inst{5} = 1; // H bit 793 let Inst{6} = 1; // S bit 794 let Inst{7} = 1; 795 let Inst{20} = 1; // L bit 796 let Inst{21} = 1; // W bit 797 let Inst{24} = 1; // P bit 798 let Inst{27-25} = 0b000; 799} 800class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin, 801 string opc, string asm, string cstr, list<dag> pattern> 802 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 803 opc, asm, cstr, pattern> { 804 let Inst{4} = 1; 805 let Inst{5} = 0; // H bit 806 let Inst{6} = 1; // S bit 807 let Inst{7} = 1; 808 let Inst{20} = 1; // L bit 809 let Inst{21} = 1; // W bit 810 let Inst{24} = 1; // P bit 811 let Inst{27-25} = 0b000; 812} 813class AI3lddpr<dag oops, dag iops, Format f, InstrItinClass itin, 814 string opc, string asm, string cstr, list<dag> pattern> 815 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 816 opc, asm, cstr, pattern> { 817 let Inst{4} = 1; 818 let Inst{5} = 0; // H bit 819 let Inst{6} = 1; // S bit 820 let Inst{7} = 1; 821 let Inst{20} = 0; // L bit 822 let Inst{21} = 1; // W bit 823 let Inst{24} = 1; // P bit 824 let Inst{27-25} = 0b000; 825} 826 827 828// Pre-indexed stores 829class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin, 830 string opc, string asm, string cstr, list<dag> pattern> 831 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 832 opc, asm, cstr, pattern> { 833 let Inst{4} = 1; 834 let Inst{5} = 1; // H bit 835 let Inst{6} = 0; // S bit 836 let Inst{7} = 1; 837 let Inst{20} = 0; // L bit 838 let Inst{21} = 1; // W bit 839 let Inst{24} = 1; // P bit 840 let Inst{27-25} = 0b000; 841} 842class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin, 843 string opc, string asm, string cstr, list<dag> pattern> 844 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin, 845 opc, asm, cstr, pattern> { 846 let Inst{4} = 1; 847 let Inst{5} = 1; // H bit 848 let Inst{6} = 1; // S bit 849 let Inst{7} = 1; 850 let Inst{20} = 0; // L bit 851 let Inst{21} = 1; // W bit 852 let Inst{24} = 1; // P bit 853 let Inst{27-25} = 0b000; 854} 855 856// Post-indexed loads 857class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin, 858 string opc, string asm, string cstr, list<dag> pattern> 859 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 860 opc, asm, cstr,pattern> { 861 let Inst{4} = 1; 862 let Inst{5} = 1; // H bit 863 let Inst{6} = 0; // S bit 864 let Inst{7} = 1; 865 let Inst{20} = 1; // L bit 866 let Inst{21} = 0; // W bit 867 let Inst{24} = 0; // P bit 868 let Inst{27-25} = 0b000; 869} 870class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin, 871 string opc, string asm, string cstr, list<dag> pattern> 872 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 873 opc, asm, cstr,pattern> { 874 let Inst{4} = 1; 875 let Inst{5} = 1; // H bit 876 let Inst{6} = 1; // S bit 877 let Inst{7} = 1; 878 let Inst{20} = 1; // L bit 879 let Inst{21} = 0; // W bit 880 let Inst{24} = 0; // P bit 881 let Inst{27-25} = 0b000; 882} 883class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin, 884 string opc, string asm, string cstr, list<dag> pattern> 885 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 886 opc, asm, cstr,pattern> { 887 let Inst{4} = 1; 888 let Inst{5} = 0; // H bit 889 let Inst{6} = 1; // S bit 890 let Inst{7} = 1; 891 let Inst{20} = 1; // L bit 892 let Inst{21} = 0; // W bit 893 let Inst{24} = 0; // P bit 894 let Inst{27-25} = 0b000; 895} 896class AI3lddpo<dag oops, dag iops, Format f, InstrItinClass itin, 897 string opc, string asm, string cstr, list<dag> pattern> 898 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 899 opc, asm, cstr, pattern> { 900 let Inst{4} = 1; 901 let Inst{5} = 0; // H bit 902 let Inst{6} = 1; // S bit 903 let Inst{7} = 1; 904 let Inst{20} = 0; // L bit 905 let Inst{21} = 0; // W bit 906 let Inst{24} = 0; // P bit 907 let Inst{27-25} = 0b000; 908} 909 910// Post-indexed stores 911class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin, 912 string opc, string asm, string cstr, list<dag> pattern> 913 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 914 opc, asm, cstr,pattern> { 915 let Inst{4} = 1; 916 let Inst{5} = 1; // H bit 917 let Inst{6} = 0; // S bit 918 let Inst{7} = 1; 919 let Inst{20} = 0; // L bit 920 let Inst{21} = 0; // W bit 921 let Inst{24} = 0; // P bit 922 let Inst{27-25} = 0b000; 923} 924class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin, 925 string opc, string asm, string cstr, list<dag> pattern> 926 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin, 927 opc, asm, cstr, pattern> { 928 let Inst{4} = 1; 929 let Inst{5} = 1; // H bit 930 let Inst{6} = 1; // S bit 931 let Inst{7} = 1; 932 let Inst{20} = 0; // L bit 933 let Inst{21} = 0; // W bit 934 let Inst{24} = 0; // P bit 935 let Inst{27-25} = 0b000; 936} 937 938// addrmode4 instructions 939class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 940 string asm, string cstr, list<dag> pattern> 941 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, 942 asm, cstr, pattern> { 943 bits<16> dsts; 944 bits<4> Rn; 945 let Inst{27-25} = 0b100; 946 let Inst{22} = 0; // S bit 947 let Inst{20} = 1; // L bit 948 let Inst{19-16} = Rn; 949 let Inst{15-0} = dsts; 950} 951class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 952 string asm, string cstr, list<dag> pattern> 953 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, 954 asm, cstr, pattern> { 955 bits<16> srcs; 956 let Inst{20} = 0; // L bit 957 let Inst{22} = 0; // S bit 958 let Inst{27-25} = 0b100; 959 let Inst{15-0} = srcs; 960} 961 962// Unsigned multiply, multiply-accumulate instructions. 963class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 964 string opc, string asm, list<dag> pattern> 965 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 966 opc, asm, "", pattern> { 967 let Inst{7-4} = 0b1001; 968 let Inst{20} = 0; // S bit 969 let Inst{27-21} = opcod; 970} 971class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 972 string opc, string asm, list<dag> pattern> 973 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 974 opc, asm, "", pattern> { 975 let Inst{7-4} = 0b1001; 976 let Inst{27-21} = opcod; 977} 978 979// Most significant word multiply 980class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 981 InstrItinClass itin, string opc, string asm, list<dag> pattern> 982 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 983 opc, asm, "", pattern> { 984 bits<4> Rd; 985 bits<4> Rn; 986 bits<4> Rm; 987 let Inst{7-4} = opc7_4; 988 let Inst{20} = 1; 989 let Inst{27-21} = opcod; 990 let Inst{19-16} = Rd; 991 let Inst{11-8} = Rm; 992 let Inst{3-0} = Rn; 993} 994// MSW multiple w/ Ra operand 995class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 996 InstrItinClass itin, string opc, string asm, list<dag> pattern> 997 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> { 998 bits<4> Ra; 999 let Inst{15-12} = Ra; 1000} 1001 1002// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 1003class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 1004 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1005 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin, 1006 opc, asm, "", pattern> { 1007 bits<4> Rn; 1008 bits<4> Rm; 1009 let Inst{4} = 0; 1010 let Inst{7} = 1; 1011 let Inst{20} = 0; 1012 let Inst{27-21} = opcod; 1013 let Inst{6-5} = bit6_5; 1014 let Inst{11-8} = Rm; 1015 let Inst{3-0} = Rn; 1016} 1017class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 1018 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1019 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 1020 bits<4> Rd; 1021 let Inst{19-16} = Rd; 1022} 1023 1024// AMulxyI with Ra operand 1025class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 1026 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1027 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 1028 bits<4> Ra; 1029 let Inst{15-12} = Ra; 1030} 1031// SMLAL* 1032class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 1033 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1034 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 1035 bits<4> RdLo; 1036 bits<4> RdHi; 1037 let Inst{19-16} = RdHi; 1038 let Inst{15-12} = RdLo; 1039} 1040 1041// Extend instructions. 1042class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 1043 string opc, string asm, list<dag> pattern> 1044 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin, 1045 opc, asm, "", pattern> { 1046 // All AExtI instructions have Rd and Rm register operands. 1047 bits<4> Rd; 1048 bits<4> Rm; 1049 let Inst{15-12} = Rd; 1050 let Inst{3-0} = Rm; 1051 let Inst{7-4} = 0b0111; 1052 let Inst{9-8} = 0b00; 1053 let Inst{27-20} = opcod; 1054} 1055 1056// Misc Arithmetic instructions. 1057class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops, 1058 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1059 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 1060 opc, asm, "", pattern> { 1061 bits<4> Rd; 1062 bits<4> Rm; 1063 let Inst{27-20} = opcod; 1064 let Inst{19-16} = 0b1111; 1065 let Inst{15-12} = Rd; 1066 let Inst{11-8} = 0b1111; 1067 let Inst{7-4} = opc7_4; 1068 let Inst{3-0} = Rm; 1069} 1070 1071// PKH instructions 1072class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin, 1073 string opc, string asm, list<dag> pattern> 1074 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin, 1075 opc, asm, "", pattern> { 1076 bits<4> Rd; 1077 bits<4> Rn; 1078 bits<4> Rm; 1079 bits<8> sh; 1080 let Inst{27-20} = opcod; 1081 let Inst{19-16} = Rn; 1082 let Inst{15-12} = Rd; 1083 let Inst{11-7} = sh{7-3}; 1084 let Inst{6} = tb; 1085 let Inst{5-4} = 0b01; 1086 let Inst{3-0} = Rm; 1087} 1088 1089//===----------------------------------------------------------------------===// 1090 1091// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 1092class ARMPat<dag pattern, dag result> : Pat<pattern, result> { 1093 list<Predicate> Predicates = [IsARM]; 1094} 1095class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 1096 list<Predicate> Predicates = [IsARM, HasV5TE]; 1097} 1098class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 1099 list<Predicate> Predicates = [IsARM, HasV6]; 1100} 1101 1102//===----------------------------------------------------------------------===// 1103// 1104// Thumb Instruction Format Definitions. 1105// 1106 1107// TI - Thumb instruction. 1108 1109class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1110 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 1111 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1112 let OutOperandList = oops; 1113 let InOperandList = iops; 1114 let AsmString = asm; 1115 let Pattern = pattern; 1116 list<Predicate> Predicates = [IsThumb]; 1117} 1118 1119class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 1120 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 1121 1122// Two-address instructions 1123class TIt<dag oops, dag iops, InstrItinClass itin, string asm, 1124 list<dag> pattern> 1125 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", 1126 pattern>; 1127 1128// tBL, tBX 32-bit instructions 1129class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 1130 dag oops, dag iops, InstrItinClass itin, string asm, 1131 list<dag> pattern> 1132 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, 1133 Encoding { 1134 let Inst{31-27} = opcod1; 1135 let Inst{15-14} = opcod2; 1136 let Inst{12} = opcod3; 1137} 1138 1139// BR_JT instructions 1140class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, 1141 list<dag> pattern> 1142 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 1143 1144// Thumb1 only 1145class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1146 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 1147 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1148 let OutOperandList = oops; 1149 let InOperandList = iops; 1150 let AsmString = asm; 1151 let Pattern = pattern; 1152 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1153} 1154 1155class T1I<dag oops, dag iops, InstrItinClass itin, 1156 string asm, list<dag> pattern> 1157 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>; 1158class T1Ix2<dag oops, dag iops, InstrItinClass itin, 1159 string asm, list<dag> pattern> 1160 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 1161class T1JTI<dag oops, dag iops, InstrItinClass itin, 1162 string asm, list<dag> pattern> 1163 : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 1164 1165// Two-address instructions 1166class T1It<dag oops, dag iops, InstrItinClass itin, 1167 string asm, string cstr, list<dag> pattern> 1168 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, 1169 asm, cstr, pattern>; 1170 1171// Thumb1 instruction that can either be predicated or set CPSR. 1172class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1173 InstrItinClass itin, 1174 string opc, string asm, string cstr, list<dag> pattern> 1175 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1176 let OutOperandList = !con(oops, (outs s_cc_out:$s)); 1177 let InOperandList = !con(iops, (ins pred:$p)); 1178 let AsmString = !strconcat(opc, "${s}${p}", asm); 1179 let Pattern = pattern; 1180 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1181} 1182 1183class T1sI<dag oops, dag iops, InstrItinClass itin, 1184 string opc, string asm, list<dag> pattern> 1185 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 1186 1187// Two-address instructions 1188class T1sIt<dag oops, dag iops, InstrItinClass itin, 1189 string opc, string asm, list<dag> pattern> 1190 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 1191 "$lhs = $dst", pattern>; 1192 1193// Thumb1 instruction that can be predicated. 1194class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1195 InstrItinClass itin, 1196 string opc, string asm, string cstr, list<dag> pattern> 1197 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1198 let OutOperandList = oops; 1199 let InOperandList = !con(iops, (ins pred:$p)); 1200 let AsmString = !strconcat(opc, "${p}", asm); 1201 let Pattern = pattern; 1202 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1203} 1204 1205class T1pI<dag oops, dag iops, InstrItinClass itin, 1206 string opc, string asm, list<dag> pattern> 1207 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>; 1208 1209// Two-address instructions 1210class T1pIt<dag oops, dag iops, InstrItinClass itin, 1211 string opc, string asm, list<dag> pattern> 1212 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, 1213 "$lhs = $dst", pattern>; 1214 1215class T1pI1<dag oops, dag iops, InstrItinClass itin, 1216 string opc, string asm, list<dag> pattern> 1217 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>; 1218class T1pI2<dag oops, dag iops, InstrItinClass itin, 1219 string opc, string asm, list<dag> pattern> 1220 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>; 1221class T1pI4<dag oops, dag iops, InstrItinClass itin, 1222 string opc, string asm, list<dag> pattern> 1223 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>; 1224class T1pIs<dag oops, dag iops, 1225 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1226 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>; 1227 1228class Encoding16 : Encoding { 1229 let Inst{31-16} = 0x0000; 1230} 1231 1232// A6.2 16-bit Thumb instruction encoding 1233class T1Encoding<bits<6> opcode> : Encoding16 { 1234 let Inst{15-10} = opcode; 1235} 1236 1237// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 1238class T1General<bits<5> opcode> : Encoding16 { 1239 let Inst{15-14} = 0b00; 1240 let Inst{13-9} = opcode; 1241} 1242 1243// A6.2.2 Data-processing encoding. 1244class T1DataProcessing<bits<4> opcode> : Encoding16 { 1245 let Inst{15-10} = 0b010000; 1246 let Inst{9-6} = opcode; 1247} 1248 1249// A6.2.3 Special data instructions and branch and exchange encoding. 1250class T1Special<bits<4> opcode> : Encoding16 { 1251 let Inst{15-10} = 0b010001; 1252 let Inst{9-6} = opcode; 1253} 1254 1255// A6.2.4 Load/store single data item encoding. 1256class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 1257 let Inst{15-12} = opA; 1258 let Inst{11-9} = opB; 1259} 1260class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>; 1261class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes 1262class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte 1263class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes 1264class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 1265 1266// A6.2.5 Miscellaneous 16-bit instructions encoding. 1267class T1Misc<bits<7> opcode> : Encoding16 { 1268 let Inst{15-12} = 0b1011; 1269 let Inst{11-5} = opcode; 1270} 1271 1272// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 1273class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1274 InstrItinClass itin, 1275 string opc, string asm, string cstr, list<dag> pattern> 1276 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1277 let OutOperandList = oops; 1278 let InOperandList = !con(iops, (ins pred:$p)); 1279 let AsmString = !strconcat(opc, "${p}", asm); 1280 let Pattern = pattern; 1281 list<Predicate> Predicates = [IsThumb2]; 1282} 1283 1284// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an 1285// input operand since by default it's a zero register. It will become an 1286// implicit def once it's "flipped". 1287// 1288// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1289// more consistent. 1290class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1291 InstrItinClass itin, 1292 string opc, string asm, string cstr, list<dag> pattern> 1293 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1294 let OutOperandList = oops; 1295 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 1296 let AsmString = !strconcat(opc, "${s}${p}", asm); 1297 let Pattern = pattern; 1298 list<Predicate> Predicates = [IsThumb2]; 1299} 1300 1301// Special cases 1302class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1303 InstrItinClass itin, 1304 string asm, string cstr, list<dag> pattern> 1305 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1306 let OutOperandList = oops; 1307 let InOperandList = iops; 1308 let AsmString = asm; 1309 let Pattern = pattern; 1310 list<Predicate> Predicates = [IsThumb2]; 1311} 1312 1313class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1314 InstrItinClass itin, 1315 string asm, string cstr, list<dag> pattern> 1316 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1317 let OutOperandList = oops; 1318 let InOperandList = iops; 1319 let AsmString = asm; 1320 let Pattern = pattern; 1321 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1322} 1323 1324class T2I<dag oops, dag iops, InstrItinClass itin, 1325 string opc, string asm, list<dag> pattern> 1326 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1327class T2Ii12<dag oops, dag iops, InstrItinClass itin, 1328 string opc, string asm, list<dag> pattern> 1329 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>; 1330class T2Ii8<dag oops, dag iops, InstrItinClass itin, 1331 string opc, string asm, list<dag> pattern> 1332 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>; 1333class T2Iso<dag oops, dag iops, InstrItinClass itin, 1334 string opc, string asm, list<dag> pattern> 1335 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>; 1336class T2Ipc<dag oops, dag iops, InstrItinClass itin, 1337 string opc, string asm, list<dag> pattern> 1338 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>; 1339class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin, 1340 string opc, string asm, list<dag> pattern> 1341 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "", 1342 pattern> { 1343 let Inst{31-27} = 0b11101; 1344 let Inst{26-25} = 0b00; 1345 let Inst{24} = P; 1346 let Inst{23} = ?; // The U bit. 1347 let Inst{22} = 1; 1348 let Inst{21} = W; 1349 let Inst{20} = load; 1350} 1351 1352class T2sI<dag oops, dag iops, InstrItinClass itin, 1353 string opc, string asm, list<dag> pattern> 1354 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>; 1355 1356class T2XI<dag oops, dag iops, InstrItinClass itin, 1357 string asm, list<dag> pattern> 1358 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>; 1359class T2JTI<dag oops, dag iops, InstrItinClass itin, 1360 string asm, list<dag> pattern> 1361 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>; 1362 1363class T2Ix2<dag oops, dag iops, InstrItinClass itin, 1364 string opc, string asm, list<dag> pattern> 1365 : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>; 1366 1367// Two-address instructions 1368class T2XIt<dag oops, dag iops, InstrItinClass itin, 1369 string asm, string cstr, list<dag> pattern> 1370 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>; 1371 1372// T2Iidxldst - Thumb2 indexed load / store instructions. 1373class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre, 1374 dag oops, dag iops, 1375 AddrMode am, IndexMode im, InstrItinClass itin, 1376 string opc, string asm, string cstr, list<dag> pattern> 1377 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> { 1378 let OutOperandList = oops; 1379 let InOperandList = !con(iops, (ins pred:$p)); 1380 let AsmString = !strconcat(opc, "${p}", asm); 1381 let Pattern = pattern; 1382 list<Predicate> Predicates = [IsThumb2]; 1383 let Inst{31-27} = 0b11111; 1384 let Inst{26-25} = 0b00; 1385 let Inst{24} = signed; 1386 let Inst{23} = 0; 1387 let Inst{22-21} = opcod; 1388 let Inst{20} = load; 1389 let Inst{11} = 1; 1390 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1391 let Inst{10} = pre; // The P bit. 1392 let Inst{8} = 1; // The W bit. 1393} 1394 1395// Helper class for disassembly only 1396// A6.3.16 & A6.3.17 1397// T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions. 1398class T2I_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, dag iops, 1399 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1400 : T2I<oops, iops, itin, opc, asm, pattern> { 1401 let Inst{31-27} = 0b11111; 1402 let Inst{26-24} = 0b011; 1403 let Inst{23} = long; 1404 let Inst{22-20} = op22_20; 1405 let Inst{7-4} = op7_4; 1406} 1407 1408// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1409class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1410 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T]; 1411} 1412 1413// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1414class T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1415 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1416} 1417 1418// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1419class T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1420 list<Predicate> Predicates = [IsThumb2]; 1421} 1422 1423//===----------------------------------------------------------------------===// 1424 1425//===----------------------------------------------------------------------===// 1426// ARM VFP Instruction templates. 1427// 1428 1429// Almost all VFP instructions are predicable. 1430class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1431 IndexMode im, Format f, InstrItinClass itin, 1432 string opc, string asm, string cstr, list<dag> pattern> 1433 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1434 bits<4> p; 1435 let Inst{31-28} = p; 1436 let OutOperandList = oops; 1437 let InOperandList = !con(iops, (ins pred:$p)); 1438 let AsmString = !strconcat(opc, "${p}", asm); 1439 let Pattern = pattern; 1440 list<Predicate> Predicates = [HasVFP2]; 1441} 1442 1443// Special cases 1444class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 1445 IndexMode im, Format f, InstrItinClass itin, 1446 string asm, string cstr, list<dag> pattern> 1447 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1448 let OutOperandList = oops; 1449 let InOperandList = iops; 1450 let AsmString = asm; 1451 let Pattern = pattern; 1452 list<Predicate> Predicates = [HasVFP2]; 1453} 1454 1455class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1456 string opc, string asm, list<dag> pattern> 1457 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin, 1458 opc, asm, "", pattern>; 1459 1460// ARM VFP addrmode5 loads and stores 1461class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1462 InstrItinClass itin, 1463 string opc, string asm, list<dag> pattern> 1464 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1465 VFPLdStFrm, itin, opc, asm, "", pattern> { 1466 // Instruction operands. 1467 bits<5> Dd; 1468 bits<13> addr; 1469 1470 // Encode instruction operands. 1471 let Inst{23} = addr{8}; // U (add = (U == '1')) 1472 let Inst{22} = Dd{4}; 1473 let Inst{19-16} = addr{12-9}; // Rn 1474 let Inst{15-12} = Dd{3-0}; 1475 let Inst{7-0} = addr{7-0}; // imm8 1476 1477 // TODO: Mark the instructions with the appropriate subtarget info. 1478 let Inst{27-24} = opcod1; 1479 let Inst{21-20} = opcod2; 1480 let Inst{11-9} = 0b101; 1481 let Inst{8} = 1; // Double precision 1482 1483 // 64-bit loads & stores operate on both NEON and VFP pipelines. 1484 let D = VFPNeonDomain; 1485} 1486 1487class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1488 InstrItinClass itin, 1489 string opc, string asm, list<dag> pattern> 1490 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1491 VFPLdStFrm, itin, opc, asm, "", pattern> { 1492 // Instruction operands. 1493 bits<5> Sd; 1494 bits<13> addr; 1495 1496 // Encode instruction operands. 1497 let Inst{23} = addr{8}; // U (add = (U == '1')) 1498 let Inst{22} = Sd{0}; 1499 let Inst{19-16} = addr{12-9}; // Rn 1500 let Inst{15-12} = Sd{4-1}; 1501 let Inst{7-0} = addr{7-0}; // imm8 1502 1503 // TODO: Mark the instructions with the appropriate subtarget info. 1504 let Inst{27-24} = opcod1; 1505 let Inst{21-20} = opcod2; 1506 let Inst{11-9} = 0b101; 1507 let Inst{8} = 0; // Single precision 1508} 1509 1510// VFP Load / store multiple pseudo instructions. 1511class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr, 1512 list<dag> pattern> 1513 : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain, 1514 cstr, itin> { 1515 let OutOperandList = oops; 1516 let InOperandList = !con(iops, (ins pred:$p)); 1517 let Pattern = pattern; 1518 list<Predicate> Predicates = [HasVFP2]; 1519} 1520 1521// Load / store multiple 1522class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1523 string asm, string cstr, list<dag> pattern> 1524 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im, 1525 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1526 // TODO: Mark the instructions with the appropriate subtarget info. 1527 let Inst{27-25} = 0b110; 1528 let Inst{11-9} = 0b101; 1529 let Inst{8} = 1; // Double precision 1530 1531 // 64-bit loads & stores operate on both NEON and VFP pipelines. 1532 let D = VFPNeonDomain; 1533} 1534 1535class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1536 string asm, string cstr, list<dag> pattern> 1537 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im, 1538 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1539 // TODO: Mark the instructions with the appropriate subtarget info. 1540 let Inst{27-25} = 0b110; 1541 let Inst{11-9} = 0b101; 1542 let Inst{8} = 0; // Single precision 1543} 1544 1545// Double precision, unary 1546class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1547 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1548 string asm, list<dag> pattern> 1549 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1550 // Instruction operands. 1551 bits<5> Dd; 1552 bits<5> Dm; 1553 1554 // Encode instruction operands. 1555 let Inst{3-0} = Dm{3-0}; 1556 let Inst{5} = Dm{4}; 1557 let Inst{15-12} = Dd{3-0}; 1558 let Inst{22} = Dd{4}; 1559 1560 let Inst{27-23} = opcod1; 1561 let Inst{21-20} = opcod2; 1562 let Inst{19-16} = opcod3; 1563 let Inst{11-9} = 0b101; 1564 let Inst{8} = 1; // Double precision 1565 let Inst{7-6} = opcod4; 1566 let Inst{4} = opcod5; 1567} 1568 1569// Double precision, binary 1570class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1571 dag iops, InstrItinClass itin, string opc, string asm, 1572 list<dag> pattern> 1573 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1574 // Instruction operands. 1575 bits<5> Dd; 1576 bits<5> Dn; 1577 bits<5> Dm; 1578 1579 // Encode instruction operands. 1580 let Inst{3-0} = Dm{3-0}; 1581 let Inst{5} = Dm{4}; 1582 let Inst{19-16} = Dn{3-0}; 1583 let Inst{7} = Dn{4}; 1584 let Inst{15-12} = Dd{3-0}; 1585 let Inst{22} = Dd{4}; 1586 1587 let Inst{27-23} = opcod1; 1588 let Inst{21-20} = opcod2; 1589 let Inst{11-9} = 0b101; 1590 let Inst{8} = 1; // Double precision 1591 let Inst{6} = op6; 1592 let Inst{4} = op4; 1593} 1594 1595// Double precision, binary, VML[AS] (for additional predicate) 1596class ADbI_vmlX<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1597 dag iops, InstrItinClass itin, string opc, string asm, 1598 list<dag> pattern> 1599 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1600 // Instruction operands. 1601 bits<5> Dd; 1602 bits<5> Dn; 1603 bits<5> Dm; 1604 1605 // Encode instruction operands. 1606 let Inst{19-16} = Dn{3-0}; 1607 let Inst{7} = Dn{4}; 1608 let Inst{15-12} = Dd{3-0}; 1609 let Inst{22} = Dd{4}; 1610 let Inst{3-0} = Dm{3-0}; 1611 let Inst{5} = Dm{4}; 1612 1613 let Inst{27-23} = opcod1; 1614 let Inst{21-20} = opcod2; 1615 let Inst{11-9} = 0b101; 1616 let Inst{8} = 1; // Double precision 1617 let Inst{6} = op6; 1618 let Inst{4} = op4; 1619 list<Predicate> Predicates = [HasVFP2, UseVMLx]; 1620} 1621 1622// Single precision, unary 1623class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1624 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1625 string asm, list<dag> pattern> 1626 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1627 // Instruction operands. 1628 bits<5> Sd; 1629 bits<5> Sm; 1630 1631 // Encode instruction operands. 1632 let Inst{3-0} = Sm{4-1}; 1633 let Inst{5} = Sm{0}; 1634 let Inst{15-12} = Sd{4-1}; 1635 let Inst{22} = Sd{0}; 1636 1637 let Inst{27-23} = opcod1; 1638 let Inst{21-20} = opcod2; 1639 let Inst{19-16} = opcod3; 1640 let Inst{11-9} = 0b101; 1641 let Inst{8} = 0; // Single precision 1642 let Inst{7-6} = opcod4; 1643 let Inst{4} = opcod5; 1644} 1645 1646// Single precision unary, if no NEON 1647// Same as ASuI except not available if NEON is enabled 1648class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1649 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1650 string asm, list<dag> pattern> 1651 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, 1652 pattern> { 1653 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1654} 1655 1656// Single precision, binary 1657class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1658 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1659 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1660 // Instruction operands. 1661 bits<5> Sd; 1662 bits<5> Sn; 1663 bits<5> Sm; 1664 1665 // Encode instruction operands. 1666 let Inst{3-0} = Sm{4-1}; 1667 let Inst{5} = Sm{0}; 1668 let Inst{19-16} = Sn{4-1}; 1669 let Inst{7} = Sn{0}; 1670 let Inst{15-12} = Sd{4-1}; 1671 let Inst{22} = Sd{0}; 1672 1673 let Inst{27-23} = opcod1; 1674 let Inst{21-20} = opcod2; 1675 let Inst{11-9} = 0b101; 1676 let Inst{8} = 0; // Single precision 1677 let Inst{6} = op6; 1678 let Inst{4} = op4; 1679} 1680 1681// Single precision binary, if no NEON 1682// Same as ASbI except not available if NEON is enabled 1683class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1684 dag iops, InstrItinClass itin, string opc, string asm, 1685 list<dag> pattern> 1686 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1687 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1688 1689 // Instruction operands. 1690 bits<5> Sd; 1691 bits<5> Sn; 1692 bits<5> Sm; 1693 1694 // Encode instruction operands. 1695 let Inst{3-0} = Sm{4-1}; 1696 let Inst{5} = Sm{0}; 1697 let Inst{19-16} = Sn{4-1}; 1698 let Inst{7} = Sn{0}; 1699 let Inst{15-12} = Sd{4-1}; 1700 let Inst{22} = Sd{0}; 1701} 1702 1703// VFP conversion instructions 1704class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1705 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1706 list<dag> pattern> 1707 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1708 let Inst{27-23} = opcod1; 1709 let Inst{21-20} = opcod2; 1710 let Inst{19-16} = opcod3; 1711 let Inst{11-8} = opcod4; 1712 let Inst{6} = 1; 1713 let Inst{4} = 0; 1714} 1715 1716// VFP conversion between floating-point and fixed-point 1717class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1718 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1719 list<dag> pattern> 1720 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1721 // size (fixed-point number): sx == 0 ? 16 : 32 1722 let Inst{7} = op5; // sx 1723} 1724 1725// VFP conversion instructions, if no NEON 1726class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1727 dag oops, dag iops, InstrItinClass itin, 1728 string opc, string asm, list<dag> pattern> 1729 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1730 pattern> { 1731 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1732} 1733 1734class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1735 InstrItinClass itin, 1736 string opc, string asm, list<dag> pattern> 1737 : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1738 let Inst{27-20} = opcod1; 1739 let Inst{11-8} = opcod2; 1740 let Inst{4} = 1; 1741} 1742 1743class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1744 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1745 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1746 1747class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1748 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1749 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1750 1751class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1752 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1753 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1754 1755class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1756 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1757 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1758 1759//===----------------------------------------------------------------------===// 1760 1761//===----------------------------------------------------------------------===// 1762// ARM NEON Instruction templates. 1763// 1764 1765class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1766 InstrItinClass itin, string opc, string dt, string asm, string cstr, 1767 list<dag> pattern> 1768 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> { 1769 let OutOperandList = oops; 1770 let InOperandList = !con(iops, (ins pred:$p)); 1771 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1772 let Pattern = pattern; 1773 list<Predicate> Predicates = [HasNEON]; 1774} 1775 1776// Same as NeonI except it does not have a "data type" specifier. 1777class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1778 InstrItinClass itin, string opc, string asm, string cstr, 1779 list<dag> pattern> 1780 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> { 1781 let OutOperandList = oops; 1782 let InOperandList = !con(iops, (ins pred:$p)); 1783 let AsmString = !strconcat(opc, "${p}", "\t", asm); 1784 let Pattern = pattern; 1785 list<Predicate> Predicates = [HasNEON]; 1786} 1787 1788class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1789 dag oops, dag iops, InstrItinClass itin, 1790 string opc, string dt, string asm, string cstr, list<dag> pattern> 1791 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm, 1792 cstr, pattern> { 1793 let Inst{31-24} = 0b11110100; 1794 let Inst{23} = op23; 1795 let Inst{21-20} = op21_20; 1796 let Inst{11-8} = op11_8; 1797 let Inst{7-4} = op7_4; 1798 1799 bits<5> Vd; 1800 bits<6> Rn; 1801 bits<4> Rm; 1802 1803 let Inst{22} = Vd{4}; 1804 let Inst{15-12} = Vd{3-0}; 1805 let Inst{19-16} = Rn{3-0}; 1806 let Inst{3-0} = Rm{3-0}; 1807} 1808 1809class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1810 dag oops, dag iops, InstrItinClass itin, 1811 string opc, string dt, string asm, string cstr, list<dag> pattern> 1812 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc, 1813 dt, asm, cstr, pattern> { 1814 bits<3> lane; 1815} 1816 1817class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr> 1818 : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr, 1819 itin> { 1820 let OutOperandList = oops; 1821 let InOperandList = !con(iops, (ins pred:$p)); 1822 list<Predicate> Predicates = [HasNEON]; 1823} 1824 1825class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr, 1826 list<dag> pattern> 1827 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr, 1828 itin> { 1829 let OutOperandList = oops; 1830 let InOperandList = !con(iops, (ins pred:$p)); 1831 let Pattern = pattern; 1832 list<Predicate> Predicates = [HasNEON]; 1833} 1834 1835class NDataI<dag oops, dag iops, Format f, InstrItinClass itin, 1836 string opc, string dt, string asm, string cstr, list<dag> pattern> 1837 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr, 1838 pattern> { 1839 let Inst{31-25} = 0b1111001; 1840} 1841 1842class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin, 1843 string opc, string asm, string cstr, list<dag> pattern> 1844 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm, 1845 cstr, pattern> { 1846 let Inst{31-25} = 0b1111001; 1847} 1848 1849// NEON "one register and a modified immediate" format. 1850class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1851 bit op5, bit op4, 1852 dag oops, dag iops, InstrItinClass itin, 1853 string opc, string dt, string asm, string cstr, 1854 list<dag> pattern> 1855 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> { 1856 let Inst{23} = op23; 1857 let Inst{21-19} = op21_19; 1858 let Inst{11-8} = op11_8; 1859 let Inst{7} = op7; 1860 let Inst{6} = op6; 1861 let Inst{5} = op5; 1862 let Inst{4} = op4; 1863 1864 // Instruction operands. 1865 bits<5> Vd; 1866 bits<13> SIMM; 1867 1868 let Inst{15-12} = Vd{3-0}; 1869 let Inst{22} = Vd{4}; 1870 let Inst{24} = SIMM{7}; 1871 let Inst{18-16} = SIMM{6-4}; 1872 let Inst{3-0} = SIMM{3-0}; 1873} 1874 1875// NEON 2 vector register format. 1876class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1877 bits<5> op11_7, bit op6, bit op4, 1878 dag oops, dag iops, InstrItinClass itin, 1879 string opc, string dt, string asm, string cstr, list<dag> pattern> 1880 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> { 1881 let Inst{24-23} = op24_23; 1882 let Inst{21-20} = op21_20; 1883 let Inst{19-18} = op19_18; 1884 let Inst{17-16} = op17_16; 1885 let Inst{11-7} = op11_7; 1886 let Inst{6} = op6; 1887 let Inst{4} = op4; 1888 1889 // Instruction operands. 1890 bits<5> Vd; 1891 bits<5> Vm; 1892 1893 let Inst{15-12} = Vd{3-0}; 1894 let Inst{22} = Vd{4}; 1895 let Inst{3-0} = Vm{3-0}; 1896 let Inst{5} = Vm{4}; 1897} 1898 1899// Same as N2V except it doesn't have a datatype suffix. 1900class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1901 bits<5> op11_7, bit op6, bit op4, 1902 dag oops, dag iops, InstrItinClass itin, 1903 string opc, string asm, string cstr, list<dag> pattern> 1904 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> { 1905 let Inst{24-23} = op24_23; 1906 let Inst{21-20} = op21_20; 1907 let Inst{19-18} = op19_18; 1908 let Inst{17-16} = op17_16; 1909 let Inst{11-7} = op11_7; 1910 let Inst{6} = op6; 1911 let Inst{4} = op4; 1912 1913 // Instruction operands. 1914 bits<5> Vd; 1915 bits<5> Vm; 1916 1917 let Inst{15-12} = Vd{3-0}; 1918 let Inst{22} = Vd{4}; 1919 let Inst{3-0} = Vm{3-0}; 1920 let Inst{5} = Vm{4}; 1921} 1922 1923// NEON 2 vector register with immediate. 1924class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1925 dag oops, dag iops, Format f, InstrItinClass itin, 1926 string opc, string dt, string asm, string cstr, list<dag> pattern> 1927 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1928 let Inst{24} = op24; 1929 let Inst{23} = op23; 1930 let Inst{11-8} = op11_8; 1931 let Inst{7} = op7; 1932 let Inst{6} = op6; 1933 let Inst{4} = op4; 1934 1935 // Instruction operands. 1936 bits<5> Vd; 1937 bits<5> Vm; 1938 bits<6> SIMM; 1939 1940 let Inst{15-12} = Vd{3-0}; 1941 let Inst{22} = Vd{4}; 1942 let Inst{3-0} = Vm{3-0}; 1943 let Inst{5} = Vm{4}; 1944 let Inst{21-16} = SIMM{5-0}; 1945} 1946 1947// NEON 3 vector register format. 1948class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1949 dag oops, dag iops, Format f, InstrItinClass itin, 1950 string opc, string dt, string asm, string cstr, list<dag> pattern> 1951 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1952 let Inst{24} = op24; 1953 let Inst{23} = op23; 1954 let Inst{21-20} = op21_20; 1955 let Inst{11-8} = op11_8; 1956 let Inst{6} = op6; 1957 let Inst{4} = op4; 1958 1959 // Instruction operands. 1960 bits<5> Vd; 1961 bits<5> Vn; 1962 bits<5> Vm; 1963 1964 let Inst{15-12} = Vd{3-0}; 1965 let Inst{22} = Vd{4}; 1966 let Inst{19-16} = Vn{3-0}; 1967 let Inst{7} = Vn{4}; 1968 let Inst{3-0} = Vm{3-0}; 1969 let Inst{5} = Vm{4}; 1970} 1971 1972// Same as N3V except it doesn't have a data type suffix. 1973class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1974 bit op4, 1975 dag oops, dag iops, Format f, InstrItinClass itin, 1976 string opc, string asm, string cstr, list<dag> pattern> 1977 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> { 1978 let Inst{24} = op24; 1979 let Inst{23} = op23; 1980 let Inst{21-20} = op21_20; 1981 let Inst{11-8} = op11_8; 1982 let Inst{6} = op6; 1983 let Inst{4} = op4; 1984 1985 // Instruction operands. 1986 bits<5> Vd; 1987 bits<5> Vn; 1988 bits<5> Vm; 1989 1990 let Inst{15-12} = Vd{3-0}; 1991 let Inst{22} = Vd{4}; 1992 let Inst{19-16} = Vn{3-0}; 1993 let Inst{7} = Vn{4}; 1994 let Inst{3-0} = Vm{3-0}; 1995 let Inst{5} = Vm{4}; 1996} 1997 1998// NEON VMOVs between scalar and core registers. 1999class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2000 dag oops, dag iops, Format f, InstrItinClass itin, 2001 string opc, string dt, string asm, list<dag> pattern> 2002 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain, 2003 "", itin> { 2004 let Inst{27-20} = opcod1; 2005 let Inst{11-8} = opcod2; 2006 let Inst{6-5} = opcod3; 2007 let Inst{4} = 1; 2008 2009 let OutOperandList = oops; 2010 let InOperandList = !con(iops, (ins pred:$p)); 2011 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 2012 let Pattern = pattern; 2013 list<Predicate> Predicates = [HasNEON]; 2014 2015 bits<5> V; 2016 bits<4> R; 2017 bits<4> p; 2018 bits<4> lane; 2019 2020 let Inst{31-28} = p{3-0}; 2021 let Inst{7} = V{4}; 2022 let Inst{19-16} = V{3-0}; 2023 let Inst{15-12} = R{3-0}; 2024} 2025class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2026 dag oops, dag iops, InstrItinClass itin, 2027 string opc, string dt, string asm, list<dag> pattern> 2028 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin, 2029 opc, dt, asm, pattern>; 2030class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2031 dag oops, dag iops, InstrItinClass itin, 2032 string opc, string dt, string asm, list<dag> pattern> 2033 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin, 2034 opc, dt, asm, pattern>; 2035class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 2036 dag oops, dag iops, InstrItinClass itin, 2037 string opc, string dt, string asm, list<dag> pattern> 2038 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin, 2039 opc, dt, asm, pattern>; 2040 2041// Vector Duplicate Lane (from scalar to all elements) 2042class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops, 2043 InstrItinClass itin, string opc, string dt, string asm, 2044 list<dag> pattern> 2045 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> { 2046 let Inst{24-23} = 0b11; 2047 let Inst{21-20} = 0b11; 2048 let Inst{19-16} = op19_16; 2049 let Inst{11-7} = 0b11000; 2050 let Inst{6} = op6; 2051 let Inst{4} = 0; 2052 2053 bits<5> Vd; 2054 bits<5> Vm; 2055 bits<4> lane; 2056 2057 let Inst{22} = Vd{4}; 2058 let Inst{15-12} = Vd{3-0}; 2059 let Inst{5} = Vm{4}; 2060 let Inst{3-0} = Vm{3-0}; 2061} 2062 2063// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 2064// for single-precision FP. 2065class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 2066 list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 2067} 2068