1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// ARM specific DAG Nodes. 16// 17 18// Type profiles. 19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 21def SDT_ARMStructByVal : SDTypeProfile<0, 4, 22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 24 25def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 26 27def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 28 29def SDT_ARMCMov : SDTypeProfile<1, 3, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 31 SDTCisVT<3, i32>]>; 32 33def SDT_ARMBrcond : SDTypeProfile<0, 2, 34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 35 36def SDT_ARMBrJT : SDTypeProfile<0, 3, 37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 38 SDTCisVT<2, i32>]>; 39 40def SDT_ARMBr2JT : SDTypeProfile<0, 4, 41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 43 44def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 45 [SDTCisVT<0, i32>, 46 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 47 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 48 SDTCisVT<5, OtherVT>]>; 49 50def SDT_ARMAnd : SDTypeProfile<1, 2, 51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 52 SDTCisVT<2, i32>]>; 53 54def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 55 56def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 58 59def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 60def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 61 SDTCisInt<2>]>; 62def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 63 64def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 65 66def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 67 SDTCisInt<1>]>; 68 69def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 70 71def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 73 74def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>; 75def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>; 76 77def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 78 [SDTCisSameAs<0, 2>, 79 SDTCisSameAs<0, 3>, 80 SDTCisInt<0>, SDTCisVT<1, i32>]>; 81 82// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 83def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 84 [SDTCisSameAs<0, 2>, 85 SDTCisSameAs<0, 3>, 86 SDTCisInt<0>, 87 SDTCisVT<1, i32>, 88 SDTCisVT<4, i32>]>; 89 90def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>, 91 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 92 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >; 93def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>; 94def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>; 95 96// Node definitions. 97def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 98def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 99def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>; 100 101def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 102 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 103def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 104 [SDNPHasChain, SDNPSideEffect, 105 SDNPOptInGlue, SDNPOutGlue]>; 106def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , 107 SDT_ARMStructByVal, 108 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 109 SDNPMayStore, SDNPMayLoad]>; 110 111def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 112 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 113 SDNPVariadic]>; 114def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 116 SDNPVariadic]>; 117def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 119 SDNPVariadic]>; 120 121def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 122 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 123def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall, 124 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 125def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 126 [SDNPInGlue]>; 127 128def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 129 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 130 131def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 132 [SDNPHasChain]>; 133def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 134 [SDNPHasChain]>; 135 136def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 137 [SDNPHasChain]>; 138 139def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 140 [SDNPOutGlue]>; 141 142def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, 143 [SDNPOutGlue]>; 144 145def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 146 [SDNPOutGlue, SDNPCommutative]>; 147 148def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 149 150def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 151def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 152def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 153 154def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 155 [SDNPCommutative]>; 156def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 157def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 158def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 159 160def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 161def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 162 SDT_ARMEH_SJLJ_Setjmp, 163 [SDNPHasChain, SDNPSideEffect]>; 164def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 165 SDT_ARMEH_SJLJ_Longjmp, 166 [SDNPHasChain, SDNPSideEffect]>; 167 168def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 169 [SDNPHasChain, SDNPSideEffect]>; 170def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 171 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 172 173def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>; 174 175def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 176 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 177 178def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 179 180def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>; 181def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>; 182 183//===----------------------------------------------------------------------===// 184// ARM Instruction Predicate Definitions. 185// 186def HasV4T : Predicate<"Subtarget->hasV4TOps()">, 187 AssemblerPredicate<"HasV4TOps", "armv4t">; 188def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; 189def HasV5T : Predicate<"Subtarget->hasV5TOps()">, 190 AssemblerPredicate<"HasV5TOps", "armv5t">; 191def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, 192 AssemblerPredicate<"HasV5TEOps", "armv5te">; 193def HasV6 : Predicate<"Subtarget->hasV6Ops()">, 194 AssemblerPredicate<"HasV6Ops", "armv6">; 195def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; 196def HasV6M : Predicate<"Subtarget->hasV6MOps()">, 197 AssemblerPredicate<"HasV6MOps", 198 "armv6m or armv6t2">; 199def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, 200 AssemblerPredicate<"HasV6T2Ops", "armv6t2">; 201def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; 202def HasV7 : Predicate<"Subtarget->hasV7Ops()">, 203 AssemblerPredicate<"HasV7Ops", "armv7">; 204def HasV8 : Predicate<"Subtarget->hasV8Ops()">, 205 AssemblerPredicate<"HasV8Ops", "armv8">; 206def PreV8 : Predicate<"!Subtarget->hasV8Ops()">, 207 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">; 208def NoVFP : Predicate<"!Subtarget->hasVFP2()">; 209def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, 210 AssemblerPredicate<"FeatureVFP2", "VFP2">; 211def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, 212 AssemblerPredicate<"FeatureVFP3", "VFP3">; 213def HasVFP4 : Predicate<"Subtarget->hasVFP4()">, 214 AssemblerPredicate<"FeatureVFP4", "VFP4">; 215def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">, 216 AssemblerPredicate<"!FeatureVFPOnlySP", 217 "double precision VFP">; 218def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, 219 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">; 220def HasNEON : Predicate<"Subtarget->hasNEON()">, 221 AssemblerPredicate<"FeatureNEON", "NEON">; 222def HasCrypto : Predicate<"Subtarget->hasCrypto()">, 223 AssemblerPredicate<"FeatureCrypto", "crypto">; 224def HasCRC : Predicate<"Subtarget->hasCRC()">, 225 AssemblerPredicate<"FeatureCRC", "crc">; 226def HasFP16 : Predicate<"Subtarget->hasFP16()">, 227 AssemblerPredicate<"FeatureFP16","half-float">; 228def HasDivide : Predicate<"Subtarget->hasDivide()">, 229 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">; 230def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, 231 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">; 232def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">, 233 AssemblerPredicate<"FeatureT2XtPk", 234 "pack/extract">; 235def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">, 236 AssemblerPredicate<"FeatureDSPThumb2", 237 "thumb2-dsp">; 238def HasDB : Predicate<"Subtarget->hasDataBarrier()">, 239 AssemblerPredicate<"FeatureDB", 240 "data-barriers">; 241def HasMP : Predicate<"Subtarget->hasMPExtension()">, 242 AssemblerPredicate<"FeatureMP", 243 "mp-extensions">; 244def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">, 245 AssemblerPredicate<"FeatureTrustZone", 246 "TrustZone">; 247def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">; 248def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; 249def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; 250def IsThumb : Predicate<"Subtarget->isThumb()">, 251 AssemblerPredicate<"ModeThumb", "thumb">; 252def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; 253def IsThumb2 : Predicate<"Subtarget->isThumb2()">, 254 AssemblerPredicate<"ModeThumb,FeatureThumb2", 255 "thumb2">; 256def IsMClass : Predicate<"Subtarget->isMClass()">, 257 AssemblerPredicate<"FeatureMClass", "armv*m">; 258def IsNotMClass : Predicate<"!Subtarget->isMClass()">, 259 AssemblerPredicate<"!FeatureMClass", 260 "!armv*m">; 261def IsARM : Predicate<"!Subtarget->isThumb()">, 262 AssemblerPredicate<"!ModeThumb", "arm-mode">; 263def IsIOS : Predicate<"Subtarget->isTargetIOS()">; 264def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">; 265def IsMachO : Predicate<"Subtarget->isTargetMachO()">; 266def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">; 267def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 268def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">, 269 AssemblerPredicate<"FeatureNaClTrap", "NaCl">; 270def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">; 271 272// FIXME: Eventually this will be just "hasV6T2Ops". 273def UseMovt : Predicate<"Subtarget->useMovt(*MF)">; 274def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">; 275def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">; 276def UseMulOps : Predicate<"Subtarget->useMulOps()">; 277 278// Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available. 279// But only select them if more precision in FP computation is allowed. 280// Do not use them for Darwin platforms. 281def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion ==" 282 " FPOpFusion::Fast && " 283 " Subtarget->hasVFP4()) && " 284 "!Subtarget->isTargetDarwin()">; 285def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion ==" 286 " FPOpFusion::Fast &&" 287 " Subtarget->hasVFP4()) || " 288 "Subtarget->isTargetDarwin()">; 289 290// VGETLNi32 is microcoded on Swift - prefer VMOV. 291def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">; 292def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">; 293 294// VDUP.32 is microcoded on Swift - prefer VMOV. 295def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">; 296def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">; 297 298// Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as 299// this allows more effective execution domain optimization. See 300// setExecutionDomain(). 301def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">; 302def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">; 303 304def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">; 305def IsBE : Predicate<"getTargetLowering()->isBigEndian()">; 306 307//===----------------------------------------------------------------------===// 308// ARM Flag Definitions. 309 310class RegConstraint<string C> { 311 string Constraints = C; 312} 313 314//===----------------------------------------------------------------------===// 315// ARM specific transformation functions and pattern fragments. 316// 317 318// imm_neg_XFORM - Return the negation of an i32 immediate value. 319def imm_neg_XFORM : SDNodeXForm<imm, [{ 320 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); 321}]>; 322 323// imm_not_XFORM - Return the complement of a i32 immediate value. 324def imm_not_XFORM : SDNodeXForm<imm, [{ 325 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32); 326}]>; 327 328/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 329def imm16_31 : ImmLeaf<i32, [{ 330 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 331}]>; 332 333def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; } 334def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 335 unsigned Value = -(unsigned)N->getZExtValue(); 336 return Value && ARM_AM::getSOImmVal(Value) != -1; 337 }], imm_neg_XFORM> { 338 let ParserMatchClass = so_imm_neg_asmoperand; 339} 340 341// Note: this pattern doesn't require an encoder method and such, as it's 342// only used on aliases (Pat<> and InstAlias<>). The actual encoding 343// is handled by the destination instructions, which use so_imm. 344def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; } 345def so_imm_not : Operand<i32>, PatLeaf<(imm), [{ 346 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 347 }], imm_not_XFORM> { 348 let ParserMatchClass = so_imm_not_asmoperand; 349} 350 351// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 352def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 353 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 354}]>; 355 356/// Split a 32-bit immediate into two 16 bit parts. 357def hi16 : SDNodeXForm<imm, [{ 358 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32); 359}]>; 360 361def lo16AllZero : PatLeaf<(i32 imm), [{ 362 // Returns true if all low 16-bits are 0. 363 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 364}], hi16>; 365 366class BinOpWithFlagFrag<dag res> : 367 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>; 368class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 369class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 370 371// An 'and' node with a single use. 372def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 373 return N->hasOneUse(); 374}]>; 375 376// An 'xor' node with a single use. 377def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 378 return N->hasOneUse(); 379}]>; 380 381// An 'fmul' node with a single use. 382def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 383 return N->hasOneUse(); 384}]>; 385 386// An 'fadd' node which checks for single non-hazardous use. 387def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 388 return hasNoVMLxHazardUse(N); 389}]>; 390 391// An 'fsub' node which checks for single non-hazardous use. 392def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 393 return hasNoVMLxHazardUse(N); 394}]>; 395 396//===----------------------------------------------------------------------===// 397// Operand Definitions. 398// 399 400// Immediate operands with a shared generic asm render method. 401class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; } 402 403// Branch target. 404// FIXME: rename brtarget to t2_brtarget 405def brtarget : Operand<OtherVT> { 406 let EncoderMethod = "getBranchTargetOpValue"; 407 let OperandType = "OPERAND_PCREL"; 408 let DecoderMethod = "DecodeT2BROperand"; 409} 410 411// FIXME: get rid of this one? 412def uncondbrtarget : Operand<OtherVT> { 413 let EncoderMethod = "getUnconditionalBranchTargetOpValue"; 414 let OperandType = "OPERAND_PCREL"; 415} 416 417// Branch target for ARM. Handles conditional/unconditional 418def br_target : Operand<OtherVT> { 419 let EncoderMethod = "getARMBranchTargetOpValue"; 420 let OperandType = "OPERAND_PCREL"; 421} 422 423// Call target. 424// FIXME: rename bltarget to t2_bl_target? 425def bltarget : Operand<i32> { 426 // Encoded the same as branch targets. 427 let EncoderMethod = "getBranchTargetOpValue"; 428 let OperandType = "OPERAND_PCREL"; 429} 430 431// Call target for ARM. Handles conditional/unconditional 432// FIXME: rename bl_target to t2_bltarget? 433def bl_target : Operand<i32> { 434 let EncoderMethod = "getARMBLTargetOpValue"; 435 let OperandType = "OPERAND_PCREL"; 436} 437 438def blx_target : Operand<i32> { 439 let EncoderMethod = "getARMBLXTargetOpValue"; 440 let OperandType = "OPERAND_PCREL"; 441} 442 443// A list of registers separated by comma. Used by load/store multiple. 444def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 445def reglist : Operand<i32> { 446 let EncoderMethod = "getRegisterListOpValue"; 447 let ParserMatchClass = RegListAsmOperand; 448 let PrintMethod = "printRegisterList"; 449 let DecoderMethod = "DecodeRegListOperand"; 450} 451 452def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">; 453 454def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; } 455def dpr_reglist : Operand<i32> { 456 let EncoderMethod = "getRegisterListOpValue"; 457 let ParserMatchClass = DPRRegListAsmOperand; 458 let PrintMethod = "printRegisterList"; 459 let DecoderMethod = "DecodeDPRRegListOperand"; 460} 461 462def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; } 463def spr_reglist : Operand<i32> { 464 let EncoderMethod = "getRegisterListOpValue"; 465 let ParserMatchClass = SPRRegListAsmOperand; 466 let PrintMethod = "printRegisterList"; 467 let DecoderMethod = "DecodeSPRRegListOperand"; 468} 469 470// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 471def cpinst_operand : Operand<i32> { 472 let PrintMethod = "printCPInstOperand"; 473} 474 475// Local PC labels. 476def pclabel : Operand<i32> { 477 let PrintMethod = "printPCLabel"; 478} 479 480// ADR instruction labels. 481def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } 482def adrlabel : Operand<i32> { 483 let EncoderMethod = "getAdrLabelOpValue"; 484 let ParserMatchClass = AdrLabelAsmOperand; 485 let PrintMethod = "printAdrLabelOperand<0>"; 486} 487 488def neon_vcvt_imm32 : Operand<i32> { 489 let EncoderMethod = "getNEONVcvtImm32OpValue"; 490 let DecoderMethod = "DecodeVCVTImmOperand"; 491} 492 493// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 494def rot_imm_XFORM: SDNodeXForm<imm, [{ 495 switch (N->getZExtValue()){ 496 default: llvm_unreachable(nullptr); 497 case 0: return CurDAG->getTargetConstant(0, MVT::i32); 498 case 8: return CurDAG->getTargetConstant(1, MVT::i32); 499 case 16: return CurDAG->getTargetConstant(2, MVT::i32); 500 case 24: return CurDAG->getTargetConstant(3, MVT::i32); 501 } 502}]>; 503def RotImmAsmOperand : AsmOperandClass { 504 let Name = "RotImm"; 505 let ParserMethod = "parseRotImm"; 506} 507def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 508 int32_t v = N->getZExtValue(); 509 return v == 8 || v == 16 || v == 24; }], 510 rot_imm_XFORM> { 511 let PrintMethod = "printRotImmOperand"; 512 let ParserMatchClass = RotImmAsmOperand; 513} 514 515// shift_imm: An integer that encodes a shift amount and the type of shift 516// (asr or lsl). The 6-bit immediate encodes as: 517// {5} 0 ==> lsl 518// 1 asr 519// {4-0} imm5 shift amount. 520// asr #32 encoded as imm5 == 0. 521def ShifterImmAsmOperand : AsmOperandClass { 522 let Name = "ShifterImm"; 523 let ParserMethod = "parseShifterImm"; 524} 525def shift_imm : Operand<i32> { 526 let PrintMethod = "printShiftImmOperand"; 527 let ParserMatchClass = ShifterImmAsmOperand; 528} 529 530// shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm. 531def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 532def so_reg_reg : Operand<i32>, // reg reg imm 533 ComplexPattern<i32, 3, "SelectRegShifterOperand", 534 [shl, srl, sra, rotr]> { 535 let EncoderMethod = "getSORegRegOpValue"; 536 let PrintMethod = "printSORegRegOperand"; 537 let DecoderMethod = "DecodeSORegRegOperand"; 538 let ParserMatchClass = ShiftedRegAsmOperand; 539 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 540} 541 542def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 543def so_reg_imm : Operand<i32>, // reg imm 544 ComplexPattern<i32, 2, "SelectImmShifterOperand", 545 [shl, srl, sra, rotr]> { 546 let EncoderMethod = "getSORegImmOpValue"; 547 let PrintMethod = "printSORegImmOperand"; 548 let DecoderMethod = "DecodeSORegImmOperand"; 549 let ParserMatchClass = ShiftedImmAsmOperand; 550 let MIOperandInfo = (ops GPR, i32imm); 551} 552 553// FIXME: Does this need to be distinct from so_reg? 554def shift_so_reg_reg : Operand<i32>, // reg reg imm 555 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 556 [shl,srl,sra,rotr]> { 557 let EncoderMethod = "getSORegRegOpValue"; 558 let PrintMethod = "printSORegRegOperand"; 559 let DecoderMethod = "DecodeSORegRegOperand"; 560 let ParserMatchClass = ShiftedRegAsmOperand; 561 let MIOperandInfo = (ops GPR, GPR, i32imm); 562} 563 564// FIXME: Does this need to be distinct from so_reg? 565def shift_so_reg_imm : Operand<i32>, // reg reg imm 566 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 567 [shl,srl,sra,rotr]> { 568 let EncoderMethod = "getSORegImmOpValue"; 569 let PrintMethod = "printSORegImmOperand"; 570 let DecoderMethod = "DecodeSORegImmOperand"; 571 let ParserMatchClass = ShiftedImmAsmOperand; 572 let MIOperandInfo = (ops GPR, i32imm); 573} 574 575 576// so_imm - Match a 32-bit shifter_operand immediate operand, which is an 577// 8-bit immediate rotated by an arbitrary number of bits. 578def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; } 579def so_imm : Operand<i32>, ImmLeaf<i32, [{ 580 return ARM_AM::getSOImmVal(Imm) != -1; 581 }]> { 582 let EncoderMethod = "getSOImmOpValue"; 583 let ParserMatchClass = SOImmAsmOperand; 584 let DecoderMethod = "DecodeSOImmOperand"; 585} 586 587// Break so_imm's up into two pieces. This handles immediates with up to 16 588// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to 589// get the first/second pieces. 590def so_imm2part : PatLeaf<(imm), [{ 591 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 592}]>; 593 594/// arm_i32imm - True for +V6T2, or true only if so_imm2part is true. 595/// 596def arm_i32imm : PatLeaf<(imm), [{ 597 if (Subtarget->useMovt(*MF)) 598 return true; 599 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 600}]>; 601 602/// imm0_1 predicate - Immediate in the range [0,1]. 603def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; } 604def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 605 606/// imm0_3 predicate - Immediate in the range [0,3]. 607def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; } 608def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 609 610/// imm0_7 predicate - Immediate in the range [0,7]. 611def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; } 612def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 613 return Imm >= 0 && Imm < 8; 614}]> { 615 let ParserMatchClass = Imm0_7AsmOperand; 616} 617 618/// imm8 predicate - Immediate is exactly 8. 619def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; } 620def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 621 let ParserMatchClass = Imm8AsmOperand; 622} 623 624/// imm16 predicate - Immediate is exactly 16. 625def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; } 626def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 627 let ParserMatchClass = Imm16AsmOperand; 628} 629 630/// imm32 predicate - Immediate is exactly 32. 631def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; } 632def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 633 let ParserMatchClass = Imm32AsmOperand; 634} 635 636/// imm1_7 predicate - Immediate in the range [1,7]. 637def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; } 638def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 639 let ParserMatchClass = Imm1_7AsmOperand; 640} 641 642/// imm1_15 predicate - Immediate in the range [1,15]. 643def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; } 644def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 645 let ParserMatchClass = Imm1_15AsmOperand; 646} 647 648/// imm1_31 predicate - Immediate in the range [1,31]. 649def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; } 650def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 651 let ParserMatchClass = Imm1_31AsmOperand; 652} 653 654/// imm0_15 predicate - Immediate in the range [0,15]. 655def Imm0_15AsmOperand: ImmAsmOperand { 656 let Name = "Imm0_15"; 657 let DiagnosticType = "ImmRange0_15"; 658} 659def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 660 return Imm >= 0 && Imm < 16; 661}]> { 662 let ParserMatchClass = Imm0_15AsmOperand; 663} 664 665/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 666def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; } 667def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 668 return Imm >= 0 && Imm < 32; 669}]> { 670 let ParserMatchClass = Imm0_31AsmOperand; 671} 672 673/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 674def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; } 675def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 676 return Imm >= 0 && Imm < 32; 677}]> { 678 let ParserMatchClass = Imm0_32AsmOperand; 679} 680 681/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 682def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; } 683def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 684 return Imm >= 0 && Imm < 64; 685}]> { 686 let ParserMatchClass = Imm0_63AsmOperand; 687} 688 689/// imm0_239 predicate - Immediate in the range [0,239]. 690def Imm0_239AsmOperand : ImmAsmOperand { 691 let Name = "Imm0_239"; 692 let DiagnosticType = "ImmRange0_239"; 693} 694def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> { 695 let ParserMatchClass = Imm0_239AsmOperand; 696} 697 698/// imm0_255 predicate - Immediate in the range [0,255]. 699def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; } 700def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 701 let ParserMatchClass = Imm0_255AsmOperand; 702} 703 704/// imm0_65535 - An immediate is in the range [0.65535]. 705def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; } 706def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 707 return Imm >= 0 && Imm < 65536; 708}]> { 709 let ParserMatchClass = Imm0_65535AsmOperand; 710} 711 712// imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. 713def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{ 714 return -Imm >= 0 && -Imm < 65536; 715}]>; 716 717// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 718// a relocatable expression. 719// 720// FIXME: This really needs a Thumb version separate from the ARM version. 721// While the range is the same, and can thus use the same match class, 722// the encoding is different so it should have a different encoder method. 723def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; } 724def imm0_65535_expr : Operand<i32> { 725 let EncoderMethod = "getHiLo16ImmOpValue"; 726 let ParserMatchClass = Imm0_65535ExprAsmOperand; 727} 728 729def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; } 730def imm256_65535_expr : Operand<i32> { 731 let ParserMatchClass = Imm256_65535ExprAsmOperand; 732} 733 734/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 735def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; } 736def imm24b : Operand<i32>, ImmLeaf<i32, [{ 737 return Imm >= 0 && Imm <= 0xffffff; 738}]> { 739 let ParserMatchClass = Imm24bitAsmOperand; 740} 741 742 743/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 744/// e.g., 0xf000ffff 745def BitfieldAsmOperand : AsmOperandClass { 746 let Name = "Bitfield"; 747 let ParserMethod = "parseBitfield"; 748} 749 750def bf_inv_mask_imm : Operand<i32>, 751 PatLeaf<(imm), [{ 752 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 753}] > { 754 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 755 let PrintMethod = "printBitfieldInvMaskImmOperand"; 756 let DecoderMethod = "DecodeBitfieldMaskOperand"; 757 let ParserMatchClass = BitfieldAsmOperand; 758} 759 760def imm1_32_XFORM: SDNodeXForm<imm, [{ 761 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32); 762}]>; 763def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; } 764def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 765 uint64_t Imm = N->getZExtValue(); 766 return Imm > 0 && Imm <= 32; 767 }], 768 imm1_32_XFORM> { 769 let PrintMethod = "printImmPlusOneOperand"; 770 let ParserMatchClass = Imm1_32AsmOperand; 771} 772 773def imm1_16_XFORM: SDNodeXForm<imm, [{ 774 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32); 775}]>; 776def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; } 777def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }], 778 imm1_16_XFORM> { 779 let PrintMethod = "printImmPlusOneOperand"; 780 let ParserMatchClass = Imm1_16AsmOperand; 781} 782 783// Define ARM specific addressing modes. 784// addrmode_imm12 := reg +/- imm12 785// 786def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 787class AddrMode_Imm12 : Operand<i32>, 788 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 789 // 12-bit immediate operand. Note that instructions using this encode 790 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 791 // immediate values are as normal. 792 793 let EncoderMethod = "getAddrModeImm12OpValue"; 794 let DecoderMethod = "DecodeAddrModeImm12Operand"; 795 let ParserMatchClass = MemImm12OffsetAsmOperand; 796 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 797} 798 799def addrmode_imm12 : AddrMode_Imm12 { 800 let PrintMethod = "printAddrModeImm12Operand<false>"; 801} 802 803def addrmode_imm12_pre : AddrMode_Imm12 { 804 let PrintMethod = "printAddrModeImm12Operand<true>"; 805} 806 807// ldst_so_reg := reg +/- reg shop imm 808// 809def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 810def ldst_so_reg : Operand<i32>, 811 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 812 let EncoderMethod = "getLdStSORegOpValue"; 813 // FIXME: Simplify the printer 814 let PrintMethod = "printAddrMode2Operand"; 815 let DecoderMethod = "DecodeSORegMemOperand"; 816 let ParserMatchClass = MemRegOffsetAsmOperand; 817 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 818} 819 820// postidx_imm8 := +/- [0,255] 821// 822// 9 bit value: 823// {8} 1 is imm8 is non-negative. 0 otherwise. 824// {7-0} [0,255] imm8 value. 825def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 826def postidx_imm8 : Operand<i32> { 827 let PrintMethod = "printPostIdxImm8Operand"; 828 let ParserMatchClass = PostIdxImm8AsmOperand; 829 let MIOperandInfo = (ops i32imm); 830} 831 832// postidx_imm8s4 := +/- [0,1020] 833// 834// 9 bit value: 835// {8} 1 is imm8 is non-negative. 0 otherwise. 836// {7-0} [0,255] imm8 value, scaled by 4. 837def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 838def postidx_imm8s4 : Operand<i32> { 839 let PrintMethod = "printPostIdxImm8s4Operand"; 840 let ParserMatchClass = PostIdxImm8s4AsmOperand; 841 let MIOperandInfo = (ops i32imm); 842} 843 844 845// postidx_reg := +/- reg 846// 847def PostIdxRegAsmOperand : AsmOperandClass { 848 let Name = "PostIdxReg"; 849 let ParserMethod = "parsePostIdxReg"; 850} 851def postidx_reg : Operand<i32> { 852 let EncoderMethod = "getPostIdxRegOpValue"; 853 let DecoderMethod = "DecodePostIdxReg"; 854 let PrintMethod = "printPostIdxRegOperand"; 855 let ParserMatchClass = PostIdxRegAsmOperand; 856 let MIOperandInfo = (ops GPRnopc, i32imm); 857} 858 859 860// addrmode2 := reg +/- imm12 861// := reg +/- reg shop imm 862// 863// FIXME: addrmode2 should be refactored the rest of the way to always 864// use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg). 865def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; } 866def addrmode2 : Operand<i32>, 867 ComplexPattern<i32, 3, "SelectAddrMode2", []> { 868 let EncoderMethod = "getAddrMode2OpValue"; 869 let PrintMethod = "printAddrMode2Operand"; 870 let ParserMatchClass = AddrMode2AsmOperand; 871 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 872} 873 874def PostIdxRegShiftedAsmOperand : AsmOperandClass { 875 let Name = "PostIdxRegShifted"; 876 let ParserMethod = "parsePostIdxReg"; 877} 878def am2offset_reg : Operand<i32>, 879 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 880 [], [SDNPWantRoot]> { 881 let EncoderMethod = "getAddrMode2OffsetOpValue"; 882 let PrintMethod = "printAddrMode2OffsetOperand"; 883 // When using this for assembly, it's always as a post-index offset. 884 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 885 let MIOperandInfo = (ops GPRnopc, i32imm); 886} 887 888// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 889// the GPR is purely vestigal at this point. 890def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 891def am2offset_imm : Operand<i32>, 892 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 893 [], [SDNPWantRoot]> { 894 let EncoderMethod = "getAddrMode2OffsetOpValue"; 895 let PrintMethod = "printAddrMode2OffsetOperand"; 896 let ParserMatchClass = AM2OffsetImmAsmOperand; 897 let MIOperandInfo = (ops GPRnopc, i32imm); 898} 899 900 901// addrmode3 := reg +/- reg 902// addrmode3 := reg +/- imm8 903// 904// FIXME: split into imm vs. reg versions. 905def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 906class AddrMode3 : Operand<i32>, 907 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 908 let EncoderMethod = "getAddrMode3OpValue"; 909 let ParserMatchClass = AddrMode3AsmOperand; 910 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 911} 912 913def addrmode3 : AddrMode3 914{ 915 let PrintMethod = "printAddrMode3Operand<false>"; 916} 917 918def addrmode3_pre : AddrMode3 919{ 920 let PrintMethod = "printAddrMode3Operand<true>"; 921} 922 923// FIXME: split into imm vs. reg versions. 924// FIXME: parser method to handle +/- register. 925def AM3OffsetAsmOperand : AsmOperandClass { 926 let Name = "AM3Offset"; 927 let ParserMethod = "parseAM3Offset"; 928} 929def am3offset : Operand<i32>, 930 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 931 [], [SDNPWantRoot]> { 932 let EncoderMethod = "getAddrMode3OffsetOpValue"; 933 let PrintMethod = "printAddrMode3OffsetOperand"; 934 let ParserMatchClass = AM3OffsetAsmOperand; 935 let MIOperandInfo = (ops GPR, i32imm); 936} 937 938// ldstm_mode := {ia, ib, da, db} 939// 940def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 941 let EncoderMethod = "getLdStmModeOpValue"; 942 let PrintMethod = "printLdStmModeOperand"; 943} 944 945// addrmode5 := reg +/- imm8*4 946// 947def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 948class AddrMode5 : Operand<i32>, 949 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 950 let EncoderMethod = "getAddrMode5OpValue"; 951 let DecoderMethod = "DecodeAddrMode5Operand"; 952 let ParserMatchClass = AddrMode5AsmOperand; 953 let MIOperandInfo = (ops GPR:$base, i32imm); 954} 955 956def addrmode5 : AddrMode5 { 957 let PrintMethod = "printAddrMode5Operand<false>"; 958} 959 960def addrmode5_pre : AddrMode5 { 961 let PrintMethod = "printAddrMode5Operand<true>"; 962} 963 964// addrmode6 := reg with optional alignment 965// 966def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 967def addrmode6 : Operand<i32>, 968 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 969 let PrintMethod = "printAddrMode6Operand"; 970 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 971 let EncoderMethod = "getAddrMode6AddressOpValue"; 972 let DecoderMethod = "DecodeAddrMode6Operand"; 973 let ParserMatchClass = AddrMode6AsmOperand; 974} 975 976def am6offset : Operand<i32>, 977 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 978 [], [SDNPWantRoot]> { 979 let PrintMethod = "printAddrMode6OffsetOperand"; 980 let MIOperandInfo = (ops GPR); 981 let EncoderMethod = "getAddrMode6OffsetOpValue"; 982 let DecoderMethod = "DecodeGPRRegisterClass"; 983} 984 985// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 986// (single element from one lane) for size 32. 987def addrmode6oneL32 : Operand<i32>, 988 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 989 let PrintMethod = "printAddrMode6Operand"; 990 let MIOperandInfo = (ops GPR:$addr, i32imm); 991 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 992} 993 994// Base class for addrmode6 with specific alignment restrictions. 995class AddrMode6Align : Operand<i32>, 996 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 997 let PrintMethod = "printAddrMode6Operand"; 998 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 999 let EncoderMethod = "getAddrMode6AddressOpValue"; 1000 let DecoderMethod = "DecodeAddrMode6Operand"; 1001} 1002 1003// Special version of addrmode6 to handle no allowed alignment encoding for 1004// VLD/VST instructions and checking the alignment is not specified. 1005def AddrMode6AlignNoneAsmOperand : AsmOperandClass { 1006 let Name = "AlignedMemoryNone"; 1007 let DiagnosticType = "AlignedMemoryRequiresNone"; 1008} 1009def addrmode6alignNone : AddrMode6Align { 1010 // The alignment specifier can only be omitted. 1011 let ParserMatchClass = AddrMode6AlignNoneAsmOperand; 1012} 1013 1014// Special version of addrmode6 to handle 16-bit alignment encoding for 1015// VLD/VST instructions and checking the alignment value. 1016def AddrMode6Align16AsmOperand : AsmOperandClass { 1017 let Name = "AlignedMemory16"; 1018 let DiagnosticType = "AlignedMemoryRequires16"; 1019} 1020def addrmode6align16 : AddrMode6Align { 1021 // The alignment specifier can only be 16 or omitted. 1022 let ParserMatchClass = AddrMode6Align16AsmOperand; 1023} 1024 1025// Special version of addrmode6 to handle 32-bit alignment encoding for 1026// VLD/VST instructions and checking the alignment value. 1027def AddrMode6Align32AsmOperand : AsmOperandClass { 1028 let Name = "AlignedMemory32"; 1029 let DiagnosticType = "AlignedMemoryRequires32"; 1030} 1031def addrmode6align32 : AddrMode6Align { 1032 // The alignment specifier can only be 32 or omitted. 1033 let ParserMatchClass = AddrMode6Align32AsmOperand; 1034} 1035 1036// Special version of addrmode6 to handle 64-bit alignment encoding for 1037// VLD/VST instructions and checking the alignment value. 1038def AddrMode6Align64AsmOperand : AsmOperandClass { 1039 let Name = "AlignedMemory64"; 1040 let DiagnosticType = "AlignedMemoryRequires64"; 1041} 1042def addrmode6align64 : AddrMode6Align { 1043 // The alignment specifier can only be 64 or omitted. 1044 let ParserMatchClass = AddrMode6Align64AsmOperand; 1045} 1046 1047// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1048// for VLD/VST instructions and checking the alignment value. 1049def AddrMode6Align64or128AsmOperand : AsmOperandClass { 1050 let Name = "AlignedMemory64or128"; 1051 let DiagnosticType = "AlignedMemoryRequires64or128"; 1052} 1053def addrmode6align64or128 : AddrMode6Align { 1054 // The alignment specifier can only be 64, 128 or omitted. 1055 let ParserMatchClass = AddrMode6Align64or128AsmOperand; 1056} 1057 1058// Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment 1059// encoding for VLD/VST instructions and checking the alignment value. 1060def AddrMode6Align64or128or256AsmOperand : AsmOperandClass { 1061 let Name = "AlignedMemory64or128or256"; 1062 let DiagnosticType = "AlignedMemoryRequires64or128or256"; 1063} 1064def addrmode6align64or128or256 : AddrMode6Align { 1065 // The alignment specifier can only be 64, 128, 256 or omitted. 1066 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand; 1067} 1068 1069// Special version of addrmode6 to handle alignment encoding for VLD-dup 1070// instructions, specifically VLD4-dup. 1071def addrmode6dup : Operand<i32>, 1072 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1073 let PrintMethod = "printAddrMode6Operand"; 1074 let MIOperandInfo = (ops GPR:$addr, i32imm); 1075 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1076 // FIXME: This is close, but not quite right. The alignment specifier is 1077 // different. 1078 let ParserMatchClass = AddrMode6AsmOperand; 1079} 1080 1081// Base class for addrmode6dup with specific alignment restrictions. 1082class AddrMode6DupAlign : Operand<i32>, 1083 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1084 let PrintMethod = "printAddrMode6Operand"; 1085 let MIOperandInfo = (ops GPR:$addr, i32imm); 1086 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1087} 1088 1089// Special version of addrmode6 to handle no allowed alignment encoding for 1090// VLD-dup instruction and checking the alignment is not specified. 1091def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass { 1092 let Name = "DupAlignedMemoryNone"; 1093 let DiagnosticType = "DupAlignedMemoryRequiresNone"; 1094} 1095def addrmode6dupalignNone : AddrMode6DupAlign { 1096 // The alignment specifier can only be omitted. 1097 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand; 1098} 1099 1100// Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup 1101// instruction and checking the alignment value. 1102def AddrMode6dupAlign16AsmOperand : AsmOperandClass { 1103 let Name = "DupAlignedMemory16"; 1104 let DiagnosticType = "DupAlignedMemoryRequires16"; 1105} 1106def addrmode6dupalign16 : AddrMode6DupAlign { 1107 // The alignment specifier can only be 16 or omitted. 1108 let ParserMatchClass = AddrMode6dupAlign16AsmOperand; 1109} 1110 1111// Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup 1112// instruction and checking the alignment value. 1113def AddrMode6dupAlign32AsmOperand : AsmOperandClass { 1114 let Name = "DupAlignedMemory32"; 1115 let DiagnosticType = "DupAlignedMemoryRequires32"; 1116} 1117def addrmode6dupalign32 : AddrMode6DupAlign { 1118 // The alignment specifier can only be 32 or omitted. 1119 let ParserMatchClass = AddrMode6dupAlign32AsmOperand; 1120} 1121 1122// Special version of addrmode6 to handle 64-bit alignment encoding for VLD 1123// instructions and checking the alignment value. 1124def AddrMode6dupAlign64AsmOperand : AsmOperandClass { 1125 let Name = "DupAlignedMemory64"; 1126 let DiagnosticType = "DupAlignedMemoryRequires64"; 1127} 1128def addrmode6dupalign64 : AddrMode6DupAlign { 1129 // The alignment specifier can only be 64 or omitted. 1130 let ParserMatchClass = AddrMode6dupAlign64AsmOperand; 1131} 1132 1133// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1134// for VLD instructions and checking the alignment value. 1135def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass { 1136 let Name = "DupAlignedMemory64or128"; 1137 let DiagnosticType = "DupAlignedMemoryRequires64or128"; 1138} 1139def addrmode6dupalign64or128 : AddrMode6DupAlign { 1140 // The alignment specifier can only be 64, 128 or omitted. 1141 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand; 1142} 1143 1144// addrmodepc := pc + reg 1145// 1146def addrmodepc : Operand<i32>, 1147 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 1148 let PrintMethod = "printAddrModePCOperand"; 1149 let MIOperandInfo = (ops GPR, i32imm); 1150} 1151 1152// addr_offset_none := reg 1153// 1154def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 1155def addr_offset_none : Operand<i32>, 1156 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 1157 let PrintMethod = "printAddrMode7Operand"; 1158 let DecoderMethod = "DecodeAddrMode7Operand"; 1159 let ParserMatchClass = MemNoOffsetAsmOperand; 1160 let MIOperandInfo = (ops GPR:$base); 1161} 1162 1163def nohash_imm : Operand<i32> { 1164 let PrintMethod = "printNoHashImmediate"; 1165} 1166 1167def CoprocNumAsmOperand : AsmOperandClass { 1168 let Name = "CoprocNum"; 1169 let ParserMethod = "parseCoprocNumOperand"; 1170} 1171def p_imm : Operand<i32> { 1172 let PrintMethod = "printPImmediate"; 1173 let ParserMatchClass = CoprocNumAsmOperand; 1174 let DecoderMethod = "DecodeCoprocessor"; 1175} 1176 1177def CoprocRegAsmOperand : AsmOperandClass { 1178 let Name = "CoprocReg"; 1179 let ParserMethod = "parseCoprocRegOperand"; 1180} 1181def c_imm : Operand<i32> { 1182 let PrintMethod = "printCImmediate"; 1183 let ParserMatchClass = CoprocRegAsmOperand; 1184} 1185def CoprocOptionAsmOperand : AsmOperandClass { 1186 let Name = "CoprocOption"; 1187 let ParserMethod = "parseCoprocOptionOperand"; 1188} 1189def coproc_option_imm : Operand<i32> { 1190 let PrintMethod = "printCoprocOptionImm"; 1191 let ParserMatchClass = CoprocOptionAsmOperand; 1192} 1193 1194//===----------------------------------------------------------------------===// 1195 1196include "ARMInstrFormats.td" 1197 1198//===----------------------------------------------------------------------===// 1199// Multiclass helpers... 1200// 1201 1202/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a 1203/// binop that produces a value. 1204let TwoOperandAliasConstraint = "$Rn = $Rd" in 1205multiclass AsI1_bin_irs<bits<4> opcod, string opc, 1206 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1207 PatFrag opnode, bit Commutable = 0> { 1208 // The register-immediate version is re-materializable. This is useful 1209 // in particular for taking the address of a local. 1210 let isReMaterializable = 1 in { 1211 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, 1212 iii, opc, "\t$Rd, $Rn, $imm", 1213 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>, 1214 Sched<[WriteALU, ReadALU]> { 1215 bits<4> Rd; 1216 bits<4> Rn; 1217 bits<12> imm; 1218 let Inst{25} = 1; 1219 let Inst{19-16} = Rn; 1220 let Inst{15-12} = Rd; 1221 let Inst{11-0} = imm; 1222 } 1223 } 1224 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1225 iir, opc, "\t$Rd, $Rn, $Rm", 1226 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 1227 Sched<[WriteALU, ReadALU, ReadALU]> { 1228 bits<4> Rd; 1229 bits<4> Rn; 1230 bits<4> Rm; 1231 let Inst{25} = 0; 1232 let isCommutable = Commutable; 1233 let Inst{19-16} = Rn; 1234 let Inst{15-12} = Rd; 1235 let Inst{11-4} = 0b00000000; 1236 let Inst{3-0} = Rm; 1237 } 1238 1239 def rsi : AsI1<opcod, (outs GPR:$Rd), 1240 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1241 iis, opc, "\t$Rd, $Rn, $shift", 1242 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, 1243 Sched<[WriteALUsi, ReadALU]> { 1244 bits<4> Rd; 1245 bits<4> Rn; 1246 bits<12> shift; 1247 let Inst{25} = 0; 1248 let Inst{19-16} = Rn; 1249 let Inst{15-12} = Rd; 1250 let Inst{11-5} = shift{11-5}; 1251 let Inst{4} = 0; 1252 let Inst{3-0} = shift{3-0}; 1253 } 1254 1255 def rsr : AsI1<opcod, (outs GPR:$Rd), 1256 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1257 iis, opc, "\t$Rd, $Rn, $shift", 1258 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, 1259 Sched<[WriteALUsr, ReadALUsr]> { 1260 bits<4> Rd; 1261 bits<4> Rn; 1262 bits<12> shift; 1263 let Inst{25} = 0; 1264 let Inst{19-16} = Rn; 1265 let Inst{15-12} = Rd; 1266 let Inst{11-8} = shift{11-8}; 1267 let Inst{7} = 0; 1268 let Inst{6-5} = shift{6-5}; 1269 let Inst{4} = 1; 1270 let Inst{3-0} = shift{3-0}; 1271 } 1272} 1273 1274/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1275/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1276/// it is equivalent to the AsI1_bin_irs counterpart. 1277let TwoOperandAliasConstraint = "$Rn = $Rd" in 1278multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1279 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1280 PatFrag opnode, bit Commutable = 0> { 1281 // The register-immediate version is re-materializable. This is useful 1282 // in particular for taking the address of a local. 1283 let isReMaterializable = 1 in { 1284 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, 1285 iii, opc, "\t$Rd, $Rn, $imm", 1286 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>, 1287 Sched<[WriteALU, ReadALU]> { 1288 bits<4> Rd; 1289 bits<4> Rn; 1290 bits<12> imm; 1291 let Inst{25} = 1; 1292 let Inst{19-16} = Rn; 1293 let Inst{15-12} = Rd; 1294 let Inst{11-0} = imm; 1295 } 1296 } 1297 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1298 iir, opc, "\t$Rd, $Rn, $Rm", 1299 [/* pattern left blank */]>, 1300 Sched<[WriteALU, ReadALU, ReadALU]> { 1301 bits<4> Rd; 1302 bits<4> Rn; 1303 bits<4> Rm; 1304 let Inst{11-4} = 0b00000000; 1305 let Inst{25} = 0; 1306 let Inst{3-0} = Rm; 1307 let Inst{15-12} = Rd; 1308 let Inst{19-16} = Rn; 1309 } 1310 1311 def rsi : AsI1<opcod, (outs GPR:$Rd), 1312 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1313 iis, opc, "\t$Rd, $Rn, $shift", 1314 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>, 1315 Sched<[WriteALUsi, ReadALU]> { 1316 bits<4> Rd; 1317 bits<4> Rn; 1318 bits<12> shift; 1319 let Inst{25} = 0; 1320 let Inst{19-16} = Rn; 1321 let Inst{15-12} = Rd; 1322 let Inst{11-5} = shift{11-5}; 1323 let Inst{4} = 0; 1324 let Inst{3-0} = shift{3-0}; 1325 } 1326 1327 def rsr : AsI1<opcod, (outs GPR:$Rd), 1328 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1329 iis, opc, "\t$Rd, $Rn, $shift", 1330 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>, 1331 Sched<[WriteALUsr, ReadALUsr]> { 1332 bits<4> Rd; 1333 bits<4> Rn; 1334 bits<12> shift; 1335 let Inst{25} = 0; 1336 let Inst{19-16} = Rn; 1337 let Inst{15-12} = Rd; 1338 let Inst{11-8} = shift{11-8}; 1339 let Inst{7} = 0; 1340 let Inst{6-5} = shift{6-5}; 1341 let Inst{4} = 1; 1342 let Inst{3-0} = shift{3-0}; 1343 } 1344} 1345 1346/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1347/// 1348/// These opcodes will be converted to the real non-S opcodes by 1349/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1350let hasPostISelHook = 1, Defs = [CPSR] in { 1351multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1352 InstrItinClass iis, PatFrag opnode, 1353 bit Commutable = 0> { 1354 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p), 1355 4, iii, 1356 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>, 1357 Sched<[WriteALU, ReadALU]>; 1358 1359 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1360 4, iir, 1361 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, 1362 Sched<[WriteALU, ReadALU, ReadALU]> { 1363 let isCommutable = Commutable; 1364 } 1365 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1366 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1367 4, iis, 1368 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1369 so_reg_imm:$shift))]>, 1370 Sched<[WriteALUsi, ReadALU]>; 1371 1372 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1373 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1374 4, iis, 1375 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1376 so_reg_reg:$shift))]>, 1377 Sched<[WriteALUSsr, ReadALUsr]>; 1378} 1379} 1380 1381/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1382/// operands are reversed. 1383let hasPostISelHook = 1, Defs = [CPSR] in { 1384multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir, 1385 InstrItinClass iis, PatFrag opnode, 1386 bit Commutable = 0> { 1387 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p), 1388 4, iii, 1389 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>, 1390 Sched<[WriteALU, ReadALU]>; 1391 1392 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1393 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1394 4, iis, 1395 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1396 GPR:$Rn))]>, 1397 Sched<[WriteALUsi, ReadALU]>; 1398 1399 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1400 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1401 4, iis, 1402 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1403 GPR:$Rn))]>, 1404 Sched<[WriteALUSsr, ReadALUsr]>; 1405} 1406} 1407 1408/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 1409/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1410/// a explicit result, only implicitly set CPSR. 1411let isCompare = 1, Defs = [CPSR] in { 1412multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1413 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1414 PatFrag opnode, bit Commutable = 0> { 1415 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii, 1416 opc, "\t$Rn, $imm", 1417 [(opnode GPR:$Rn, so_imm:$imm)]>, 1418 Sched<[WriteCMP, ReadALU]> { 1419 bits<4> Rn; 1420 bits<12> imm; 1421 let Inst{25} = 1; 1422 let Inst{20} = 1; 1423 let Inst{19-16} = Rn; 1424 let Inst{15-12} = 0b0000; 1425 let Inst{11-0} = imm; 1426 1427 let Unpredictable{15-12} = 0b1111; 1428 } 1429 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1430 opc, "\t$Rn, $Rm", 1431 [(opnode GPR:$Rn, GPR:$Rm)]>, 1432 Sched<[WriteCMP, ReadALU, ReadALU]> { 1433 bits<4> Rn; 1434 bits<4> Rm; 1435 let isCommutable = Commutable; 1436 let Inst{25} = 0; 1437 let Inst{20} = 1; 1438 let Inst{19-16} = Rn; 1439 let Inst{15-12} = 0b0000; 1440 let Inst{11-4} = 0b00000000; 1441 let Inst{3-0} = Rm; 1442 1443 let Unpredictable{15-12} = 0b1111; 1444 } 1445 def rsi : AI1<opcod, (outs), 1446 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1447 opc, "\t$Rn, $shift", 1448 [(opnode GPR:$Rn, so_reg_imm:$shift)]>, 1449 Sched<[WriteCMPsi, ReadALU]> { 1450 bits<4> Rn; 1451 bits<12> shift; 1452 let Inst{25} = 0; 1453 let Inst{20} = 1; 1454 let Inst{19-16} = Rn; 1455 let Inst{15-12} = 0b0000; 1456 let Inst{11-5} = shift{11-5}; 1457 let Inst{4} = 0; 1458 let Inst{3-0} = shift{3-0}; 1459 1460 let Unpredictable{15-12} = 0b1111; 1461 } 1462 def rsr : AI1<opcod, (outs), 1463 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1464 opc, "\t$Rn, $shift", 1465 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>, 1466 Sched<[WriteCMPsr, ReadALU]> { 1467 bits<4> Rn; 1468 bits<12> shift; 1469 let Inst{25} = 0; 1470 let Inst{20} = 1; 1471 let Inst{19-16} = Rn; 1472 let Inst{15-12} = 0b0000; 1473 let Inst{11-8} = shift{11-8}; 1474 let Inst{7} = 0; 1475 let Inst{6-5} = shift{6-5}; 1476 let Inst{4} = 1; 1477 let Inst{3-0} = shift{3-0}; 1478 1479 let Unpredictable{15-12} = 0b1111; 1480 } 1481 1482} 1483} 1484 1485/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1486/// register and one whose operand is a register rotated by 8/16/24. 1487/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1488class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1489 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1490 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1491 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1492 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1493 bits<4> Rd; 1494 bits<4> Rm; 1495 bits<2> rot; 1496 let Inst{19-16} = 0b1111; 1497 let Inst{15-12} = Rd; 1498 let Inst{11-10} = rot; 1499 let Inst{3-0} = Rm; 1500} 1501 1502class AI_ext_rrot_np<bits<8> opcod, string opc> 1503 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1504 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1505 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1506 bits<2> rot; 1507 let Inst{19-16} = 0b1111; 1508 let Inst{11-10} = rot; 1509 } 1510 1511/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1512/// register and one whose operand is a register rotated by 8/16/24. 1513class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1514 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1515 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1516 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1517 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1518 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1519 bits<4> Rd; 1520 bits<4> Rm; 1521 bits<4> Rn; 1522 bits<2> rot; 1523 let Inst{19-16} = Rn; 1524 let Inst{15-12} = Rd; 1525 let Inst{11-10} = rot; 1526 let Inst{9-4} = 0b000111; 1527 let Inst{3-0} = Rm; 1528} 1529 1530class AI_exta_rrot_np<bits<8> opcod, string opc> 1531 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1532 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1533 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1534 bits<4> Rn; 1535 bits<2> rot; 1536 let Inst{19-16} = Rn; 1537 let Inst{11-10} = rot; 1538} 1539 1540/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1541let TwoOperandAliasConstraint = "$Rn = $Rd" in 1542multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, 1543 bit Commutable = 0> { 1544 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1545 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), 1546 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1547 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>, 1548 Requires<[IsARM]>, 1549 Sched<[WriteALU, ReadALU]> { 1550 bits<4> Rd; 1551 bits<4> Rn; 1552 bits<12> imm; 1553 let Inst{25} = 1; 1554 let Inst{15-12} = Rd; 1555 let Inst{19-16} = Rn; 1556 let Inst{11-0} = imm; 1557 } 1558 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1559 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1560 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1561 Requires<[IsARM]>, 1562 Sched<[WriteALU, ReadALU, ReadALU]> { 1563 bits<4> Rd; 1564 bits<4> Rn; 1565 bits<4> Rm; 1566 let Inst{11-4} = 0b00000000; 1567 let Inst{25} = 0; 1568 let isCommutable = Commutable; 1569 let Inst{3-0} = Rm; 1570 let Inst{15-12} = Rd; 1571 let Inst{19-16} = Rn; 1572 } 1573 def rsi : AsI1<opcod, (outs GPR:$Rd), 1574 (ins GPR:$Rn, so_reg_imm:$shift), 1575 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1576 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1577 Requires<[IsARM]>, 1578 Sched<[WriteALUsi, ReadALU]> { 1579 bits<4> Rd; 1580 bits<4> Rn; 1581 bits<12> shift; 1582 let Inst{25} = 0; 1583 let Inst{19-16} = Rn; 1584 let Inst{15-12} = Rd; 1585 let Inst{11-5} = shift{11-5}; 1586 let Inst{4} = 0; 1587 let Inst{3-0} = shift{3-0}; 1588 } 1589 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1590 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1591 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1592 [(set GPRnopc:$Rd, CPSR, 1593 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1594 Requires<[IsARM]>, 1595 Sched<[WriteALUsr, ReadALUsr]> { 1596 bits<4> Rd; 1597 bits<4> Rn; 1598 bits<12> shift; 1599 let Inst{25} = 0; 1600 let Inst{19-16} = Rn; 1601 let Inst{15-12} = Rd; 1602 let Inst{11-8} = shift{11-8}; 1603 let Inst{7} = 0; 1604 let Inst{6-5} = shift{6-5}; 1605 let Inst{4} = 1; 1606 let Inst{3-0} = shift{3-0}; 1607 } 1608 } 1609} 1610 1611/// AI1_rsc_irs - Define instructions and patterns for rsc 1612let TwoOperandAliasConstraint = "$Rn = $Rd" in 1613multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> { 1614 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1615 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), 1616 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1617 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>, 1618 Requires<[IsARM]>, 1619 Sched<[WriteALU, ReadALU]> { 1620 bits<4> Rd; 1621 bits<4> Rn; 1622 bits<12> imm; 1623 let Inst{25} = 1; 1624 let Inst{15-12} = Rd; 1625 let Inst{19-16} = Rn; 1626 let Inst{11-0} = imm; 1627 } 1628 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1629 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1630 [/* pattern left blank */]>, 1631 Sched<[WriteALU, ReadALU, ReadALU]> { 1632 bits<4> Rd; 1633 bits<4> Rn; 1634 bits<4> Rm; 1635 let Inst{11-4} = 0b00000000; 1636 let Inst{25} = 0; 1637 let Inst{3-0} = Rm; 1638 let Inst{15-12} = Rd; 1639 let Inst{19-16} = Rn; 1640 } 1641 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1642 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1643 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1644 Requires<[IsARM]>, 1645 Sched<[WriteALUsi, ReadALU]> { 1646 bits<4> Rd; 1647 bits<4> Rn; 1648 bits<12> shift; 1649 let Inst{25} = 0; 1650 let Inst{19-16} = Rn; 1651 let Inst{15-12} = Rd; 1652 let Inst{11-5} = shift{11-5}; 1653 let Inst{4} = 0; 1654 let Inst{3-0} = shift{3-0}; 1655 } 1656 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1657 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1658 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1659 Requires<[IsARM]>, 1660 Sched<[WriteALUsr, ReadALUsr]> { 1661 bits<4> Rd; 1662 bits<4> Rn; 1663 bits<12> shift; 1664 let Inst{25} = 0; 1665 let Inst{19-16} = Rn; 1666 let Inst{15-12} = Rd; 1667 let Inst{11-8} = shift{11-8}; 1668 let Inst{7} = 0; 1669 let Inst{6-5} = shift{6-5}; 1670 let Inst{4} = 1; 1671 let Inst{3-0} = shift{3-0}; 1672 } 1673 } 1674} 1675 1676let canFoldAsLoad = 1, isReMaterializable = 1 in { 1677multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1678 InstrItinClass iir, PatFrag opnode> { 1679 // Note: We use the complex addrmode_imm12 rather than just an input 1680 // GPR and a constrained immediate so that we can use this to match 1681 // frame index references and avoid matching constant pool references. 1682 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1683 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1684 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1685 bits<4> Rt; 1686 bits<17> addr; 1687 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1688 let Inst{19-16} = addr{16-13}; // Rn 1689 let Inst{15-12} = Rt; 1690 let Inst{11-0} = addr{11-0}; // imm12 1691 } 1692 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 1693 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1694 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 1695 bits<4> Rt; 1696 bits<17> shift; 1697 let shift{4} = 0; // Inst{4} = 0 1698 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1699 let Inst{19-16} = shift{16-13}; // Rn 1700 let Inst{15-12} = Rt; 1701 let Inst{11-0} = shift{11-0}; 1702 } 1703} 1704} 1705 1706let canFoldAsLoad = 1, isReMaterializable = 1 in { 1707multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 1708 InstrItinClass iir, PatFrag opnode> { 1709 // Note: We use the complex addrmode_imm12 rather than just an input 1710 // GPR and a constrained immediate so that we can use this to match 1711 // frame index references and avoid matching constant pool references. 1712 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 1713 (ins addrmode_imm12:$addr), 1714 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1715 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 1716 bits<4> Rt; 1717 bits<17> addr; 1718 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1719 let Inst{19-16} = addr{16-13}; // Rn 1720 let Inst{15-12} = Rt; 1721 let Inst{11-0} = addr{11-0}; // imm12 1722 } 1723 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), 1724 (ins ldst_so_reg:$shift), 1725 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1726 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 1727 bits<4> Rt; 1728 bits<17> shift; 1729 let shift{4} = 0; // Inst{4} = 0 1730 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1731 let Inst{19-16} = shift{16-13}; // Rn 1732 let Inst{15-12} = Rt; 1733 let Inst{11-0} = shift{11-0}; 1734 } 1735} 1736} 1737 1738 1739multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 1740 InstrItinClass iir, PatFrag opnode> { 1741 // Note: We use the complex addrmode_imm12 rather than just an input 1742 // GPR and a constrained immediate so that we can use this to match 1743 // frame index references and avoid matching constant pool references. 1744 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1745 (ins GPR:$Rt, addrmode_imm12:$addr), 1746 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1747 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 1748 bits<4> Rt; 1749 bits<17> addr; 1750 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1751 let Inst{19-16} = addr{16-13}; // Rn 1752 let Inst{15-12} = Rt; 1753 let Inst{11-0} = addr{11-0}; // imm12 1754 } 1755 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 1756 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1757 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 1758 bits<4> Rt; 1759 bits<17> shift; 1760 let shift{4} = 0; // Inst{4} = 0 1761 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1762 let Inst{19-16} = shift{16-13}; // Rn 1763 let Inst{15-12} = Rt; 1764 let Inst{11-0} = shift{11-0}; 1765 } 1766} 1767 1768multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 1769 InstrItinClass iir, PatFrag opnode> { 1770 // Note: We use the complex addrmode_imm12 rather than just an input 1771 // GPR and a constrained immediate so that we can use this to match 1772 // frame index references and avoid matching constant pool references. 1773 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1774 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 1775 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1776 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 1777 bits<4> Rt; 1778 bits<17> addr; 1779 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1780 let Inst{19-16} = addr{16-13}; // Rn 1781 let Inst{15-12} = Rt; 1782 let Inst{11-0} = addr{11-0}; // imm12 1783 } 1784 def rs : AI2ldst<0b011, 0, isByte, (outs), 1785 (ins GPRnopc:$Rt, ldst_so_reg:$shift), 1786 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1787 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 1788 bits<4> Rt; 1789 bits<17> shift; 1790 let shift{4} = 0; // Inst{4} = 0 1791 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1792 let Inst{19-16} = shift{16-13}; // Rn 1793 let Inst{15-12} = Rt; 1794 let Inst{11-0} = shift{11-0}; 1795 } 1796} 1797 1798 1799//===----------------------------------------------------------------------===// 1800// Instructions 1801//===----------------------------------------------------------------------===// 1802 1803//===----------------------------------------------------------------------===// 1804// Miscellaneous Instructions. 1805// 1806 1807/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 1808/// the function. The first operand is the ID# for this instruction, the second 1809/// is the index into the MachineConstantPool that this is, the third is the 1810/// size in bytes of this constant pool entry. 1811let neverHasSideEffects = 1, isNotDuplicable = 1 in 1812def CONSTPOOL_ENTRY : 1813PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1814 i32imm:$size), NoItinerary, []>; 1815 1816// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 1817// from removing one half of the matched pairs. That breaks PEI, which assumes 1818// these will always be in pairs, and asserts if it finds otherwise. Better way? 1819let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 1820def ADJCALLSTACKUP : 1821PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 1822 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 1823 1824def ADJCALLSTACKDOWN : 1825PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, 1826 [(ARMcallseq_start timm:$amt)]>; 1827} 1828 1829def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary, 1830 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>, 1831 Requires<[IsARM, HasV6]> { 1832 bits<8> imm; 1833 let Inst{27-8} = 0b00110010000011110000; 1834 let Inst{7-0} = imm; 1835} 1836 1837def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1838def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1839def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1840def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1841def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1842def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; 1843 1844def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 1845 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> { 1846 bits<4> Rd; 1847 bits<4> Rn; 1848 bits<4> Rm; 1849 let Inst{3-0} = Rm; 1850 let Inst{15-12} = Rd; 1851 let Inst{19-16} = Rn; 1852 let Inst{27-20} = 0b01101000; 1853 let Inst{7-4} = 0b1011; 1854 let Inst{11-8} = 0b1111; 1855 let Unpredictable{11-8} = 0b1111; 1856} 1857 1858// The 16-bit operand $val can be used by a debugger to store more information 1859// about the breakpoint. 1860def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 1861 "bkpt", "\t$val", []>, Requires<[IsARM]> { 1862 bits<16> val; 1863 let Inst{3-0} = val{3-0}; 1864 let Inst{19-8} = val{15-4}; 1865 let Inst{27-20} = 0b00010010; 1866 let Inst{31-28} = 0xe; // AL 1867 let Inst{7-4} = 0b0111; 1868} 1869// default immediate for breakpoint mnemonic 1870def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>; 1871 1872def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 1873 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> { 1874 bits<16> val; 1875 let Inst{3-0} = val{3-0}; 1876 let Inst{19-8} = val{15-4}; 1877 let Inst{27-20} = 0b00010000; 1878 let Inst{31-28} = 0xe; // AL 1879 let Inst{7-4} = 0b0111; 1880} 1881 1882// Change Processor State 1883// FIXME: We should use InstAlias to handle the optional operands. 1884class CPS<dag iops, string asm_ops> 1885 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 1886 []>, Requires<[IsARM]> { 1887 bits<2> imod; 1888 bits<3> iflags; 1889 bits<5> mode; 1890 bit M; 1891 1892 let Inst{31-28} = 0b1111; 1893 let Inst{27-20} = 0b00010000; 1894 let Inst{19-18} = imod; 1895 let Inst{17} = M; // Enabled if mode is set; 1896 let Inst{16-9} = 0b00000000; 1897 let Inst{8-6} = iflags; 1898 let Inst{5} = 0; 1899 let Inst{4-0} = mode; 1900} 1901 1902let DecoderMethod = "DecodeCPSInstruction" in { 1903let M = 1 in 1904 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 1905 "$imod\t$iflags, $mode">; 1906let mode = 0, M = 0 in 1907 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 1908 1909let imod = 0, iflags = 0, M = 1 in 1910 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 1911} 1912 1913// Preload signals the memory system of possible future data/instruction access. 1914multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 1915 1916 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm, 1917 IIC_Preload, !strconcat(opc, "\t$addr"), 1918 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, 1919 Sched<[WritePreLd]> { 1920 bits<4> Rt; 1921 bits<17> addr; 1922 let Inst{31-26} = 0b111101; 1923 let Inst{25} = 0; // 0 for immediate form 1924 let Inst{24} = data; 1925 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1926 let Inst{22} = read; 1927 let Inst{21-20} = 0b01; 1928 let Inst{19-16} = addr{16-13}; // Rn 1929 let Inst{15-12} = 0b1111; 1930 let Inst{11-0} = addr{11-0}; // imm12 1931 } 1932 1933 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 1934 !strconcat(opc, "\t$shift"), 1935 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, 1936 Sched<[WritePreLd]> { 1937 bits<17> shift; 1938 let Inst{31-26} = 0b111101; 1939 let Inst{25} = 1; // 1 for register form 1940 let Inst{24} = data; 1941 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1942 let Inst{22} = read; 1943 let Inst{21-20} = 0b01; 1944 let Inst{19-16} = shift{16-13}; // Rn 1945 let Inst{15-12} = 0b1111; 1946 let Inst{11-0} = shift{11-0}; 1947 let Inst{4} = 0; 1948 } 1949} 1950 1951defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 1952defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 1953defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 1954 1955def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 1956 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> { 1957 bits<1> end; 1958 let Inst{31-10} = 0b1111000100000001000000; 1959 let Inst{9} = end; 1960 let Inst{8-0} = 0; 1961} 1962 1963def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 1964 []>, Requires<[IsARM, HasV7]> { 1965 bits<4> opt; 1966 let Inst{27-4} = 0b001100100000111100001111; 1967 let Inst{3-0} = opt; 1968} 1969 1970// A8.8.247 UDF - Undefined (Encoding A1) 1971def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, 1972 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> { 1973 bits<16> imm16; 1974 let Inst{31-28} = 0b1110; // AL 1975 let Inst{27-25} = 0b011; 1976 let Inst{24-20} = 0b11111; 1977 let Inst{19-8} = imm16{15-4}; 1978 let Inst{7-4} = 0b1111; 1979 let Inst{3-0} = imm16{3-0}; 1980} 1981 1982/* 1983 * A5.4 Permanently UNDEFINED instructions. 1984 * 1985 * For most targets use UDF #65006, for which the OS will generate SIGTRAP. 1986 * Other UDF encodings generate SIGILL. 1987 * 1988 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. 1989 * Encoding A1: 1990 * 1110 0111 1111 iiii iiii iiii 1111 iiii 1991 * Encoding T1: 1992 * 1101 1110 iiii iiii 1993 * It uses the following encoding: 1994 * 1110 0111 1111 1110 1101 1110 1111 0000 1995 * - In ARM: UDF #60896; 1996 * - In Thumb: UDF #254 followed by a branch-to-self. 1997 */ 1998let isBarrier = 1, isTerminator = 1 in 1999def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, 2000 "trap", [(trap)]>, 2001 Requires<[IsARM,UseNaClTrap]> { 2002 let Inst = 0xe7fedef0; 2003} 2004let isBarrier = 1, isTerminator = 1 in 2005def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 2006 "trap", [(trap)]>, 2007 Requires<[IsARM,DontUseNaClTrap]> { 2008 let Inst = 0xe7ffdefe; 2009} 2010 2011// Address computation and loads and stores in PIC mode. 2012let isNotDuplicable = 1 in { 2013def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 2014 4, IIC_iALUr, 2015 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>, 2016 Sched<[WriteALU, ReadALU]>; 2017 2018let AddedComplexity = 10 in { 2019def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 2020 4, IIC_iLoad_r, 2021 [(set GPR:$dst, (load addrmodepc:$addr))]>; 2022 2023def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2024 4, IIC_iLoad_bh_r, 2025 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 2026 2027def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2028 4, IIC_iLoad_bh_r, 2029 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 2030 2031def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2032 4, IIC_iLoad_bh_r, 2033 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 2034 2035def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2036 4, IIC_iLoad_bh_r, 2037 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 2038} 2039let AddedComplexity = 10 in { 2040def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2041 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 2042 2043def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2044 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 2045 addrmodepc:$addr)]>; 2046 2047def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2048 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 2049} 2050} // isNotDuplicable = 1 2051 2052 2053// LEApcrel - Load a pc-relative address into a register without offending the 2054// assembler. 2055let neverHasSideEffects = 1, isReMaterializable = 1 in 2056// The 'adr' mnemonic encodes differently if the label is before or after 2057// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 2058// know until then which form of the instruction will be used. 2059def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 2060 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>, 2061 Sched<[WriteALU, ReadALU]> { 2062 bits<4> Rd; 2063 bits<14> label; 2064 let Inst{27-25} = 0b001; 2065 let Inst{24} = 0; 2066 let Inst{23-22} = label{13-12}; 2067 let Inst{21} = 0; 2068 let Inst{20} = 0; 2069 let Inst{19-16} = 0b1111; 2070 let Inst{15-12} = Rd; 2071 let Inst{11-0} = label{11-0}; 2072} 2073 2074let hasSideEffects = 1 in { 2075def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 2076 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2077 2078def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 2079 (ins i32imm:$label, nohash_imm:$id, pred:$p), 2080 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2081} 2082 2083//===----------------------------------------------------------------------===// 2084// Control Flow Instructions. 2085// 2086 2087let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 2088 // ARMV4T and above 2089 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2090 "bx", "\tlr", [(ARMretflag)]>, 2091 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2092 let Inst{27-0} = 0b0001001011111111111100011110; 2093 } 2094 2095 // ARMV4 only 2096 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2097 "mov", "\tpc, lr", [(ARMretflag)]>, 2098 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> { 2099 let Inst{27-0} = 0b0001101000001111000000001110; 2100 } 2101 2102 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets 2103 // the user-space one). 2104 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p), 2105 4, IIC_Br, 2106 [(ARMintretflag imm:$offset)]>; 2107} 2108 2109// Indirect branches 2110let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 2111 // ARMV4T and above 2112 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 2113 [(brind GPR:$dst)]>, 2114 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2115 bits<4> dst; 2116 let Inst{31-4} = 0b1110000100101111111111110001; 2117 let Inst{3-0} = dst; 2118 } 2119 2120 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 2121 "bx", "\t$dst", [/* pattern left blank */]>, 2122 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2123 bits<4> dst; 2124 let Inst{27-4} = 0b000100101111111111110001; 2125 let Inst{3-0} = dst; 2126 } 2127} 2128 2129// SP is marked as a use to prevent stack-pointer assignments that appear 2130// immediately before calls from potentially appearing dead. 2131let isCall = 1, 2132 // FIXME: Do we really need a non-predicated version? If so, it should 2133 // at least be a pseudo instruction expanding to the predicated version 2134 // at MC lowering time. 2135 Defs = [LR], Uses = [SP] in { 2136 def BL : ABXI<0b1011, (outs), (ins bl_target:$func), 2137 IIC_Br, "bl\t$func", 2138 [(ARMcall tglobaladdr:$func)]>, 2139 Requires<[IsARM]>, Sched<[WriteBrL]> { 2140 let Inst{31-28} = 0b1110; 2141 bits<24> func; 2142 let Inst{23-0} = func; 2143 let DecoderMethod = "DecodeBranchImmInstruction"; 2144 } 2145 2146 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func), 2147 IIC_Br, "bl", "\t$func", 2148 [(ARMcall_pred tglobaladdr:$func)]>, 2149 Requires<[IsARM]>, Sched<[WriteBrL]> { 2150 bits<24> func; 2151 let Inst{23-0} = func; 2152 let DecoderMethod = "DecodeBranchImmInstruction"; 2153 } 2154 2155 // ARMv5T and above 2156 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, 2157 IIC_Br, "blx\t$func", 2158 [(ARMcall GPR:$func)]>, 2159 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2160 bits<4> func; 2161 let Inst{31-4} = 0b1110000100101111111111110011; 2162 let Inst{3-0} = func; 2163 } 2164 2165 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, 2166 IIC_Br, "blx", "\t$func", 2167 [(ARMcall_pred GPR:$func)]>, 2168 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2169 bits<4> func; 2170 let Inst{27-4} = 0b000100101111111111110011; 2171 let Inst{3-0} = func; 2172 } 2173 2174 // ARMv4T 2175 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 2176 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2177 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2178 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>; 2179 2180 // ARMv4 2181 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2182 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2183 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 2184 2185 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 2186 // return stack predictor. 2187 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func), 2188 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 2189 Requires<[IsARM]>, Sched<[WriteBr]>; 2190} 2191 2192let isBranch = 1, isTerminator = 1 in { 2193 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 2194 // a two-value operand where a dag node expects two operands. :( 2195 def Bcc : ABI<0b1010, (outs), (ins br_target:$target), 2196 IIC_Br, "b", "\t$target", 2197 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>, 2198 Sched<[WriteBr]> { 2199 bits<24> target; 2200 let Inst{23-0} = target; 2201 let DecoderMethod = "DecodeBranchImmInstruction"; 2202 } 2203 2204 let isBarrier = 1 in { 2205 // B is "predicable" since it's just a Bcc with an 'always' condition. 2206 let isPredicable = 1 in 2207 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 2208 // should be sufficient. 2209 // FIXME: Is B really a Barrier? That doesn't seem right. 2210 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br, 2211 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>, 2212 Sched<[WriteBr]>; 2213 2214 let isNotDuplicable = 1, isIndirectBranch = 1 in { 2215 def BR_JTr : ARMPseudoInst<(outs), 2216 (ins GPR:$target, i32imm:$jt, i32imm:$id), 2217 0, IIC_Br, 2218 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>, 2219 Sched<[WriteBr]>; 2220 // FIXME: This shouldn't use the generic "addrmode2," but rather be split 2221 // into i12 and rs suffixed versions. 2222 def BR_JTm : ARMPseudoInst<(outs), 2223 (ins addrmode2:$target, i32imm:$jt, i32imm:$id), 2224 0, IIC_Br, 2225 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, 2226 imm:$id)]>, Sched<[WriteBrTbl]>; 2227 def BR_JTadd : ARMPseudoInst<(outs), 2228 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id), 2229 0, IIC_Br, 2230 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, 2231 imm:$id)]>, Sched<[WriteBrTbl]>; 2232 } // isNotDuplicable = 1, isIndirectBranch = 1 2233 } // isBarrier = 1 2234 2235} 2236 2237// BLX (immediate) 2238def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary, 2239 "blx\t$target", []>, 2240 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2241 let Inst{31-25} = 0b1111101; 2242 bits<25> target; 2243 let Inst{23-0} = target{24-1}; 2244 let Inst{24} = target{0}; 2245} 2246 2247// Branch and Exchange Jazelle 2248def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2249 [/* pattern left blank */]>, Sched<[WriteBr]> { 2250 bits<4> func; 2251 let Inst{23-20} = 0b0010; 2252 let Inst{19-8} = 0xfff; 2253 let Inst{7-4} = 0b0010; 2254 let Inst{3-0} = func; 2255} 2256 2257// Tail calls. 2258 2259let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2260 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>, 2261 Sched<[WriteBr]>; 2262 2263 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>, 2264 Sched<[WriteBr]>; 2265 2266 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst), 2267 4, IIC_Br, [], 2268 (Bcc br_target:$dst, (ops 14, zero_reg))>, 2269 Requires<[IsARM]>, Sched<[WriteBr]>; 2270 2271 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 2272 4, IIC_Br, [], 2273 (BX GPR:$dst)>, Sched<[WriteBr]>, 2274 Requires<[IsARM]>; 2275} 2276 2277// Secure Monitor Call is a system instruction. 2278def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2279 []>, Requires<[IsARM, HasTrustZone]> { 2280 bits<4> opt; 2281 let Inst{23-4} = 0b01100000000000000111; 2282 let Inst{3-0} = opt; 2283} 2284 2285// Supervisor Call (Software Interrupt) 2286let isCall = 1, Uses = [SP] in { 2287def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>, 2288 Sched<[WriteBr]> { 2289 bits<24> svc; 2290 let Inst{23-0} = svc; 2291} 2292} 2293 2294// Store Return State 2295class SRSI<bit wb, string asm> 2296 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2297 NoItinerary, asm, "", []> { 2298 bits<5> mode; 2299 let Inst{31-28} = 0b1111; 2300 let Inst{27-25} = 0b100; 2301 let Inst{22} = 1; 2302 let Inst{21} = wb; 2303 let Inst{20} = 0; 2304 let Inst{19-16} = 0b1101; // SP 2305 let Inst{15-5} = 0b00000101000; 2306 let Inst{4-0} = mode; 2307} 2308 2309def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2310 let Inst{24-23} = 0; 2311} 2312def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2313 let Inst{24-23} = 0; 2314} 2315def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2316 let Inst{24-23} = 0b10; 2317} 2318def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2319 let Inst{24-23} = 0b10; 2320} 2321def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2322 let Inst{24-23} = 0b01; 2323} 2324def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2325 let Inst{24-23} = 0b01; 2326} 2327def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2328 let Inst{24-23} = 0b11; 2329} 2330def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2331 let Inst{24-23} = 0b11; 2332} 2333 2334def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; 2335def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; 2336 2337def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; 2338def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; 2339 2340def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; 2341def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; 2342 2343def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; 2344def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; 2345 2346// Return From Exception 2347class RFEI<bit wb, string asm> 2348 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2349 NoItinerary, asm, "", []> { 2350 bits<4> Rn; 2351 let Inst{31-28} = 0b1111; 2352 let Inst{27-25} = 0b100; 2353 let Inst{22} = 0; 2354 let Inst{21} = wb; 2355 let Inst{20} = 1; 2356 let Inst{19-16} = Rn; 2357 let Inst{15-0} = 0xa00; 2358} 2359 2360def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2361 let Inst{24-23} = 0; 2362} 2363def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2364 let Inst{24-23} = 0; 2365} 2366def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2367 let Inst{24-23} = 0b10; 2368} 2369def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2370 let Inst{24-23} = 0b10; 2371} 2372def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2373 let Inst{24-23} = 0b01; 2374} 2375def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2376 let Inst{24-23} = 0b01; 2377} 2378def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2379 let Inst{24-23} = 0b11; 2380} 2381def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2382 let Inst{24-23} = 0b11; 2383} 2384 2385//===----------------------------------------------------------------------===// 2386// Load / Store Instructions. 2387// 2388 2389// Load 2390 2391 2392defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, 2393 UnOpFrag<(load node:$Src)>>; 2394defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2395 UnOpFrag<(zextloadi8 node:$Src)>>; 2396defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, 2397 BinOpFrag<(store node:$LHS, node:$RHS)>>; 2398defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2399 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 2400 2401// Special LDR for loads from non-pc-relative constpools. 2402let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1, 2403 isReMaterializable = 1, isCodeGenOnly = 1 in 2404def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2405 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2406 []> { 2407 bits<4> Rt; 2408 bits<17> addr; 2409 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2410 let Inst{19-16} = 0b1111; 2411 let Inst{15-12} = Rt; 2412 let Inst{11-0} = addr{11-0}; // imm12 2413} 2414 2415// Loads with zero extension 2416def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2417 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2418 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2419 2420// Loads with sign extension 2421def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2422 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2423 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2424 2425def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2426 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2427 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2428 2429let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { 2430 // Load doubleword 2431 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr), 2432 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>, 2433 Requires<[IsARM, HasV5TE]>; 2434} 2435 2436def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2437 NoItinerary, "lda", "\t$Rt, $addr", []>; 2438def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2439 NoItinerary, "ldab", "\t$Rt, $addr", []>; 2440def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2441 NoItinerary, "ldah", "\t$Rt, $addr", []>; 2442 2443// Indexed loads 2444multiclass AI2_ldridx<bit isByte, string opc, 2445 InstrItinClass iii, InstrItinClass iir> { 2446 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2447 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii, 2448 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2449 bits<17> addr; 2450 let Inst{25} = 0; 2451 let Inst{23} = addr{12}; 2452 let Inst{19-16} = addr{16-13}; 2453 let Inst{11-0} = addr{11-0}; 2454 let DecoderMethod = "DecodeLDRPreImm"; 2455 } 2456 2457 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2458 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2459 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2460 bits<17> addr; 2461 let Inst{25} = 1; 2462 let Inst{23} = addr{12}; 2463 let Inst{19-16} = addr{16-13}; 2464 let Inst{11-0} = addr{11-0}; 2465 let Inst{4} = 0; 2466 let DecoderMethod = "DecodeLDRPreReg"; 2467 } 2468 2469 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2470 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2471 IndexModePost, LdFrm, iir, 2472 opc, "\t$Rt, $addr, $offset", 2473 "$addr.base = $Rn_wb", []> { 2474 // {12} isAdd 2475 // {11-0} imm12/Rm 2476 bits<14> offset; 2477 bits<4> addr; 2478 let Inst{25} = 1; 2479 let Inst{23} = offset{12}; 2480 let Inst{19-16} = addr; 2481 let Inst{11-0} = offset{11-0}; 2482 let Inst{4} = 0; 2483 2484 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2485 } 2486 2487 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2488 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2489 IndexModePost, LdFrm, iii, 2490 opc, "\t$Rt, $addr, $offset", 2491 "$addr.base = $Rn_wb", []> { 2492 // {12} isAdd 2493 // {11-0} imm12/Rm 2494 bits<14> offset; 2495 bits<4> addr; 2496 let Inst{25} = 0; 2497 let Inst{23} = offset{12}; 2498 let Inst{19-16} = addr; 2499 let Inst{11-0} = offset{11-0}; 2500 2501 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2502 } 2503 2504} 2505 2506let mayLoad = 1, neverHasSideEffects = 1 in { 2507// FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or 2508// IIC_iLoad_siu depending on whether it the offset register is shifted. 2509defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2510defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2511} 2512 2513multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2514 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2515 (ins addrmode3_pre:$addr), IndexModePre, 2516 LdMiscFrm, itin, 2517 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2518 bits<14> addr; 2519 let Inst{23} = addr{8}; // U bit 2520 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2521 let Inst{19-16} = addr{12-9}; // Rn 2522 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2523 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2524 let DecoderMethod = "DecodeAddrMode3Instruction"; 2525 } 2526 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2527 (ins addr_offset_none:$addr, am3offset:$offset), 2528 IndexModePost, LdMiscFrm, itin, 2529 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2530 []> { 2531 bits<10> offset; 2532 bits<4> addr; 2533 let Inst{23} = offset{8}; // U bit 2534 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2535 let Inst{19-16} = addr; 2536 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2537 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2538 let DecoderMethod = "DecodeAddrMode3Instruction"; 2539 } 2540} 2541 2542let mayLoad = 1, neverHasSideEffects = 1 in { 2543defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2544defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2545defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2546let hasExtraDefRegAllocReq = 1 in { 2547def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2548 (ins addrmode3_pre:$addr), IndexModePre, 2549 LdMiscFrm, IIC_iLoad_d_ru, 2550 "ldrd", "\t$Rt, $Rt2, $addr!", 2551 "$addr.base = $Rn_wb", []> { 2552 bits<14> addr; 2553 let Inst{23} = addr{8}; // U bit 2554 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2555 let Inst{19-16} = addr{12-9}; // Rn 2556 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2557 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2558 let DecoderMethod = "DecodeAddrMode3Instruction"; 2559} 2560def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2561 (ins addr_offset_none:$addr, am3offset:$offset), 2562 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2563 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2564 "$addr.base = $Rn_wb", []> { 2565 bits<10> offset; 2566 bits<4> addr; 2567 let Inst{23} = offset{8}; // U bit 2568 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2569 let Inst{19-16} = addr; 2570 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2571 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2572 let DecoderMethod = "DecodeAddrMode3Instruction"; 2573} 2574} // hasExtraDefRegAllocReq = 1 2575} // mayLoad = 1, neverHasSideEffects = 1 2576 2577// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2578let mayLoad = 1, neverHasSideEffects = 1 in { 2579def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2580 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2581 IndexModePost, LdFrm, IIC_iLoad_ru, 2582 "ldrt", "\t$Rt, $addr, $offset", 2583 "$addr.base = $Rn_wb", []> { 2584 // {12} isAdd 2585 // {11-0} imm12/Rm 2586 bits<14> offset; 2587 bits<4> addr; 2588 let Inst{25} = 1; 2589 let Inst{23} = offset{12}; 2590 let Inst{21} = 1; // overwrite 2591 let Inst{19-16} = addr; 2592 let Inst{11-5} = offset{11-5}; 2593 let Inst{4} = 0; 2594 let Inst{3-0} = offset{3-0}; 2595 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2596} 2597 2598def LDRT_POST_IMM 2599 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2600 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2601 IndexModePost, LdFrm, IIC_iLoad_ru, 2602 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2603 // {12} isAdd 2604 // {11-0} imm12/Rm 2605 bits<14> offset; 2606 bits<4> addr; 2607 let Inst{25} = 0; 2608 let Inst{23} = offset{12}; 2609 let Inst{21} = 1; // overwrite 2610 let Inst{19-16} = addr; 2611 let Inst{11-0} = offset{11-0}; 2612 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2613} 2614 2615def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2616 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2617 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2618 "ldrbt", "\t$Rt, $addr, $offset", 2619 "$addr.base = $Rn_wb", []> { 2620 // {12} isAdd 2621 // {11-0} imm12/Rm 2622 bits<14> offset; 2623 bits<4> addr; 2624 let Inst{25} = 1; 2625 let Inst{23} = offset{12}; 2626 let Inst{21} = 1; // overwrite 2627 let Inst{19-16} = addr; 2628 let Inst{11-5} = offset{11-5}; 2629 let Inst{4} = 0; 2630 let Inst{3-0} = offset{3-0}; 2631 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2632} 2633 2634def LDRBT_POST_IMM 2635 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2636 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2637 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2638 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2639 // {12} isAdd 2640 // {11-0} imm12/Rm 2641 bits<14> offset; 2642 bits<4> addr; 2643 let Inst{25} = 0; 2644 let Inst{23} = offset{12}; 2645 let Inst{21} = 1; // overwrite 2646 let Inst{19-16} = addr; 2647 let Inst{11-0} = offset{11-0}; 2648 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2649} 2650 2651multiclass AI3ldrT<bits<4> op, string opc> { 2652 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 2653 (ins addr_offset_none:$addr, postidx_imm8:$offset), 2654 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2655 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2656 bits<9> offset; 2657 let Inst{23} = offset{8}; 2658 let Inst{22} = 1; 2659 let Inst{11-8} = offset{7-4}; 2660 let Inst{3-0} = offset{3-0}; 2661 } 2662 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 2663 (ins addr_offset_none:$addr, postidx_reg:$Rm), 2664 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2665 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2666 bits<5> Rm; 2667 let Inst{23} = Rm{4}; 2668 let Inst{22} = 0; 2669 let Inst{11-8} = 0; 2670 let Unpredictable{11-8} = 0b1111; 2671 let Inst{3-0} = Rm{3-0}; 2672 let DecoderMethod = "DecodeLDR"; 2673 } 2674} 2675 2676defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 2677defm LDRHT : AI3ldrT<0b1011, "ldrht">; 2678defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 2679} 2680 2681def LDRT_POST 2682 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2683 (outs GPR:$Rt)>; 2684 2685def LDRBT_POST 2686 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2687 (outs GPR:$Rt)>; 2688 2689// Store 2690 2691// Stores with truncate 2692def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 2693 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 2694 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 2695 2696// Store doubleword 2697let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { 2698 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 2699 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>, 2700 Requires<[IsARM, HasV5TE]> { 2701 let Inst{21} = 0; 2702 } 2703} 2704 2705// Indexed stores 2706multiclass AI2_stridx<bit isByte, string opc, 2707 InstrItinClass iii, InstrItinClass iir> { 2708 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2709 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre, 2710 StFrm, iii, 2711 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2712 bits<17> addr; 2713 let Inst{25} = 0; 2714 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2715 let Inst{19-16} = addr{16-13}; // Rn 2716 let Inst{11-0} = addr{11-0}; // imm12 2717 let DecoderMethod = "DecodeSTRPreImm"; 2718 } 2719 2720 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2721 (ins GPR:$Rt, ldst_so_reg:$addr), 2722 IndexModePre, StFrm, iir, 2723 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2724 bits<17> addr; 2725 let Inst{25} = 1; 2726 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2727 let Inst{19-16} = addr{16-13}; // Rn 2728 let Inst{11-0} = addr{11-0}; 2729 let Inst{4} = 0; // Inst{4} = 0 2730 let DecoderMethod = "DecodeSTRPreReg"; 2731 } 2732 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2733 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2734 IndexModePost, StFrm, iir, 2735 opc, "\t$Rt, $addr, $offset", 2736 "$addr.base = $Rn_wb", []> { 2737 // {12} isAdd 2738 // {11-0} imm12/Rm 2739 bits<14> offset; 2740 bits<4> addr; 2741 let Inst{25} = 1; 2742 let Inst{23} = offset{12}; 2743 let Inst{19-16} = addr; 2744 let Inst{11-0} = offset{11-0}; 2745 let Inst{4} = 0; 2746 2747 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2748 } 2749 2750 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2751 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2752 IndexModePost, StFrm, iii, 2753 opc, "\t$Rt, $addr, $offset", 2754 "$addr.base = $Rn_wb", []> { 2755 // {12} isAdd 2756 // {11-0} imm12/Rm 2757 bits<14> offset; 2758 bits<4> addr; 2759 let Inst{25} = 0; 2760 let Inst{23} = offset{12}; 2761 let Inst{19-16} = addr; 2762 let Inst{11-0} = offset{11-0}; 2763 2764 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2765 } 2766} 2767 2768let mayStore = 1, neverHasSideEffects = 1 in { 2769// FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or 2770// IIC_iStore_siu depending on whether it the offset register is shifted. 2771defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 2772defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 2773} 2774 2775def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2776 am2offset_reg:$offset), 2777 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 2778 am2offset_reg:$offset)>; 2779def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2780 am2offset_imm:$offset), 2781 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2782 am2offset_imm:$offset)>; 2783def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2784 am2offset_reg:$offset), 2785 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 2786 am2offset_reg:$offset)>; 2787def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2788 am2offset_imm:$offset), 2789 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2790 am2offset_imm:$offset)>; 2791 2792// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 2793// put the patterns on the instruction definitions directly as ISel wants 2794// the address base and offset to be separate operands, not a single 2795// complex operand like we represent the instructions themselves. The 2796// pseudos map between the two. 2797let usesCustomInserter = 1, 2798 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 2799def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2800 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 2801 4, IIC_iStore_ru, 2802 [(set GPR:$Rn_wb, 2803 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 2804def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2805 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 2806 4, IIC_iStore_ru, 2807 [(set GPR:$Rn_wb, 2808 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 2809def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2810 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 2811 4, IIC_iStore_ru, 2812 [(set GPR:$Rn_wb, 2813 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 2814def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2815 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 2816 4, IIC_iStore_ru, 2817 [(set GPR:$Rn_wb, 2818 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 2819def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2820 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 2821 4, IIC_iStore_ru, 2822 [(set GPR:$Rn_wb, 2823 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 2824} 2825 2826 2827 2828def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 2829 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, 2830 StMiscFrm, IIC_iStore_bh_ru, 2831 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2832 bits<14> addr; 2833 let Inst{23} = addr{8}; // U bit 2834 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2835 let Inst{19-16} = addr{12-9}; // Rn 2836 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2837 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2838 let DecoderMethod = "DecodeAddrMode3Instruction"; 2839} 2840 2841def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 2842 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 2843 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 2844 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2845 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 2846 addr_offset_none:$addr, 2847 am3offset:$offset))]> { 2848 bits<10> offset; 2849 bits<4> addr; 2850 let Inst{23} = offset{8}; // U bit 2851 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2852 let Inst{19-16} = addr; 2853 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2854 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2855 let DecoderMethod = "DecodeAddrMode3Instruction"; 2856} 2857 2858let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { 2859def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 2860 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr), 2861 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 2862 "strd", "\t$Rt, $Rt2, $addr!", 2863 "$addr.base = $Rn_wb", []> { 2864 bits<14> addr; 2865 let Inst{23} = addr{8}; // U bit 2866 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2867 let Inst{19-16} = addr{12-9}; // Rn 2868 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2869 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2870 let DecoderMethod = "DecodeAddrMode3Instruction"; 2871} 2872 2873def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 2874 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 2875 am3offset:$offset), 2876 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 2877 "strd", "\t$Rt, $Rt2, $addr, $offset", 2878 "$addr.base = $Rn_wb", []> { 2879 bits<10> offset; 2880 bits<4> addr; 2881 let Inst{23} = offset{8}; // U bit 2882 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2883 let Inst{19-16} = addr; 2884 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2885 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2886 let DecoderMethod = "DecodeAddrMode3Instruction"; 2887} 2888} // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 2889 2890// STRT, STRBT, and STRHT 2891 2892def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 2893 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2894 IndexModePost, StFrm, IIC_iStore_bh_ru, 2895 "strbt", "\t$Rt, $addr, $offset", 2896 "$addr.base = $Rn_wb", []> { 2897 // {12} isAdd 2898 // {11-0} imm12/Rm 2899 bits<14> offset; 2900 bits<4> addr; 2901 let Inst{25} = 1; 2902 let Inst{23} = offset{12}; 2903 let Inst{21} = 1; // overwrite 2904 let Inst{19-16} = addr; 2905 let Inst{11-5} = offset{11-5}; 2906 let Inst{4} = 0; 2907 let Inst{3-0} = offset{3-0}; 2908 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2909} 2910 2911def STRBT_POST_IMM 2912 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 2913 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2914 IndexModePost, StFrm, IIC_iStore_bh_ru, 2915 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2916 // {12} isAdd 2917 // {11-0} imm12/Rm 2918 bits<14> offset; 2919 bits<4> addr; 2920 let Inst{25} = 0; 2921 let Inst{23} = offset{12}; 2922 let Inst{21} = 1; // overwrite 2923 let Inst{19-16} = addr; 2924 let Inst{11-0} = offset{11-0}; 2925 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2926} 2927 2928def STRBT_POST 2929 : ARMAsmPseudo<"strbt${q} $Rt, $addr", 2930 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 2931 2932let mayStore = 1, neverHasSideEffects = 1 in { 2933def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 2934 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2935 IndexModePost, StFrm, IIC_iStore_ru, 2936 "strt", "\t$Rt, $addr, $offset", 2937 "$addr.base = $Rn_wb", []> { 2938 // {12} isAdd 2939 // {11-0} imm12/Rm 2940 bits<14> offset; 2941 bits<4> addr; 2942 let Inst{25} = 1; 2943 let Inst{23} = offset{12}; 2944 let Inst{21} = 1; // overwrite 2945 let Inst{19-16} = addr; 2946 let Inst{11-5} = offset{11-5}; 2947 let Inst{4} = 0; 2948 let Inst{3-0} = offset{3-0}; 2949 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2950} 2951 2952def STRT_POST_IMM 2953 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 2954 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2955 IndexModePost, StFrm, IIC_iStore_ru, 2956 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2957 // {12} isAdd 2958 // {11-0} imm12/Rm 2959 bits<14> offset; 2960 bits<4> addr; 2961 let Inst{25} = 0; 2962 let Inst{23} = offset{12}; 2963 let Inst{21} = 1; // overwrite 2964 let Inst{19-16} = addr; 2965 let Inst{11-0} = offset{11-0}; 2966 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2967} 2968} 2969 2970def STRT_POST 2971 : ARMAsmPseudo<"strt${q} $Rt, $addr", 2972 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 2973 2974multiclass AI3strT<bits<4> op, string opc> { 2975 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 2976 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 2977 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 2978 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2979 bits<9> offset; 2980 let Inst{23} = offset{8}; 2981 let Inst{22} = 1; 2982 let Inst{11-8} = offset{7-4}; 2983 let Inst{3-0} = offset{3-0}; 2984 } 2985 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 2986 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 2987 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 2988 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2989 bits<5> Rm; 2990 let Inst{23} = Rm{4}; 2991 let Inst{22} = 0; 2992 let Inst{11-8} = 0; 2993 let Inst{3-0} = Rm{3-0}; 2994 } 2995} 2996 2997 2998defm STRHT : AI3strT<0b1011, "strht">; 2999 3000def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3001 NoItinerary, "stl", "\t$Rt, $addr", []>; 3002def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3003 NoItinerary, "stlb", "\t$Rt, $addr", []>; 3004def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3005 NoItinerary, "stlh", "\t$Rt, $addr", []>; 3006 3007//===----------------------------------------------------------------------===// 3008// Load / store multiple Instructions. 3009// 3010 3011multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 3012 InstrItinClass itin, InstrItinClass itin_upd> { 3013 // IA is the default, so no need for an explicit suffix on the 3014 // mnemonic here. Without it is the canonical spelling. 3015 def IA : 3016 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3017 IndexModeNone, f, itin, 3018 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 3019 let Inst{24-23} = 0b01; // Increment After 3020 let Inst{22} = P_bit; 3021 let Inst{21} = 0; // No writeback 3022 let Inst{20} = L_bit; 3023 } 3024 def IA_UPD : 3025 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3026 IndexModeUpd, f, itin_upd, 3027 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3028 let Inst{24-23} = 0b01; // Increment After 3029 let Inst{22} = P_bit; 3030 let Inst{21} = 1; // Writeback 3031 let Inst{20} = L_bit; 3032 3033 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3034 } 3035 def DA : 3036 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3037 IndexModeNone, f, itin, 3038 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 3039 let Inst{24-23} = 0b00; // Decrement After 3040 let Inst{22} = P_bit; 3041 let Inst{21} = 0; // No writeback 3042 let Inst{20} = L_bit; 3043 } 3044 def DA_UPD : 3045 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3046 IndexModeUpd, f, itin_upd, 3047 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3048 let Inst{24-23} = 0b00; // Decrement After 3049 let Inst{22} = P_bit; 3050 let Inst{21} = 1; // Writeback 3051 let Inst{20} = L_bit; 3052 3053 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3054 } 3055 def DB : 3056 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3057 IndexModeNone, f, itin, 3058 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 3059 let Inst{24-23} = 0b10; // Decrement Before 3060 let Inst{22} = P_bit; 3061 let Inst{21} = 0; // No writeback 3062 let Inst{20} = L_bit; 3063 } 3064 def DB_UPD : 3065 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3066 IndexModeUpd, f, itin_upd, 3067 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3068 let Inst{24-23} = 0b10; // Decrement Before 3069 let Inst{22} = P_bit; 3070 let Inst{21} = 1; // Writeback 3071 let Inst{20} = L_bit; 3072 3073 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3074 } 3075 def IB : 3076 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3077 IndexModeNone, f, itin, 3078 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 3079 let Inst{24-23} = 0b11; // Increment Before 3080 let Inst{22} = P_bit; 3081 let Inst{21} = 0; // No writeback 3082 let Inst{20} = L_bit; 3083 } 3084 def IB_UPD : 3085 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3086 IndexModeUpd, f, itin_upd, 3087 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3088 let Inst{24-23} = 0b11; // Increment Before 3089 let Inst{22} = P_bit; 3090 let Inst{21} = 1; // Writeback 3091 let Inst{20} = L_bit; 3092 3093 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3094 } 3095} 3096 3097let neverHasSideEffects = 1 in { 3098 3099let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3100defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 3101 IIC_iLoad_mu>; 3102 3103let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3104defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 3105 IIC_iStore_mu>; 3106 3107} // neverHasSideEffects 3108 3109// FIXME: remove when we have a way to marking a MI with these properties. 3110// FIXME: Should pc be an implicit operand like PICADD, etc? 3111let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3112 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3113def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3114 reglist:$regs, variable_ops), 3115 4, IIC_iLoad_mBr, [], 3116 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3117 RegConstraint<"$Rn = $wb">; 3118 3119let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3120defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 3121 IIC_iLoad_mu>; 3122 3123let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3124defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 3125 IIC_iStore_mu>; 3126 3127 3128 3129//===----------------------------------------------------------------------===// 3130// Move Instructions. 3131// 3132 3133let neverHasSideEffects = 1 in 3134def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 3135 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3136 bits<4> Rd; 3137 bits<4> Rm; 3138 3139 let Inst{19-16} = 0b0000; 3140 let Inst{11-4} = 0b00000000; 3141 let Inst{25} = 0; 3142 let Inst{3-0} = Rm; 3143 let Inst{15-12} = Rd; 3144} 3145 3146// A version for the smaller set of tail call registers. 3147let neverHasSideEffects = 1 in 3148def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 3149 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3150 bits<4> Rd; 3151 bits<4> Rm; 3152 3153 let Inst{11-4} = 0b00000000; 3154 let Inst{25} = 0; 3155 let Inst{3-0} = Rm; 3156 let Inst{15-12} = Rd; 3157} 3158 3159def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 3160 DPSoRegRegFrm, IIC_iMOVsr, 3161 "mov", "\t$Rd, $src", 3162 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP, 3163 Sched<[WriteALU]> { 3164 bits<4> Rd; 3165 bits<12> src; 3166 let Inst{15-12} = Rd; 3167 let Inst{19-16} = 0b0000; 3168 let Inst{11-8} = src{11-8}; 3169 let Inst{7} = 0; 3170 let Inst{6-5} = src{6-5}; 3171 let Inst{4} = 1; 3172 let Inst{3-0} = src{3-0}; 3173 let Inst{25} = 0; 3174} 3175 3176def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 3177 DPSoRegImmFrm, IIC_iMOVsr, 3178 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 3179 UnaryDP, Sched<[WriteALU]> { 3180 bits<4> Rd; 3181 bits<12> src; 3182 let Inst{15-12} = Rd; 3183 let Inst{19-16} = 0b0000; 3184 let Inst{11-5} = src{11-5}; 3185 let Inst{4} = 0; 3186 let Inst{3-0} = src{3-0}; 3187 let Inst{25} = 0; 3188} 3189 3190let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3191def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi, 3192 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP, 3193 Sched<[WriteALU]> { 3194 bits<4> Rd; 3195 bits<12> imm; 3196 let Inst{25} = 1; 3197 let Inst{15-12} = Rd; 3198 let Inst{19-16} = 0b0000; 3199 let Inst{11-0} = imm; 3200} 3201 3202let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3203def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 3204 DPFrm, IIC_iMOVi, 3205 "movw", "\t$Rd, $imm", 3206 [(set GPR:$Rd, imm0_65535:$imm)]>, 3207 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> { 3208 bits<4> Rd; 3209 bits<16> imm; 3210 let Inst{15-12} = Rd; 3211 let Inst{11-0} = imm{11-0}; 3212 let Inst{19-16} = imm{15-12}; 3213 let Inst{20} = 0; 3214 let Inst{25} = 1; 3215 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3216} 3217 3218def : InstAlias<"mov${p} $Rd, $imm", 3219 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>, 3220 Requires<[IsARM]>; 3221 3222def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3223 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3224 Sched<[WriteALU]>; 3225 3226let Constraints = "$src = $Rd" in { 3227def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 3228 (ins GPR:$src, imm0_65535_expr:$imm), 3229 DPFrm, IIC_iMOVi, 3230 "movt", "\t$Rd, $imm", 3231 [(set GPRnopc:$Rd, 3232 (or (and GPR:$src, 0xffff), 3233 lo16AllZero:$imm))]>, UnaryDP, 3234 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> { 3235 bits<4> Rd; 3236 bits<16> imm; 3237 let Inst{15-12} = Rd; 3238 let Inst{11-0} = imm{11-0}; 3239 let Inst{19-16} = imm{15-12}; 3240 let Inst{20} = 0; 3241 let Inst{25} = 1; 3242 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3243} 3244 3245def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3246 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3247 Sched<[WriteALU]>; 3248 3249} // Constraints 3250 3251def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 3252 Requires<[IsARM, HasV6T2]>; 3253 3254let Uses = [CPSR] in 3255def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 3256 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 3257 Requires<[IsARM]>, Sched<[WriteALU]>; 3258 3259// These aren't really mov instructions, but we have to define them this way 3260// due to flag operands. 3261 3262let Defs = [CPSR] in { 3263def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3264 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3265 Sched<[WriteALU]>, Requires<[IsARM]>; 3266def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3267 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3268 Sched<[WriteALU]>, Requires<[IsARM]>; 3269} 3270 3271//===----------------------------------------------------------------------===// 3272// Extend Instructions. 3273// 3274 3275// Sign extenders 3276 3277def SXTB : AI_ext_rrot<0b01101010, 3278 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3279def SXTH : AI_ext_rrot<0b01101011, 3280 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3281 3282def SXTAB : AI_exta_rrot<0b01101010, 3283 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3284def SXTAH : AI_exta_rrot<0b01101011, 3285 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3286 3287def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3288 3289def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3290 3291// Zero extenders 3292 3293let AddedComplexity = 16 in { 3294def UXTB : AI_ext_rrot<0b01101110, 3295 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3296def UXTH : AI_ext_rrot<0b01101111, 3297 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3298def UXTB16 : AI_ext_rrot<0b01101100, 3299 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3300 3301// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3302// The transformation should probably be done as a combiner action 3303// instead so we can include a check for masking back in the upper 3304// eight bits of the source into the lower eight bits of the result. 3305//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3306// (UXTB16r_rot GPR:$Src, 3)>; 3307def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3308 (UXTB16 GPR:$Src, 1)>; 3309 3310def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3311 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3312def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3313 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3314} 3315 3316// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3317def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3318 3319 3320def SBFX : I<(outs GPRnopc:$Rd), 3321 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3322 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3323 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3324 Requires<[IsARM, HasV6T2]> { 3325 bits<4> Rd; 3326 bits<4> Rn; 3327 bits<5> lsb; 3328 bits<5> width; 3329 let Inst{27-21} = 0b0111101; 3330 let Inst{6-4} = 0b101; 3331 let Inst{20-16} = width; 3332 let Inst{15-12} = Rd; 3333 let Inst{11-7} = lsb; 3334 let Inst{3-0} = Rn; 3335} 3336 3337def UBFX : I<(outs GPRnopc:$Rd), 3338 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3339 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3340 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3341 Requires<[IsARM, HasV6T2]> { 3342 bits<4> Rd; 3343 bits<4> Rn; 3344 bits<5> lsb; 3345 bits<5> width; 3346 let Inst{27-21} = 0b0111111; 3347 let Inst{6-4} = 0b101; 3348 let Inst{20-16} = width; 3349 let Inst{15-12} = Rd; 3350 let Inst{11-7} = lsb; 3351 let Inst{3-0} = Rn; 3352} 3353 3354//===----------------------------------------------------------------------===// 3355// Arithmetic Instructions. 3356// 3357 3358defm ADD : AsI1_bin_irs<0b0100, "add", 3359 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3360 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 3361defm SUB : AsI1_bin_irs<0b0010, "sub", 3362 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3363 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 3364 3365// ADD and SUB with 's' bit set. 3366// 3367// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3368// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3369// AdjustInstrPostInstrSelection where we determine whether or not to 3370// set the "s" bit based on CPSR liveness. 3371// 3372// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3373// support for an optional CPSR definition that corresponds to the DAG 3374// node's second value. We can then eliminate the implicit def of CPSR. 3375defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3376 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>; 3377defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3378 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 3379 3380defm ADC : AI1_adde_sube_irs<0b0101, "adc", 3381 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>; 3382defm SBC : AI1_adde_sube_irs<0b0110, "sbc", 3383 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; 3384 3385defm RSB : AsI1_rbin_irs<0b0011, "rsb", 3386 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3387 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 3388 3389// FIXME: Eliminate them if we can write def : Pat patterns which defines 3390// CPSR and the implicit def of CPSR is not needed. 3391defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3392 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 3393 3394defm RSC : AI1_rsc_irs<0b0111, "rsc", 3395 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; 3396 3397// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3398// The assume-no-carry-in form uses the negation of the input since add/sub 3399// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3400// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3401// details. 3402def : ARMPat<(add GPR:$src, so_imm_neg:$imm), 3403 (SUBri GPR:$src, so_imm_neg:$imm)>; 3404def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm), 3405 (SUBSri GPR:$src, so_imm_neg:$imm)>; 3406 3407def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), 3408 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3409 Requires<[IsARM, HasV6T2]>; 3410def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), 3411 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3412 Requires<[IsARM, HasV6T2]>; 3413 3414// The with-carry-in form matches bitwise not instead of the negation. 3415// Effectively, the inverse interpretation of the carry flag already accounts 3416// for part of the negation. 3417def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR), 3418 (SBCri GPR:$src, so_imm_not:$imm)>; 3419def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), 3420 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>; 3421 3422// Note: These are implemented in C++ code, because they have to generate 3423// ADD/SUBrs instructions, which use a complex pattern that a xform function 3424// cannot produce. 3425// (mul X, 2^n+1) -> (add (X << n), X) 3426// (mul X, 2^n-1) -> (rsb X, (X << n)) 3427 3428// ARM Arithmetic Instruction 3429// GPR:$dst = GPR:$a op GPR:$b 3430class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3431 list<dag> pattern = [], 3432 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3433 string asm = "\t$Rd, $Rn, $Rm"> 3434 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>, 3435 Sched<[WriteALU, ReadALU, ReadALU]> { 3436 bits<4> Rn; 3437 bits<4> Rd; 3438 bits<4> Rm; 3439 let Inst{27-20} = op27_20; 3440 let Inst{11-4} = op11_4; 3441 let Inst{19-16} = Rn; 3442 let Inst{15-12} = Rd; 3443 let Inst{3-0} = Rm; 3444 3445 let Unpredictable{11-8} = 0b1111; 3446} 3447 3448// Saturating add/subtract 3449 3450let DecoderMethod = "DecodeQADDInstruction" in 3451def QADD : AAI<0b00010000, 0b00000101, "qadd", 3452 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))], 3453 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">; 3454 3455def QSUB : AAI<0b00010010, 0b00000101, "qsub", 3456 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))], 3457 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">; 3458def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], 3459 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3460 "\t$Rd, $Rm, $Rn">; 3461def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], 3462 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3463 "\t$Rd, $Rm, $Rn">; 3464 3465def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">; 3466def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">; 3467def QASX : AAI<0b01100010, 0b11110011, "qasx">; 3468def QSAX : AAI<0b01100010, 0b11110101, "qsax">; 3469def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">; 3470def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">; 3471def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">; 3472def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">; 3473def UQASX : AAI<0b01100110, 0b11110011, "uqasx">; 3474def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">; 3475def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">; 3476def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">; 3477 3478// Signed/Unsigned add/subtract 3479 3480def SASX : AAI<0b01100001, 0b11110011, "sasx">; 3481def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">; 3482def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">; 3483def SSAX : AAI<0b01100001, 0b11110101, "ssax">; 3484def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">; 3485def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">; 3486def UASX : AAI<0b01100101, 0b11110011, "uasx">; 3487def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">; 3488def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">; 3489def USAX : AAI<0b01100101, 0b11110101, "usax">; 3490def USUB16 : AAI<0b01100101, 0b11110111, "usub16">; 3491def USUB8 : AAI<0b01100101, 0b11111111, "usub8">; 3492 3493// Signed/Unsigned halving add/subtract 3494 3495def SHASX : AAI<0b01100011, 0b11110011, "shasx">; 3496def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">; 3497def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">; 3498def SHSAX : AAI<0b01100011, 0b11110101, "shsax">; 3499def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">; 3500def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">; 3501def UHASX : AAI<0b01100111, 0b11110011, "uhasx">; 3502def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">; 3503def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">; 3504def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">; 3505def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">; 3506def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">; 3507 3508// Unsigned Sum of Absolute Differences [and Accumulate]. 3509 3510def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3511 MulFrm /* for convenience */, NoItinerary, "usad8", 3512 "\t$Rd, $Rn, $Rm", []>, 3513 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> { 3514 bits<4> Rd; 3515 bits<4> Rn; 3516 bits<4> Rm; 3517 let Inst{27-20} = 0b01111000; 3518 let Inst{15-12} = 0b1111; 3519 let Inst{7-4} = 0b0001; 3520 let Inst{19-16} = Rd; 3521 let Inst{11-8} = Rm; 3522 let Inst{3-0} = Rn; 3523} 3524def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3525 MulFrm /* for convenience */, NoItinerary, "usada8", 3526 "\t$Rd, $Rn, $Rm, $Ra", []>, 3527 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{ 3528 bits<4> Rd; 3529 bits<4> Rn; 3530 bits<4> Rm; 3531 bits<4> Ra; 3532 let Inst{27-20} = 0b01111000; 3533 let Inst{7-4} = 0b0001; 3534 let Inst{19-16} = Rd; 3535 let Inst{15-12} = Ra; 3536 let Inst{11-8} = Rm; 3537 let Inst{3-0} = Rn; 3538} 3539 3540// Signed/Unsigned saturate 3541 3542def SSAT : AI<(outs GPRnopc:$Rd), 3543 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3544 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> { 3545 bits<4> Rd; 3546 bits<5> sat_imm; 3547 bits<4> Rn; 3548 bits<8> sh; 3549 let Inst{27-21} = 0b0110101; 3550 let Inst{5-4} = 0b01; 3551 let Inst{20-16} = sat_imm; 3552 let Inst{15-12} = Rd; 3553 let Inst{11-7} = sh{4-0}; 3554 let Inst{6} = sh{5}; 3555 let Inst{3-0} = Rn; 3556} 3557 3558def SSAT16 : AI<(outs GPRnopc:$Rd), 3559 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 3560 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> { 3561 bits<4> Rd; 3562 bits<4> sat_imm; 3563 bits<4> Rn; 3564 let Inst{27-20} = 0b01101010; 3565 let Inst{11-4} = 0b11110011; 3566 let Inst{15-12} = Rd; 3567 let Inst{19-16} = sat_imm; 3568 let Inst{3-0} = Rn; 3569} 3570 3571def USAT : AI<(outs GPRnopc:$Rd), 3572 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3573 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> { 3574 bits<4> Rd; 3575 bits<5> sat_imm; 3576 bits<4> Rn; 3577 bits<8> sh; 3578 let Inst{27-21} = 0b0110111; 3579 let Inst{5-4} = 0b01; 3580 let Inst{15-12} = Rd; 3581 let Inst{11-7} = sh{4-0}; 3582 let Inst{6} = sh{5}; 3583 let Inst{20-16} = sat_imm; 3584 let Inst{3-0} = Rn; 3585} 3586 3587def USAT16 : AI<(outs GPRnopc:$Rd), 3588 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 3589 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> { 3590 bits<4> Rd; 3591 bits<4> sat_imm; 3592 bits<4> Rn; 3593 let Inst{27-20} = 0b01101110; 3594 let Inst{11-4} = 0b11110011; 3595 let Inst{15-12} = Rd; 3596 let Inst{19-16} = sat_imm; 3597 let Inst{3-0} = Rn; 3598} 3599 3600def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos), 3601 (SSAT imm:$pos, GPRnopc:$a, 0)>; 3602def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos), 3603 (USAT imm:$pos, GPRnopc:$a, 0)>; 3604 3605//===----------------------------------------------------------------------===// 3606// Bitwise Instructions. 3607// 3608 3609defm AND : AsI1_bin_irs<0b0000, "and", 3610 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3611 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 3612defm ORR : AsI1_bin_irs<0b1100, "orr", 3613 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3614 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 3615defm EOR : AsI1_bin_irs<0b0001, "eor", 3616 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3617 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 3618defm BIC : AsI1_bin_irs<0b1110, "bic", 3619 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3620 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 3621 3622// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 3623// like in the actual instruction encoding. The complexity of mapping the mask 3624// to the lsb/msb pair should be handled by ISel, not encapsulated in the 3625// instruction description. 3626def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 3627 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3628 "bfc", "\t$Rd, $imm", "$src = $Rd", 3629 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 3630 Requires<[IsARM, HasV6T2]> { 3631 bits<4> Rd; 3632 bits<10> imm; 3633 let Inst{27-21} = 0b0111110; 3634 let Inst{6-0} = 0b0011111; 3635 let Inst{15-12} = Rd; 3636 let Inst{11-7} = imm{4-0}; // lsb 3637 let Inst{20-16} = imm{9-5}; // msb 3638} 3639 3640// A8.6.18 BFI - Bitfield insert (Encoding A1) 3641def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 3642 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3643 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 3644 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 3645 bf_inv_mask_imm:$imm))]>, 3646 Requires<[IsARM, HasV6T2]> { 3647 bits<4> Rd; 3648 bits<4> Rn; 3649 bits<10> imm; 3650 let Inst{27-21} = 0b0111110; 3651 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 3652 let Inst{15-12} = Rd; 3653 let Inst{11-7} = imm{4-0}; // lsb 3654 let Inst{20-16} = imm{9-5}; // width 3655 let Inst{3-0} = Rn; 3656} 3657 3658def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 3659 "mvn", "\t$Rd, $Rm", 3660 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> { 3661 bits<4> Rd; 3662 bits<4> Rm; 3663 let Inst{25} = 0; 3664 let Inst{19-16} = 0b0000; 3665 let Inst{11-4} = 0b00000000; 3666 let Inst{15-12} = Rd; 3667 let Inst{3-0} = Rm; 3668} 3669def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 3670 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3671 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP, 3672 Sched<[WriteALU]> { 3673 bits<4> Rd; 3674 bits<12> shift; 3675 let Inst{25} = 0; 3676 let Inst{19-16} = 0b0000; 3677 let Inst{15-12} = Rd; 3678 let Inst{11-5} = shift{11-5}; 3679 let Inst{4} = 0; 3680 let Inst{3-0} = shift{3-0}; 3681} 3682def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift), 3683 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3684 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP, 3685 Sched<[WriteALU]> { 3686 bits<4> Rd; 3687 bits<12> shift; 3688 let Inst{25} = 0; 3689 let Inst{19-16} = 0b0000; 3690 let Inst{15-12} = Rd; 3691 let Inst{11-8} = shift{11-8}; 3692 let Inst{7} = 0; 3693 let Inst{6-5} = shift{6-5}; 3694 let Inst{4} = 1; 3695 let Inst{3-0} = shift{3-0}; 3696} 3697let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3698def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, 3699 IIC_iMVNi, "mvn", "\t$Rd, $imm", 3700 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> { 3701 bits<4> Rd; 3702 bits<12> imm; 3703 let Inst{25} = 1; 3704 let Inst{19-16} = 0b0000; 3705 let Inst{15-12} = Rd; 3706 let Inst{11-0} = imm; 3707} 3708 3709def : ARMPat<(and GPR:$src, so_imm_not:$imm), 3710 (BICri GPR:$src, so_imm_not:$imm)>; 3711 3712//===----------------------------------------------------------------------===// 3713// Multiply Instructions. 3714// 3715class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3716 string opc, string asm, list<dag> pattern> 3717 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3718 bits<4> Rd; 3719 bits<4> Rm; 3720 bits<4> Rn; 3721 let Inst{19-16} = Rd; 3722 let Inst{11-8} = Rm; 3723 let Inst{3-0} = Rn; 3724} 3725class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3726 string opc, string asm, list<dag> pattern> 3727 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3728 bits<4> RdLo; 3729 bits<4> RdHi; 3730 bits<4> Rm; 3731 bits<4> Rn; 3732 let Inst{19-16} = RdHi; 3733 let Inst{15-12} = RdLo; 3734 let Inst{11-8} = Rm; 3735 let Inst{3-0} = Rn; 3736} 3737class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3738 string opc, string asm, list<dag> pattern> 3739 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3740 bits<4> RdLo; 3741 bits<4> RdHi; 3742 bits<4> Rm; 3743 bits<4> Rn; 3744 let Inst{19-16} = RdHi; 3745 let Inst{15-12} = RdLo; 3746 let Inst{11-8} = Rm; 3747 let Inst{3-0} = Rn; 3748} 3749 3750// FIXME: The v5 pseudos are only necessary for the additional Constraint 3751// property. Remove them when it's possible to add those properties 3752// on an individual MachineInstr, not just an instruction description. 3753let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { 3754def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), 3755 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3756 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 3757 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 3758 Requires<[IsARM, HasV6]> { 3759 let Inst{15-12} = 0b0000; 3760 let Unpredictable{15-12} = 0b1111; 3761} 3762 3763let Constraints = "@earlyclobber $Rd" in 3764def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 3765 pred:$p, cc_out:$s), 3766 4, IIC_iMUL32, 3767 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 3768 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 3769 Requires<[IsARM, NoV6, UseMulOps]>; 3770} 3771 3772def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd), 3773 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra), 3774 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 3775 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>, 3776 Requires<[IsARM, HasV6, UseMulOps]> { 3777 bits<4> Ra; 3778 let Inst{15-12} = Ra; 3779} 3780 3781let Constraints = "@earlyclobber $Rd" in 3782def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd), 3783 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 3784 pred:$p, cc_out:$s), 4, IIC_iMAC32, 3785 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))], 3786 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>, 3787 Requires<[IsARM, NoV6]>; 3788 3789def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3790 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 3791 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 3792 Requires<[IsARM, HasV6T2, UseMulOps]> { 3793 bits<4> Rd; 3794 bits<4> Rm; 3795 bits<4> Rn; 3796 bits<4> Ra; 3797 let Inst{19-16} = Rd; 3798 let Inst{15-12} = Ra; 3799 let Inst{11-8} = Rm; 3800 let Inst{3-0} = Rn; 3801} 3802 3803// Extra precision multiplies with low / high results 3804let neverHasSideEffects = 1 in { 3805let isCommutable = 1 in { 3806def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 3807 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 3808 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3809 Requires<[IsARM, HasV6]>; 3810 3811def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 3812 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 3813 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3814 Requires<[IsARM, HasV6]>; 3815 3816let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 3817def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3818 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3819 4, IIC_iMUL64, [], 3820 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3821 Requires<[IsARM, NoV6]>; 3822 3823def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3824 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3825 4, IIC_iMUL64, [], 3826 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3827 Requires<[IsARM, NoV6]>; 3828} 3829} 3830 3831// Multiply + accumulate 3832def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 3833 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3834 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3835 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3836def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 3837 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3838 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3839 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3840 3841def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 3842 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64, 3843 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3844 Requires<[IsARM, HasV6]> { 3845 bits<4> RdLo; 3846 bits<4> RdHi; 3847 bits<4> Rm; 3848 bits<4> Rn; 3849 let Inst{19-16} = RdHi; 3850 let Inst{15-12} = RdLo; 3851 let Inst{11-8} = Rm; 3852 let Inst{3-0} = Rn; 3853} 3854 3855let Constraints = 3856 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 3857def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3858 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 3859 4, IIC_iMAC64, [], 3860 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 3861 pred:$p, cc_out:$s)>, 3862 Requires<[IsARM, NoV6]>; 3863def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3864 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 3865 4, IIC_iMAC64, [], 3866 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 3867 pred:$p, cc_out:$s)>, 3868 Requires<[IsARM, NoV6]>; 3869} 3870 3871} // neverHasSideEffects 3872 3873// Most significant word multiply 3874def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3875 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 3876 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 3877 Requires<[IsARM, HasV6]> { 3878 let Inst{15-12} = 0b1111; 3879} 3880 3881def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3882 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>, 3883 Requires<[IsARM, HasV6]> { 3884 let Inst{15-12} = 0b1111; 3885} 3886 3887def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 3888 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3889 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 3890 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 3891 Requires<[IsARM, HasV6, UseMulOps]>; 3892 3893def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 3894 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3895 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>, 3896 Requires<[IsARM, HasV6]>; 3897 3898def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 3899 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3900 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, 3901 Requires<[IsARM, HasV6, UseMulOps]>; 3902 3903def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 3904 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3905 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>, 3906 Requires<[IsARM, HasV6]>; 3907 3908multiclass AI_smul<string opc, PatFrag opnode> { 3909 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3910 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 3911 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16), 3912 (sext_inreg GPR:$Rm, i16)))]>, 3913 Requires<[IsARM, HasV5TE]>; 3914 3915 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3916 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 3917 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16), 3918 (sra GPR:$Rm, (i32 16))))]>, 3919 Requires<[IsARM, HasV5TE]>; 3920 3921 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3922 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 3923 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)), 3924 (sext_inreg GPR:$Rm, i16)))]>, 3925 Requires<[IsARM, HasV5TE]>; 3926 3927 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3928 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 3929 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)), 3930 (sra GPR:$Rm, (i32 16))))]>, 3931 Requires<[IsARM, HasV5TE]>; 3932 3933 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3934 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 3935 [(set GPR:$Rd, (sra (opnode GPR:$Rn, 3936 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>, 3937 Requires<[IsARM, HasV5TE]>; 3938 3939 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3940 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 3941 [(set GPR:$Rd, (sra (opnode GPR:$Rn, 3942 (sra GPR:$Rm, (i32 16))), (i32 16)))]>, 3943 Requires<[IsARM, HasV5TE]>; 3944} 3945 3946 3947multiclass AI_smla<string opc, PatFrag opnode> { 3948 let DecoderMethod = "DecodeSMLAInstruction" in { 3949 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 3950 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3951 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 3952 [(set GPRnopc:$Rd, (add GPR:$Ra, 3953 (opnode (sext_inreg GPRnopc:$Rn, i16), 3954 (sext_inreg GPRnopc:$Rm, i16))))]>, 3955 Requires<[IsARM, HasV5TE, UseMulOps]>; 3956 3957 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 3958 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3959 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 3960 [(set GPRnopc:$Rd, 3961 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16), 3962 (sra GPRnopc:$Rm, (i32 16)))))]>, 3963 Requires<[IsARM, HasV5TE, UseMulOps]>; 3964 3965 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 3966 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3967 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 3968 [(set GPRnopc:$Rd, 3969 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)), 3970 (sext_inreg GPRnopc:$Rm, i16))))]>, 3971 Requires<[IsARM, HasV5TE, UseMulOps]>; 3972 3973 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 3974 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3975 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 3976 [(set GPRnopc:$Rd, 3977 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)), 3978 (sra GPRnopc:$Rm, (i32 16)))))]>, 3979 Requires<[IsARM, HasV5TE, UseMulOps]>; 3980 3981 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 3982 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3983 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 3984 [(set GPRnopc:$Rd, 3985 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn, 3986 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>, 3987 Requires<[IsARM, HasV5TE, UseMulOps]>; 3988 3989 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 3990 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3991 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 3992 [(set GPRnopc:$Rd, 3993 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn, 3994 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>, 3995 Requires<[IsARM, HasV5TE, UseMulOps]>; 3996 } 3997} 3998 3999defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 4000defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 4001 4002// Halfword multiply accumulate long: SMLAL<x><y>. 4003def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4004 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4005 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4006 Requires<[IsARM, HasV5TE]>; 4007 4008def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4009 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4010 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4011 Requires<[IsARM, HasV5TE]>; 4012 4013def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4014 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4015 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4016 Requires<[IsARM, HasV5TE]>; 4017 4018def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4019 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4020 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4021 Requires<[IsARM, HasV5TE]>; 4022 4023// Helper class for AI_smld. 4024class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 4025 InstrItinClass itin, string opc, string asm> 4026 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> { 4027 bits<4> Rn; 4028 bits<4> Rm; 4029 let Inst{27-23} = 0b01110; 4030 let Inst{22} = long; 4031 let Inst{21-20} = 0b00; 4032 let Inst{11-8} = Rm; 4033 let Inst{7} = 0; 4034 let Inst{6} = sub; 4035 let Inst{5} = swap; 4036 let Inst{4} = 1; 4037 let Inst{3-0} = Rn; 4038} 4039class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 4040 InstrItinClass itin, string opc, string asm> 4041 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4042 bits<4> Rd; 4043 let Inst{15-12} = 0b1111; 4044 let Inst{19-16} = Rd; 4045} 4046class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 4047 InstrItinClass itin, string opc, string asm> 4048 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4049 bits<4> Ra; 4050 bits<4> Rd; 4051 let Inst{19-16} = Rd; 4052 let Inst{15-12} = Ra; 4053} 4054class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 4055 InstrItinClass itin, string opc, string asm> 4056 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4057 bits<4> RdLo; 4058 bits<4> RdHi; 4059 let Inst{19-16} = RdHi; 4060 let Inst{15-12} = RdLo; 4061} 4062 4063multiclass AI_smld<bit sub, string opc> { 4064 4065 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 4066 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4067 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">; 4068 4069 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 4070 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4071 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">; 4072 4073 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4074 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, 4075 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">; 4076 4077 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4078 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, 4079 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">; 4080 4081} 4082 4083defm SMLA : AI_smld<0, "smla">; 4084defm SMLS : AI_smld<1, "smls">; 4085 4086multiclass AI_sdml<bit sub, string opc> { 4087 4088 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 4089 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">; 4090 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 4091 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">; 4092} 4093 4094defm SMUA : AI_sdml<0, "smua">; 4095defm SMUS : AI_sdml<1, "smus">; 4096 4097//===----------------------------------------------------------------------===// 4098// Division Instructions (ARMv7-A with virtualization extension) 4099// 4100def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4101 "sdiv", "\t$Rd, $Rn, $Rm", 4102 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, 4103 Requires<[IsARM, HasDivideInARM]>; 4104 4105def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4106 "udiv", "\t$Rd, $Rn, $Rm", 4107 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, 4108 Requires<[IsARM, HasDivideInARM]>; 4109 4110//===----------------------------------------------------------------------===// 4111// Misc. Arithmetic Instructions. 4112// 4113 4114def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 4115 IIC_iUNAr, "clz", "\t$Rd, $Rm", 4116 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>, 4117 Sched<[WriteALU]>; 4118 4119def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4120 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 4121 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>, 4122 Requires<[IsARM, HasV6T2]>, 4123 Sched<[WriteALU]>; 4124 4125def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4126 IIC_iUNAr, "rev", "\t$Rd, $Rm", 4127 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>, 4128 Sched<[WriteALU]>; 4129 4130let AddedComplexity = 5 in 4131def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4132 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 4133 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 4134 Requires<[IsARM, HasV6]>, 4135 Sched<[WriteALU]>; 4136 4137def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)), 4138 (REV16 (LDRH addrmode3:$addr))>; 4139def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr), 4140 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>; 4141 4142let AddedComplexity = 5 in 4143def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4144 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 4145 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 4146 Requires<[IsARM, HasV6]>, 4147 Sched<[WriteALU]>; 4148 4149def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 4150 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 4151 (REVSH GPR:$Rm)>; 4152 4153def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 4154 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 4155 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 4156 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 4157 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 4158 0xFFFF0000)))]>, 4159 Requires<[IsARM, HasV6]>, 4160 Sched<[WriteALUsi, ReadALU]>; 4161 4162// Alternate cases for PKHBT where identities eliminate some nodes. 4163def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 4164 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 4165def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 4166 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 4167 4168// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 4169// will match the pattern below. 4170def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 4171 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 4172 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 4173 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 4174 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 4175 0xFFFF)))]>, 4176 Requires<[IsARM, HasV6]>, 4177 Sched<[WriteALUsi, ReadALU]>; 4178 4179// Alternate cases for PKHTB where identities eliminate some nodes. Note that 4180// a shift amount of 0 is *not legal* here, it is PKHBT instead. 4181// We also can not replace a srl (17..31) by an arithmetic shift we would use in 4182// pkhtb src1, src2, asr (17..31). 4183def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4184 (srl GPRnopc:$src2, imm16:$sh)), 4185 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>; 4186def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4187 (sra GPRnopc:$src2, imm16_31:$sh)), 4188 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 4189def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4190 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 4191 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 4192 4193//===----------------------------------------------------------------------===// 4194// CRC Instructions 4195// 4196// Polynomials: 4197// + CRC32{B,H,W} 0x04C11DB7 4198// + CRC32C{B,H,W} 0x1EDC6F41 4199// 4200 4201class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 4202 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, 4203 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", 4204 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, 4205 Requires<[IsARM, HasV8, HasCRC]> { 4206 bits<4> Rd; 4207 bits<4> Rn; 4208 bits<4> Rm; 4209 4210 let Inst{31-28} = 0b1110; 4211 let Inst{27-23} = 0b00010; 4212 let Inst{22-21} = sz; 4213 let Inst{20} = 0; 4214 let Inst{19-16} = Rn; 4215 let Inst{15-12} = Rd; 4216 let Inst{11-10} = 0b00; 4217 let Inst{9} = C; 4218 let Inst{8} = 0; 4219 let Inst{7-4} = 0b0100; 4220 let Inst{3-0} = Rm; 4221 4222 let Unpredictable{11-8} = 0b1101; 4223} 4224 4225def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>; 4226def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>; 4227def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>; 4228def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>; 4229def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>; 4230def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>; 4231 4232//===----------------------------------------------------------------------===// 4233// Comparison Instructions... 4234// 4235 4236defm CMP : AI1_cmp_irs<0b1010, "cmp", 4237 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, 4238 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 4239 4240// ARMcmpZ can re-use the above instruction definitions. 4241def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm), 4242 (CMPri GPR:$src, so_imm:$imm)>; 4243def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 4244 (CMPrr GPR:$src, GPR:$rhs)>; 4245def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 4246 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 4247def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 4248 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 4249 4250// CMN register-integer 4251let isCompare = 1, Defs = [CPSR] in { 4252def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi, 4253 "cmn", "\t$Rn, $imm", 4254 [(ARMcmn GPR:$Rn, so_imm:$imm)]>, 4255 Sched<[WriteCMP, ReadALU]> { 4256 bits<4> Rn; 4257 bits<12> imm; 4258 let Inst{25} = 1; 4259 let Inst{20} = 1; 4260 let Inst{19-16} = Rn; 4261 let Inst{15-12} = 0b0000; 4262 let Inst{11-0} = imm; 4263 4264 let Unpredictable{15-12} = 0b1111; 4265} 4266 4267// CMN register-register/shift 4268def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, 4269 "cmn", "\t$Rn, $Rm", 4270 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4271 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 4272 bits<4> Rn; 4273 bits<4> Rm; 4274 let isCommutable = 1; 4275 let Inst{25} = 0; 4276 let Inst{20} = 1; 4277 let Inst{19-16} = Rn; 4278 let Inst{15-12} = 0b0000; 4279 let Inst{11-4} = 0b00000000; 4280 let Inst{3-0} = Rm; 4281 4282 let Unpredictable{15-12} = 0b1111; 4283} 4284 4285def CMNzrsi : AI1<0b1011, (outs), 4286 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, 4287 "cmn", "\t$Rn, $shift", 4288 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4289 GPR:$Rn, so_reg_imm:$shift)]>, 4290 Sched<[WriteCMPsi, ReadALU]> { 4291 bits<4> Rn; 4292 bits<12> shift; 4293 let Inst{25} = 0; 4294 let Inst{20} = 1; 4295 let Inst{19-16} = Rn; 4296 let Inst{15-12} = 0b0000; 4297 let Inst{11-5} = shift{11-5}; 4298 let Inst{4} = 0; 4299 let Inst{3-0} = shift{3-0}; 4300 4301 let Unpredictable{15-12} = 0b1111; 4302} 4303 4304def CMNzrsr : AI1<0b1011, (outs), 4305 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, 4306 "cmn", "\t$Rn, $shift", 4307 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4308 GPRnopc:$Rn, so_reg_reg:$shift)]>, 4309 Sched<[WriteCMPsr, ReadALU]> { 4310 bits<4> Rn; 4311 bits<12> shift; 4312 let Inst{25} = 0; 4313 let Inst{20} = 1; 4314 let Inst{19-16} = Rn; 4315 let Inst{15-12} = 0b0000; 4316 let Inst{11-8} = shift{11-8}; 4317 let Inst{7} = 0; 4318 let Inst{6-5} = shift{6-5}; 4319 let Inst{4} = 1; 4320 let Inst{3-0} = shift{3-0}; 4321 4322 let Unpredictable{15-12} = 0b1111; 4323} 4324 4325} 4326 4327def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm), 4328 (CMNri GPR:$src, so_imm_neg:$imm)>; 4329 4330def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm), 4331 (CMNri GPR:$src, so_imm_neg:$imm)>; 4332 4333// Note that TST/TEQ don't set all the same flags that CMP does! 4334defm TST : AI1_cmp_irs<0b1000, "tst", 4335 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4336 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>; 4337defm TEQ : AI1_cmp_irs<0b1001, "teq", 4338 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4339 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 4340 4341// Pseudo i64 compares for some floating point compares. 4342let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 4343 Defs = [CPSR] in { 4344def BCCi64 : PseudoInst<(outs), 4345 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 4346 IIC_Br, 4347 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>, 4348 Sched<[WriteBr]>; 4349 4350def BCCZi64 : PseudoInst<(outs), 4351 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 4352 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>, 4353 Sched<[WriteBr]>; 4354} // usesCustomInserter 4355 4356 4357// Conditional moves 4358let neverHasSideEffects = 1 in { 4359 4360let isCommutable = 1, isSelect = 1 in 4361def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), 4362 (ins GPR:$false, GPR:$Rm, cmovpred:$p), 4363 4, IIC_iCMOVr, 4364 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, 4365 cmovpred:$p))]>, 4366 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4367 4368def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 4369 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p), 4370 4, IIC_iCMOVsr, 4371 [(set GPR:$Rd, 4372 (ARMcmov GPR:$false, so_reg_imm:$shift, 4373 cmovpred:$p))]>, 4374 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4375def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 4376 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p), 4377 4, IIC_iCMOVsr, 4378 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 4379 cmovpred:$p))]>, 4380 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4381 4382 4383let isMoveImm = 1 in 4384def MOVCCi16 4385 : ARMPseudoInst<(outs GPR:$Rd), 4386 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 4387 4, IIC_iMOVi, 4388 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, 4389 cmovpred:$p))]>, 4390 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>, 4391 Sched<[WriteALU]>; 4392 4393let isMoveImm = 1 in 4394def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 4395 (ins GPR:$false, so_imm:$imm, cmovpred:$p), 4396 4, IIC_iCMOVi, 4397 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, 4398 cmovpred:$p))]>, 4399 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4400 4401// Two instruction predicate mov immediate. 4402let isMoveImm = 1 in 4403def MOVCCi32imm 4404 : ARMPseudoInst<(outs GPR:$Rd), 4405 (ins GPR:$false, i32imm:$src, cmovpred:$p), 4406 8, IIC_iCMOVix2, 4407 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, 4408 cmovpred:$p))]>, 4409 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 4410 4411let isMoveImm = 1 in 4412def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 4413 (ins GPR:$false, so_imm:$imm, cmovpred:$p), 4414 4, IIC_iCMOVi, 4415 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, 4416 cmovpred:$p))]>, 4417 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4418 4419} // neverHasSideEffects 4420 4421 4422//===----------------------------------------------------------------------===// 4423// Atomic operations intrinsics 4424// 4425 4426def MemBarrierOptOperand : AsmOperandClass { 4427 let Name = "MemBarrierOpt"; 4428 let ParserMethod = "parseMemBarrierOptOperand"; 4429} 4430def memb_opt : Operand<i32> { 4431 let PrintMethod = "printMemBOption"; 4432 let ParserMatchClass = MemBarrierOptOperand; 4433 let DecoderMethod = "DecodeMemBarrierOption"; 4434} 4435 4436def InstSyncBarrierOptOperand : AsmOperandClass { 4437 let Name = "InstSyncBarrierOpt"; 4438 let ParserMethod = "parseInstSyncBarrierOptOperand"; 4439} 4440def instsyncb_opt : Operand<i32> { 4441 let PrintMethod = "printInstSyncBOption"; 4442 let ParserMatchClass = InstSyncBarrierOptOperand; 4443 let DecoderMethod = "DecodeInstSyncBarrierOption"; 4444} 4445 4446// Memory barriers protect the atomic sequences 4447let hasSideEffects = 1 in { 4448def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4449 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 4450 Requires<[IsARM, HasDB]> { 4451 bits<4> opt; 4452 let Inst{31-4} = 0xf57ff05; 4453 let Inst{3-0} = opt; 4454} 4455 4456def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4457 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 4458 Requires<[IsARM, HasDB]> { 4459 bits<4> opt; 4460 let Inst{31-4} = 0xf57ff04; 4461 let Inst{3-0} = opt; 4462} 4463 4464// ISB has only full system option 4465def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary, 4466 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, 4467 Requires<[IsARM, HasDB]> { 4468 bits<4> opt; 4469 let Inst{31-4} = 0xf57ff06; 4470 let Inst{3-0} = opt; 4471} 4472} 4473 4474let usesCustomInserter = 1, Defs = [CPSR] in { 4475 4476// Pseudo instruction that combines movs + predicated rsbmi 4477// to implement integer ABS 4478 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; 4479} 4480 4481let usesCustomInserter = 1 in { 4482 def COPY_STRUCT_BYVAL_I32 : PseudoInst< 4483 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), 4484 NoItinerary, 4485 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; 4486} 4487 4488def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4489 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4490}]>; 4491 4492def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4493 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4494}]>; 4495 4496def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4497 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4498}]>; 4499 4500def strex_1 : PatFrag<(ops node:$val, node:$ptr), 4501 (int_arm_strex node:$val, node:$ptr), [{ 4502 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4503}]>; 4504 4505def strex_2 : PatFrag<(ops node:$val, node:$ptr), 4506 (int_arm_strex node:$val, node:$ptr), [{ 4507 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4508}]>; 4509 4510def strex_4 : PatFrag<(ops node:$val, node:$ptr), 4511 (int_arm_strex node:$val, node:$ptr), [{ 4512 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4513}]>; 4514 4515def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4516 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4517}]>; 4518 4519def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4520 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4521}]>; 4522 4523def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4524 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4525}]>; 4526 4527def stlex_1 : PatFrag<(ops node:$val, node:$ptr), 4528 (int_arm_stlex node:$val, node:$ptr), [{ 4529 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4530}]>; 4531 4532def stlex_2 : PatFrag<(ops node:$val, node:$ptr), 4533 (int_arm_stlex node:$val, node:$ptr), [{ 4534 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4535}]>; 4536 4537def stlex_4 : PatFrag<(ops node:$val, node:$ptr), 4538 (int_arm_stlex node:$val, node:$ptr), [{ 4539 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4540}]>; 4541 4542let mayLoad = 1 in { 4543def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4544 NoItinerary, "ldrexb", "\t$Rt, $addr", 4545 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; 4546def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4547 NoItinerary, "ldrexh", "\t$Rt, $addr", 4548 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; 4549def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4550 NoItinerary, "ldrex", "\t$Rt, $addr", 4551 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; 4552let hasExtraDefRegAllocReq = 1 in 4553def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4554 NoItinerary, "ldrexd", "\t$Rt, $addr", []> { 4555 let DecoderMethod = "DecodeDoubleRegLoad"; 4556} 4557 4558def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4559 NoItinerary, "ldaexb", "\t$Rt, $addr", 4560 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>; 4561def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4562 NoItinerary, "ldaexh", "\t$Rt, $addr", 4563 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>; 4564def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4565 NoItinerary, "ldaex", "\t$Rt, $addr", 4566 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>; 4567let hasExtraDefRegAllocReq = 1 in 4568def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4569 NoItinerary, "ldaexd", "\t$Rt, $addr", []> { 4570 let DecoderMethod = "DecodeDoubleRegLoad"; 4571} 4572} 4573 4574let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 4575def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4576 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", 4577 [(set GPR:$Rd, (strex_1 GPR:$Rt, 4578 addr_offset_none:$addr))]>; 4579def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4580 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", 4581 [(set GPR:$Rd, (strex_2 GPR:$Rt, 4582 addr_offset_none:$addr))]>; 4583def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4584 NoItinerary, "strex", "\t$Rd, $Rt, $addr", 4585 [(set GPR:$Rd, (strex_4 GPR:$Rt, 4586 addr_offset_none:$addr))]>; 4587let hasExtraSrcRegAllocReq = 1 in 4588def STREXD : AIstrex<0b01, (outs GPR:$Rd), 4589 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 4590 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { 4591 let DecoderMethod = "DecodeDoubleRegStore"; 4592} 4593def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4594 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", 4595 [(set GPR:$Rd, 4596 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>; 4597def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4598 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", 4599 [(set GPR:$Rd, 4600 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>; 4601def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4602 NoItinerary, "stlex", "\t$Rd, $Rt, $addr", 4603 [(set GPR:$Rd, 4604 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>; 4605let hasExtraSrcRegAllocReq = 1 in 4606def STLEXD : AIstlex<0b01, (outs GPR:$Rd), 4607 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 4608 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { 4609 let DecoderMethod = "DecodeDoubleRegStore"; 4610} 4611} 4612 4613def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 4614 [(int_arm_clrex)]>, 4615 Requires<[IsARM, HasV7]> { 4616 let Inst{31-0} = 0b11110101011111111111000000011111; 4617} 4618 4619def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 4620 (STREXB GPR:$Rt, addr_offset_none:$addr)>; 4621def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 4622 (STREXH GPR:$Rt, addr_offset_none:$addr)>; 4623 4624def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 4625 (STLEXB GPR:$Rt, addr_offset_none:$addr)>; 4626def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 4627 (STLEXH GPR:$Rt, addr_offset_none:$addr)>; 4628 4629class acquiring_load<PatFrag base> 4630 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 4631 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 4632 return Ordering == Acquire || Ordering == SequentiallyConsistent; 4633}]>; 4634 4635def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 4636def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 4637def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 4638 4639class releasing_store<PatFrag base> 4640 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 4641 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 4642 return Ordering == Release || Ordering == SequentiallyConsistent; 4643}]>; 4644 4645def atomic_store_release_8 : releasing_store<atomic_store_8>; 4646def atomic_store_release_16 : releasing_store<atomic_store_16>; 4647def atomic_store_release_32 : releasing_store<atomic_store_32>; 4648 4649let AddedComplexity = 8 in { 4650 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>; 4651 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>; 4652 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>; 4653 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>; 4654 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>; 4655 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>; 4656} 4657 4658// SWP/SWPB are deprecated in V6/V7. 4659let mayLoad = 1, mayStore = 1 in { 4660def SWP : AIswp<0, (outs GPRnopc:$Rt), 4661 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>, 4662 Requires<[PreV8]>; 4663def SWPB: AIswp<1, (outs GPRnopc:$Rt), 4664 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>, 4665 Requires<[PreV8]>; 4666} 4667 4668//===----------------------------------------------------------------------===// 4669// Coprocessor Instructions. 4670// 4671 4672def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4673 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4674 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4675 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4676 imm:$CRm, imm:$opc2)]>, 4677 Requires<[PreV8]> { 4678 bits<4> opc1; 4679 bits<4> CRn; 4680 bits<4> CRd; 4681 bits<4> cop; 4682 bits<3> opc2; 4683 bits<4> CRm; 4684 4685 let Inst{3-0} = CRm; 4686 let Inst{4} = 0; 4687 let Inst{7-5} = opc2; 4688 let Inst{11-8} = cop; 4689 let Inst{15-12} = CRd; 4690 let Inst{19-16} = CRn; 4691 let Inst{23-20} = opc1; 4692} 4693 4694def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4695 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4696 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4697 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4698 imm:$CRm, imm:$opc2)]>, 4699 Requires<[PreV8]> { 4700 let Inst{31-28} = 0b1111; 4701 bits<4> opc1; 4702 bits<4> CRn; 4703 bits<4> CRd; 4704 bits<4> cop; 4705 bits<3> opc2; 4706 bits<4> CRm; 4707 4708 let Inst{3-0} = CRm; 4709 let Inst{4} = 0; 4710 let Inst{7-5} = opc2; 4711 let Inst{11-8} = cop; 4712 let Inst{15-12} = CRd; 4713 let Inst{19-16} = CRn; 4714 let Inst{23-20} = opc1; 4715} 4716 4717class ACI<dag oops, dag iops, string opc, string asm, 4718 IndexMode im = IndexModeNone> 4719 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 4720 opc, asm, "", []> { 4721 let Inst{27-25} = 0b110; 4722} 4723class ACInoP<dag oops, dag iops, string opc, string asm, 4724 IndexMode im = IndexModeNone> 4725 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 4726 opc, asm, "", []> { 4727 let Inst{31-28} = 0b1111; 4728 let Inst{27-25} = 0b110; 4729} 4730multiclass LdStCop<bit load, bit Dbit, string asm> { 4731 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4732 asm, "\t$cop, $CRd, $addr"> { 4733 bits<13> addr; 4734 bits<4> cop; 4735 bits<4> CRd; 4736 let Inst{24} = 1; // P = 1 4737 let Inst{23} = addr{8}; 4738 let Inst{22} = Dbit; 4739 let Inst{21} = 0; // W = 0 4740 let Inst{20} = load; 4741 let Inst{19-16} = addr{12-9}; 4742 let Inst{15-12} = CRd; 4743 let Inst{11-8} = cop; 4744 let Inst{7-0} = addr{7-0}; 4745 let DecoderMethod = "DecodeCopMemInstruction"; 4746 } 4747 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 4748 asm, "\t$cop, $CRd, $addr!", IndexModePre> { 4749 bits<13> addr; 4750 bits<4> cop; 4751 bits<4> CRd; 4752 let Inst{24} = 1; // P = 1 4753 let Inst{23} = addr{8}; 4754 let Inst{22} = Dbit; 4755 let Inst{21} = 1; // W = 1 4756 let Inst{20} = load; 4757 let Inst{19-16} = addr{12-9}; 4758 let Inst{15-12} = CRd; 4759 let Inst{11-8} = cop; 4760 let Inst{7-0} = addr{7-0}; 4761 let DecoderMethod = "DecodeCopMemInstruction"; 4762 } 4763 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4764 postidx_imm8s4:$offset), 4765 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> { 4766 bits<9> offset; 4767 bits<4> addr; 4768 bits<4> cop; 4769 bits<4> CRd; 4770 let Inst{24} = 0; // P = 0 4771 let Inst{23} = offset{8}; 4772 let Inst{22} = Dbit; 4773 let Inst{21} = 1; // W = 1 4774 let Inst{20} = load; 4775 let Inst{19-16} = addr; 4776 let Inst{15-12} = CRd; 4777 let Inst{11-8} = cop; 4778 let Inst{7-0} = offset{7-0}; 4779 let DecoderMethod = "DecodeCopMemInstruction"; 4780 } 4781 def _OPTION : ACI<(outs), 4782 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4783 coproc_option_imm:$option), 4784 asm, "\t$cop, $CRd, $addr, $option"> { 4785 bits<8> option; 4786 bits<4> addr; 4787 bits<4> cop; 4788 bits<4> CRd; 4789 let Inst{24} = 0; // P = 0 4790 let Inst{23} = 1; // U = 1 4791 let Inst{22} = Dbit; 4792 let Inst{21} = 0; // W = 0 4793 let Inst{20} = load; 4794 let Inst{19-16} = addr; 4795 let Inst{15-12} = CRd; 4796 let Inst{11-8} = cop; 4797 let Inst{7-0} = option; 4798 let DecoderMethod = "DecodeCopMemInstruction"; 4799 } 4800} 4801multiclass LdSt2Cop<bit load, bit Dbit, string asm> { 4802 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4803 asm, "\t$cop, $CRd, $addr"> { 4804 bits<13> addr; 4805 bits<4> cop; 4806 bits<4> CRd; 4807 let Inst{24} = 1; // P = 1 4808 let Inst{23} = addr{8}; 4809 let Inst{22} = Dbit; 4810 let Inst{21} = 0; // W = 0 4811 let Inst{20} = load; 4812 let Inst{19-16} = addr{12-9}; 4813 let Inst{15-12} = CRd; 4814 let Inst{11-8} = cop; 4815 let Inst{7-0} = addr{7-0}; 4816 let DecoderMethod = "DecodeCopMemInstruction"; 4817 } 4818 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 4819 asm, "\t$cop, $CRd, $addr!", IndexModePre> { 4820 bits<13> addr; 4821 bits<4> cop; 4822 bits<4> CRd; 4823 let Inst{24} = 1; // P = 1 4824 let Inst{23} = addr{8}; 4825 let Inst{22} = Dbit; 4826 let Inst{21} = 1; // W = 1 4827 let Inst{20} = load; 4828 let Inst{19-16} = addr{12-9}; 4829 let Inst{15-12} = CRd; 4830 let Inst{11-8} = cop; 4831 let Inst{7-0} = addr{7-0}; 4832 let DecoderMethod = "DecodeCopMemInstruction"; 4833 } 4834 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4835 postidx_imm8s4:$offset), 4836 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> { 4837 bits<9> offset; 4838 bits<4> addr; 4839 bits<4> cop; 4840 bits<4> CRd; 4841 let Inst{24} = 0; // P = 0 4842 let Inst{23} = offset{8}; 4843 let Inst{22} = Dbit; 4844 let Inst{21} = 1; // W = 1 4845 let Inst{20} = load; 4846 let Inst{19-16} = addr; 4847 let Inst{15-12} = CRd; 4848 let Inst{11-8} = cop; 4849 let Inst{7-0} = offset{7-0}; 4850 let DecoderMethod = "DecodeCopMemInstruction"; 4851 } 4852 def _OPTION : ACInoP<(outs), 4853 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4854 coproc_option_imm:$option), 4855 asm, "\t$cop, $CRd, $addr, $option"> { 4856 bits<8> option; 4857 bits<4> addr; 4858 bits<4> cop; 4859 bits<4> CRd; 4860 let Inst{24} = 0; // P = 0 4861 let Inst{23} = 1; // U = 1 4862 let Inst{22} = Dbit; 4863 let Inst{21} = 0; // W = 0 4864 let Inst{20} = load; 4865 let Inst{19-16} = addr; 4866 let Inst{15-12} = CRd; 4867 let Inst{11-8} = cop; 4868 let Inst{7-0} = option; 4869 let DecoderMethod = "DecodeCopMemInstruction"; 4870 } 4871} 4872 4873defm LDC : LdStCop <1, 0, "ldc">; 4874defm LDCL : LdStCop <1, 1, "ldcl">; 4875defm STC : LdStCop <0, 0, "stc">; 4876defm STCL : LdStCop <0, 1, "stcl">; 4877defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>; 4878defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>; 4879defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>; 4880defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>; 4881 4882//===----------------------------------------------------------------------===// 4883// Move between coprocessor and ARM core register. 4884// 4885 4886class MovRCopro<string opc, bit direction, dag oops, dag iops, 4887 list<dag> pattern> 4888 : ABI<0b1110, oops, iops, NoItinerary, opc, 4889 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 4890 let Inst{20} = direction; 4891 let Inst{4} = 1; 4892 4893 bits<4> Rt; 4894 bits<4> cop; 4895 bits<3> opc1; 4896 bits<3> opc2; 4897 bits<4> CRm; 4898 bits<4> CRn; 4899 4900 let Inst{15-12} = Rt; 4901 let Inst{11-8} = cop; 4902 let Inst{23-21} = opc1; 4903 let Inst{7-5} = opc2; 4904 let Inst{3-0} = CRm; 4905 let Inst{19-16} = CRn; 4906} 4907 4908def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 4909 (outs), 4910 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4911 c_imm:$CRm, imm0_7:$opc2), 4912 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4913 imm:$CRm, imm:$opc2)]>, 4914 ComplexDeprecationPredicate<"MCR">; 4915def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 4916 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4917 c_imm:$CRm, 0, pred:$p)>; 4918def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 4919 (outs GPRwithAPSR:$Rt), 4920 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 4921 imm0_7:$opc2), []>; 4922def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 4923 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4924 c_imm:$CRm, 0, pred:$p)>; 4925 4926def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 4927 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 4928 4929class MovRCopro2<string opc, bit direction, dag oops, dag iops, 4930 list<dag> pattern> 4931 : ABXI<0b1110, oops, iops, NoItinerary, 4932 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 4933 let Inst{31-24} = 0b11111110; 4934 let Inst{20} = direction; 4935 let Inst{4} = 1; 4936 4937 bits<4> Rt; 4938 bits<4> cop; 4939 bits<3> opc1; 4940 bits<3> opc2; 4941 bits<4> CRm; 4942 bits<4> CRn; 4943 4944 let Inst{15-12} = Rt; 4945 let Inst{11-8} = cop; 4946 let Inst{23-21} = opc1; 4947 let Inst{7-5} = opc2; 4948 let Inst{3-0} = CRm; 4949 let Inst{19-16} = CRn; 4950} 4951 4952def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 4953 (outs), 4954 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4955 c_imm:$CRm, imm0_7:$opc2), 4956 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4957 imm:$CRm, imm:$opc2)]>, 4958 Requires<[PreV8]>; 4959def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm", 4960 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4961 c_imm:$CRm, 0)>; 4962def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 4963 (outs GPRwithAPSR:$Rt), 4964 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 4965 imm0_7:$opc2), []>, 4966 Requires<[PreV8]>; 4967def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm", 4968 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4969 c_imm:$CRm, 0)>; 4970 4971def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, 4972 imm:$CRm, imm:$opc2), 4973 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 4974 4975class MovRRCopro<string opc, bit direction, list<dag> pattern = []> 4976 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4977 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), 4978 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> { 4979 let Inst{23-21} = 0b010; 4980 let Inst{20} = direction; 4981 4982 bits<4> Rt; 4983 bits<4> Rt2; 4984 bits<4> cop; 4985 bits<4> opc1; 4986 bits<4> CRm; 4987 4988 let Inst{15-12} = Rt; 4989 let Inst{19-16} = Rt2; 4990 let Inst{11-8} = cop; 4991 let Inst{7-4} = opc1; 4992 let Inst{3-0} = CRm; 4993} 4994 4995def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 4996 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt, 4997 GPRnopc:$Rt2, imm:$CRm)]>; 4998def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>; 4999 5000class MovRRCopro2<string opc, bit direction, list<dag> pattern = []> 5001 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5002 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary, 5003 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, 5004 Requires<[PreV8]> { 5005 let Inst{31-28} = 0b1111; 5006 let Inst{23-21} = 0b010; 5007 let Inst{20} = direction; 5008 5009 bits<4> Rt; 5010 bits<4> Rt2; 5011 bits<4> cop; 5012 bits<4> opc1; 5013 bits<4> CRm; 5014 5015 let Inst{15-12} = Rt; 5016 let Inst{19-16} = Rt2; 5017 let Inst{11-8} = cop; 5018 let Inst{7-4} = opc1; 5019 let Inst{3-0} = CRm; 5020 5021 let DecoderMethod = "DecodeMRRC2"; 5022} 5023 5024def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 5025 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt, 5026 GPRnopc:$Rt2, imm:$CRm)]>; 5027def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>; 5028 5029//===----------------------------------------------------------------------===// 5030// Move between special register and ARM core register 5031// 5032 5033// Move to ARM core register from Special Register 5034def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5035 "mrs", "\t$Rd, apsr", []> { 5036 bits<4> Rd; 5037 let Inst{23-16} = 0b00001111; 5038 let Unpredictable{19-17} = 0b111; 5039 5040 let Inst{15-12} = Rd; 5041 5042 let Inst{11-0} = 0b000000000000; 5043 let Unpredictable{11-0} = 0b110100001111; 5044} 5045 5046def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>, 5047 Requires<[IsARM]>; 5048 5049// The MRSsys instruction is the MRS instruction from the ARM ARM, 5050// section B9.3.9, with the R bit set to 1. 5051def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5052 "mrs", "\t$Rd, spsr", []> { 5053 bits<4> Rd; 5054 let Inst{23-16} = 0b01001111; 5055 let Unpredictable{19-16} = 0b1111; 5056 5057 let Inst{15-12} = Rd; 5058 5059 let Inst{11-0} = 0b000000000000; 5060 let Unpredictable{11-0} = 0b110100001111; 5061} 5062 5063// Move from ARM core register to Special Register 5064// 5065// No need to have both system and application versions, the encodings are the 5066// same and the assembly parser has no way to distinguish between them. The mask 5067// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains 5068// the mask with the fields to be accessed in the special register. 5069def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 5070 "msr", "\t$mask, $Rn", []> { 5071 bits<5> mask; 5072 bits<4> Rn; 5073 5074 let Inst{23} = 0; 5075 let Inst{22} = mask{4}; // R bit 5076 let Inst{21-20} = 0b10; 5077 let Inst{19-16} = mask{3-0}; 5078 let Inst{15-12} = 0b1111; 5079 let Inst{11-4} = 0b00000000; 5080 let Inst{3-0} = Rn; 5081} 5082 5083def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary, 5084 "msr", "\t$mask, $a", []> { 5085 bits<5> mask; 5086 bits<12> a; 5087 5088 let Inst{23} = 0; 5089 let Inst{22} = mask{4}; // R bit 5090 let Inst{21-20} = 0b10; 5091 let Inst{19-16} = mask{3-0}; 5092 let Inst{15-12} = 0b1111; 5093 let Inst{11-0} = a; 5094} 5095 5096// Dynamic stack allocation yields a _chkstk for Windows targets. These calls 5097// are needed to probe the stack when allocating more than 5098// 4k bytes in one go. Touching the stack at 4K increments is necessary to 5099// ensure that the guard pages used by the OS virtual memory manager are 5100// allocated in correct sequence. 5101// The main point of having separate instruction are extra unmodelled effects 5102// (compared to ordinary calls) like stack pointer change. 5103 5104def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone, 5105 [SDNPHasChain, SDNPSideEffect]>; 5106let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in 5107 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>; 5108 5109//===----------------------------------------------------------------------===// 5110// TLS Instructions 5111// 5112 5113// __aeabi_read_tp preserves the registers r1-r3. 5114// This is a pseudo inst so that we can get the encoding right, 5115// complete with fixup for the aeabi_read_tp function. 5116// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern 5117// is defined in "ARMInstrThumb.td". 5118let isCall = 1, 5119 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 5120 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br, 5121 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>; 5122} 5123 5124//===----------------------------------------------------------------------===// 5125// SJLJ Exception handling intrinsics 5126// eh_sjlj_setjmp() is an instruction sequence to store the return 5127// address and save #0 in R0 for the non-longjmp case. 5128// Since by its nature we may be coming from some other function to get 5129// here, and we're using the stack frame for the containing function to 5130// save/restore registers, we can't keep anything live in regs across 5131// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 5132// when we get here from a longjmp(). We force everything out of registers 5133// except for our own input by listing the relevant registers in Defs. By 5134// doing so, we also cause the prologue/epilogue code to actively preserve 5135// all of the callee-saved resgisters, which is exactly what we want. 5136// A constant value is passed in $val, and we use the location as a scratch. 5137// 5138// These are pseudo-instructions and are lowered to individual MC-insts, so 5139// no encoding information is necessary. 5140let Defs = 5141 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 5142 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 5143 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5144 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5145 NoItinerary, 5146 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5147 Requires<[IsARM, HasVFP2]>; 5148} 5149 5150let Defs = 5151 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 5152 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5153 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5154 NoItinerary, 5155 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5156 Requires<[IsARM, NoVFP]>; 5157} 5158 5159// FIXME: Non-IOS version(s) 5160let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 5161 Defs = [ R7, LR, SP ] in { 5162def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 5163 NoItinerary, 5164 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 5165 Requires<[IsARM, IsIOS]>; 5166} 5167 5168// eh.sjlj.dispatchsetup pseudo-instruction. 5169// This pseudo is used for both ARM and Thumb. Any differences are handled when 5170// the pseudo is expanded (which happens before any passes that need the 5171// instruction size). 5172let isBarrier = 1 in 5173def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 5174 5175 5176//===----------------------------------------------------------------------===// 5177// Non-Instruction Patterns 5178// 5179 5180// ARMv4 indirect branch using (MOVr PC, dst) 5181let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 5182 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 5183 4, IIC_Br, [(brind GPR:$dst)], 5184 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5185 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5186 5187// Large immediate handling. 5188 5189// 32-bit immediate using two piece so_imms or movw + movt. 5190// This is a single pseudo instruction, the benefit is that it can be remat'd 5191// as a single unit instead of having to handle reg inputs. 5192// FIXME: Remove this when we can do generalized remat. 5193let isReMaterializable = 1, isMoveImm = 1 in 5194def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 5195 [(set GPR:$dst, (arm_i32imm:$src))]>, 5196 Requires<[IsARM]>; 5197 5198def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i, 5199 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>, 5200 Requires<[IsARM, DontUseMovt]>; 5201 5202// Pseudo instruction that combines movw + movt + add pc (if PIC). 5203// It also makes it possible to rematerialize the instructions. 5204// FIXME: Remove this when we can do generalized remat and when machine licm 5205// can properly the instructions. 5206let isReMaterializable = 1 in { 5207def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5208 IIC_iMOVix2addpc, 5209 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 5210 Requires<[IsARM, UseMovt]>; 5211 5212def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5213 IIC_iLoadiALU, 5214 [(set GPR:$dst, 5215 (ARMWrapperPIC tglobaladdr:$addr))]>, 5216 Requires<[IsARM, DontUseMovt]>; 5217 5218def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5219 NoItinerary, 5220 [(set GPR:$dst, 5221 (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5222 Requires<[IsARM, DontUseMovt]>; 5223 5224let AddedComplexity = 10 in 5225def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5226 IIC_iMOVix2ld, 5227 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5228 Requires<[IsARM, UseMovt]>; 5229} // isReMaterializable 5230 5231// ConstantPool, GlobalAddress, and JumpTable 5232def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 5233def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 5234 Requires<[IsARM, UseMovt]>; 5235def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id), 5236 (LEApcrelJT tjumptable:$dst, imm:$id)>; 5237 5238// TODO: add,sub,and, 3-instr forms? 5239 5240// Tail calls. These patterns also apply to Thumb mode. 5241def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; 5242def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; 5243def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; 5244 5245// Direct calls 5246def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 5247def : ARMPat<(ARMcall_nolink texternalsym:$func), 5248 (BMOVPCB_CALL texternalsym:$func)>; 5249 5250// zextload i1 -> zextload i8 5251def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5252def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5253 5254// extload -> zextload 5255def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5256def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5257def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5258def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5259 5260def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 5261 5262def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 5263def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 5264 5265// smul* and smla* 5266def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5267 (sra (shl GPR:$b, (i32 16)), (i32 16))), 5268 (SMULBB GPR:$a, GPR:$b)>; 5269def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 5270 (SMULBB GPR:$a, GPR:$b)>; 5271def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5272 (sra GPR:$b, (i32 16))), 5273 (SMULBT GPR:$a, GPR:$b)>; 5274def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))), 5275 (SMULBT GPR:$a, GPR:$b)>; 5276def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), 5277 (sra (shl GPR:$b, (i32 16)), (i32 16))), 5278 (SMULTB GPR:$a, GPR:$b)>; 5279def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b), 5280 (SMULTB GPR:$a, GPR:$b)>; 5281def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), 5282 (i32 16)), 5283 (SMULWB GPR:$a, GPR:$b)>; 5284def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)), 5285 (SMULWB GPR:$a, GPR:$b)>; 5286 5287def : ARMV5MOPat<(add GPR:$acc, 5288 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5289 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 5290 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5291def : ARMV5MOPat<(add GPR:$acc, 5292 (mul sext_16_node:$a, sext_16_node:$b)), 5293 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5294def : ARMV5MOPat<(add GPR:$acc, 5295 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5296 (sra GPR:$b, (i32 16)))), 5297 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5298def : ARMV5MOPat<(add GPR:$acc, 5299 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))), 5300 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5301def : ARMV5MOPat<(add GPR:$acc, 5302 (mul (sra GPR:$a, (i32 16)), 5303 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 5304 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5305def : ARMV5MOPat<(add GPR:$acc, 5306 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)), 5307 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5308def : ARMV5MOPat<(add GPR:$acc, 5309 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), 5310 (i32 16))), 5311 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 5312def : ARMV5MOPat<(add GPR:$acc, 5313 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))), 5314 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 5315 5316 5317// Pre-v7 uses MCR for synchronization barriers. 5318def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 5319 Requires<[IsARM, HasV6]>; 5320 5321// SXT/UXT with no rotate 5322let AddedComplexity = 16 in { 5323def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 5324def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 5325def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 5326def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 5327 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 5328def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 5329 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 5330} 5331 5332def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 5333def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 5334 5335def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 5336 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 5337def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 5338 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 5339 5340// Atomic load/store patterns 5341def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 5342 (LDRBrs ldst_so_reg:$src)>; 5343def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 5344 (LDRBi12 addrmode_imm12:$src)>; 5345def : ARMPat<(atomic_load_16 addrmode3:$src), 5346 (LDRH addrmode3:$src)>; 5347def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 5348 (LDRrs ldst_so_reg:$src)>; 5349def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 5350 (LDRi12 addrmode_imm12:$src)>; 5351def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 5352 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 5353def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 5354 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 5355def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 5356 (STRH GPR:$val, addrmode3:$ptr)>; 5357def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 5358 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 5359def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 5360 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 5361 5362 5363//===----------------------------------------------------------------------===// 5364// Thumb Support 5365// 5366 5367include "ARMInstrThumb.td" 5368 5369//===----------------------------------------------------------------------===// 5370// Thumb2 Support 5371// 5372 5373include "ARMInstrThumb2.td" 5374 5375//===----------------------------------------------------------------------===// 5376// Floating Point Support 5377// 5378 5379include "ARMInstrVFP.td" 5380 5381//===----------------------------------------------------------------------===// 5382// Advanced SIMD (NEON) Support 5383// 5384 5385include "ARMInstrNEON.td" 5386 5387//===----------------------------------------------------------------------===// 5388// Assembler aliases 5389// 5390 5391// Memory barriers 5392def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>; 5393def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>; 5394def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>; 5395 5396// System instructions 5397def : MnemonicAlias<"swi", "svc">; 5398 5399// Load / Store Multiple 5400def : MnemonicAlias<"ldmfd", "ldm">; 5401def : MnemonicAlias<"ldmia", "ldm">; 5402def : MnemonicAlias<"ldmea", "ldmdb">; 5403def : MnemonicAlias<"stmfd", "stmdb">; 5404def : MnemonicAlias<"stmia", "stm">; 5405def : MnemonicAlias<"stmea", "stm">; 5406 5407// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the 5408// shift amount is zero (i.e., unspecified). 5409def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 5410 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>, 5411 Requires<[IsARM, HasV6]>; 5412def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 5413 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>, 5414 Requires<[IsARM, HasV6]>; 5415 5416// PUSH/POP aliases for STM/LDM 5417def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 5418def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 5419 5420// SSAT/USAT optional shift operand. 5421def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 5422 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5423def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 5424 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5425 5426 5427// Extend instruction optional rotate operand. 5428def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 5429 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5430def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 5431 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5432def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 5433 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5434def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 5435 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5436def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 5437 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5438def : ARMInstAlias<"sxth${p} $Rd, $Rm", 5439 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5440 5441def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 5442 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5443def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 5444 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5445def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 5446 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5447def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 5448 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5449def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 5450 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5451def : ARMInstAlias<"uxth${p} $Rd, $Rm", 5452 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5453 5454 5455// RFE aliases 5456def : MnemonicAlias<"rfefa", "rfeda">; 5457def : MnemonicAlias<"rfeea", "rfedb">; 5458def : MnemonicAlias<"rfefd", "rfeia">; 5459def : MnemonicAlias<"rfeed", "rfeib">; 5460def : MnemonicAlias<"rfe", "rfeia">; 5461 5462// SRS aliases 5463def : MnemonicAlias<"srsfa", "srsib">; 5464def : MnemonicAlias<"srsea", "srsia">; 5465def : MnemonicAlias<"srsfd", "srsdb">; 5466def : MnemonicAlias<"srsed", "srsda">; 5467def : MnemonicAlias<"srs", "srsia">; 5468 5469// QSAX == QSUBADDX 5470def : MnemonicAlias<"qsubaddx", "qsax">; 5471// SASX == SADDSUBX 5472def : MnemonicAlias<"saddsubx", "sasx">; 5473// SHASX == SHADDSUBX 5474def : MnemonicAlias<"shaddsubx", "shasx">; 5475// SHSAX == SHSUBADDX 5476def : MnemonicAlias<"shsubaddx", "shsax">; 5477// SSAX == SSUBADDX 5478def : MnemonicAlias<"ssubaddx", "ssax">; 5479// UASX == UADDSUBX 5480def : MnemonicAlias<"uaddsubx", "uasx">; 5481// UHASX == UHADDSUBX 5482def : MnemonicAlias<"uhaddsubx", "uhasx">; 5483// UHSAX == UHSUBADDX 5484def : MnemonicAlias<"uhsubaddx", "uhsax">; 5485// UQASX == UQADDSUBX 5486def : MnemonicAlias<"uqaddsubx", "uqasx">; 5487// UQSAX == UQSUBADDX 5488def : MnemonicAlias<"uqsubaddx", "uqsax">; 5489// USAX == USUBADDX 5490def : MnemonicAlias<"usubaddx", "usax">; 5491 5492// "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like 5493// for isel. 5494def : ARMInstAlias<"mov${s}${p} $Rd, $imm", 5495 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>; 5496def : ARMInstAlias<"mvn${s}${p} $Rd, $imm", 5497 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>; 5498// Same for AND <--> BIC 5499def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm", 5500 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm, 5501 pred:$p, cc_out:$s)>; 5502def : ARMInstAlias<"bic${s}${p} $Rdn, $imm", 5503 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm, 5504 pred:$p, cc_out:$s)>; 5505def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm", 5506 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm, 5507 pred:$p, cc_out:$s)>; 5508def : ARMInstAlias<"and${s}${p} $Rdn, $imm", 5509 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm, 5510 pred:$p, cc_out:$s)>; 5511 5512// Likewise, "add Rd, so_imm_neg" -> sub 5513def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm", 5514 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>; 5515def : ARMInstAlias<"add${s}${p} $Rd, $imm", 5516 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>; 5517// Same for CMP <--> CMN via so_imm_neg 5518def : ARMInstAlias<"cmp${p} $Rd, $imm", 5519 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>; 5520def : ARMInstAlias<"cmn${p} $Rd, $imm", 5521 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>; 5522 5523// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 5524// LSR, ROR, and RRX instructions. 5525// FIXME: We need C++ parser hooks to map the alias to the MOV 5526// encoding. It seems we should be able to do that sort of thing 5527// in tblgen, but it could get ugly. 5528let TwoOperandAliasConstraint = "$Rm = $Rd" in { 5529def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 5530 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 5531 cc_out:$s)>; 5532def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 5533 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 5534 cc_out:$s)>; 5535def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 5536 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 5537 cc_out:$s)>; 5538def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 5539 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 5540 cc_out:$s)>; 5541} 5542def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 5543 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; 5544let TwoOperandAliasConstraint = "$Rn = $Rd" in { 5545def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 5546 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5547 cc_out:$s)>; 5548def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 5549 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5550 cc_out:$s)>; 5551def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 5552 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5553 cc_out:$s)>; 5554def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 5555 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5556 cc_out:$s)>; 5557} 5558 5559// "neg" is and alias for "rsb rd, rn, #0" 5560def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 5561 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 5562 5563// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 5564def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 5565 Requires<[IsARM, NoV6]>; 5566 5567// MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 5568// the instruction definitions need difference constraints pre-v6. 5569// Use these aliases for the assembly parsing on pre-v6. 5570def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm", 5571 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 5572 Requires<[IsARM, NoV6]>; 5573def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra", 5574 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 5575 pred:$p, cc_out:$s)>, 5576 Requires<[IsARM, NoV6]>; 5577def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5578 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5579 Requires<[IsARM, NoV6]>; 5580def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5581 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5582 Requires<[IsARM, NoV6]>; 5583def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5584 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5585 Requires<[IsARM, NoV6]>; 5586def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5587 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5588 Requires<[IsARM, NoV6]>; 5589 5590// 'it' blocks in ARM mode just validate the predicates. The IT itself 5591// is discarded. 5592def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>, 5593 ComplexDeprecationPredicate<"IT">; 5594