ARMInstrInfo.td revision 6e141fd04897e5eb4925bb6351297170ebd8a756
1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the "Instituto Nokia de Tecnologia" and 6// is distributed under the University of Illinois Open Source 7// License. See LICENSE.TXT for details. 8// 9//===----------------------------------------------------------------------===// 10// 11// This file describes the ARM instructions in TableGen format. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// ARM specific DAG Nodes. 17// 18 19// Type profiles. 20def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 21def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 22 23def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 24 25def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 26 27def SDT_ARMCMov : SDTypeProfile<1, 3, 28 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 29 SDTCisVT<3, i32>]>; 30 31def SDT_ARMBrcond : SDTypeProfile<0, 2, 32 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 33 34def SDT_ARMBrJT : SDTypeProfile<0, 3, 35 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 36 SDTCisVT<2, i32>]>; 37 38def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 39 40def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 41 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 42 43def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 44 45// Node definitions. 46def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 47def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>; 48 49def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 50 [SDNPHasChain, SDNPOutFlag]>; 51def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 52 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 53 54def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 55 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 56def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 57 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 58def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 60 61def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTRet, 62 [SDNPHasChain, SDNPOptInFlag]>; 63 64def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 65 [SDNPInFlag]>; 66def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov, 67 [SDNPInFlag]>; 68 69def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 70 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; 71 72def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 73 [SDNPHasChain]>; 74 75def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 76 [SDNPOutFlag]>; 77 78def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp, 79 [SDNPOutFlag]>; 80 81def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 82 83def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>; 84def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>; 85def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>; 86 87def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 88 89//===----------------------------------------------------------------------===// 90// ARM Instruction Predicate Definitions. 91// 92def HasV5T : Predicate<"Subtarget->hasV5TOps()">; 93def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">; 94def HasV6 : Predicate<"Subtarget->hasV6Ops()">; 95def IsThumb : Predicate<"Subtarget->isThumb()">; 96def IsARM : Predicate<"!Subtarget->isThumb()">; 97 98//===----------------------------------------------------------------------===// 99// ARM Flag Definitions. 100 101class RegConstraint<string C> { 102 string Constraints = C; 103} 104 105//===----------------------------------------------------------------------===// 106// ARM specific transformation functions and pattern fragments. 107// 108 109// so_imm_XFORM - Return a so_imm value packed into the format described for 110// so_imm def below. 111def so_imm_XFORM : SDNodeXForm<imm, [{ 112 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getValue()), 113 MVT::i32); 114}]>; 115 116// so_imm_neg_XFORM - Return a so_imm value packed into the format described for 117// so_imm_neg def below. 118def so_imm_neg_XFORM : SDNodeXForm<imm, [{ 119 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getValue()), 120 MVT::i32); 121}]>; 122 123// so_imm_not_XFORM - Return a so_imm value packed into the format described for 124// so_imm_not def below. 125def so_imm_not_XFORM : SDNodeXForm<imm, [{ 126 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getValue()), 127 MVT::i32); 128}]>; 129 130// rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24. 131def rot_imm : PatLeaf<(i32 imm), [{ 132 int32_t v = (int32_t)N->getValue(); 133 return v == 8 || v == 16 || v == 24; 134}]>; 135 136/// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15]. 137def imm1_15 : PatLeaf<(i32 imm), [{ 138 return (int32_t)N->getValue() >= 1 && (int32_t)N->getValue() < 16; 139}]>; 140 141/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 142def imm16_31 : PatLeaf<(i32 imm), [{ 143 return (int32_t)N->getValue() >= 16 && (int32_t)N->getValue() < 32; 144}]>; 145 146def so_imm_neg : 147 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }], 148 so_imm_neg_XFORM>; 149 150def so_imm_not : 151 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }], 152 so_imm_not_XFORM>; 153 154// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 155def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 156 return CurDAG->ComputeNumSignBits(SDOperand(N,0)) >= 17; 157}]>; 158 159 160 161//===----------------------------------------------------------------------===// 162// Operand Definitions. 163// 164 165// Branch target. 166def brtarget : Operand<OtherVT>; 167 168// A list of registers separated by comma. Used by load/store multiple. 169def reglist : Operand<i32> { 170 let PrintMethod = "printRegisterList"; 171} 172 173// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 174def cpinst_operand : Operand<i32> { 175 let PrintMethod = "printCPInstOperand"; 176} 177 178def jtblock_operand : Operand<i32> { 179 let PrintMethod = "printJTBlockOperand"; 180} 181 182// Local PC labels. 183def pclabel : Operand<i32> { 184 let PrintMethod = "printPCLabel"; 185} 186 187// shifter_operand operands: so_reg and so_imm. 188def so_reg : Operand<i32>, // reg reg imm 189 ComplexPattern<i32, 3, "SelectShifterOperandReg", 190 [shl,srl,sra,rotr]> { 191 let PrintMethod = "printSORegOperand"; 192 let MIOperandInfo = (ops GPR, GPR, i32imm); 193} 194 195// so_imm - Match a 32-bit shifter_operand immediate operand, which is an 196// 8-bit immediate rotated by an arbitrary number of bits. so_imm values are 197// represented in the imm field in the same 12-bit form that they are encoded 198// into so_imm instructions: the 8-bit immediate is the least significant bits 199// [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11]. 200def so_imm : Operand<i32>, 201 PatLeaf<(imm), 202 [{ return ARM_AM::getSOImmVal(N->getValue()) != -1; }], 203 so_imm_XFORM> { 204 let PrintMethod = "printSOImmOperand"; 205} 206 207// Break so_imm's up into two pieces. This handles immediates with up to 16 208// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to 209// get the first/second pieces. 210def so_imm2part : Operand<i32>, 211 PatLeaf<(imm), 212 [{ return ARM_AM::isSOImmTwoPartVal((unsigned)N->getValue()); }]> { 213 let PrintMethod = "printSOImm2PartOperand"; 214} 215 216def so_imm2part_1 : SDNodeXForm<imm, [{ 217 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getValue()); 218 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32); 219}]>; 220 221def so_imm2part_2 : SDNodeXForm<imm, [{ 222 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getValue()); 223 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32); 224}]>; 225 226 227// Define ARM specific addressing modes. 228 229// addrmode2 := reg +/- reg shop imm 230// addrmode2 := reg +/- imm12 231// 232def addrmode2 : Operand<i32>, 233 ComplexPattern<i32, 3, "SelectAddrMode2", []> { 234 let PrintMethod = "printAddrMode2Operand"; 235 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 236} 237 238def am2offset : Operand<i32>, 239 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> { 240 let PrintMethod = "printAddrMode2OffsetOperand"; 241 let MIOperandInfo = (ops GPR, i32imm); 242} 243 244// addrmode3 := reg +/- reg 245// addrmode3 := reg +/- imm8 246// 247def addrmode3 : Operand<i32>, 248 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 249 let PrintMethod = "printAddrMode3Operand"; 250 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 251} 252 253def am3offset : Operand<i32>, 254 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> { 255 let PrintMethod = "printAddrMode3OffsetOperand"; 256 let MIOperandInfo = (ops GPR, i32imm); 257} 258 259// addrmode4 := reg, <mode|W> 260// 261def addrmode4 : Operand<i32>, 262 ComplexPattern<i32, 2, "", []> { 263 let PrintMethod = "printAddrMode4Operand"; 264 let MIOperandInfo = (ops GPR, i32imm); 265} 266 267// addrmode5 := reg +/- imm8*4 268// 269def addrmode5 : Operand<i32>, 270 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 271 let PrintMethod = "printAddrMode5Operand"; 272 let MIOperandInfo = (ops GPR, i32imm); 273} 274 275// addrmodepc := pc + reg 276// 277def addrmodepc : Operand<i32>, 278 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 279 let PrintMethod = "printAddrModePCOperand"; 280 let MIOperandInfo = (ops GPR, i32imm); 281} 282 283// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 284// register whose default is 0 (no register). 285def pred : PredicateOperand<OtherVT, (ops i32imm, CCR), 286 (ops (i32 14), (i32 zero_reg))> { 287 let PrintMethod = "printPredicateOperand"; 288} 289 290// Conditional code result for instructions whose 's' bit is set, e.g. subs. 291// 292def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 293 let PrintMethod = "printSBitModifierOperand"; 294} 295 296//===----------------------------------------------------------------------===// 297// ARM Instruction flags. These need to match ARMInstrInfo.h. 298// 299 300// Addressing mode. 301class AddrMode<bits<4> val> { 302 bits<4> Value = val; 303} 304def AddrModeNone : AddrMode<0>; 305def AddrMode1 : AddrMode<1>; 306def AddrMode2 : AddrMode<2>; 307def AddrMode3 : AddrMode<3>; 308def AddrMode4 : AddrMode<4>; 309def AddrMode5 : AddrMode<5>; 310def AddrModeT1 : AddrMode<6>; 311def AddrModeT2 : AddrMode<7>; 312def AddrModeT4 : AddrMode<8>; 313def AddrModeTs : AddrMode<9>; 314 315// Instruction size. 316class SizeFlagVal<bits<3> val> { 317 bits<3> Value = val; 318} 319def SizeInvalid : SizeFlagVal<0>; // Unset. 320def SizeSpecial : SizeFlagVal<1>; // Pseudo or special. 321def Size8Bytes : SizeFlagVal<2>; 322def Size4Bytes : SizeFlagVal<3>; 323def Size2Bytes : SizeFlagVal<4>; 324 325// Load / store index mode. 326class IndexMode<bits<2> val> { 327 bits<2> Value = val; 328} 329def IndexModeNone : IndexMode<0>; 330def IndexModePre : IndexMode<1>; 331def IndexModePost : IndexMode<2>; 332 333//===----------------------------------------------------------------------===// 334// ARM Instruction Format Definitions. 335// 336 337// Format specifies the encoding used by the instruction. This is part of the 338// ad-hoc solution used to emit machine instruction encodings by our machine 339// code emitter. 340class Format<bits<5> val> { 341 bits<5> Value = val; 342} 343 344def Pseudo : Format<1>; 345def MulFrm : Format<2>; 346def MulSMLAW : Format<3>; 347def MulSMULW : Format<4>; 348def MulSMLA : Format<5>; 349def MulSMUL : Format<6>; 350def Branch : Format<7>; 351def BranchMisc : Format<8>; 352 353def DPRdIm : Format<9>; 354def DPRdReg : Format<10>; 355def DPRdSoReg : Format<11>; 356def DPRdMisc : Format<12>; 357def DPRnIm : Format<13>; 358def DPRnReg : Format<14>; 359def DPRnSoReg : Format<15>; 360def DPRIm : Format<16>; 361def DPRReg : Format<17>; 362def DPRSoReg : Format<18>; 363def DPRImS : Format<19>; 364def DPRRegS : Format<20>; 365def DPRSoRegS : Format<21>; 366 367def LdFrm : Format<22>; 368def StFrm : Format<23>; 369 370def ArithMisc : Format<24>; 371def ThumbFrm : Format<25>; 372def VFPFrm : Format<26>; 373 374 375 376//===----------------------------------------------------------------------===// 377 378// ARM Instruction templates. 379// 380 381// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 382class ARMPat<dag pattern, dag result> : Pat<pattern, result> { 383 list<Predicate> Predicates = [IsARM]; 384} 385class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 386 list<Predicate> Predicates = [IsARM, HasV5TE]; 387} 388class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 389 list<Predicate> Predicates = [IsARM, HasV6]; 390} 391 392class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im, 393 Format f, string cstr> 394 : Instruction { 395 let Namespace = "ARM"; 396 397 bits<4> Opcode = opcod; 398 AddrMode AM = am; 399 bits<4> AddrModeBits = AM.Value; 400 401 SizeFlagVal SZ = sz; 402 bits<3> SizeFlag = SZ.Value; 403 404 IndexMode IM = im; 405 bits<2> IndexModeBits = IM.Value; 406 407 Format F = f; 408 bits<5> Form = F.Value; 409 410 let Constraints = cstr; 411} 412 413class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern> 414 : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> { 415 let OutOperandList = oops; 416 let InOperandList = iops; 417 let AsmString = asm; 418 let Pattern = pattern; 419} 420 421// Almost all ARM instructions are predicable. 422class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, 423 IndexMode im, Format f, string opc, string asm, string cstr, 424 list<dag> pattern> 425 : InstARM<opcod, am, sz, im, f, cstr> { 426 let OutOperandList = oops; 427 let InOperandList = !con(iops, (ops pred:$p)); 428 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 429 let Pattern = pattern; 430 list<Predicate> Predicates = [IsARM]; 431} 432 433// Same as I except it can optionally modify CPSR. Note it's modeled as 434// an input operand since by default it's a zero register. It will 435// become an implicit def once it's "flipped". 436class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, 437 IndexMode im, Format f, string opc, string asm, string cstr, 438 list<dag> pattern> 439 : InstARM<opcod, am, sz, im, f, cstr> { 440 let OutOperandList = oops; 441 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); 442 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm)); 443 let Pattern = pattern; 444 list<Predicate> Predicates = [IsARM]; 445} 446 447class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc, 448 string asm, list<dag> pattern> 449 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, 450 asm,"",pattern>; 451class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc, 452 string asm, list<dag> pattern> 453 : sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, 454 asm,"",pattern>; 455class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc, 456 string asm, list<dag> pattern> 457 : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc, 458 asm, "", pattern>; 459class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc, 460 string asm, list<dag> pattern> 461 : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc, 462 asm, "", pattern>; 463class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc, 464 string asm, list<dag> pattern> 465 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 466 asm, "", pattern>; 467class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc, 468 string asm, list<dag> pattern> 469 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 470 asm, "", pattern>; 471class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc, 472 string asm, list<dag> pattern> 473 : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc, 474 asm, "", pattern>; 475class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc, 476 string asm, list<dag> pattern> 477 : I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc, 478 asm, "", pattern>; 479 480// Pre-indexed ops 481class AI2pr<bits<4> opcod, dag oops, dag iops, Format f, string opc, 482 string asm, string cstr, list<dag> pattern> 483 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 484 asm, cstr, pattern>; 485class AI3pr<bits<4> opcod, dag oops, dag iops, Format f, string opc, 486 string asm, string cstr, list<dag> pattern> 487 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 488 asm, cstr, pattern>; 489 490// Post-indexed ops 491class AI2po<bits<4> opcod, dag oops, dag iops, Format f, string opc, 492 string asm, string cstr, list<dag> pattern> 493 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 494 asm, cstr,pattern>; 495class AI3po<bits<4> opcod, dag oops, dag iops, Format f, string opc, 496 string asm, string cstr, list<dag> pattern> 497 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 498 asm, cstr,pattern>; 499 500 501class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 502class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 503 504 505/// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a 506/// binop that produces a value. 507multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> { 508 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm, 509 opc, " $dst, $a, $b", 510 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>; 511 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPRReg, 512 opc, " $dst, $a, $b", 513 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>; 514 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg, 515 opc, " $dst, $a, $b", 516 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>; 517} 518 519/// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the 520/// instruction modifies the CSPR register. 521let Defs = [CPSR] in { 522multiclass ASI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> { 523 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRImS, 524 opc, "s $dst, $a, $b", 525 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>; 526 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPRRegS, 527 opc, "s $dst, $a, $b", 528 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>; 529 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoRegS, 530 opc, "s $dst, $a, $b", 531 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>; 532} 533} 534 535/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 536/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 537/// a explicit result, only implicitly set CPSR. 538let Defs = [CPSR] in { 539multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> { 540 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPRnIm, 541 opc, " $a, $b", 542 [(opnode GPR:$a, so_imm:$b)]>; 543 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPRnReg, 544 opc, " $a, $b", 545 [(opnode GPR:$a, GPR:$b)]>; 546 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPRnSoReg, 547 opc, " $a, $b", 548 [(opnode GPR:$a, so_reg:$b)]>; 549} 550} 551 552/// AI_unary_rrot - A unary operation with two forms: one whose operand is a 553/// register and one whose operand is a register rotated by 8/16/24. 554multiclass AI_unary_rrot<bits<4> opcod, string opc, PatFrag opnode> { 555 def r : AI<opcod, (outs GPR:$dst), (ins GPR:$Src), Pseudo, 556 opc, " $dst, $Src", 557 [(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>; 558 def r_rot : AI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), Pseudo, 559 opc, " $dst, $Src, ror $rot", 560 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>, 561 Requires<[IsARM, HasV6]>; 562} 563 564/// AI_bin_rrot - A binary operation with two forms: one whose operand is a 565/// register and one whose operand is a register rotated by 8/16/24. 566multiclass AI_bin_rrot<bits<4> opcod, string opc, PatFrag opnode> { 567 def rr : AI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), 568 Pseudo, opc, " $dst, $LHS, $RHS", 569 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>, 570 Requires<[IsARM, HasV6]>; 571 def rr_rot : AI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot), 572 Pseudo, opc, " $dst, $LHS, $RHS, ror $rot", 573 [(set GPR:$dst, (opnode GPR:$LHS, 574 (rotr GPR:$RHS, rot_imm:$rot)))]>, 575 Requires<[IsARM, HasV6]>; 576} 577 578// Special cases. 579class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, 580 IndexMode im, Format f, string asm, string cstr, list<dag> pattern> 581 : InstARM<opcod, am, sz, im, f, cstr> { 582 let OutOperandList = oops; 583 let InOperandList = iops; 584 let AsmString = asm; 585 let Pattern = pattern; 586 list<Predicate> Predicates = [IsARM]; 587} 588 589class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm, 590 list<dag> pattern> 591 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, 592 "", pattern>; 593class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm, 594 list<dag> pattern> 595 : XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm, 596 "", pattern>; 597class AXI2<bits<4> opcod, dag oops, dag iops, Format f, string asm, 598 list<dag> pattern> 599 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm, 600 "", pattern>; 601class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm, 602 list<dag> pattern> 603 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm, 604 "", pattern>; 605class AXI4<bits<4> opcod, dag oops, dag iops, Format f, string asm, 606 list<dag> pattern> 607 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, 608 "", pattern>; 609 610class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm, 611 list<dag> pattern> 612 : XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm, 613 "", pattern>; 614 615// BR_JT instructions 616class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> 617 : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc, 618 asm, "", pattern>; 619class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> 620 : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc, 621 asm, "", pattern>; 622class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> 623 : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc, 624 asm, "", pattern>; 625 626/// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and 627/// setting carry bit. But it can optionally set CPSR. 628let Uses = [CPSR] in { 629multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> { 630 def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s), 631 DPRIm, !strconcat(opc, "${s} $dst, $a, $b"), 632 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>; 633 def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s), 634 DPRReg, !strconcat(opc, "${s} $dst, $a, $b"), 635 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>; 636 def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s), 637 DPRSoReg, !strconcat(opc, "${s} $dst, $a, $b"), 638 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>; 639} 640} 641 642//===----------------------------------------------------------------------===// 643// Instructions 644//===----------------------------------------------------------------------===// 645 646//===----------------------------------------------------------------------===// 647// Miscellaneous Instructions. 648// 649let isImplicitDef = 1 in 650def IMPLICIT_DEF_GPR : 651PseudoInst<(outs GPR:$rD), (ins pred:$p), 652 "@ IMPLICIT_DEF_GPR $rD", 653 [(set GPR:$rD, (undef))]>; 654 655 656/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 657/// the function. The first operand is the ID# for this instruction, the second 658/// is the index into the MachineConstantPool that this is, the third is the 659/// size in bytes of this constant pool entry. 660let isNotDuplicable = 1 in 661def CONSTPOOL_ENTRY : 662PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 663 i32imm:$size), 664 "${instid:label} ${cpidx:cpentry}", []>; 665 666let Defs = [SP], Uses = [SP] in { 667def ADJCALLSTACKUP : 668PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), 669 "@ ADJCALLSTACKUP $amt1", 670 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>; 671 672def ADJCALLSTACKDOWN : 673PseudoInst<(outs), (ins i32imm:$amt, pred:$p), 674 "@ ADJCALLSTACKDOWN $amt", 675 [(ARMcallseq_start imm:$amt)]>; 676} 677 678def DWARF_LOC : 679PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), 680 ".loc $file, $line, $col", 681 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>; 682 683let isNotDuplicable = 1 in { 684def PICADD : AXI1<0x0, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 685 Pseudo, "$cp:\n\tadd$p $dst, pc, $a", 686 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; 687 688let isLoad = 1, AddedComplexity = 10 in { 689def PICLD : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 690 Pseudo, "${addr:label}:\n\tldr$p $dst, $addr", 691 [(set GPR:$dst, (load addrmodepc:$addr))]>; 692 693def PICLDZH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 694 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr", 695 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>; 696 697def PICLDZB : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 698 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr", 699 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>; 700 701def PICLDH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 702 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr", 703 [(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>; 704 705def PICLDB : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 706 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr", 707 [(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>; 708 709def PICLDSH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 710 Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr", 711 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>; 712 713def PICLDSB : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 714 Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr", 715 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>; 716} 717let isStore = 1, AddedComplexity = 10 in { 718def PICSTR : AXI2<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 719 Pseudo, "${addr:label}:\n\tstr$p $src, $addr", 720 [(store GPR:$src, addrmodepc:$addr)]>; 721 722def PICSTRH : AXI3<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 723 Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr", 724 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>; 725 726def PICSTRB : AXI2<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 727 Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr", 728 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 729} 730} 731 732//===----------------------------------------------------------------------===// 733// Control Flow Instructions. 734// 735 736let isReturn = 1, isTerminator = 1 in 737 def BX_RET : AI<0x1, (outs), (ins), BranchMisc, "bx", " lr", [(ARMretflag)]>; 738 739// FIXME: remove when we have a way to marking a MI with these properties. 740// FIXME: $dst1 should be a def. But the extra ops must be in the end of the 741// operand list. 742let isLoad = 1, isReturn = 1, isTerminator = 1 in 743 def LDM_RET : AXI4<0x0, (outs), 744 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), 745 LdFrm, "ldm${p}${addr:submode} $addr, $dst1", 746 []>; 747 748let isCall = 1, 749 Defs = [R0, R1, R2, R3, R12, LR, 750 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { 751 def BL : AXI<0xB, (outs), (ins i32imm:$func, variable_ops), Branch, 752 "bl ${func:call}", 753 [(ARMcall tglobaladdr:$func)]>; 754 755 def BL_pred : AI<0xB, (outs), (ins i32imm:$func, variable_ops), 756 Branch, "bl", " ${func:call}", 757 [(ARMcall_pred tglobaladdr:$func)]>; 758 759 // ARMv5T and above 760 def BLX : AXI<0x2, (outs), (ins GPR:$func, variable_ops), BranchMisc, 761 "blx $func", 762 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]>; 763 let Uses = [LR] in { 764 // ARMv4T 765 def BX : AXIx2<0x0, (outs), (ins GPR:$func, variable_ops), 766 BranchMisc, "mov lr, pc\n\tbx $func", 767 [(ARMcall_nolink GPR:$func)]>; 768 } 769} 770 771let isBranch = 1, isTerminator = 1 in { 772 // B is "predicable" since it can be xformed into a Bcc. 773 let isBarrier = 1 in { 774 let isPredicable = 1 in 775 def B : AXI<0xA, (outs), (ins brtarget:$target), Branch, "b $target", 776 [(br bb:$target)]>; 777 778 let isNotDuplicable = 1, isIndirectBranch = 1 in { 779 def BR_JTr : JTI<0x0, (outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), 780 "mov pc, $target \n$jt", 781 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>; 782 def BR_JTm : JTI2<0x0, (outs), (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id), 783 "ldr pc, $target \n$jt", 784 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, 785 imm:$id)]>; 786 def BR_JTadd : JTI1<0x0, (outs), (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, 787 i32imm:$id), 788 "add pc, $target, $idx \n$jt", 789 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, 790 imm:$id)]>; 791 } 792 } 793 794 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 795 // a two-value operand where a dag node expects two operands. :( 796 def Bcc : AI<0xA, (outs), (ins brtarget:$target), Branch, 797 "b", " $target", 798 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>; 799} 800 801//===----------------------------------------------------------------------===// 802// Load / store Instructions. 803// 804 805// Load 806let isLoad = 1 in { 807def LDR : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm, 808 "ldr", " $dst, $addr", 809 [(set GPR:$dst, (load addrmode2:$addr))]>; 810 811// Special LDR for loads from non-pc-relative constpools. 812let isReMaterializable = 1 in 813def LDRcp : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm, 814 "ldr", " $dst, $addr", []>; 815 816// Loads with zero extension 817def LDRH : AI3<0xB, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm, 818 "ldr", "h $dst, $addr", 819 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>; 820 821def LDRB : AI2<0x1, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm, 822 "ldr", "b $dst, $addr", 823 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>; 824 825// Loads with sign extension 826def LDRSH : AI3<0xE, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm, 827 "ldr", "sh $dst, $addr", 828 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>; 829 830def LDRSB : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm, 831 "ldr", "sb $dst, $addr", 832 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>; 833 834// Load doubleword 835def LDRD : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm, 836 "ldr", "d $dst, $addr", 837 []>, Requires<[IsARM, HasV5T]>; 838 839// Indexed loads 840def LDR_PRE : AI2pr<0x0, (outs GPR:$dst, GPR:$base_wb), 841 (ins addrmode2:$addr), LdFrm, 842 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>; 843 844def LDR_POST : AI2po<0x0, (outs GPR:$dst, GPR:$base_wb), 845 (ins GPR:$base, am2offset:$offset), LdFrm, 846 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>; 847 848def LDRH_PRE : AI3pr<0xB, (outs GPR:$dst, GPR:$base_wb), 849 (ins addrmode3:$addr), LdFrm, 850 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>; 851 852def LDRH_POST : AI3po<0xB, (outs GPR:$dst, GPR:$base_wb), 853 (ins GPR:$base,am3offset:$offset), LdFrm, 854 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>; 855 856def LDRB_PRE : AI2pr<0x1, (outs GPR:$dst, GPR:$base_wb), 857 (ins addrmode2:$addr), LdFrm, 858 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>; 859 860def LDRB_POST : AI2po<0x1, (outs GPR:$dst, GPR:$base_wb), 861 (ins GPR:$base,am2offset:$offset), LdFrm, 862 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>; 863 864def LDRSH_PRE : AI3pr<0xE, (outs GPR:$dst, GPR:$base_wb), 865 (ins addrmode3:$addr), LdFrm, 866 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>; 867 868def LDRSH_POST: AI3po<0xE, (outs GPR:$dst, GPR:$base_wb), 869 (ins GPR:$base,am3offset:$offset), LdFrm, 870 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>; 871 872def LDRSB_PRE : AI3pr<0xD, (outs GPR:$dst, GPR:$base_wb), 873 (ins addrmode3:$addr), LdFrm, 874 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>; 875 876def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb), 877 (ins GPR:$base,am3offset:$offset), LdFrm, 878 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>; 879} // isLoad 880 881// Store 882let isStore = 1 in { 883def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm, 884 "str", " $src, $addr", 885 [(store GPR:$src, addrmode2:$addr)]>; 886 887// Stores with truncate 888def STRH : AI3<0xB, (outs), (ins GPR:$src, addrmode3:$addr), StFrm, 889 "str", "h $src, $addr", 890 [(truncstorei16 GPR:$src, addrmode3:$addr)]>; 891 892def STRB : AI2<0x1, (outs), (ins GPR:$src, addrmode2:$addr), StFrm, 893 "str", "b $src, $addr", 894 [(truncstorei8 GPR:$src, addrmode2:$addr)]>; 895 896// Store doubleword 897def STRD : AI3<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm, 898 "str", "d $src, $addr", 899 []>, Requires<[IsARM, HasV5T]>; 900 901// Indexed stores 902def STR_PRE : AI2pr<0x0, (outs GPR:$base_wb), 903 (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm, 904 "str", " $src, [$base, $offset]!", "$base = $base_wb", 905 [(set GPR:$base_wb, 906 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>; 907 908def STR_POST : AI2po<0x0, (outs GPR:$base_wb), 909 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, 910 "str", " $src, [$base], $offset", "$base = $base_wb", 911 [(set GPR:$base_wb, 912 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>; 913 914def STRH_PRE : AI3pr<0xB, (outs GPR:$base_wb), 915 (ins GPR:$src, GPR:$base,am3offset:$offset), StFrm, 916 "str", "h $src, [$base, $offset]!", "$base = $base_wb", 917 [(set GPR:$base_wb, 918 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>; 919 920def STRH_POST: AI3po<0xB, (outs GPR:$base_wb), 921 (ins GPR:$src, GPR:$base,am3offset:$offset), StFrm, 922 "str", "h $src, [$base], $offset", "$base = $base_wb", 923 [(set GPR:$base_wb, (post_truncsti16 GPR:$src, 924 GPR:$base, am3offset:$offset))]>; 925 926def STRB_PRE : AI2pr<0x1, (outs GPR:$base_wb), 927 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, 928 "str", "b $src, [$base, $offset]!", "$base = $base_wb", 929 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src, 930 GPR:$base, am2offset:$offset))]>; 931 932def STRB_POST: AI2po<0x1, (outs GPR:$base_wb), 933 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, 934 "str", "b $src, [$base], $offset", "$base = $base_wb", 935 [(set GPR:$base_wb, (post_truncsti8 GPR:$src, 936 GPR:$base, am2offset:$offset))]>; 937} // isStore 938 939//===----------------------------------------------------------------------===// 940// Load / store multiple Instructions. 941// 942 943// FIXME: $dst1 should be a def. 944let isLoad = 1 in 945def LDM : AXI4<0x0, (outs), 946 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), 947 LdFrm, "ldm${p}${addr:submode} $addr, $dst1", 948 []>; 949 950let isStore = 1 in 951def STM : AXI4<0x0, (outs), 952 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), 953 StFrm, "stm${p}${addr:submode} $addr, $src1", 954 []>; 955 956//===----------------------------------------------------------------------===// 957// Move Instructions. 958// 959 960def MOVr : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdReg, 961 "mov", " $dst, $src", []>; 962def MOVs : AsI1<0xD, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg, 963 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>; 964 965let isReMaterializable = 1 in 966def MOVi : AsI1<0xD, (outs GPR:$dst), (ins so_imm:$src), DPRdIm, 967 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>; 968 969def MOVrx : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc, 970 "mov", " $dst, $src, rrx", 971 [(set GPR:$dst, (ARMrrx GPR:$src))]>; 972 973// These aren't really mov instructions, but we have to define them this way 974// due to flag operands. 975 976let Defs = [CPSR] in { 977def MOVsrl_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc, 978 "mov", "s $dst, $src, lsr #1", 979 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>; 980def MOVsra_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc, 981 "mov", "s $dst, $src, asr #1", 982 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>; 983} 984 985//===----------------------------------------------------------------------===// 986// Extend Instructions. 987// 988 989// Sign extenders 990 991defm SXTB : AI_unary_rrot<0x0, "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 992defm SXTH : AI_unary_rrot<0x0, "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 993 994defm SXTAB : AI_bin_rrot<0x0, "sxtab", 995 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 996defm SXTAH : AI_bin_rrot<0x0, "sxtah", 997 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 998 999// TODO: SXT(A){B|H}16 1000 1001// Zero extenders 1002 1003let AddedComplexity = 16 in { 1004defm UXTB : AI_unary_rrot<0x0, "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 1005defm UXTH : AI_unary_rrot<0x0, "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 1006defm UXTB16 : AI_unary_rrot<0x0, "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 1007 1008def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF), 1009 (UXTB16r_rot GPR:$Src, 24)>; 1010def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF), 1011 (UXTB16r_rot GPR:$Src, 8)>; 1012 1013defm UXTAB : AI_bin_rrot<0x0, "uxtab", 1014 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 1015defm UXTAH : AI_bin_rrot<0x0, "uxtah", 1016 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 1017} 1018 1019// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 1020//defm UXTAB16 : xxx<"uxtab16", 0xff00ff>; 1021 1022// TODO: UXT(A){B|H}16 1023 1024//===----------------------------------------------------------------------===// 1025// Arithmetic Instructions. 1026// 1027 1028defm ADD : AsI1_bin_irs<0x4, "add", BinOpFrag<(add node:$LHS, node:$RHS)>>; 1029defm SUB : AsI1_bin_irs<0x2, "sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>; 1030 1031// ADD and SUB with 's' bit set. 1032defm ADDS : ASI1_bin_s_irs<0x4, "add", BinOpFrag<(addc node:$LHS, node:$RHS)>>; 1033defm SUBS : ASI1_bin_s_irs<0x2, "sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>; 1034 1035// FIXME: Do not allow ADC / SBC to be predicated for now. 1036defm ADC : AsXI1_bin_c_irs<0x5, "adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>; 1037defm SBC : AsXI1_bin_c_irs<0x6, "sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>; 1038 1039// These don't define reg/reg forms, because they are handled above. 1040def RSBri : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm, 1041 "rsb", " $dst, $a, $b", 1042 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>; 1043 1044def RSBrs : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg, 1045 "rsb", " $dst, $a, $b", 1046 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>; 1047 1048// RSB with 's' bit set. 1049let Defs = [CPSR] in { 1050def RSBSri : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm, 1051 "rsb", "s $dst, $a, $b", 1052 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>; 1053def RSBSrs : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg, 1054 "rsb", "s $dst, $a, $b", 1055 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>; 1056} 1057 1058// FIXME: Do not allow RSC to be predicated for now. But they can set CPSR. 1059let Uses = [CPSR] in { 1060def RSCri : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s), 1061 DPRIm, "rsc${s} $dst, $a, $b", 1062 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>; 1063def RSCrs : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s), 1064 DPRSoReg, "rsc${s} $dst, $a, $b", 1065 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>; 1066} 1067 1068// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 1069def : ARMPat<(add GPR:$src, so_imm_neg:$imm), 1070 (SUBri GPR:$src, so_imm_neg:$imm)>; 1071 1072//def : ARMPat<(addc GPR:$src, so_imm_neg:$imm), 1073// (SUBSri GPR:$src, so_imm_neg:$imm)>; 1074//def : ARMPat<(adde GPR:$src, so_imm_neg:$imm), 1075// (SBCri GPR:$src, so_imm_neg:$imm)>; 1076 1077// Note: These are implemented in C++ code, because they have to generate 1078// ADD/SUBrs instructions, which use a complex pattern that a xform function 1079// cannot produce. 1080// (mul X, 2^n+1) -> (add (X << n), X) 1081// (mul X, 2^n-1) -> (rsb X, (X << n)) 1082 1083 1084//===----------------------------------------------------------------------===// 1085// Bitwise Instructions. 1086// 1087 1088defm AND : AsI1_bin_irs<0x0, "and", BinOpFrag<(and node:$LHS, node:$RHS)>>; 1089defm ORR : AsI1_bin_irs<0xC, "orr", BinOpFrag<(or node:$LHS, node:$RHS)>>; 1090defm EOR : AsI1_bin_irs<0x1, "eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>; 1091defm BIC : AsI1_bin_irs<0xE, "bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 1092 1093def MVNr : AsI<0xE, (outs GPR:$dst), (ins GPR:$src), DPRdReg, 1094 "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>; 1095def MVNs : AsI<0xE, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg, 1096 "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>; 1097let isReMaterializable = 1 in 1098def MVNi : AsI<0xE, (outs GPR:$dst), (ins so_imm:$imm), DPRdIm, 1099 "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>; 1100 1101def : ARMPat<(and GPR:$src, so_imm_not:$imm), 1102 (BICri GPR:$src, so_imm_not:$imm)>; 1103 1104//===----------------------------------------------------------------------===// 1105// Multiply Instructions. 1106// 1107 1108def MUL : AsI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm, 1109 "mul", " $dst, $a, $b", 1110 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; 1111 1112def MLA : AsI<0x2, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 1113 MulFrm, "mla", " $dst, $a, $b, $c", 1114 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; 1115 1116// Extra precision multiplies with low / high results 1117def SMULL : AsI<0xC, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 1118 MulFrm, "smull", " $ldst, $hdst, $a, $b", []>; 1119 1120def UMULL : AsI<0x8, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 1121 MulFrm, "umull", " $ldst, $hdst, $a, $b", []>; 1122 1123// Multiply + accumulate 1124def SMLAL : AsI<0xE, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 1125 MulFrm, "smlal", " $ldst, $hdst, $a, $b", []>; 1126 1127def UMLAL : AsI<0xA, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 1128 MulFrm, "umlal", " $ldst, $hdst, $a, $b", []>; 1129 1130def UMAAL : AI<0x0, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), MulFrm, 1131 "umaal", " $ldst, $hdst, $a, $b", []>, 1132 Requires<[IsARM, HasV6]>; 1133 1134// Most significant word multiply 1135def SMMUL : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm, 1136 "smmul", " $dst, $a, $b", 1137 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>, 1138 Requires<[IsARM, HasV6]>; 1139 1140def SMMLA : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm, 1141 "smmla", " $dst, $a, $b, $c", 1142 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>, 1143 Requires<[IsARM, HasV6]>; 1144 1145 1146def SMMLS : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm, 1147 "smmls", " $dst, $a, $b, $c", 1148 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>, 1149 Requires<[IsARM, HasV6]>; 1150 1151multiclass AI_smul<string opc, PatFrag opnode> { 1152 def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL, 1153 !strconcat(opc, "bb"), " $dst, $a, $b", 1154 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 1155 (sext_inreg GPR:$b, i16)))]>, 1156 Requires<[IsARM, HasV5TE]>; 1157 1158 def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL, 1159 !strconcat(opc, "bt"), " $dst, $a, $b", 1160 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 1161 (sra GPR:$b, 16)))]>, 1162 Requires<[IsARM, HasV5TE]>; 1163 1164 def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL, 1165 !strconcat(opc, "tb"), " $dst, $a, $b", 1166 [(set GPR:$dst, (opnode (sra GPR:$a, 16), 1167 (sext_inreg GPR:$b, i16)))]>, 1168 Requires<[IsARM, HasV5TE]>; 1169 1170 def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL, 1171 !strconcat(opc, "tt"), " $dst, $a, $b", 1172 [(set GPR:$dst, (opnode (sra GPR:$a, 16), 1173 (sra GPR:$b, 16)))]>, 1174 Requires<[IsARM, HasV5TE]>; 1175 1176 def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW, 1177 !strconcat(opc, "wb"), " $dst, $a, $b", 1178 [(set GPR:$dst, (sra (opnode GPR:$a, 1179 (sext_inreg GPR:$b, i16)), 16))]>, 1180 Requires<[IsARM, HasV5TE]>; 1181 1182 def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW, 1183 !strconcat(opc, "wt"), " $dst, $a, $b", 1184 [(set GPR:$dst, (sra (opnode GPR:$a, 1185 (sra GPR:$b, 16)), 16))]>, 1186 Requires<[IsARM, HasV5TE]>; 1187} 1188 1189 1190multiclass AI_smla<string opc, PatFrag opnode> { 1191 def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA, 1192 !strconcat(opc, "bb"), " $dst, $a, $b, $acc", 1193 [(set GPR:$dst, (add GPR:$acc, 1194 (opnode (sext_inreg GPR:$a, i16), 1195 (sext_inreg GPR:$b, i16))))]>, 1196 Requires<[IsARM, HasV5TE]>; 1197 1198 def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA, 1199 !strconcat(opc, "bt"), " $dst, $a, $b, $acc", 1200 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), 1201 (sra GPR:$b, 16))))]>, 1202 Requires<[IsARM, HasV5TE]>; 1203 1204 def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA, 1205 !strconcat(opc, "tb"), " $dst, $a, $b, $acc", 1206 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16), 1207 (sext_inreg GPR:$b, i16))))]>, 1208 Requires<[IsARM, HasV5TE]>; 1209 1210 def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA, 1211 !strconcat(opc, "tt"), " $dst, $a, $b, $acc", 1212 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16), 1213 (sra GPR:$b, 16))))]>, 1214 Requires<[IsARM, HasV5TE]>; 1215 1216 def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW, 1217 !strconcat(opc, "wb"), " $dst, $a, $b, $acc", 1218 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 1219 (sext_inreg GPR:$b, i16)), 16)))]>, 1220 Requires<[IsARM, HasV5TE]>; 1221 1222 def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW, 1223 !strconcat(opc, "wt"), " $dst, $a, $b, $acc", 1224 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 1225 (sra GPR:$b, 16)), 16)))]>, 1226 Requires<[IsARM, HasV5TE]>; 1227} 1228 1229defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 1230defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 1231 1232// TODO: Halfword multiple accumulate long: SMLAL<x><y> 1233// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 1234 1235//===----------------------------------------------------------------------===// 1236// Misc. Arithmetic Instructions. 1237// 1238 1239def CLZ : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc, 1240 "clz", " $dst, $src", 1241 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>; 1242 1243def REV : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc, 1244 "rev", " $dst, $src", 1245 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>; 1246 1247def REV16 : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc, 1248 "rev16", " $dst, $src", 1249 [(set GPR:$dst, 1250 (or (and (srl GPR:$src, 8), 0xFF), 1251 (or (and (shl GPR:$src, 8), 0xFF00), 1252 (or (and (srl GPR:$src, 8), 0xFF0000), 1253 (and (shl GPR:$src, 8), 0xFF000000)))))]>, 1254 Requires<[IsARM, HasV6]>; 1255 1256def REVSH : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc, 1257 "revsh", " $dst, $src", 1258 [(set GPR:$dst, 1259 (sext_inreg 1260 (or (srl (and GPR:$src, 0xFF00), 8), 1261 (shl GPR:$src, 8)), i16))]>, 1262 Requires<[IsARM, HasV6]>; 1263 1264def PKHBT : AI<0x0, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 1265 Pseudo, "pkhbt", " $dst, $src1, $src2, LSL $shamt", 1266 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), 1267 (and (shl GPR:$src2, (i32 imm:$shamt)), 1268 0xFFFF0000)))]>, 1269 Requires<[IsARM, HasV6]>; 1270 1271// Alternate cases for PKHBT where identities eliminate some nodes. 1272def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)), 1273 (PKHBT GPR:$src1, GPR:$src2, 0)>; 1274def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)), 1275 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>; 1276 1277 1278def PKHTB : AI<0x0, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 1279 Pseudo, "pkhtb", " $dst, $src1, $src2, ASR $shamt", 1280 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), 1281 (and (sra GPR:$src2, imm16_31:$shamt), 1282 0xFFFF)))]>, Requires<[IsARM, HasV6]>; 1283 1284// Alternate cases for PKHTB where identities eliminate some nodes. Note that 1285// a shift amount of 0 is *not legal* here, it is PKHBT instead. 1286def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)), 1287 (PKHTB GPR:$src1, GPR:$src2, 16)>; 1288def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), 1289 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)), 1290 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>; 1291 1292 1293//===----------------------------------------------------------------------===// 1294// Comparison Instructions... 1295// 1296 1297defm CMP : AI1_cmp_irs<0xA, "cmp", 1298 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 1299defm CMN : AI1_cmp_irs<0xB, "cmn", 1300 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; 1301 1302// Note that TST/TEQ don't set all the same flags that CMP does! 1303defm TST : AI1_cmp_irs<0x8, "tst", 1304 BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>; 1305defm TEQ : AI1_cmp_irs<0x9, "teq", 1306 BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>; 1307 1308defm CMPnz : AI1_cmp_irs<0xA, "cmp", 1309 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>; 1310defm CMNnz : AI1_cmp_irs<0xA, "cmn", 1311 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>; 1312 1313def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm), 1314 (CMNri GPR:$src, so_imm_neg:$imm)>; 1315 1316def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm), 1317 (CMNri GPR:$src, so_imm_neg:$imm)>; 1318 1319 1320// Conditional moves 1321// FIXME: should be able to write a pattern for ARMcmov, but can't use 1322// a two-value operand where a dag node expects two operands. :( 1323def MOVCCr : AI<0xD, (outs GPR:$dst), (ins GPR:$false, GPR:$true), 1324 DPRdReg, "mov", " $dst, $true", 1325 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, 1326 RegConstraint<"$false = $dst">; 1327 1328def MOVCCs : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_reg:$true), 1329 DPRdSoReg, "mov", " $dst, $true", 1330 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>, 1331 RegConstraint<"$false = $dst">; 1332 1333def MOVCCi : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_imm:$true), 1334 DPRdIm, "mov", " $dst, $true", 1335 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>, 1336 RegConstraint<"$false = $dst">; 1337 1338 1339// LEApcrel - Load a pc-relative address into a register without offending the 1340// assembler. 1341def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo, 1342 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(", 1343 "${:private}PCRELL${:uid}+8))\n"), 1344 !strconcat("${:private}PCRELL${:uid}:\n\t", 1345 "add$p $dst, pc, #PCRELV${:uid}")), 1346 []>; 1347 1348def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p), 1349 Pseudo, 1350 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(", 1351 "${:private}PCRELL${:uid}+8))\n"), 1352 !strconcat("${:private}PCRELL${:uid}:\n\t", 1353 "add$p $dst, pc, #PCRELV${:uid}")), 1354 []>; 1355 1356//===----------------------------------------------------------------------===// 1357// TLS Instructions 1358// 1359 1360// __aeabi_read_tp preserves the registers r1-r3. 1361let isCall = 1, 1362 Defs = [R0, R12, LR, CPSR] in { 1363 def TPsoft : AXI<0x0, (outs), (ins), BranchMisc, 1364 "bl __aeabi_read_tp", 1365 [(set R0, ARMthread_pointer)]>; 1366} 1367 1368//===----------------------------------------------------------------------===// 1369// Non-Instruction Patterns 1370// 1371 1372// ConstantPool, GlobalAddress, and JumpTable 1373def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>; 1374def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 1375def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1376 (LEApcrelJT tjumptable:$dst, imm:$id)>; 1377 1378// Large immediate handling. 1379 1380// Two piece so_imms. 1381let isReMaterializable = 1 in 1382def MOVi2pieces : AI1x2<0x0, (outs GPR:$dst), (ins so_imm2part:$src), DPRdMisc, 1383 "mov", " $dst, $src", 1384 [(set GPR:$dst, so_imm2part:$src)]>; 1385 1386def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS), 1387 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)), 1388 (so_imm2part_2 imm:$RHS))>; 1389def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS), 1390 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)), 1391 (so_imm2part_2 imm:$RHS))>; 1392 1393// TODO: add,sub,and, 3-instr forms? 1394 1395 1396// Direct calls 1397def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 1398 1399// zextload i1 -> zextload i8 1400def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>; 1401 1402// extload -> zextload 1403def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>; 1404def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>; 1405def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 1406 1407// truncstore i1 -> truncstore i8 1408def : ARMPat<(truncstorei1 GPR:$src, addrmode2:$dst), 1409 (STRB GPR:$src, addrmode2:$dst)>; 1410def : ARMPat<(pre_truncsti1 GPR:$src, GPR:$base, am2offset:$offset), 1411 (STRB_PRE GPR:$src, GPR:$base, am2offset:$offset)>; 1412def : ARMPat<(post_truncsti1 GPR:$src, GPR:$base, am2offset:$offset), 1413 (STRB_POST GPR:$src, GPR:$base, am2offset:$offset)>; 1414 1415// smul* and smla* 1416def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)), 1417 (SMULBB GPR:$a, GPR:$b)>; 1418def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 1419 (SMULBB GPR:$a, GPR:$b)>; 1420def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)), 1421 (SMULBT GPR:$a, GPR:$b)>; 1422def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)), 1423 (SMULBT GPR:$a, GPR:$b)>; 1424def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)), 1425 (SMULTB GPR:$a, GPR:$b)>; 1426def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b), 1427 (SMULTB GPR:$a, GPR:$b)>; 1428def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16), 1429 (SMULWB GPR:$a, GPR:$b)>; 1430def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16), 1431 (SMULWB GPR:$a, GPR:$b)>; 1432 1433def : ARMV5TEPat<(add GPR:$acc, 1434 (mul (sra (shl GPR:$a, 16), 16), 1435 (sra (shl GPR:$b, 16), 16))), 1436 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 1437def : ARMV5TEPat<(add GPR:$acc, 1438 (mul sext_16_node:$a, sext_16_node:$b)), 1439 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 1440def : ARMV5TEPat<(add GPR:$acc, 1441 (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))), 1442 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 1443def : ARMV5TEPat<(add GPR:$acc, 1444 (mul sext_16_node:$a, (sra GPR:$b, 16))), 1445 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 1446def : ARMV5TEPat<(add GPR:$acc, 1447 (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))), 1448 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 1449def : ARMV5TEPat<(add GPR:$acc, 1450 (mul (sra GPR:$a, 16), sext_16_node:$b)), 1451 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 1452def : ARMV5TEPat<(add GPR:$acc, 1453 (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)), 1454 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 1455def : ARMV5TEPat<(add GPR:$acc, 1456 (sra (mul GPR:$a, sext_16_node:$b), 16)), 1457 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 1458 1459//===----------------------------------------------------------------------===// 1460// Thumb Support 1461// 1462 1463include "ARMInstrThumb.td" 1464 1465//===----------------------------------------------------------------------===// 1466// Floating Point Support 1467// 1468 1469include "ARMInstrVFP.td" 1470