ARMInstrInfo.td revision a5dbe29ff54ce5bb3aecefc7d42af6f31bd7e903
1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// ARM specific DAG Nodes. 16// 17 18// Type profiles. 19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 21def SDT_ARMStructByVal : SDTypeProfile<0, 4, 22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 24 25def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 26 27def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 28 29def SDT_ARMCMov : SDTypeProfile<1, 3, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 31 SDTCisVT<3, i32>]>; 32 33def SDT_ARMBrcond : SDTypeProfile<0, 2, 34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 35 36def SDT_ARMBrJT : SDTypeProfile<0, 3, 37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 38 SDTCisVT<2, i32>]>; 39 40def SDT_ARMBr2JT : SDTypeProfile<0, 4, 41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 43 44def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 45 [SDTCisVT<0, i32>, 46 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 47 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 48 SDTCisVT<5, OtherVT>]>; 49 50def SDT_ARMAnd : SDTypeProfile<1, 2, 51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 52 SDTCisVT<2, i32>]>; 53 54def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 55 56def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 58 59def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 60def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 61 SDTCisInt<2>]>; 62def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 63 64def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 65 66def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 67 SDTCisInt<1>]>; 68 69def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 70 71def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 73 74def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 75 [SDTCisSameAs<0, 2>, 76 SDTCisSameAs<0, 3>, 77 SDTCisInt<0>, SDTCisVT<1, i32>]>; 78 79// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 80def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 81 [SDTCisSameAs<0, 2>, 82 SDTCisSameAs<0, 3>, 83 SDTCisInt<0>, 84 SDTCisVT<1, i32>, 85 SDTCisVT<4, i32>]>; 86 87def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>, 88 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 89 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >; 90def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>; 91def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>; 92 93// Node definitions. 94def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 95def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>; 96def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 97def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>; 98 99def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 100 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 101def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 102 [SDNPHasChain, SDNPSideEffect, 103 SDNPOptInGlue, SDNPOutGlue]>; 104def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , 105 SDT_ARMStructByVal, 106 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 107 SDNPMayStore, SDNPMayLoad]>; 108 109def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 111 SDNPVariadic]>; 112def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 113 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 114 SDNPVariadic]>; 115def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 117 SDNPVariadic]>; 118 119def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 120 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 121 122def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 123 [SDNPInGlue]>; 124 125def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 126 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 127 128def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 129 [SDNPHasChain]>; 130def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 131 [SDNPHasChain]>; 132 133def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 134 [SDNPHasChain]>; 135 136def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 137 [SDNPOutGlue]>; 138 139def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, 140 [SDNPOutGlue]>; 141 142def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 143 [SDNPOutGlue, SDNPCommutative]>; 144 145def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 146 147def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 148def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 149def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 150 151def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 152 [SDNPCommutative]>; 153def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 154def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 155def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 156 157def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 158def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 159 SDT_ARMEH_SJLJ_Setjmp, 160 [SDNPHasChain, SDNPSideEffect]>; 161def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 162 SDT_ARMEH_SJLJ_Longjmp, 163 [SDNPHasChain, SDNPSideEffect]>; 164 165def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER, 166 [SDNPHasChain, SDNPSideEffect]>; 167def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 168 [SDNPHasChain, SDNPSideEffect]>; 169def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 170 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 171 172def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>; 173 174def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 175 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 176 177 178def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 179 180//===----------------------------------------------------------------------===// 181// ARM Instruction Predicate Definitions. 182// 183def HasV4T : Predicate<"Subtarget->hasV4TOps()">, 184 AssemblerPredicate<"HasV4TOps", "armv4t">; 185def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; 186def HasV5T : Predicate<"Subtarget->hasV5TOps()">; 187def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, 188 AssemblerPredicate<"HasV5TEOps", "armv5te">; 189def HasV6 : Predicate<"Subtarget->hasV6Ops()">, 190 AssemblerPredicate<"HasV6Ops", "armv6">; 191def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; 192def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, 193 AssemblerPredicate<"HasV6T2Ops", "armv6t2">; 194def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; 195def HasV7 : Predicate<"Subtarget->hasV7Ops()">, 196 AssemblerPredicate<"HasV7Ops", "armv7">; 197def NoVFP : Predicate<"!Subtarget->hasVFP2()">; 198def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, 199 AssemblerPredicate<"FeatureVFP2", "VFP2">; 200def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, 201 AssemblerPredicate<"FeatureVFP3", "VFP3">; 202def HasVFP4 : Predicate<"Subtarget->hasVFP4()">, 203 AssemblerPredicate<"FeatureVFP4", "VFP4">; 204def HasNEON : Predicate<"Subtarget->hasNEON()">, 205 AssemblerPredicate<"FeatureNEON", "NEON">; 206def HasFP16 : Predicate<"Subtarget->hasFP16()">, 207 AssemblerPredicate<"FeatureFP16","half-float">; 208def HasDivide : Predicate<"Subtarget->hasDivide()">, 209 AssemblerPredicate<"FeatureHWDiv", "divide">; 210def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, 211 AssemblerPredicate<"FeatureHWDivARM">; 212def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">, 213 AssemblerPredicate<"FeatureT2XtPk", 214 "pack/extract">; 215def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">, 216 AssemblerPredicate<"FeatureDSPThumb2", 217 "thumb2-dsp">; 218def HasDB : Predicate<"Subtarget->hasDataBarrier()">, 219 AssemblerPredicate<"FeatureDB", 220 "data-barriers">; 221def HasMP : Predicate<"Subtarget->hasMPExtension()">, 222 AssemblerPredicate<"FeatureMP", 223 "mp-extensions">; 224def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; 225def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; 226def IsThumb : Predicate<"Subtarget->isThumb()">, 227 AssemblerPredicate<"ModeThumb", "thumb">; 228def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; 229def IsThumb2 : Predicate<"Subtarget->isThumb2()">, 230 AssemblerPredicate<"ModeThumb,FeatureThumb2", 231 "thumb2">; 232def IsMClass : Predicate<"Subtarget->isMClass()">, 233 AssemblerPredicate<"FeatureMClass", "armv7m">; 234def IsARClass : Predicate<"!Subtarget->isMClass()">, 235 AssemblerPredicate<"!FeatureMClass", 236 "armv7a/r">; 237def IsARM : Predicate<"!Subtarget->isThumb()">, 238 AssemblerPredicate<"!ModeThumb", "arm-mode">; 239def IsIOS : Predicate<"Subtarget->isTargetIOS()">; 240def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">; 241def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 242def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">, 243 AssemblerPredicate<"FeatureNaClTrap", "NaCl">; 244def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">; 245 246// FIXME: Eventually this will be just "hasV6T2Ops". 247def UseMovt : Predicate<"Subtarget->useMovt()">; 248def DontUseMovt : Predicate<"!Subtarget->useMovt()">; 249def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">; 250def UseMulOps : Predicate<"Subtarget->useMulOps()">; 251 252// Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available. 253// But only select them if more precision in FP computation is allowed. 254// Do not use them for Darwin platforms. 255def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion ==" 256 " FPOpFusion::Fast) && " 257 "!Subtarget->isTargetDarwin()">; 258def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || " 259 "Subtarget->isTargetDarwin()">; 260 261// VGETLNi32 is microcoded on Swift - prefer VMOV. 262def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">; 263def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">; 264 265// VDUP.32 is microcoded on Swift - prefer VMOV. 266def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">; 267def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">; 268 269// Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as 270// this allows more effective execution domain optimization. See 271// setExecutionDomain(). 272def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">; 273def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">; 274 275def IsLE : Predicate<"TLI.isLittleEndian()">; 276def IsBE : Predicate<"TLI.isBigEndian()">; 277 278//===----------------------------------------------------------------------===// 279// ARM Flag Definitions. 280 281class RegConstraint<string C> { 282 string Constraints = C; 283} 284 285//===----------------------------------------------------------------------===// 286// ARM specific transformation functions and pattern fragments. 287// 288 289// imm_neg_XFORM - Return the negation of an i32 immediate value. 290def imm_neg_XFORM : SDNodeXForm<imm, [{ 291 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); 292}]>; 293 294// imm_not_XFORM - Return the complement of a i32 immediate value. 295def imm_not_XFORM : SDNodeXForm<imm, [{ 296 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32); 297}]>; 298 299/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 300def imm16_31 : ImmLeaf<i32, [{ 301 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 302}]>; 303 304def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; } 305def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 306 unsigned Value = -(unsigned)N->getZExtValue(); 307 return Value && ARM_AM::getSOImmVal(Value) != -1; 308 }], imm_neg_XFORM> { 309 let ParserMatchClass = so_imm_neg_asmoperand; 310} 311 312// Note: this pattern doesn't require an encoder method and such, as it's 313// only used on aliases (Pat<> and InstAlias<>). The actual encoding 314// is handled by the destination instructions, which use so_imm. 315def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; } 316def so_imm_not : Operand<i32>, PatLeaf<(imm), [{ 317 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 318 }], imm_not_XFORM> { 319 let ParserMatchClass = so_imm_not_asmoperand; 320} 321 322// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 323def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 324 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 325}]>; 326 327/// Split a 32-bit immediate into two 16 bit parts. 328def hi16 : SDNodeXForm<imm, [{ 329 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32); 330}]>; 331 332def lo16AllZero : PatLeaf<(i32 imm), [{ 333 // Returns true if all low 16-bits are 0. 334 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 335}], hi16>; 336 337class BinOpWithFlagFrag<dag res> : 338 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>; 339class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 340class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 341 342// An 'and' node with a single use. 343def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 344 return N->hasOneUse(); 345}]>; 346 347// An 'xor' node with a single use. 348def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 349 return N->hasOneUse(); 350}]>; 351 352// An 'fmul' node with a single use. 353def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 354 return N->hasOneUse(); 355}]>; 356 357// An 'fadd' node which checks for single non-hazardous use. 358def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 359 return hasNoVMLxHazardUse(N); 360}]>; 361 362// An 'fsub' node which checks for single non-hazardous use. 363def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 364 return hasNoVMLxHazardUse(N); 365}]>; 366 367//===----------------------------------------------------------------------===// 368// Operand Definitions. 369// 370 371// Immediate operands with a shared generic asm render method. 372class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; } 373 374// Branch target. 375// FIXME: rename brtarget to t2_brtarget 376def brtarget : Operand<OtherVT> { 377 let EncoderMethod = "getBranchTargetOpValue"; 378 let OperandType = "OPERAND_PCREL"; 379 let DecoderMethod = "DecodeT2BROperand"; 380} 381 382// FIXME: get rid of this one? 383def uncondbrtarget : Operand<OtherVT> { 384 let EncoderMethod = "getUnconditionalBranchTargetOpValue"; 385 let OperandType = "OPERAND_PCREL"; 386} 387 388// Branch target for ARM. Handles conditional/unconditional 389def br_target : Operand<OtherVT> { 390 let EncoderMethod = "getARMBranchTargetOpValue"; 391 let OperandType = "OPERAND_PCREL"; 392} 393 394// Call target. 395// FIXME: rename bltarget to t2_bl_target? 396def bltarget : Operand<i32> { 397 // Encoded the same as branch targets. 398 let EncoderMethod = "getBranchTargetOpValue"; 399 let OperandType = "OPERAND_PCREL"; 400} 401 402// Call target for ARM. Handles conditional/unconditional 403// FIXME: rename bl_target to t2_bltarget? 404def bl_target : Operand<i32> { 405 let EncoderMethod = "getARMBLTargetOpValue"; 406 let OperandType = "OPERAND_PCREL"; 407} 408 409def blx_target : Operand<i32> { 410 let EncoderMethod = "getARMBLXTargetOpValue"; 411 let OperandType = "OPERAND_PCREL"; 412} 413 414// A list of registers separated by comma. Used by load/store multiple. 415def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 416def reglist : Operand<i32> { 417 let EncoderMethod = "getRegisterListOpValue"; 418 let ParserMatchClass = RegListAsmOperand; 419 let PrintMethod = "printRegisterList"; 420 let DecoderMethod = "DecodeRegListOperand"; 421} 422 423def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">; 424 425def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; } 426def dpr_reglist : Operand<i32> { 427 let EncoderMethod = "getRegisterListOpValue"; 428 let ParserMatchClass = DPRRegListAsmOperand; 429 let PrintMethod = "printRegisterList"; 430 let DecoderMethod = "DecodeDPRRegListOperand"; 431} 432 433def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; } 434def spr_reglist : Operand<i32> { 435 let EncoderMethod = "getRegisterListOpValue"; 436 let ParserMatchClass = SPRRegListAsmOperand; 437 let PrintMethod = "printRegisterList"; 438 let DecoderMethod = "DecodeSPRRegListOperand"; 439} 440 441// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 442def cpinst_operand : Operand<i32> { 443 let PrintMethod = "printCPInstOperand"; 444} 445 446// Local PC labels. 447def pclabel : Operand<i32> { 448 let PrintMethod = "printPCLabel"; 449} 450 451// ADR instruction labels. 452def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } 453def adrlabel : Operand<i32> { 454 let EncoderMethod = "getAdrLabelOpValue"; 455 let ParserMatchClass = AdrLabelAsmOperand; 456 let PrintMethod = "printAdrLabelOperand"; 457} 458 459def neon_vcvt_imm32 : Operand<i32> { 460 let EncoderMethod = "getNEONVcvtImm32OpValue"; 461 let DecoderMethod = "DecodeVCVTImmOperand"; 462} 463 464// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 465def rot_imm_XFORM: SDNodeXForm<imm, [{ 466 switch (N->getZExtValue()){ 467 default: assert(0); 468 case 0: return CurDAG->getTargetConstant(0, MVT::i32); 469 case 8: return CurDAG->getTargetConstant(1, MVT::i32); 470 case 16: return CurDAG->getTargetConstant(2, MVT::i32); 471 case 24: return CurDAG->getTargetConstant(3, MVT::i32); 472 } 473}]>; 474def RotImmAsmOperand : AsmOperandClass { 475 let Name = "RotImm"; 476 let ParserMethod = "parseRotImm"; 477} 478def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 479 int32_t v = N->getZExtValue(); 480 return v == 8 || v == 16 || v == 24; }], 481 rot_imm_XFORM> { 482 let PrintMethod = "printRotImmOperand"; 483 let ParserMatchClass = RotImmAsmOperand; 484} 485 486// shift_imm: An integer that encodes a shift amount and the type of shift 487// (asr or lsl). The 6-bit immediate encodes as: 488// {5} 0 ==> lsl 489// 1 asr 490// {4-0} imm5 shift amount. 491// asr #32 encoded as imm5 == 0. 492def ShifterImmAsmOperand : AsmOperandClass { 493 let Name = "ShifterImm"; 494 let ParserMethod = "parseShifterImm"; 495} 496def shift_imm : Operand<i32> { 497 let PrintMethod = "printShiftImmOperand"; 498 let ParserMatchClass = ShifterImmAsmOperand; 499} 500 501// shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm. 502def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 503def so_reg_reg : Operand<i32>, // reg reg imm 504 ComplexPattern<i32, 3, "SelectRegShifterOperand", 505 [shl, srl, sra, rotr]> { 506 let EncoderMethod = "getSORegRegOpValue"; 507 let PrintMethod = "printSORegRegOperand"; 508 let DecoderMethod = "DecodeSORegRegOperand"; 509 let ParserMatchClass = ShiftedRegAsmOperand; 510 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 511} 512 513def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 514def so_reg_imm : Operand<i32>, // reg imm 515 ComplexPattern<i32, 2, "SelectImmShifterOperand", 516 [shl, srl, sra, rotr]> { 517 let EncoderMethod = "getSORegImmOpValue"; 518 let PrintMethod = "printSORegImmOperand"; 519 let DecoderMethod = "DecodeSORegImmOperand"; 520 let ParserMatchClass = ShiftedImmAsmOperand; 521 let MIOperandInfo = (ops GPR, i32imm); 522} 523 524// FIXME: Does this need to be distinct from so_reg? 525def shift_so_reg_reg : Operand<i32>, // reg reg imm 526 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 527 [shl,srl,sra,rotr]> { 528 let EncoderMethod = "getSORegRegOpValue"; 529 let PrintMethod = "printSORegRegOperand"; 530 let DecoderMethod = "DecodeSORegRegOperand"; 531 let ParserMatchClass = ShiftedRegAsmOperand; 532 let MIOperandInfo = (ops GPR, GPR, i32imm); 533} 534 535// FIXME: Does this need to be distinct from so_reg? 536def shift_so_reg_imm : Operand<i32>, // reg reg imm 537 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 538 [shl,srl,sra,rotr]> { 539 let EncoderMethod = "getSORegImmOpValue"; 540 let PrintMethod = "printSORegImmOperand"; 541 let DecoderMethod = "DecodeSORegImmOperand"; 542 let ParserMatchClass = ShiftedImmAsmOperand; 543 let MIOperandInfo = (ops GPR, i32imm); 544} 545 546 547// so_imm - Match a 32-bit shifter_operand immediate operand, which is an 548// 8-bit immediate rotated by an arbitrary number of bits. 549def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; } 550def so_imm : Operand<i32>, ImmLeaf<i32, [{ 551 return ARM_AM::getSOImmVal(Imm) != -1; 552 }]> { 553 let EncoderMethod = "getSOImmOpValue"; 554 let ParserMatchClass = SOImmAsmOperand; 555 let DecoderMethod = "DecodeSOImmOperand"; 556} 557 558// Break so_imm's up into two pieces. This handles immediates with up to 16 559// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to 560// get the first/second pieces. 561def so_imm2part : PatLeaf<(imm), [{ 562 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 563}]>; 564 565/// arm_i32imm - True for +V6T2, or true only if so_imm2part is true. 566/// 567def arm_i32imm : PatLeaf<(imm), [{ 568 if (Subtarget->hasV6T2Ops()) 569 return true; 570 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 571}]>; 572 573/// imm0_1 predicate - Immediate in the range [0,1]. 574def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; } 575def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 576 577/// imm0_3 predicate - Immediate in the range [0,3]. 578def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; } 579def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 580 581/// imm0_7 predicate - Immediate in the range [0,7]. 582def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; } 583def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 584 return Imm >= 0 && Imm < 8; 585}]> { 586 let ParserMatchClass = Imm0_7AsmOperand; 587} 588 589/// imm8 predicate - Immediate is exactly 8. 590def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; } 591def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 592 let ParserMatchClass = Imm8AsmOperand; 593} 594 595/// imm16 predicate - Immediate is exactly 16. 596def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; } 597def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 598 let ParserMatchClass = Imm16AsmOperand; 599} 600 601/// imm32 predicate - Immediate is exactly 32. 602def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; } 603def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 604 let ParserMatchClass = Imm32AsmOperand; 605} 606 607/// imm1_7 predicate - Immediate in the range [1,7]. 608def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; } 609def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 610 let ParserMatchClass = Imm1_7AsmOperand; 611} 612 613/// imm1_15 predicate - Immediate in the range [1,15]. 614def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; } 615def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 616 let ParserMatchClass = Imm1_15AsmOperand; 617} 618 619/// imm1_31 predicate - Immediate in the range [1,31]. 620def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; } 621def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 622 let ParserMatchClass = Imm1_31AsmOperand; 623} 624 625/// imm0_15 predicate - Immediate in the range [0,15]. 626def Imm0_15AsmOperand: ImmAsmOperand { 627 let Name = "Imm0_15"; 628 let DiagnosticType = "ImmRange0_15"; 629} 630def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 631 return Imm >= 0 && Imm < 16; 632}]> { 633 let ParserMatchClass = Imm0_15AsmOperand; 634} 635 636/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 637def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; } 638def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 639 return Imm >= 0 && Imm < 32; 640}]> { 641 let ParserMatchClass = Imm0_31AsmOperand; 642} 643 644/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 645def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; } 646def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 647 return Imm >= 0 && Imm < 32; 648}]> { 649 let ParserMatchClass = Imm0_32AsmOperand; 650} 651 652/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 653def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; } 654def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 655 return Imm >= 0 && Imm < 64; 656}]> { 657 let ParserMatchClass = Imm0_63AsmOperand; 658} 659 660/// imm0_255 predicate - Immediate in the range [0,255]. 661def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; } 662def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 663 let ParserMatchClass = Imm0_255AsmOperand; 664} 665 666/// imm0_65535 - An immediate is in the range [0.65535]. 667def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; } 668def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 669 return Imm >= 0 && Imm < 65536; 670}]> { 671 let ParserMatchClass = Imm0_65535AsmOperand; 672} 673 674// imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. 675def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{ 676 return -Imm >= 0 && -Imm < 65536; 677}]>; 678 679// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 680// a relocatable expression. 681// 682// FIXME: This really needs a Thumb version separate from the ARM version. 683// While the range is the same, and can thus use the same match class, 684// the encoding is different so it should have a different encoder method. 685def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; } 686def imm0_65535_expr : Operand<i32> { 687 let EncoderMethod = "getHiLo16ImmOpValue"; 688 let ParserMatchClass = Imm0_65535ExprAsmOperand; 689} 690 691/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 692def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; } 693def imm24b : Operand<i32>, ImmLeaf<i32, [{ 694 return Imm >= 0 && Imm <= 0xffffff; 695}]> { 696 let ParserMatchClass = Imm24bitAsmOperand; 697} 698 699 700/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 701/// e.g., 0xf000ffff 702def BitfieldAsmOperand : AsmOperandClass { 703 let Name = "Bitfield"; 704 let ParserMethod = "parseBitfield"; 705} 706 707def bf_inv_mask_imm : Operand<i32>, 708 PatLeaf<(imm), [{ 709 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 710}] > { 711 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 712 let PrintMethod = "printBitfieldInvMaskImmOperand"; 713 let DecoderMethod = "DecodeBitfieldMaskOperand"; 714 let ParserMatchClass = BitfieldAsmOperand; 715} 716 717def imm1_32_XFORM: SDNodeXForm<imm, [{ 718 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32); 719}]>; 720def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; } 721def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 722 uint64_t Imm = N->getZExtValue(); 723 return Imm > 0 && Imm <= 32; 724 }], 725 imm1_32_XFORM> { 726 let PrintMethod = "printImmPlusOneOperand"; 727 let ParserMatchClass = Imm1_32AsmOperand; 728} 729 730def imm1_16_XFORM: SDNodeXForm<imm, [{ 731 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32); 732}]>; 733def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; } 734def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }], 735 imm1_16_XFORM> { 736 let PrintMethod = "printImmPlusOneOperand"; 737 let ParserMatchClass = Imm1_16AsmOperand; 738} 739 740// Define ARM specific addressing modes. 741// addrmode_imm12 := reg +/- imm12 742// 743def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 744def addrmode_imm12 : Operand<i32>, 745 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 746 // 12-bit immediate operand. Note that instructions using this encode 747 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 748 // immediate values are as normal. 749 750 let EncoderMethod = "getAddrModeImm12OpValue"; 751 let PrintMethod = "printAddrModeImm12Operand"; 752 let DecoderMethod = "DecodeAddrModeImm12Operand"; 753 let ParserMatchClass = MemImm12OffsetAsmOperand; 754 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 755} 756// ldst_so_reg := reg +/- reg shop imm 757// 758def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 759def ldst_so_reg : Operand<i32>, 760 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 761 let EncoderMethod = "getLdStSORegOpValue"; 762 // FIXME: Simplify the printer 763 let PrintMethod = "printAddrMode2Operand"; 764 let DecoderMethod = "DecodeSORegMemOperand"; 765 let ParserMatchClass = MemRegOffsetAsmOperand; 766 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 767} 768 769// postidx_imm8 := +/- [0,255] 770// 771// 9 bit value: 772// {8} 1 is imm8 is non-negative. 0 otherwise. 773// {7-0} [0,255] imm8 value. 774def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 775def postidx_imm8 : Operand<i32> { 776 let PrintMethod = "printPostIdxImm8Operand"; 777 let ParserMatchClass = PostIdxImm8AsmOperand; 778 let MIOperandInfo = (ops i32imm); 779} 780 781// postidx_imm8s4 := +/- [0,1020] 782// 783// 9 bit value: 784// {8} 1 is imm8 is non-negative. 0 otherwise. 785// {7-0} [0,255] imm8 value, scaled by 4. 786def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 787def postidx_imm8s4 : Operand<i32> { 788 let PrintMethod = "printPostIdxImm8s4Operand"; 789 let ParserMatchClass = PostIdxImm8s4AsmOperand; 790 let MIOperandInfo = (ops i32imm); 791} 792 793 794// postidx_reg := +/- reg 795// 796def PostIdxRegAsmOperand : AsmOperandClass { 797 let Name = "PostIdxReg"; 798 let ParserMethod = "parsePostIdxReg"; 799} 800def postidx_reg : Operand<i32> { 801 let EncoderMethod = "getPostIdxRegOpValue"; 802 let DecoderMethod = "DecodePostIdxReg"; 803 let PrintMethod = "printPostIdxRegOperand"; 804 let ParserMatchClass = PostIdxRegAsmOperand; 805 let MIOperandInfo = (ops GPRnopc, i32imm); 806} 807 808 809// addrmode2 := reg +/- imm12 810// := reg +/- reg shop imm 811// 812// FIXME: addrmode2 should be refactored the rest of the way to always 813// use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg). 814def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; } 815def addrmode2 : Operand<i32>, 816 ComplexPattern<i32, 3, "SelectAddrMode2", []> { 817 let EncoderMethod = "getAddrMode2OpValue"; 818 let PrintMethod = "printAddrMode2Operand"; 819 let ParserMatchClass = AddrMode2AsmOperand; 820 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 821} 822 823def PostIdxRegShiftedAsmOperand : AsmOperandClass { 824 let Name = "PostIdxRegShifted"; 825 let ParserMethod = "parsePostIdxReg"; 826} 827def am2offset_reg : Operand<i32>, 828 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 829 [], [SDNPWantRoot]> { 830 let EncoderMethod = "getAddrMode2OffsetOpValue"; 831 let PrintMethod = "printAddrMode2OffsetOperand"; 832 // When using this for assembly, it's always as a post-index offset. 833 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 834 let MIOperandInfo = (ops GPRnopc, i32imm); 835} 836 837// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 838// the GPR is purely vestigal at this point. 839def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 840def am2offset_imm : Operand<i32>, 841 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 842 [], [SDNPWantRoot]> { 843 let EncoderMethod = "getAddrMode2OffsetOpValue"; 844 let PrintMethod = "printAddrMode2OffsetOperand"; 845 let ParserMatchClass = AM2OffsetImmAsmOperand; 846 let MIOperandInfo = (ops GPRnopc, i32imm); 847} 848 849 850// addrmode3 := reg +/- reg 851// addrmode3 := reg +/- imm8 852// 853// FIXME: split into imm vs. reg versions. 854def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 855def addrmode3 : Operand<i32>, 856 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 857 let EncoderMethod = "getAddrMode3OpValue"; 858 let PrintMethod = "printAddrMode3Operand"; 859 let ParserMatchClass = AddrMode3AsmOperand; 860 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 861} 862 863// FIXME: split into imm vs. reg versions. 864// FIXME: parser method to handle +/- register. 865def AM3OffsetAsmOperand : AsmOperandClass { 866 let Name = "AM3Offset"; 867 let ParserMethod = "parseAM3Offset"; 868} 869def am3offset : Operand<i32>, 870 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 871 [], [SDNPWantRoot]> { 872 let EncoderMethod = "getAddrMode3OffsetOpValue"; 873 let PrintMethod = "printAddrMode3OffsetOperand"; 874 let ParserMatchClass = AM3OffsetAsmOperand; 875 let MIOperandInfo = (ops GPR, i32imm); 876} 877 878// ldstm_mode := {ia, ib, da, db} 879// 880def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 881 let EncoderMethod = "getLdStmModeOpValue"; 882 let PrintMethod = "printLdStmModeOperand"; 883} 884 885// addrmode5 := reg +/- imm8*4 886// 887def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 888def addrmode5 : Operand<i32>, 889 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 890 let PrintMethod = "printAddrMode5Operand"; 891 let EncoderMethod = "getAddrMode5OpValue"; 892 let DecoderMethod = "DecodeAddrMode5Operand"; 893 let ParserMatchClass = AddrMode5AsmOperand; 894 let MIOperandInfo = (ops GPR:$base, i32imm); 895} 896 897// addrmode6 := reg with optional alignment 898// 899def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 900def addrmode6 : Operand<i32>, 901 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 902 let PrintMethod = "printAddrMode6Operand"; 903 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 904 let EncoderMethod = "getAddrMode6AddressOpValue"; 905 let DecoderMethod = "DecodeAddrMode6Operand"; 906 let ParserMatchClass = AddrMode6AsmOperand; 907} 908 909def am6offset : Operand<i32>, 910 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 911 [], [SDNPWantRoot]> { 912 let PrintMethod = "printAddrMode6OffsetOperand"; 913 let MIOperandInfo = (ops GPR); 914 let EncoderMethod = "getAddrMode6OffsetOpValue"; 915 let DecoderMethod = "DecodeGPRRegisterClass"; 916} 917 918// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 919// (single element from one lane) for size 32. 920def addrmode6oneL32 : Operand<i32>, 921 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 922 let PrintMethod = "printAddrMode6Operand"; 923 let MIOperandInfo = (ops GPR:$addr, i32imm); 924 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 925} 926 927// Special version of addrmode6 to handle alignment encoding for VLD-dup 928// instructions, specifically VLD4-dup. 929def addrmode6dup : Operand<i32>, 930 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 931 let PrintMethod = "printAddrMode6Operand"; 932 let MIOperandInfo = (ops GPR:$addr, i32imm); 933 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 934 // FIXME: This is close, but not quite right. The alignment specifier is 935 // different. 936 let ParserMatchClass = AddrMode6AsmOperand; 937} 938 939// addrmodepc := pc + reg 940// 941def addrmodepc : Operand<i32>, 942 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 943 let PrintMethod = "printAddrModePCOperand"; 944 let MIOperandInfo = (ops GPR, i32imm); 945} 946 947// addr_offset_none := reg 948// 949def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 950def addr_offset_none : Operand<i32>, 951 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 952 let PrintMethod = "printAddrMode7Operand"; 953 let DecoderMethod = "DecodeAddrMode7Operand"; 954 let ParserMatchClass = MemNoOffsetAsmOperand; 955 let MIOperandInfo = (ops GPR:$base); 956} 957 958def nohash_imm : Operand<i32> { 959 let PrintMethod = "printNoHashImmediate"; 960} 961 962def CoprocNumAsmOperand : AsmOperandClass { 963 let Name = "CoprocNum"; 964 let ParserMethod = "parseCoprocNumOperand"; 965} 966def p_imm : Operand<i32> { 967 let PrintMethod = "printPImmediate"; 968 let ParserMatchClass = CoprocNumAsmOperand; 969 let DecoderMethod = "DecodeCoprocessor"; 970} 971 972def pf_imm : Operand<i32> { 973 let PrintMethod = "printPImmediate"; 974 let ParserMatchClass = CoprocNumAsmOperand; 975} 976 977def CoprocRegAsmOperand : AsmOperandClass { 978 let Name = "CoprocReg"; 979 let ParserMethod = "parseCoprocRegOperand"; 980} 981def c_imm : Operand<i32> { 982 let PrintMethod = "printCImmediate"; 983 let ParserMatchClass = CoprocRegAsmOperand; 984} 985def CoprocOptionAsmOperand : AsmOperandClass { 986 let Name = "CoprocOption"; 987 let ParserMethod = "parseCoprocOptionOperand"; 988} 989def coproc_option_imm : Operand<i32> { 990 let PrintMethod = "printCoprocOptionImm"; 991 let ParserMatchClass = CoprocOptionAsmOperand; 992} 993 994//===----------------------------------------------------------------------===// 995 996include "ARMInstrFormats.td" 997 998//===----------------------------------------------------------------------===// 999// Multiclass helpers... 1000// 1001 1002/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a 1003/// binop that produces a value. 1004let TwoOperandAliasConstraint = "$Rn = $Rd" in 1005multiclass AsI1_bin_irs<bits<4> opcod, string opc, 1006 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1007 PatFrag opnode, bit Commutable = 0> { 1008 // The register-immediate version is re-materializable. This is useful 1009 // in particular for taking the address of a local. 1010 let isReMaterializable = 1 in { 1011 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, 1012 iii, opc, "\t$Rd, $Rn, $imm", 1013 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>, 1014 Sched<[WriteALU, ReadAdvanceALU]> { 1015 bits<4> Rd; 1016 bits<4> Rn; 1017 bits<12> imm; 1018 let Inst{25} = 1; 1019 let Inst{19-16} = Rn; 1020 let Inst{15-12} = Rd; 1021 let Inst{11-0} = imm; 1022 } 1023 } 1024 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1025 iir, opc, "\t$Rd, $Rn, $Rm", 1026 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 1027 Sched<[WriteALU, ReadAdvanceALU, ReadAdvanceALU]> { 1028 bits<4> Rd; 1029 bits<4> Rn; 1030 bits<4> Rm; 1031 let Inst{25} = 0; 1032 let isCommutable = Commutable; 1033 let Inst{19-16} = Rn; 1034 let Inst{15-12} = Rd; 1035 let Inst{11-4} = 0b00000000; 1036 let Inst{3-0} = Rm; 1037 } 1038 1039 def rsi : AsI1<opcod, (outs GPR:$Rd), 1040 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1041 iis, opc, "\t$Rd, $Rn, $shift", 1042 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, 1043 Sched<[WriteALUsi, ReadAdvanceALU]> { 1044 bits<4> Rd; 1045 bits<4> Rn; 1046 bits<12> shift; 1047 let Inst{25} = 0; 1048 let Inst{19-16} = Rn; 1049 let Inst{15-12} = Rd; 1050 let Inst{11-5} = shift{11-5}; 1051 let Inst{4} = 0; 1052 let Inst{3-0} = shift{3-0}; 1053 } 1054 1055 def rsr : AsI1<opcod, (outs GPR:$Rd), 1056 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1057 iis, opc, "\t$Rd, $Rn, $shift", 1058 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, 1059 Sched<[WriteALUsr, ReadAdvanceALUsr]> { 1060 bits<4> Rd; 1061 bits<4> Rn; 1062 bits<12> shift; 1063 let Inst{25} = 0; 1064 let Inst{19-16} = Rn; 1065 let Inst{15-12} = Rd; 1066 let Inst{11-8} = shift{11-8}; 1067 let Inst{7} = 0; 1068 let Inst{6-5} = shift{6-5}; 1069 let Inst{4} = 1; 1070 let Inst{3-0} = shift{3-0}; 1071 } 1072} 1073 1074/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1075/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1076/// it is equivalent to the AsI1_bin_irs counterpart. 1077let TwoOperandAliasConstraint = "$Rn = $Rd" in 1078multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1079 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1080 PatFrag opnode, bit Commutable = 0> { 1081 // The register-immediate version is re-materializable. This is useful 1082 // in particular for taking the address of a local. 1083 let isReMaterializable = 1 in { 1084 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, 1085 iii, opc, "\t$Rd, $Rn, $imm", 1086 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>, 1087 Sched<[WriteALU, ReadAdvanceALU]> { 1088 bits<4> Rd; 1089 bits<4> Rn; 1090 bits<12> imm; 1091 let Inst{25} = 1; 1092 let Inst{19-16} = Rn; 1093 let Inst{15-12} = Rd; 1094 let Inst{11-0} = imm; 1095 } 1096 } 1097 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1098 iir, opc, "\t$Rd, $Rn, $Rm", 1099 [/* pattern left blank */]>, 1100 Sched<[WriteALU, ReadAdvanceALU, ReadAdvanceALU]> { 1101 bits<4> Rd; 1102 bits<4> Rn; 1103 bits<4> Rm; 1104 let Inst{11-4} = 0b00000000; 1105 let Inst{25} = 0; 1106 let Inst{3-0} = Rm; 1107 let Inst{15-12} = Rd; 1108 let Inst{19-16} = Rn; 1109 } 1110 1111 def rsi : AsI1<opcod, (outs GPR:$Rd), 1112 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1113 iis, opc, "\t$Rd, $Rn, $shift", 1114 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>, 1115 Sched<[WriteALUsi, ReadAdvanceALU]> { 1116 bits<4> Rd; 1117 bits<4> Rn; 1118 bits<12> shift; 1119 let Inst{25} = 0; 1120 let Inst{19-16} = Rn; 1121 let Inst{15-12} = Rd; 1122 let Inst{11-5} = shift{11-5}; 1123 let Inst{4} = 0; 1124 let Inst{3-0} = shift{3-0}; 1125 } 1126 1127 def rsr : AsI1<opcod, (outs GPR:$Rd), 1128 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1129 iis, opc, "\t$Rd, $Rn, $shift", 1130 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>, 1131 Sched<[WriteALUsr, ReadAdvanceALUsr]> { 1132 bits<4> Rd; 1133 bits<4> Rn; 1134 bits<12> shift; 1135 let Inst{25} = 0; 1136 let Inst{19-16} = Rn; 1137 let Inst{15-12} = Rd; 1138 let Inst{11-8} = shift{11-8}; 1139 let Inst{7} = 0; 1140 let Inst{6-5} = shift{6-5}; 1141 let Inst{4} = 1; 1142 let Inst{3-0} = shift{3-0}; 1143 } 1144} 1145 1146/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1147/// 1148/// These opcodes will be converted to the real non-S opcodes by 1149/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1150let hasPostISelHook = 1, Defs = [CPSR] in { 1151multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1152 InstrItinClass iis, PatFrag opnode, 1153 bit Commutable = 0> { 1154 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p), 1155 4, iii, 1156 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>, 1157 Sched<[WriteALU, ReadAdvanceALU]>; 1158 1159 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1160 4, iir, 1161 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, 1162 Sched<[WriteALU, ReadAdvanceALU, ReadAdvanceALU]> { 1163 let isCommutable = Commutable; 1164 } 1165 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1166 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1167 4, iis, 1168 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1169 so_reg_imm:$shift))]>, 1170 Sched<[WriteALUsi, ReadAdvanceALU]>; 1171 1172 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1173 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1174 4, iis, 1175 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1176 so_reg_reg:$shift))]>, 1177 Sched<[WriteALUSsr, ReadAdvanceALUsr]>; 1178} 1179} 1180 1181/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1182/// operands are reversed. 1183let hasPostISelHook = 1, Defs = [CPSR] in { 1184multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir, 1185 InstrItinClass iis, PatFrag opnode, 1186 bit Commutable = 0> { 1187 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p), 1188 4, iii, 1189 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>, 1190 Sched<[WriteALU, ReadAdvanceALU]>; 1191 1192 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1193 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1194 4, iis, 1195 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1196 GPR:$Rn))]>, 1197 Sched<[WriteALUsi, ReadAdvanceALU]>; 1198 1199 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1200 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1201 4, iis, 1202 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1203 GPR:$Rn))]>, 1204 Sched<[WriteALUSsr, ReadAdvanceALUsr]>; 1205} 1206} 1207 1208/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 1209/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1210/// a explicit result, only implicitly set CPSR. 1211let isCompare = 1, Defs = [CPSR] in { 1212multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1213 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1214 PatFrag opnode, bit Commutable = 0> { 1215 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii, 1216 opc, "\t$Rn, $imm", 1217 [(opnode GPR:$Rn, so_imm:$imm)]> { 1218 bits<4> Rn; 1219 bits<12> imm; 1220 let Inst{25} = 1; 1221 let Inst{20} = 1; 1222 let Inst{19-16} = Rn; 1223 let Inst{15-12} = 0b0000; 1224 let Inst{11-0} = imm; 1225 1226 let Unpredictable{15-12} = 0b1111; 1227 } 1228 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1229 opc, "\t$Rn, $Rm", 1230 [(opnode GPR:$Rn, GPR:$Rm)]> { 1231 bits<4> Rn; 1232 bits<4> Rm; 1233 let isCommutable = Commutable; 1234 let Inst{25} = 0; 1235 let Inst{20} = 1; 1236 let Inst{19-16} = Rn; 1237 let Inst{15-12} = 0b0000; 1238 let Inst{11-4} = 0b00000000; 1239 let Inst{3-0} = Rm; 1240 1241 let Unpredictable{15-12} = 0b1111; 1242 } 1243 def rsi : AI1<opcod, (outs), 1244 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1245 opc, "\t$Rn, $shift", 1246 [(opnode GPR:$Rn, so_reg_imm:$shift)]> { 1247 bits<4> Rn; 1248 bits<12> shift; 1249 let Inst{25} = 0; 1250 let Inst{20} = 1; 1251 let Inst{19-16} = Rn; 1252 let Inst{15-12} = 0b0000; 1253 let Inst{11-5} = shift{11-5}; 1254 let Inst{4} = 0; 1255 let Inst{3-0} = shift{3-0}; 1256 1257 let Unpredictable{15-12} = 0b1111; 1258 } 1259 def rsr : AI1<opcod, (outs), 1260 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1261 opc, "\t$Rn, $shift", 1262 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]> { 1263 bits<4> Rn; 1264 bits<12> shift; 1265 let Inst{25} = 0; 1266 let Inst{20} = 1; 1267 let Inst{19-16} = Rn; 1268 let Inst{15-12} = 0b0000; 1269 let Inst{11-8} = shift{11-8}; 1270 let Inst{7} = 0; 1271 let Inst{6-5} = shift{6-5}; 1272 let Inst{4} = 1; 1273 let Inst{3-0} = shift{3-0}; 1274 1275 let Unpredictable{15-12} = 0b1111; 1276 } 1277 1278} 1279} 1280 1281/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1282/// register and one whose operand is a register rotated by 8/16/24. 1283/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1284class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1285 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1286 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1287 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1288 Requires<[IsARM, HasV6]> { 1289 bits<4> Rd; 1290 bits<4> Rm; 1291 bits<2> rot; 1292 let Inst{19-16} = 0b1111; 1293 let Inst{15-12} = Rd; 1294 let Inst{11-10} = rot; 1295 let Inst{3-0} = Rm; 1296} 1297 1298class AI_ext_rrot_np<bits<8> opcod, string opc> 1299 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1300 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1301 Requires<[IsARM, HasV6]> { 1302 bits<2> rot; 1303 let Inst{19-16} = 0b1111; 1304 let Inst{11-10} = rot; 1305} 1306 1307/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1308/// register and one whose operand is a register rotated by 8/16/24. 1309class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1310 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1311 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1312 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1313 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1314 Requires<[IsARM, HasV6]> { 1315 bits<4> Rd; 1316 bits<4> Rm; 1317 bits<4> Rn; 1318 bits<2> rot; 1319 let Inst{19-16} = Rn; 1320 let Inst{15-12} = Rd; 1321 let Inst{11-10} = rot; 1322 let Inst{9-4} = 0b000111; 1323 let Inst{3-0} = Rm; 1324} 1325 1326class AI_exta_rrot_np<bits<8> opcod, string opc> 1327 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1328 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1329 Requires<[IsARM, HasV6]> { 1330 bits<4> Rn; 1331 bits<2> rot; 1332 let Inst{19-16} = Rn; 1333 let Inst{11-10} = rot; 1334} 1335 1336/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1337let TwoOperandAliasConstraint = "$Rn = $Rd" in 1338multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, 1339 bit Commutable = 0> { 1340 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1341 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), 1342 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1343 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>, 1344 Requires<[IsARM]> { 1345 bits<4> Rd; 1346 bits<4> Rn; 1347 bits<12> imm; 1348 let Inst{25} = 1; 1349 let Inst{15-12} = Rd; 1350 let Inst{19-16} = Rn; 1351 let Inst{11-0} = imm; 1352 } 1353 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1354 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1355 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1356 Requires<[IsARM]> { 1357 bits<4> Rd; 1358 bits<4> Rn; 1359 bits<4> Rm; 1360 let Inst{11-4} = 0b00000000; 1361 let Inst{25} = 0; 1362 let isCommutable = Commutable; 1363 let Inst{3-0} = Rm; 1364 let Inst{15-12} = Rd; 1365 let Inst{19-16} = Rn; 1366 } 1367 def rsi : AsI1<opcod, (outs GPR:$Rd), 1368 (ins GPR:$Rn, so_reg_imm:$shift), 1369 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1370 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1371 Requires<[IsARM]> { 1372 bits<4> Rd; 1373 bits<4> Rn; 1374 bits<12> shift; 1375 let Inst{25} = 0; 1376 let Inst{19-16} = Rn; 1377 let Inst{15-12} = Rd; 1378 let Inst{11-5} = shift{11-5}; 1379 let Inst{4} = 0; 1380 let Inst{3-0} = shift{3-0}; 1381 } 1382 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1383 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1384 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1385 [(set GPRnopc:$Rd, CPSR, 1386 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1387 Requires<[IsARM]> { 1388 bits<4> Rd; 1389 bits<4> Rn; 1390 bits<12> shift; 1391 let Inst{25} = 0; 1392 let Inst{19-16} = Rn; 1393 let Inst{15-12} = Rd; 1394 let Inst{11-8} = shift{11-8}; 1395 let Inst{7} = 0; 1396 let Inst{6-5} = shift{6-5}; 1397 let Inst{4} = 1; 1398 let Inst{3-0} = shift{3-0}; 1399 } 1400 } 1401} 1402 1403/// AI1_rsc_irs - Define instructions and patterns for rsc 1404let TwoOperandAliasConstraint = "$Rn = $Rd" in 1405multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> { 1406 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1407 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), 1408 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1409 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>, 1410 Requires<[IsARM]> { 1411 bits<4> Rd; 1412 bits<4> Rn; 1413 bits<12> imm; 1414 let Inst{25} = 1; 1415 let Inst{15-12} = Rd; 1416 let Inst{19-16} = Rn; 1417 let Inst{11-0} = imm; 1418 } 1419 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1420 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1421 [/* pattern left blank */]> { 1422 bits<4> Rd; 1423 bits<4> Rn; 1424 bits<4> Rm; 1425 let Inst{11-4} = 0b00000000; 1426 let Inst{25} = 0; 1427 let Inst{3-0} = Rm; 1428 let Inst{15-12} = Rd; 1429 let Inst{19-16} = Rn; 1430 } 1431 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1432 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1433 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1434 Requires<[IsARM]> { 1435 bits<4> Rd; 1436 bits<4> Rn; 1437 bits<12> shift; 1438 let Inst{25} = 0; 1439 let Inst{19-16} = Rn; 1440 let Inst{15-12} = Rd; 1441 let Inst{11-5} = shift{11-5}; 1442 let Inst{4} = 0; 1443 let Inst{3-0} = shift{3-0}; 1444 } 1445 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1446 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1447 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1448 Requires<[IsARM]> { 1449 bits<4> Rd; 1450 bits<4> Rn; 1451 bits<12> shift; 1452 let Inst{25} = 0; 1453 let Inst{19-16} = Rn; 1454 let Inst{15-12} = Rd; 1455 let Inst{11-8} = shift{11-8}; 1456 let Inst{7} = 0; 1457 let Inst{6-5} = shift{6-5}; 1458 let Inst{4} = 1; 1459 let Inst{3-0} = shift{3-0}; 1460 } 1461 } 1462} 1463 1464let canFoldAsLoad = 1, isReMaterializable = 1 in { 1465multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1466 InstrItinClass iir, PatFrag opnode> { 1467 // Note: We use the complex addrmode_imm12 rather than just an input 1468 // GPR and a constrained immediate so that we can use this to match 1469 // frame index references and avoid matching constant pool references. 1470 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1471 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1472 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1473 bits<4> Rt; 1474 bits<17> addr; 1475 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1476 let Inst{19-16} = addr{16-13}; // Rn 1477 let Inst{15-12} = Rt; 1478 let Inst{11-0} = addr{11-0}; // imm12 1479 } 1480 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 1481 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1482 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 1483 bits<4> Rt; 1484 bits<17> shift; 1485 let shift{4} = 0; // Inst{4} = 0 1486 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1487 let Inst{19-16} = shift{16-13}; // Rn 1488 let Inst{15-12} = Rt; 1489 let Inst{11-0} = shift{11-0}; 1490 } 1491} 1492} 1493 1494let canFoldAsLoad = 1, isReMaterializable = 1 in { 1495multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 1496 InstrItinClass iir, PatFrag opnode> { 1497 // Note: We use the complex addrmode_imm12 rather than just an input 1498 // GPR and a constrained immediate so that we can use this to match 1499 // frame index references and avoid matching constant pool references. 1500 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 1501 (ins addrmode_imm12:$addr), 1502 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1503 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 1504 bits<4> Rt; 1505 bits<17> addr; 1506 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1507 let Inst{19-16} = addr{16-13}; // Rn 1508 let Inst{15-12} = Rt; 1509 let Inst{11-0} = addr{11-0}; // imm12 1510 } 1511 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), 1512 (ins ldst_so_reg:$shift), 1513 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1514 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 1515 bits<4> Rt; 1516 bits<17> shift; 1517 let shift{4} = 0; // Inst{4} = 0 1518 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1519 let Inst{19-16} = shift{16-13}; // Rn 1520 let Inst{15-12} = Rt; 1521 let Inst{11-0} = shift{11-0}; 1522 } 1523} 1524} 1525 1526 1527multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 1528 InstrItinClass iir, PatFrag opnode> { 1529 // Note: We use the complex addrmode_imm12 rather than just an input 1530 // GPR and a constrained immediate so that we can use this to match 1531 // frame index references and avoid matching constant pool references. 1532 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1533 (ins GPR:$Rt, addrmode_imm12:$addr), 1534 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1535 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 1536 bits<4> Rt; 1537 bits<17> addr; 1538 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1539 let Inst{19-16} = addr{16-13}; // Rn 1540 let Inst{15-12} = Rt; 1541 let Inst{11-0} = addr{11-0}; // imm12 1542 } 1543 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 1544 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1545 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 1546 bits<4> Rt; 1547 bits<17> shift; 1548 let shift{4} = 0; // Inst{4} = 0 1549 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1550 let Inst{19-16} = shift{16-13}; // Rn 1551 let Inst{15-12} = Rt; 1552 let Inst{11-0} = shift{11-0}; 1553 } 1554} 1555 1556multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 1557 InstrItinClass iir, PatFrag opnode> { 1558 // Note: We use the complex addrmode_imm12 rather than just an input 1559 // GPR and a constrained immediate so that we can use this to match 1560 // frame index references and avoid matching constant pool references. 1561 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1562 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 1563 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1564 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 1565 bits<4> Rt; 1566 bits<17> addr; 1567 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1568 let Inst{19-16} = addr{16-13}; // Rn 1569 let Inst{15-12} = Rt; 1570 let Inst{11-0} = addr{11-0}; // imm12 1571 } 1572 def rs : AI2ldst<0b011, 0, isByte, (outs), 1573 (ins GPRnopc:$Rt, ldst_so_reg:$shift), 1574 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1575 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 1576 bits<4> Rt; 1577 bits<17> shift; 1578 let shift{4} = 0; // Inst{4} = 0 1579 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1580 let Inst{19-16} = shift{16-13}; // Rn 1581 let Inst{15-12} = Rt; 1582 let Inst{11-0} = shift{11-0}; 1583 } 1584} 1585 1586 1587//===----------------------------------------------------------------------===// 1588// Instructions 1589//===----------------------------------------------------------------------===// 1590 1591//===----------------------------------------------------------------------===// 1592// Miscellaneous Instructions. 1593// 1594 1595/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 1596/// the function. The first operand is the ID# for this instruction, the second 1597/// is the index into the MachineConstantPool that this is, the third is the 1598/// size in bytes of this constant pool entry. 1599let neverHasSideEffects = 1, isNotDuplicable = 1 in 1600def CONSTPOOL_ENTRY : 1601PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1602 i32imm:$size), NoItinerary, []>; 1603 1604// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 1605// from removing one half of the matched pairs. That breaks PEI, which assumes 1606// these will always be in pairs, and asserts if it finds otherwise. Better way? 1607let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 1608def ADJCALLSTACKUP : 1609PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 1610 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 1611 1612def ADJCALLSTACKDOWN : 1613PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, 1614 [(ARMcallseq_start timm:$amt)]>; 1615} 1616 1617// Atomic pseudo-insts which will be lowered to ldrexd/strexd loops. 1618// (These pseudos use a hand-written selection code). 1619let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in { 1620def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1621 (ins GPR:$addr, GPR:$src1, GPR:$src2), 1622 NoItinerary, []>; 1623def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1624 (ins GPR:$addr, GPR:$src1, GPR:$src2), 1625 NoItinerary, []>; 1626def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1627 (ins GPR:$addr, GPR:$src1, GPR:$src2), 1628 NoItinerary, []>; 1629def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1630 (ins GPR:$addr, GPR:$src1, GPR:$src2), 1631 NoItinerary, []>; 1632def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1633 (ins GPR:$addr, GPR:$src1, GPR:$src2), 1634 NoItinerary, []>; 1635def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1636 (ins GPR:$addr, GPR:$src1, GPR:$src2), 1637 NoItinerary, []>; 1638def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1639 (ins GPR:$addr, GPR:$src1, GPR:$src2), 1640 NoItinerary, []>; 1641def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1642 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2, 1643 GPR:$set1, GPR:$set2), 1644 NoItinerary, []>; 1645def ATOMMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1646 (ins GPR:$addr, GPR:$src1, GPR:$src2), 1647 NoItinerary, []>; 1648def ATOMUMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1649 (ins GPR:$addr, GPR:$src1, GPR:$src2), 1650 NoItinerary, []>; 1651def ATOMMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1652 (ins GPR:$addr, GPR:$src1, GPR:$src2), 1653 NoItinerary, []>; 1654def ATOMUMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1655 (ins GPR:$addr, GPR:$src1, GPR:$src2), 1656 NoItinerary, []>; 1657} 1658 1659def HINT : AI<(outs), (ins imm0_255:$imm), MiscFrm, NoItinerary, 1660 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> { 1661 bits<8> imm; 1662 let Inst{27-8} = 0b00110010000011110000; 1663 let Inst{7-0} = imm; 1664} 1665 1666def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1667def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1668def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1669def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1670def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1671 1672def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 1673 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> { 1674 bits<4> Rd; 1675 bits<4> Rn; 1676 bits<4> Rm; 1677 let Inst{3-0} = Rm; 1678 let Inst{15-12} = Rd; 1679 let Inst{19-16} = Rn; 1680 let Inst{27-20} = 0b01101000; 1681 let Inst{7-4} = 0b1011; 1682 let Inst{11-8} = 0b1111; 1683 let Unpredictable{11-8} = 0b1111; 1684} 1685 1686// The 16-bit operand $val can be used by a debugger to store more information 1687// about the breakpoint. 1688def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 1689 "bkpt", "\t$val", []>, Requires<[IsARM]> { 1690 bits<16> val; 1691 let Inst{3-0} = val{3-0}; 1692 let Inst{19-8} = val{15-4}; 1693 let Inst{27-20} = 0b00010010; 1694 let Inst{7-4} = 0b0111; 1695} 1696 1697// Change Processor State 1698// FIXME: We should use InstAlias to handle the optional operands. 1699class CPS<dag iops, string asm_ops> 1700 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 1701 []>, Requires<[IsARM]> { 1702 bits<2> imod; 1703 bits<3> iflags; 1704 bits<5> mode; 1705 bit M; 1706 1707 let Inst{31-28} = 0b1111; 1708 let Inst{27-20} = 0b00010000; 1709 let Inst{19-18} = imod; 1710 let Inst{17} = M; // Enabled if mode is set; 1711 let Inst{16-9} = 0b00000000; 1712 let Inst{8-6} = iflags; 1713 let Inst{5} = 0; 1714 let Inst{4-0} = mode; 1715} 1716 1717let DecoderMethod = "DecodeCPSInstruction" in { 1718let M = 1 in 1719 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 1720 "$imod\t$iflags, $mode">; 1721let mode = 0, M = 0 in 1722 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 1723 1724let imod = 0, iflags = 0, M = 1 in 1725 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 1726} 1727 1728// Preload signals the memory system of possible future data/instruction access. 1729multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 1730 1731 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload, 1732 !strconcat(opc, "\t$addr"), 1733 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> { 1734 bits<4> Rt; 1735 bits<17> addr; 1736 let Inst{31-26} = 0b111101; 1737 let Inst{25} = 0; // 0 for immediate form 1738 let Inst{24} = data; 1739 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1740 let Inst{22} = read; 1741 let Inst{21-20} = 0b01; 1742 let Inst{19-16} = addr{16-13}; // Rn 1743 let Inst{15-12} = 0b1111; 1744 let Inst{11-0} = addr{11-0}; // imm12 1745 } 1746 1747 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 1748 !strconcat(opc, "\t$shift"), 1749 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> { 1750 bits<17> shift; 1751 let Inst{31-26} = 0b111101; 1752 let Inst{25} = 1; // 1 for register form 1753 let Inst{24} = data; 1754 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1755 let Inst{22} = read; 1756 let Inst{21-20} = 0b01; 1757 let Inst{19-16} = shift{16-13}; // Rn 1758 let Inst{15-12} = 0b1111; 1759 let Inst{11-0} = shift{11-0}; 1760 let Inst{4} = 0; 1761 } 1762} 1763 1764defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 1765defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 1766defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 1767 1768def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 1769 "setend\t$end", []>, Requires<[IsARM]> { 1770 bits<1> end; 1771 let Inst{31-10} = 0b1111000100000001000000; 1772 let Inst{9} = end; 1773 let Inst{8-0} = 0; 1774} 1775 1776def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 1777 []>, Requires<[IsARM, HasV7]> { 1778 bits<4> opt; 1779 let Inst{27-4} = 0b001100100000111100001111; 1780 let Inst{3-0} = opt; 1781} 1782 1783/* 1784 * A5.4 Permanently UNDEFINED instructions. 1785 * 1786 * For most targets use UDF #65006, for which the OS will generate SIGTRAP. 1787 * Other UDF encodings generate SIGILL. 1788 * 1789 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. 1790 * Encoding A1: 1791 * 1110 0111 1111 iiii iiii iiii 1111 iiii 1792 * Encoding T1: 1793 * 1101 1110 iiii iiii 1794 * It uses the following encoding: 1795 * 1110 0111 1111 1110 1101 1110 1111 0000 1796 * - In ARM: UDF #60896; 1797 * - In Thumb: UDF #254 followed by a branch-to-self. 1798 */ 1799let isBarrier = 1, isTerminator = 1 in 1800def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, 1801 "trap", [(trap)]>, 1802 Requires<[IsARM,UseNaClTrap]> { 1803 let Inst = 0xe7fedef0; 1804} 1805let isBarrier = 1, isTerminator = 1 in 1806def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 1807 "trap", [(trap)]>, 1808 Requires<[IsARM,DontUseNaClTrap]> { 1809 let Inst = 0xe7ffdefe; 1810} 1811 1812// Address computation and loads and stores in PIC mode. 1813let isNotDuplicable = 1 in { 1814def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 1815 4, IIC_iALUr, 1816 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; 1817 1818let AddedComplexity = 10 in { 1819def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 1820 4, IIC_iLoad_r, 1821 [(set GPR:$dst, (load addrmodepc:$addr))]>; 1822 1823def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 1824 4, IIC_iLoad_bh_r, 1825 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 1826 1827def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 1828 4, IIC_iLoad_bh_r, 1829 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 1830 1831def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 1832 4, IIC_iLoad_bh_r, 1833 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 1834 1835def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 1836 4, IIC_iLoad_bh_r, 1837 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 1838} 1839let AddedComplexity = 10 in { 1840def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 1841 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 1842 1843def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 1844 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 1845 addrmodepc:$addr)]>; 1846 1847def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 1848 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 1849} 1850} // isNotDuplicable = 1 1851 1852 1853// LEApcrel - Load a pc-relative address into a register without offending the 1854// assembler. 1855let neverHasSideEffects = 1, isReMaterializable = 1 in 1856// The 'adr' mnemonic encodes differently if the label is before or after 1857// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 1858// know until then which form of the instruction will be used. 1859def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 1860 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> { 1861 bits<4> Rd; 1862 bits<14> label; 1863 let Inst{27-25} = 0b001; 1864 let Inst{24} = 0; 1865 let Inst{23-22} = label{13-12}; 1866 let Inst{21} = 0; 1867 let Inst{20} = 0; 1868 let Inst{19-16} = 0b1111; 1869 let Inst{15-12} = Rd; 1870 let Inst{11-0} = label{11-0}; 1871} 1872 1873let hasSideEffects = 1 in { 1874def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 1875 4, IIC_iALUi, []>; 1876 1877def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 1878 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1879 4, IIC_iALUi, []>; 1880} 1881 1882//===----------------------------------------------------------------------===// 1883// Control Flow Instructions. 1884// 1885 1886let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 1887 // ARMV4T and above 1888 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 1889 "bx", "\tlr", [(ARMretflag)]>, 1890 Requires<[IsARM, HasV4T]> { 1891 let Inst{27-0} = 0b0001001011111111111100011110; 1892 } 1893 1894 // ARMV4 only 1895 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 1896 "mov", "\tpc, lr", [(ARMretflag)]>, 1897 Requires<[IsARM, NoV4T]> { 1898 let Inst{27-0} = 0b0001101000001111000000001110; 1899 } 1900} 1901 1902// Indirect branches 1903let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1904 // ARMV4T and above 1905 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 1906 [(brind GPR:$dst)]>, 1907 Requires<[IsARM, HasV4T]> { 1908 bits<4> dst; 1909 let Inst{31-4} = 0b1110000100101111111111110001; 1910 let Inst{3-0} = dst; 1911 } 1912 1913 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 1914 "bx", "\t$dst", [/* pattern left blank */]>, 1915 Requires<[IsARM, HasV4T]> { 1916 bits<4> dst; 1917 let Inst{27-4} = 0b000100101111111111110001; 1918 let Inst{3-0} = dst; 1919 } 1920} 1921 1922// SP is marked as a use to prevent stack-pointer assignments that appear 1923// immediately before calls from potentially appearing dead. 1924let isCall = 1, 1925 // FIXME: Do we really need a non-predicated version? If so, it should 1926 // at least be a pseudo instruction expanding to the predicated version 1927 // at MC lowering time. 1928 Defs = [LR], Uses = [SP] in { 1929 def BL : ABXI<0b1011, (outs), (ins bl_target:$func), 1930 IIC_Br, "bl\t$func", 1931 [(ARMcall tglobaladdr:$func)]>, 1932 Requires<[IsARM]> { 1933 let Inst{31-28} = 0b1110; 1934 bits<24> func; 1935 let Inst{23-0} = func; 1936 let DecoderMethod = "DecodeBranchImmInstruction"; 1937 } 1938 1939 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func), 1940 IIC_Br, "bl", "\t$func", 1941 [(ARMcall_pred tglobaladdr:$func)]>, 1942 Requires<[IsARM]> { 1943 bits<24> func; 1944 let Inst{23-0} = func; 1945 let DecoderMethod = "DecodeBranchImmInstruction"; 1946 } 1947 1948 // ARMv5T and above 1949 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, 1950 IIC_Br, "blx\t$func", 1951 [(ARMcall GPR:$func)]>, 1952 Requires<[IsARM, HasV5T]> { 1953 bits<4> func; 1954 let Inst{31-4} = 0b1110000100101111111111110011; 1955 let Inst{3-0} = func; 1956 } 1957 1958 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, 1959 IIC_Br, "blx", "\t$func", 1960 [(ARMcall_pred GPR:$func)]>, 1961 Requires<[IsARM, HasV5T]> { 1962 bits<4> func; 1963 let Inst{27-4} = 0b000100101111111111110011; 1964 let Inst{3-0} = func; 1965 } 1966 1967 // ARMv4T 1968 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 1969 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 1970 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 1971 Requires<[IsARM, HasV4T]>; 1972 1973 // ARMv4 1974 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 1975 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 1976 Requires<[IsARM, NoV4T]>; 1977 1978 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 1979 // return stack predictor. 1980 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func), 1981 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 1982 Requires<[IsARM]>; 1983} 1984 1985let isBranch = 1, isTerminator = 1 in { 1986 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 1987 // a two-value operand where a dag node expects two operands. :( 1988 def Bcc : ABI<0b1010, (outs), (ins br_target:$target), 1989 IIC_Br, "b", "\t$target", 1990 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> { 1991 bits<24> target; 1992 let Inst{23-0} = target; 1993 let DecoderMethod = "DecodeBranchImmInstruction"; 1994 } 1995 1996 let isBarrier = 1 in { 1997 // B is "predicable" since it's just a Bcc with an 'always' condition. 1998 let isPredicable = 1 in 1999 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 2000 // should be sufficient. 2001 // FIXME: Is B really a Barrier? That doesn't seem right. 2002 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br, 2003 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>; 2004 2005 let isNotDuplicable = 1, isIndirectBranch = 1 in { 2006 def BR_JTr : ARMPseudoInst<(outs), 2007 (ins GPR:$target, i32imm:$jt, i32imm:$id), 2008 0, IIC_Br, 2009 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>; 2010 // FIXME: This shouldn't use the generic "addrmode2," but rather be split 2011 // into i12 and rs suffixed versions. 2012 def BR_JTm : ARMPseudoInst<(outs), 2013 (ins addrmode2:$target, i32imm:$jt, i32imm:$id), 2014 0, IIC_Br, 2015 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, 2016 imm:$id)]>; 2017 def BR_JTadd : ARMPseudoInst<(outs), 2018 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id), 2019 0, IIC_Br, 2020 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, 2021 imm:$id)]>; 2022 } // isNotDuplicable = 1, isIndirectBranch = 1 2023 } // isBarrier = 1 2024 2025} 2026 2027// BLX (immediate) 2028def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary, 2029 "blx\t$target", []>, 2030 Requires<[IsARM, HasV5T]> { 2031 let Inst{31-25} = 0b1111101; 2032 bits<25> target; 2033 let Inst{23-0} = target{24-1}; 2034 let Inst{24} = target{0}; 2035} 2036 2037// Branch and Exchange Jazelle 2038def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2039 [/* pattern left blank */]> { 2040 bits<4> func; 2041 let Inst{23-20} = 0b0010; 2042 let Inst{19-8} = 0xfff; 2043 let Inst{7-4} = 0b0010; 2044 let Inst{3-0} = func; 2045} 2046 2047// Tail calls. 2048 2049let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2050 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>; 2051 2052 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>; 2053 2054 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst), 2055 4, IIC_Br, [], 2056 (Bcc br_target:$dst, (ops 14, zero_reg))>, 2057 Requires<[IsARM]>; 2058 2059 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 2060 4, IIC_Br, [], 2061 (BX GPR:$dst)>, 2062 Requires<[IsARM]>; 2063} 2064 2065// Secure Monitor Call is a system instruction. 2066def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2067 []> { 2068 bits<4> opt; 2069 let Inst{23-4} = 0b01100000000000000111; 2070 let Inst{3-0} = opt; 2071} 2072 2073// Supervisor Call (Software Interrupt) 2074let isCall = 1, Uses = [SP] in { 2075def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> { 2076 bits<24> svc; 2077 let Inst{23-0} = svc; 2078} 2079} 2080 2081// Store Return State 2082class SRSI<bit wb, string asm> 2083 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2084 NoItinerary, asm, "", []> { 2085 bits<5> mode; 2086 let Inst{31-28} = 0b1111; 2087 let Inst{27-25} = 0b100; 2088 let Inst{22} = 1; 2089 let Inst{21} = wb; 2090 let Inst{20} = 0; 2091 let Inst{19-16} = 0b1101; // SP 2092 let Inst{15-5} = 0b00000101000; 2093 let Inst{4-0} = mode; 2094} 2095 2096def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2097 let Inst{24-23} = 0; 2098} 2099def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2100 let Inst{24-23} = 0; 2101} 2102def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2103 let Inst{24-23} = 0b10; 2104} 2105def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2106 let Inst{24-23} = 0b10; 2107} 2108def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2109 let Inst{24-23} = 0b01; 2110} 2111def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2112 let Inst{24-23} = 0b01; 2113} 2114def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2115 let Inst{24-23} = 0b11; 2116} 2117def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2118 let Inst{24-23} = 0b11; 2119} 2120 2121def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; 2122def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; 2123 2124def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; 2125def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; 2126 2127def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; 2128def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; 2129 2130def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; 2131def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; 2132 2133// Return From Exception 2134class RFEI<bit wb, string asm> 2135 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2136 NoItinerary, asm, "", []> { 2137 bits<4> Rn; 2138 let Inst{31-28} = 0b1111; 2139 let Inst{27-25} = 0b100; 2140 let Inst{22} = 0; 2141 let Inst{21} = wb; 2142 let Inst{20} = 1; 2143 let Inst{19-16} = Rn; 2144 let Inst{15-0} = 0xa00; 2145} 2146 2147def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2148 let Inst{24-23} = 0; 2149} 2150def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2151 let Inst{24-23} = 0; 2152} 2153def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2154 let Inst{24-23} = 0b10; 2155} 2156def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2157 let Inst{24-23} = 0b10; 2158} 2159def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2160 let Inst{24-23} = 0b01; 2161} 2162def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2163 let Inst{24-23} = 0b01; 2164} 2165def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2166 let Inst{24-23} = 0b11; 2167} 2168def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2169 let Inst{24-23} = 0b11; 2170} 2171 2172//===----------------------------------------------------------------------===// 2173// Load / Store Instructions. 2174// 2175 2176// Load 2177 2178 2179defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, 2180 UnOpFrag<(load node:$Src)>>; 2181defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2182 UnOpFrag<(zextloadi8 node:$Src)>>; 2183defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, 2184 BinOpFrag<(store node:$LHS, node:$RHS)>>; 2185defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2186 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 2187 2188// Special LDR for loads from non-pc-relative constpools. 2189let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1, 2190 isReMaterializable = 1, isCodeGenOnly = 1 in 2191def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2192 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2193 []> { 2194 bits<4> Rt; 2195 bits<17> addr; 2196 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2197 let Inst{19-16} = 0b1111; 2198 let Inst{15-12} = Rt; 2199 let Inst{11-0} = addr{11-0}; // imm12 2200} 2201 2202// Loads with zero extension 2203def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2204 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2205 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2206 2207// Loads with sign extension 2208def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2209 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2210 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2211 2212def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2213 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2214 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2215 2216let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { 2217// Load doubleword 2218def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2), 2219 (ins addrmode3:$addr), LdMiscFrm, 2220 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr", 2221 []>, Requires<[IsARM, HasV5TE]>; 2222} 2223 2224// Indexed loads 2225multiclass AI2_ldridx<bit isByte, string opc, 2226 InstrItinClass iii, InstrItinClass iir> { 2227 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2228 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii, 2229 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2230 bits<17> addr; 2231 let Inst{25} = 0; 2232 let Inst{23} = addr{12}; 2233 let Inst{19-16} = addr{16-13}; 2234 let Inst{11-0} = addr{11-0}; 2235 let DecoderMethod = "DecodeLDRPreImm"; 2236 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12"; 2237 } 2238 2239 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2240 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2241 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2242 bits<17> addr; 2243 let Inst{25} = 1; 2244 let Inst{23} = addr{12}; 2245 let Inst{19-16} = addr{16-13}; 2246 let Inst{11-0} = addr{11-0}; 2247 let Inst{4} = 0; 2248 let DecoderMethod = "DecodeLDRPreReg"; 2249 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2"; 2250 } 2251 2252 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2253 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2254 IndexModePost, LdFrm, iir, 2255 opc, "\t$Rt, $addr, $offset", 2256 "$addr.base = $Rn_wb", []> { 2257 // {12} isAdd 2258 // {11-0} imm12/Rm 2259 bits<14> offset; 2260 bits<4> addr; 2261 let Inst{25} = 1; 2262 let Inst{23} = offset{12}; 2263 let Inst{19-16} = addr; 2264 let Inst{11-0} = offset{11-0}; 2265 2266 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2267 } 2268 2269 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2270 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2271 IndexModePost, LdFrm, iii, 2272 opc, "\t$Rt, $addr, $offset", 2273 "$addr.base = $Rn_wb", []> { 2274 // {12} isAdd 2275 // {11-0} imm12/Rm 2276 bits<14> offset; 2277 bits<4> addr; 2278 let Inst{25} = 0; 2279 let Inst{23} = offset{12}; 2280 let Inst{19-16} = addr; 2281 let Inst{11-0} = offset{11-0}; 2282 2283 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2284 } 2285 2286} 2287 2288let mayLoad = 1, neverHasSideEffects = 1 in { 2289// FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or 2290// IIC_iLoad_siu depending on whether it the offset register is shifted. 2291defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2292defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2293} 2294 2295multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2296 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2297 (ins addrmode3:$addr), IndexModePre, 2298 LdMiscFrm, itin, 2299 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2300 bits<14> addr; 2301 let Inst{23} = addr{8}; // U bit 2302 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2303 let Inst{19-16} = addr{12-9}; // Rn 2304 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2305 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2306 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3"; 2307 let DecoderMethod = "DecodeAddrMode3Instruction"; 2308 } 2309 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2310 (ins addr_offset_none:$addr, am3offset:$offset), 2311 IndexModePost, LdMiscFrm, itin, 2312 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2313 []> { 2314 bits<10> offset; 2315 bits<4> addr; 2316 let Inst{23} = offset{8}; // U bit 2317 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2318 let Inst{19-16} = addr; 2319 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2320 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2321 let DecoderMethod = "DecodeAddrMode3Instruction"; 2322 } 2323} 2324 2325let mayLoad = 1, neverHasSideEffects = 1 in { 2326defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2327defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2328defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2329let hasExtraDefRegAllocReq = 1 in { 2330def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2331 (ins addrmode3:$addr), IndexModePre, 2332 LdMiscFrm, IIC_iLoad_d_ru, 2333 "ldrd", "\t$Rt, $Rt2, $addr!", 2334 "$addr.base = $Rn_wb", []> { 2335 bits<14> addr; 2336 let Inst{23} = addr{8}; // U bit 2337 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2338 let Inst{19-16} = addr{12-9}; // Rn 2339 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2340 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2341 let DecoderMethod = "DecodeAddrMode3Instruction"; 2342 let AsmMatchConverter = "cvtLdrdPre"; 2343} 2344def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2345 (ins addr_offset_none:$addr, am3offset:$offset), 2346 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2347 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2348 "$addr.base = $Rn_wb", []> { 2349 bits<10> offset; 2350 bits<4> addr; 2351 let Inst{23} = offset{8}; // U bit 2352 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2353 let Inst{19-16} = addr; 2354 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2355 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2356 let DecoderMethod = "DecodeAddrMode3Instruction"; 2357} 2358} // hasExtraDefRegAllocReq = 1 2359} // mayLoad = 1, neverHasSideEffects = 1 2360 2361// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2362let mayLoad = 1, neverHasSideEffects = 1 in { 2363def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2364 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2365 IndexModePost, LdFrm, IIC_iLoad_ru, 2366 "ldrt", "\t$Rt, $addr, $offset", 2367 "$addr.base = $Rn_wb", []> { 2368 // {12} isAdd 2369 // {11-0} imm12/Rm 2370 bits<14> offset; 2371 bits<4> addr; 2372 let Inst{25} = 1; 2373 let Inst{23} = offset{12}; 2374 let Inst{21} = 1; // overwrite 2375 let Inst{19-16} = addr; 2376 let Inst{11-5} = offset{11-5}; 2377 let Inst{4} = 0; 2378 let Inst{3-0} = offset{3-0}; 2379 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2380} 2381 2382def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2383 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2384 IndexModePost, LdFrm, IIC_iLoad_ru, 2385 "ldrt", "\t$Rt, $addr, $offset", 2386 "$addr.base = $Rn_wb", []> { 2387 // {12} isAdd 2388 // {11-0} imm12/Rm 2389 bits<14> offset; 2390 bits<4> addr; 2391 let Inst{25} = 0; 2392 let Inst{23} = offset{12}; 2393 let Inst{21} = 1; // overwrite 2394 let Inst{19-16} = addr; 2395 let Inst{11-0} = offset{11-0}; 2396 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2397} 2398 2399def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2400 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2401 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2402 "ldrbt", "\t$Rt, $addr, $offset", 2403 "$addr.base = $Rn_wb", []> { 2404 // {12} isAdd 2405 // {11-0} imm12/Rm 2406 bits<14> offset; 2407 bits<4> addr; 2408 let Inst{25} = 1; 2409 let Inst{23} = offset{12}; 2410 let Inst{21} = 1; // overwrite 2411 let Inst{19-16} = addr; 2412 let Inst{11-5} = offset{11-5}; 2413 let Inst{4} = 0; 2414 let Inst{3-0} = offset{3-0}; 2415 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2416} 2417 2418def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2419 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2420 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2421 "ldrbt", "\t$Rt, $addr, $offset", 2422 "$addr.base = $Rn_wb", []> { 2423 // {12} isAdd 2424 // {11-0} imm12/Rm 2425 bits<14> offset; 2426 bits<4> addr; 2427 let Inst{25} = 0; 2428 let Inst{23} = offset{12}; 2429 let Inst{21} = 1; // overwrite 2430 let Inst{19-16} = addr; 2431 let Inst{11-0} = offset{11-0}; 2432 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2433} 2434 2435multiclass AI3ldrT<bits<4> op, string opc> { 2436 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 2437 (ins addr_offset_none:$addr, postidx_imm8:$offset), 2438 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2439 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2440 bits<9> offset; 2441 let Inst{23} = offset{8}; 2442 let Inst{22} = 1; 2443 let Inst{11-8} = offset{7-4}; 2444 let Inst{3-0} = offset{3-0}; 2445 let AsmMatchConverter = "cvtLdExtTWriteBackImm"; 2446 } 2447 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 2448 (ins addr_offset_none:$addr, postidx_reg:$Rm), 2449 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2450 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2451 bits<5> Rm; 2452 let Inst{23} = Rm{4}; 2453 let Inst{22} = 0; 2454 let Inst{11-8} = 0; 2455 let Unpredictable{11-8} = 0b1111; 2456 let Inst{3-0} = Rm{3-0}; 2457 let AsmMatchConverter = "cvtLdExtTWriteBackReg"; 2458 let DecoderMethod = "DecodeLDR"; 2459 } 2460} 2461 2462defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 2463defm LDRHT : AI3ldrT<0b1011, "ldrht">; 2464defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 2465} 2466 2467// Store 2468 2469// Stores with truncate 2470def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 2471 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 2472 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 2473 2474// Store doubleword 2475let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in 2476def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr), 2477 StMiscFrm, IIC_iStore_d_r, 2478 "strd", "\t$Rt, $src2, $addr", []>, 2479 Requires<[IsARM, HasV5TE]> { 2480 let Inst{21} = 0; 2481} 2482 2483// Indexed stores 2484multiclass AI2_stridx<bit isByte, string opc, 2485 InstrItinClass iii, InstrItinClass iir> { 2486 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2487 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre, 2488 StFrm, iii, 2489 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2490 bits<17> addr; 2491 let Inst{25} = 0; 2492 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2493 let Inst{19-16} = addr{16-13}; // Rn 2494 let Inst{11-0} = addr{11-0}; // imm12 2495 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12"; 2496 let DecoderMethod = "DecodeSTRPreImm"; 2497 } 2498 2499 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2500 (ins GPR:$Rt, ldst_so_reg:$addr), 2501 IndexModePre, StFrm, iir, 2502 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2503 bits<17> addr; 2504 let Inst{25} = 1; 2505 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2506 let Inst{19-16} = addr{16-13}; // Rn 2507 let Inst{11-0} = addr{11-0}; 2508 let Inst{4} = 0; // Inst{4} = 0 2509 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; 2510 let DecoderMethod = "DecodeSTRPreReg"; 2511 } 2512 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2513 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2514 IndexModePost, StFrm, iir, 2515 opc, "\t$Rt, $addr, $offset", 2516 "$addr.base = $Rn_wb", []> { 2517 // {12} isAdd 2518 // {11-0} imm12/Rm 2519 bits<14> offset; 2520 bits<4> addr; 2521 let Inst{25} = 1; 2522 let Inst{23} = offset{12}; 2523 let Inst{19-16} = addr; 2524 let Inst{11-0} = offset{11-0}; 2525 let Inst{4} = 0; 2526 2527 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2528 } 2529 2530 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2531 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2532 IndexModePost, StFrm, iii, 2533 opc, "\t$Rt, $addr, $offset", 2534 "$addr.base = $Rn_wb", []> { 2535 // {12} isAdd 2536 // {11-0} imm12/Rm 2537 bits<14> offset; 2538 bits<4> addr; 2539 let Inst{25} = 0; 2540 let Inst{23} = offset{12}; 2541 let Inst{19-16} = addr; 2542 let Inst{11-0} = offset{11-0}; 2543 2544 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2545 } 2546} 2547 2548let mayStore = 1, neverHasSideEffects = 1 in { 2549// FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or 2550// IIC_iStore_siu depending on whether it the offset register is shifted. 2551defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 2552defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 2553} 2554 2555def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2556 am2offset_reg:$offset), 2557 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 2558 am2offset_reg:$offset)>; 2559def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2560 am2offset_imm:$offset), 2561 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2562 am2offset_imm:$offset)>; 2563def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2564 am2offset_reg:$offset), 2565 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 2566 am2offset_reg:$offset)>; 2567def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2568 am2offset_imm:$offset), 2569 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2570 am2offset_imm:$offset)>; 2571 2572// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 2573// put the patterns on the instruction definitions directly as ISel wants 2574// the address base and offset to be separate operands, not a single 2575// complex operand like we represent the instructions themselves. The 2576// pseudos map between the two. 2577let usesCustomInserter = 1, 2578 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 2579def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2580 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 2581 4, IIC_iStore_ru, 2582 [(set GPR:$Rn_wb, 2583 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 2584def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2585 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 2586 4, IIC_iStore_ru, 2587 [(set GPR:$Rn_wb, 2588 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 2589def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2590 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 2591 4, IIC_iStore_ru, 2592 [(set GPR:$Rn_wb, 2593 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 2594def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2595 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 2596 4, IIC_iStore_ru, 2597 [(set GPR:$Rn_wb, 2598 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 2599def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2600 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 2601 4, IIC_iStore_ru, 2602 [(set GPR:$Rn_wb, 2603 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 2604} 2605 2606 2607 2608def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 2609 (ins GPR:$Rt, addrmode3:$addr), IndexModePre, 2610 StMiscFrm, IIC_iStore_bh_ru, 2611 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2612 bits<14> addr; 2613 let Inst{23} = addr{8}; // U bit 2614 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2615 let Inst{19-16} = addr{12-9}; // Rn 2616 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2617 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2618 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3"; 2619 let DecoderMethod = "DecodeAddrMode3Instruction"; 2620} 2621 2622def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 2623 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 2624 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 2625 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2626 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 2627 addr_offset_none:$addr, 2628 am3offset:$offset))]> { 2629 bits<10> offset; 2630 bits<4> addr; 2631 let Inst{23} = offset{8}; // U bit 2632 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2633 let Inst{19-16} = addr; 2634 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2635 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2636 let DecoderMethod = "DecodeAddrMode3Instruction"; 2637} 2638 2639let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { 2640def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 2641 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 2642 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 2643 "strd", "\t$Rt, $Rt2, $addr!", 2644 "$addr.base = $Rn_wb", []> { 2645 bits<14> addr; 2646 let Inst{23} = addr{8}; // U bit 2647 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2648 let Inst{19-16} = addr{12-9}; // Rn 2649 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2650 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2651 let DecoderMethod = "DecodeAddrMode3Instruction"; 2652 let AsmMatchConverter = "cvtStrdPre"; 2653} 2654 2655def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 2656 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 2657 am3offset:$offset), 2658 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 2659 "strd", "\t$Rt, $Rt2, $addr, $offset", 2660 "$addr.base = $Rn_wb", []> { 2661 bits<10> offset; 2662 bits<4> addr; 2663 let Inst{23} = offset{8}; // U bit 2664 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2665 let Inst{19-16} = addr; 2666 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2667 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2668 let DecoderMethod = "DecodeAddrMode3Instruction"; 2669} 2670} // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 2671 2672// STRT, STRBT, and STRHT 2673 2674def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 2675 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2676 IndexModePost, StFrm, IIC_iStore_bh_ru, 2677 "strbt", "\t$Rt, $addr, $offset", 2678 "$addr.base = $Rn_wb", []> { 2679 // {12} isAdd 2680 // {11-0} imm12/Rm 2681 bits<14> offset; 2682 bits<4> addr; 2683 let Inst{25} = 1; 2684 let Inst{23} = offset{12}; 2685 let Inst{21} = 1; // overwrite 2686 let Inst{19-16} = addr; 2687 let Inst{11-5} = offset{11-5}; 2688 let Inst{4} = 0; 2689 let Inst{3-0} = offset{3-0}; 2690 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2691} 2692 2693def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 2694 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2695 IndexModePost, StFrm, IIC_iStore_bh_ru, 2696 "strbt", "\t$Rt, $addr, $offset", 2697 "$addr.base = $Rn_wb", []> { 2698 // {12} isAdd 2699 // {11-0} imm12/Rm 2700 bits<14> offset; 2701 bits<4> addr; 2702 let Inst{25} = 0; 2703 let Inst{23} = offset{12}; 2704 let Inst{21} = 1; // overwrite 2705 let Inst{19-16} = addr; 2706 let Inst{11-0} = offset{11-0}; 2707 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2708} 2709 2710let mayStore = 1, neverHasSideEffects = 1 in { 2711def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 2712 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2713 IndexModePost, StFrm, IIC_iStore_ru, 2714 "strt", "\t$Rt, $addr, $offset", 2715 "$addr.base = $Rn_wb", []> { 2716 // {12} isAdd 2717 // {11-0} imm12/Rm 2718 bits<14> offset; 2719 bits<4> addr; 2720 let Inst{25} = 1; 2721 let Inst{23} = offset{12}; 2722 let Inst{21} = 1; // overwrite 2723 let Inst{19-16} = addr; 2724 let Inst{11-5} = offset{11-5}; 2725 let Inst{4} = 0; 2726 let Inst{3-0} = offset{3-0}; 2727 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2728} 2729 2730def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 2731 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2732 IndexModePost, StFrm, IIC_iStore_ru, 2733 "strt", "\t$Rt, $addr, $offset", 2734 "$addr.base = $Rn_wb", []> { 2735 // {12} isAdd 2736 // {11-0} imm12/Rm 2737 bits<14> offset; 2738 bits<4> addr; 2739 let Inst{25} = 0; 2740 let Inst{23} = offset{12}; 2741 let Inst{21} = 1; // overwrite 2742 let Inst{19-16} = addr; 2743 let Inst{11-0} = offset{11-0}; 2744 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2745} 2746} 2747 2748 2749multiclass AI3strT<bits<4> op, string opc> { 2750 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 2751 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 2752 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 2753 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2754 bits<9> offset; 2755 let Inst{23} = offset{8}; 2756 let Inst{22} = 1; 2757 let Inst{11-8} = offset{7-4}; 2758 let Inst{3-0} = offset{3-0}; 2759 let AsmMatchConverter = "cvtStExtTWriteBackImm"; 2760 } 2761 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 2762 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 2763 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 2764 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2765 bits<5> Rm; 2766 let Inst{23} = Rm{4}; 2767 let Inst{22} = 0; 2768 let Inst{11-8} = 0; 2769 let Inst{3-0} = Rm{3-0}; 2770 let AsmMatchConverter = "cvtStExtTWriteBackReg"; 2771 } 2772} 2773 2774 2775defm STRHT : AI3strT<0b1011, "strht">; 2776 2777 2778//===----------------------------------------------------------------------===// 2779// Load / store multiple Instructions. 2780// 2781 2782multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 2783 InstrItinClass itin, InstrItinClass itin_upd> { 2784 // IA is the default, so no need for an explicit suffix on the 2785 // mnemonic here. Without it is the canonical spelling. 2786 def IA : 2787 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2788 IndexModeNone, f, itin, 2789 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 2790 let Inst{24-23} = 0b01; // Increment After 2791 let Inst{22} = P_bit; 2792 let Inst{21} = 0; // No writeback 2793 let Inst{20} = L_bit; 2794 } 2795 def IA_UPD : 2796 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2797 IndexModeUpd, f, itin_upd, 2798 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 2799 let Inst{24-23} = 0b01; // Increment After 2800 let Inst{22} = P_bit; 2801 let Inst{21} = 1; // Writeback 2802 let Inst{20} = L_bit; 2803 2804 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 2805 } 2806 def DA : 2807 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2808 IndexModeNone, f, itin, 2809 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 2810 let Inst{24-23} = 0b00; // Decrement After 2811 let Inst{22} = P_bit; 2812 let Inst{21} = 0; // No writeback 2813 let Inst{20} = L_bit; 2814 } 2815 def DA_UPD : 2816 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2817 IndexModeUpd, f, itin_upd, 2818 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 2819 let Inst{24-23} = 0b00; // Decrement After 2820 let Inst{22} = P_bit; 2821 let Inst{21} = 1; // Writeback 2822 let Inst{20} = L_bit; 2823 2824 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 2825 } 2826 def DB : 2827 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2828 IndexModeNone, f, itin, 2829 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 2830 let Inst{24-23} = 0b10; // Decrement Before 2831 let Inst{22} = P_bit; 2832 let Inst{21} = 0; // No writeback 2833 let Inst{20} = L_bit; 2834 } 2835 def DB_UPD : 2836 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2837 IndexModeUpd, f, itin_upd, 2838 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 2839 let Inst{24-23} = 0b10; // Decrement Before 2840 let Inst{22} = P_bit; 2841 let Inst{21} = 1; // Writeback 2842 let Inst{20} = L_bit; 2843 2844 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 2845 } 2846 def IB : 2847 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2848 IndexModeNone, f, itin, 2849 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 2850 let Inst{24-23} = 0b11; // Increment Before 2851 let Inst{22} = P_bit; 2852 let Inst{21} = 0; // No writeback 2853 let Inst{20} = L_bit; 2854 } 2855 def IB_UPD : 2856 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2857 IndexModeUpd, f, itin_upd, 2858 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 2859 let Inst{24-23} = 0b11; // Increment Before 2860 let Inst{22} = P_bit; 2861 let Inst{21} = 1; // Writeback 2862 let Inst{20} = L_bit; 2863 2864 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 2865 } 2866} 2867 2868let neverHasSideEffects = 1 in { 2869 2870let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 2871defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 2872 IIC_iLoad_mu>; 2873 2874let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 2875defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 2876 IIC_iStore_mu>; 2877 2878} // neverHasSideEffects 2879 2880// FIXME: remove when we have a way to marking a MI with these properties. 2881// FIXME: Should pc be an implicit operand like PICADD, etc? 2882let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 2883 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 2884def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 2885 reglist:$regs, variable_ops), 2886 4, IIC_iLoad_mBr, [], 2887 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 2888 RegConstraint<"$Rn = $wb">; 2889 2890let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 2891defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 2892 IIC_iLoad_mu>; 2893 2894let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 2895defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 2896 IIC_iStore_mu>; 2897 2898 2899 2900//===----------------------------------------------------------------------===// 2901// Move Instructions. 2902// 2903 2904let neverHasSideEffects = 1 in 2905def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 2906 "mov", "\t$Rd, $Rm", []>, UnaryDP { 2907 bits<4> Rd; 2908 bits<4> Rm; 2909 2910 let Inst{19-16} = 0b0000; 2911 let Inst{11-4} = 0b00000000; 2912 let Inst{25} = 0; 2913 let Inst{3-0} = Rm; 2914 let Inst{15-12} = Rd; 2915} 2916 2917// A version for the smaller set of tail call registers. 2918let neverHasSideEffects = 1 in 2919def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 2920 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP { 2921 bits<4> Rd; 2922 bits<4> Rm; 2923 2924 let Inst{11-4} = 0b00000000; 2925 let Inst{25} = 0; 2926 let Inst{3-0} = Rm; 2927 let Inst{15-12} = Rd; 2928} 2929 2930def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 2931 DPSoRegRegFrm, IIC_iMOVsr, 2932 "mov", "\t$Rd, $src", 2933 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP { 2934 bits<4> Rd; 2935 bits<12> src; 2936 let Inst{15-12} = Rd; 2937 let Inst{19-16} = 0b0000; 2938 let Inst{11-8} = src{11-8}; 2939 let Inst{7} = 0; 2940 let Inst{6-5} = src{6-5}; 2941 let Inst{4} = 1; 2942 let Inst{3-0} = src{3-0}; 2943 let Inst{25} = 0; 2944} 2945 2946def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 2947 DPSoRegImmFrm, IIC_iMOVsr, 2948 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 2949 UnaryDP { 2950 bits<4> Rd; 2951 bits<12> src; 2952 let Inst{15-12} = Rd; 2953 let Inst{19-16} = 0b0000; 2954 let Inst{11-5} = src{11-5}; 2955 let Inst{4} = 0; 2956 let Inst{3-0} = src{3-0}; 2957 let Inst{25} = 0; 2958} 2959 2960let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 2961def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi, 2962 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP { 2963 bits<4> Rd; 2964 bits<12> imm; 2965 let Inst{25} = 1; 2966 let Inst{15-12} = Rd; 2967 let Inst{19-16} = 0b0000; 2968 let Inst{11-0} = imm; 2969} 2970 2971let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 2972def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 2973 DPFrm, IIC_iMOVi, 2974 "movw", "\t$Rd, $imm", 2975 [(set GPR:$Rd, imm0_65535:$imm)]>, 2976 Requires<[IsARM, HasV6T2]>, UnaryDP { 2977 bits<4> Rd; 2978 bits<16> imm; 2979 let Inst{15-12} = Rd; 2980 let Inst{11-0} = imm{11-0}; 2981 let Inst{19-16} = imm{15-12}; 2982 let Inst{20} = 0; 2983 let Inst{25} = 1; 2984 let DecoderMethod = "DecodeArmMOVTWInstruction"; 2985} 2986 2987def : InstAlias<"mov${p} $Rd, $imm", 2988 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>, 2989 Requires<[IsARM]>; 2990 2991def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 2992 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>; 2993 2994let Constraints = "$src = $Rd" in { 2995def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 2996 (ins GPR:$src, imm0_65535_expr:$imm), 2997 DPFrm, IIC_iMOVi, 2998 "movt", "\t$Rd, $imm", 2999 [(set GPRnopc:$Rd, 3000 (or (and GPR:$src, 0xffff), 3001 lo16AllZero:$imm))]>, UnaryDP, 3002 Requires<[IsARM, HasV6T2]> { 3003 bits<4> Rd; 3004 bits<16> imm; 3005 let Inst{15-12} = Rd; 3006 let Inst{11-0} = imm{11-0}; 3007 let Inst{19-16} = imm{15-12}; 3008 let Inst{20} = 0; 3009 let Inst{25} = 1; 3010 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3011} 3012 3013def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3014 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>; 3015 3016} // Constraints 3017 3018def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 3019 Requires<[IsARM, HasV6T2]>; 3020 3021let Uses = [CPSR] in 3022def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 3023 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 3024 Requires<[IsARM]>; 3025 3026// These aren't really mov instructions, but we have to define them this way 3027// due to flag operands. 3028 3029let Defs = [CPSR] in { 3030def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3031 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3032 Requires<[IsARM]>; 3033def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3034 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3035 Requires<[IsARM]>; 3036} 3037 3038//===----------------------------------------------------------------------===// 3039// Extend Instructions. 3040// 3041 3042// Sign extenders 3043 3044def SXTB : AI_ext_rrot<0b01101010, 3045 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3046def SXTH : AI_ext_rrot<0b01101011, 3047 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3048 3049def SXTAB : AI_exta_rrot<0b01101010, 3050 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3051def SXTAH : AI_exta_rrot<0b01101011, 3052 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3053 3054def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3055 3056def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3057 3058// Zero extenders 3059 3060let AddedComplexity = 16 in { 3061def UXTB : AI_ext_rrot<0b01101110, 3062 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3063def UXTH : AI_ext_rrot<0b01101111, 3064 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3065def UXTB16 : AI_ext_rrot<0b01101100, 3066 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3067 3068// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3069// The transformation should probably be done as a combiner action 3070// instead so we can include a check for masking back in the upper 3071// eight bits of the source into the lower eight bits of the result. 3072//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3073// (UXTB16r_rot GPR:$Src, 3)>; 3074def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3075 (UXTB16 GPR:$Src, 1)>; 3076 3077def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3078 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3079def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3080 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3081} 3082 3083// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3084def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3085 3086 3087def SBFX : I<(outs GPRnopc:$Rd), 3088 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3089 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3090 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3091 Requires<[IsARM, HasV6T2]> { 3092 bits<4> Rd; 3093 bits<4> Rn; 3094 bits<5> lsb; 3095 bits<5> width; 3096 let Inst{27-21} = 0b0111101; 3097 let Inst{6-4} = 0b101; 3098 let Inst{20-16} = width; 3099 let Inst{15-12} = Rd; 3100 let Inst{11-7} = lsb; 3101 let Inst{3-0} = Rn; 3102} 3103 3104def UBFX : I<(outs GPR:$Rd), 3105 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width), 3106 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3107 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3108 Requires<[IsARM, HasV6T2]> { 3109 bits<4> Rd; 3110 bits<4> Rn; 3111 bits<5> lsb; 3112 bits<5> width; 3113 let Inst{27-21} = 0b0111111; 3114 let Inst{6-4} = 0b101; 3115 let Inst{20-16} = width; 3116 let Inst{15-12} = Rd; 3117 let Inst{11-7} = lsb; 3118 let Inst{3-0} = Rn; 3119} 3120 3121//===----------------------------------------------------------------------===// 3122// Arithmetic Instructions. 3123// 3124 3125defm ADD : AsI1_bin_irs<0b0100, "add", 3126 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3127 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 3128defm SUB : AsI1_bin_irs<0b0010, "sub", 3129 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3130 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 3131 3132// ADD and SUB with 's' bit set. 3133// 3134// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3135// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3136// AdjustInstrPostInstrSelection where we determine whether or not to 3137// set the "s" bit based on CPSR liveness. 3138// 3139// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3140// support for an optional CPSR definition that corresponds to the DAG 3141// node's second value. We can then eliminate the implicit def of CPSR. 3142defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3143 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>; 3144defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3145 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 3146 3147defm ADC : AI1_adde_sube_irs<0b0101, "adc", 3148 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>; 3149defm SBC : AI1_adde_sube_irs<0b0110, "sbc", 3150 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; 3151 3152defm RSB : AsI1_rbin_irs<0b0011, "rsb", 3153 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3154 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 3155 3156// FIXME: Eliminate them if we can write def : Pat patterns which defines 3157// CPSR and the implicit def of CPSR is not needed. 3158defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3159 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 3160 3161defm RSC : AI1_rsc_irs<0b0111, "rsc", 3162 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; 3163 3164// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3165// The assume-no-carry-in form uses the negation of the input since add/sub 3166// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3167// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3168// details. 3169def : ARMPat<(add GPR:$src, so_imm_neg:$imm), 3170 (SUBri GPR:$src, so_imm_neg:$imm)>; 3171def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm), 3172 (SUBSri GPR:$src, so_imm_neg:$imm)>; 3173 3174def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), 3175 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3176 Requires<[IsARM, HasV6T2]>; 3177def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), 3178 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3179 Requires<[IsARM, HasV6T2]>; 3180 3181// The with-carry-in form matches bitwise not instead of the negation. 3182// Effectively, the inverse interpretation of the carry flag already accounts 3183// for part of the negation. 3184def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR), 3185 (SBCri GPR:$src, so_imm_not:$imm)>; 3186def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), 3187 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>; 3188 3189// Note: These are implemented in C++ code, because they have to generate 3190// ADD/SUBrs instructions, which use a complex pattern that a xform function 3191// cannot produce. 3192// (mul X, 2^n+1) -> (add (X << n), X) 3193// (mul X, 2^n-1) -> (rsb X, (X << n)) 3194 3195// ARM Arithmetic Instruction 3196// GPR:$dst = GPR:$a op GPR:$b 3197class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3198 list<dag> pattern = [], 3199 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3200 string asm = "\t$Rd, $Rn, $Rm"> 3201 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> { 3202 bits<4> Rn; 3203 bits<4> Rd; 3204 bits<4> Rm; 3205 let Inst{27-20} = op27_20; 3206 let Inst{11-4} = op11_4; 3207 let Inst{19-16} = Rn; 3208 let Inst{15-12} = Rd; 3209 let Inst{3-0} = Rm; 3210 3211 let Unpredictable{11-8} = 0b1111; 3212} 3213 3214// Saturating add/subtract 3215 3216def QADD : AAI<0b00010000, 0b00000101, "qadd", 3217 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))], 3218 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">; 3219def QSUB : AAI<0b00010010, 0b00000101, "qsub", 3220 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))], 3221 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">; 3222def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], 3223 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3224 "\t$Rd, $Rm, $Rn">; 3225def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], 3226 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3227 "\t$Rd, $Rm, $Rn">; 3228 3229def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">; 3230def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">; 3231def QASX : AAI<0b01100010, 0b11110011, "qasx">; 3232def QSAX : AAI<0b01100010, 0b11110101, "qsax">; 3233def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">; 3234def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">; 3235def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">; 3236def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">; 3237def UQASX : AAI<0b01100110, 0b11110011, "uqasx">; 3238def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">; 3239def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">; 3240def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">; 3241 3242// Signed/Unsigned add/subtract 3243 3244def SASX : AAI<0b01100001, 0b11110011, "sasx">; 3245def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">; 3246def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">; 3247def SSAX : AAI<0b01100001, 0b11110101, "ssax">; 3248def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">; 3249def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">; 3250def UASX : AAI<0b01100101, 0b11110011, "uasx">; 3251def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">; 3252def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">; 3253def USAX : AAI<0b01100101, 0b11110101, "usax">; 3254def USUB16 : AAI<0b01100101, 0b11110111, "usub16">; 3255def USUB8 : AAI<0b01100101, 0b11111111, "usub8">; 3256 3257// Signed/Unsigned halving add/subtract 3258 3259def SHASX : AAI<0b01100011, 0b11110011, "shasx">; 3260def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">; 3261def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">; 3262def SHSAX : AAI<0b01100011, 0b11110101, "shsax">; 3263def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">; 3264def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">; 3265def UHASX : AAI<0b01100111, 0b11110011, "uhasx">; 3266def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">; 3267def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">; 3268def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">; 3269def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">; 3270def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">; 3271 3272// Unsigned Sum of Absolute Differences [and Accumulate]. 3273 3274def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3275 MulFrm /* for convenience */, NoItinerary, "usad8", 3276 "\t$Rd, $Rn, $Rm", []>, 3277 Requires<[IsARM, HasV6]> { 3278 bits<4> Rd; 3279 bits<4> Rn; 3280 bits<4> Rm; 3281 let Inst{27-20} = 0b01111000; 3282 let Inst{15-12} = 0b1111; 3283 let Inst{7-4} = 0b0001; 3284 let Inst{19-16} = Rd; 3285 let Inst{11-8} = Rm; 3286 let Inst{3-0} = Rn; 3287} 3288def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3289 MulFrm /* for convenience */, NoItinerary, "usada8", 3290 "\t$Rd, $Rn, $Rm, $Ra", []>, 3291 Requires<[IsARM, HasV6]> { 3292 bits<4> Rd; 3293 bits<4> Rn; 3294 bits<4> Rm; 3295 bits<4> Ra; 3296 let Inst{27-20} = 0b01111000; 3297 let Inst{7-4} = 0b0001; 3298 let Inst{19-16} = Rd; 3299 let Inst{15-12} = Ra; 3300 let Inst{11-8} = Rm; 3301 let Inst{3-0} = Rn; 3302} 3303 3304// Signed/Unsigned saturate 3305 3306def SSAT : AI<(outs GPRnopc:$Rd), 3307 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3308 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> { 3309 bits<4> Rd; 3310 bits<5> sat_imm; 3311 bits<4> Rn; 3312 bits<8> sh; 3313 let Inst{27-21} = 0b0110101; 3314 let Inst{5-4} = 0b01; 3315 let Inst{20-16} = sat_imm; 3316 let Inst{15-12} = Rd; 3317 let Inst{11-7} = sh{4-0}; 3318 let Inst{6} = sh{5}; 3319 let Inst{3-0} = Rn; 3320} 3321 3322def SSAT16 : AI<(outs GPRnopc:$Rd), 3323 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 3324 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> { 3325 bits<4> Rd; 3326 bits<4> sat_imm; 3327 bits<4> Rn; 3328 let Inst{27-20} = 0b01101010; 3329 let Inst{11-4} = 0b11110011; 3330 let Inst{15-12} = Rd; 3331 let Inst{19-16} = sat_imm; 3332 let Inst{3-0} = Rn; 3333} 3334 3335def USAT : AI<(outs GPRnopc:$Rd), 3336 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3337 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> { 3338 bits<4> Rd; 3339 bits<5> sat_imm; 3340 bits<4> Rn; 3341 bits<8> sh; 3342 let Inst{27-21} = 0b0110111; 3343 let Inst{5-4} = 0b01; 3344 let Inst{15-12} = Rd; 3345 let Inst{11-7} = sh{4-0}; 3346 let Inst{6} = sh{5}; 3347 let Inst{20-16} = sat_imm; 3348 let Inst{3-0} = Rn; 3349} 3350 3351def USAT16 : AI<(outs GPRnopc:$Rd), 3352 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 3353 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> { 3354 bits<4> Rd; 3355 bits<4> sat_imm; 3356 bits<4> Rn; 3357 let Inst{27-20} = 0b01101110; 3358 let Inst{11-4} = 0b11110011; 3359 let Inst{15-12} = Rd; 3360 let Inst{19-16} = sat_imm; 3361 let Inst{3-0} = Rn; 3362} 3363 3364def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos), 3365 (SSAT imm:$pos, GPRnopc:$a, 0)>; 3366def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos), 3367 (USAT imm:$pos, GPRnopc:$a, 0)>; 3368 3369//===----------------------------------------------------------------------===// 3370// Bitwise Instructions. 3371// 3372 3373defm AND : AsI1_bin_irs<0b0000, "and", 3374 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3375 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 3376defm ORR : AsI1_bin_irs<0b1100, "orr", 3377 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3378 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 3379defm EOR : AsI1_bin_irs<0b0001, "eor", 3380 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3381 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 3382defm BIC : AsI1_bin_irs<0b1110, "bic", 3383 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3384 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 3385 3386// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 3387// like in the actual instruction encoding. The complexity of mapping the mask 3388// to the lsb/msb pair should be handled by ISel, not encapsulated in the 3389// instruction description. 3390def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 3391 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3392 "bfc", "\t$Rd, $imm", "$src = $Rd", 3393 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 3394 Requires<[IsARM, HasV6T2]> { 3395 bits<4> Rd; 3396 bits<10> imm; 3397 let Inst{27-21} = 0b0111110; 3398 let Inst{6-0} = 0b0011111; 3399 let Inst{15-12} = Rd; 3400 let Inst{11-7} = imm{4-0}; // lsb 3401 let Inst{20-16} = imm{9-5}; // msb 3402} 3403 3404// A8.6.18 BFI - Bitfield insert (Encoding A1) 3405def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 3406 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3407 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 3408 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 3409 bf_inv_mask_imm:$imm))]>, 3410 Requires<[IsARM, HasV6T2]> { 3411 bits<4> Rd; 3412 bits<4> Rn; 3413 bits<10> imm; 3414 let Inst{27-21} = 0b0111110; 3415 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 3416 let Inst{15-12} = Rd; 3417 let Inst{11-7} = imm{4-0}; // lsb 3418 let Inst{20-16} = imm{9-5}; // width 3419 let Inst{3-0} = Rn; 3420} 3421 3422def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 3423 "mvn", "\t$Rd, $Rm", 3424 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP { 3425 bits<4> Rd; 3426 bits<4> Rm; 3427 let Inst{25} = 0; 3428 let Inst{19-16} = 0b0000; 3429 let Inst{11-4} = 0b00000000; 3430 let Inst{15-12} = Rd; 3431 let Inst{3-0} = Rm; 3432} 3433def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 3434 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3435 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP { 3436 bits<4> Rd; 3437 bits<12> shift; 3438 let Inst{25} = 0; 3439 let Inst{19-16} = 0b0000; 3440 let Inst{15-12} = Rd; 3441 let Inst{11-5} = shift{11-5}; 3442 let Inst{4} = 0; 3443 let Inst{3-0} = shift{3-0}; 3444} 3445def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift), 3446 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3447 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP { 3448 bits<4> Rd; 3449 bits<12> shift; 3450 let Inst{25} = 0; 3451 let Inst{19-16} = 0b0000; 3452 let Inst{15-12} = Rd; 3453 let Inst{11-8} = shift{11-8}; 3454 let Inst{7} = 0; 3455 let Inst{6-5} = shift{6-5}; 3456 let Inst{4} = 1; 3457 let Inst{3-0} = shift{3-0}; 3458} 3459let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3460def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, 3461 IIC_iMVNi, "mvn", "\t$Rd, $imm", 3462 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP { 3463 bits<4> Rd; 3464 bits<12> imm; 3465 let Inst{25} = 1; 3466 let Inst{19-16} = 0b0000; 3467 let Inst{15-12} = Rd; 3468 let Inst{11-0} = imm; 3469} 3470 3471def : ARMPat<(and GPR:$src, so_imm_not:$imm), 3472 (BICri GPR:$src, so_imm_not:$imm)>; 3473 3474//===----------------------------------------------------------------------===// 3475// Multiply Instructions. 3476// 3477class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3478 string opc, string asm, list<dag> pattern> 3479 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3480 bits<4> Rd; 3481 bits<4> Rm; 3482 bits<4> Rn; 3483 let Inst{19-16} = Rd; 3484 let Inst{11-8} = Rm; 3485 let Inst{3-0} = Rn; 3486} 3487class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3488 string opc, string asm, list<dag> pattern> 3489 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3490 bits<4> RdLo; 3491 bits<4> RdHi; 3492 bits<4> Rm; 3493 bits<4> Rn; 3494 let Inst{19-16} = RdHi; 3495 let Inst{15-12} = RdLo; 3496 let Inst{11-8} = Rm; 3497 let Inst{3-0} = Rn; 3498} 3499class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3500 string opc, string asm, list<dag> pattern> 3501 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3502 bits<4> RdLo; 3503 bits<4> RdHi; 3504 bits<4> Rm; 3505 bits<4> Rn; 3506 let Inst{19-16} = RdHi; 3507 let Inst{15-12} = RdLo; 3508 let Inst{11-8} = Rm; 3509 let Inst{3-0} = Rn; 3510} 3511 3512// FIXME: The v5 pseudos are only necessary for the additional Constraint 3513// property. Remove them when it's possible to add those properties 3514// on an individual MachineInstr, not just an instruction description. 3515let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { 3516def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), 3517 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3518 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 3519 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 3520 Requires<[IsARM, HasV6]> { 3521 let Inst{15-12} = 0b0000; 3522 let Unpredictable{15-12} = 0b1111; 3523} 3524 3525let Constraints = "@earlyclobber $Rd" in 3526def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 3527 pred:$p, cc_out:$s), 3528 4, IIC_iMUL32, 3529 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 3530 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 3531 Requires<[IsARM, NoV6, UseMulOps]>; 3532} 3533 3534def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3535 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 3536 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 3537 Requires<[IsARM, HasV6, UseMulOps]> { 3538 bits<4> Ra; 3539 let Inst{15-12} = Ra; 3540} 3541 3542let Constraints = "@earlyclobber $Rd" in 3543def MLAv5: ARMPseudoExpand<(outs GPR:$Rd), 3544 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s), 3545 4, IIC_iMAC32, 3546 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))], 3547 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>, 3548 Requires<[IsARM, NoV6]>; 3549 3550def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3551 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 3552 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 3553 Requires<[IsARM, HasV6T2, UseMulOps]> { 3554 bits<4> Rd; 3555 bits<4> Rm; 3556 bits<4> Rn; 3557 bits<4> Ra; 3558 let Inst{19-16} = Rd; 3559 let Inst{15-12} = Ra; 3560 let Inst{11-8} = Rm; 3561 let Inst{3-0} = Rn; 3562} 3563 3564// Extra precision multiplies with low / high results 3565let neverHasSideEffects = 1 in { 3566let isCommutable = 1 in { 3567def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 3568 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 3569 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3570 Requires<[IsARM, HasV6]>; 3571 3572def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 3573 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 3574 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3575 Requires<[IsARM, HasV6]>; 3576 3577let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 3578def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3579 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3580 4, IIC_iMUL64, [], 3581 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3582 Requires<[IsARM, NoV6]>; 3583 3584def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3585 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3586 4, IIC_iMUL64, [], 3587 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3588 Requires<[IsARM, NoV6]>; 3589} 3590} 3591 3592// Multiply + accumulate 3593def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 3594 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3595 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3596 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3597def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 3598 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3599 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3600 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3601 3602def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 3603 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64, 3604 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3605 Requires<[IsARM, HasV6]> { 3606 bits<4> RdLo; 3607 bits<4> RdHi; 3608 bits<4> Rm; 3609 bits<4> Rn; 3610 let Inst{19-16} = RdHi; 3611 let Inst{15-12} = RdLo; 3612 let Inst{11-8} = Rm; 3613 let Inst{3-0} = Rn; 3614} 3615 3616let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in { 3617def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3618 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 3619 4, IIC_iMAC64, [], 3620 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 3621 pred:$p, cc_out:$s)>, 3622 Requires<[IsARM, NoV6]>; 3623def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3624 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 3625 4, IIC_iMAC64, [], 3626 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 3627 pred:$p, cc_out:$s)>, 3628 Requires<[IsARM, NoV6]>; 3629} 3630 3631let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 3632def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3633 (ins GPR:$Rn, GPR:$Rm, pred:$p), 3634 4, IIC_iMAC64, [], 3635 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>, 3636 Requires<[IsARM, NoV6]>; 3637} 3638 3639} // neverHasSideEffects 3640 3641// Most significant word multiply 3642def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3643 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 3644 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 3645 Requires<[IsARM, HasV6]> { 3646 let Inst{15-12} = 0b1111; 3647} 3648 3649def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3650 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>, 3651 Requires<[IsARM, HasV6]> { 3652 let Inst{15-12} = 0b1111; 3653} 3654 3655def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 3656 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3657 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 3658 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 3659 Requires<[IsARM, HasV6, UseMulOps]>; 3660 3661def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 3662 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3663 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>, 3664 Requires<[IsARM, HasV6]>; 3665 3666def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 3667 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3668 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, 3669 Requires<[IsARM, HasV6, UseMulOps]>; 3670 3671def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 3672 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3673 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>, 3674 Requires<[IsARM, HasV6]>; 3675 3676multiclass AI_smul<string opc, PatFrag opnode> { 3677 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3678 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 3679 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16), 3680 (sext_inreg GPR:$Rm, i16)))]>, 3681 Requires<[IsARM, HasV5TE]>; 3682 3683 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3684 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 3685 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16), 3686 (sra GPR:$Rm, (i32 16))))]>, 3687 Requires<[IsARM, HasV5TE]>; 3688 3689 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3690 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 3691 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)), 3692 (sext_inreg GPR:$Rm, i16)))]>, 3693 Requires<[IsARM, HasV5TE]>; 3694 3695 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3696 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 3697 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)), 3698 (sra GPR:$Rm, (i32 16))))]>, 3699 Requires<[IsARM, HasV5TE]>; 3700 3701 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3702 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 3703 [(set GPR:$Rd, (sra (opnode GPR:$Rn, 3704 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>, 3705 Requires<[IsARM, HasV5TE]>; 3706 3707 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3708 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 3709 [(set GPR:$Rd, (sra (opnode GPR:$Rn, 3710 (sra GPR:$Rm, (i32 16))), (i32 16)))]>, 3711 Requires<[IsARM, HasV5TE]>; 3712} 3713 3714 3715multiclass AI_smla<string opc, PatFrag opnode> { 3716 let DecoderMethod = "DecodeSMLAInstruction" in { 3717 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 3718 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3719 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 3720 [(set GPRnopc:$Rd, (add GPR:$Ra, 3721 (opnode (sext_inreg GPRnopc:$Rn, i16), 3722 (sext_inreg GPRnopc:$Rm, i16))))]>, 3723 Requires<[IsARM, HasV5TE, UseMulOps]>; 3724 3725 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 3726 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3727 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 3728 [(set GPRnopc:$Rd, 3729 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16), 3730 (sra GPRnopc:$Rm, (i32 16)))))]>, 3731 Requires<[IsARM, HasV5TE, UseMulOps]>; 3732 3733 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 3734 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3735 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 3736 [(set GPRnopc:$Rd, 3737 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)), 3738 (sext_inreg GPRnopc:$Rm, i16))))]>, 3739 Requires<[IsARM, HasV5TE, UseMulOps]>; 3740 3741 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 3742 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3743 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 3744 [(set GPRnopc:$Rd, 3745 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)), 3746 (sra GPRnopc:$Rm, (i32 16)))))]>, 3747 Requires<[IsARM, HasV5TE, UseMulOps]>; 3748 3749 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 3750 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3751 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 3752 [(set GPRnopc:$Rd, 3753 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn, 3754 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>, 3755 Requires<[IsARM, HasV5TE, UseMulOps]>; 3756 3757 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 3758 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3759 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 3760 [(set GPRnopc:$Rd, 3761 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn, 3762 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>, 3763 Requires<[IsARM, HasV5TE, UseMulOps]>; 3764 } 3765} 3766 3767defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 3768defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 3769 3770// Halfword multiply accumulate long: SMLAL<x><y>. 3771def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3772 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3773 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3774 Requires<[IsARM, HasV5TE]>; 3775 3776def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3777 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3778 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3779 Requires<[IsARM, HasV5TE]>; 3780 3781def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3782 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3783 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3784 Requires<[IsARM, HasV5TE]>; 3785 3786def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3787 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3788 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3789 Requires<[IsARM, HasV5TE]>; 3790 3791// Helper class for AI_smld. 3792class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 3793 InstrItinClass itin, string opc, string asm> 3794 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> { 3795 bits<4> Rn; 3796 bits<4> Rm; 3797 let Inst{27-23} = 0b01110; 3798 let Inst{22} = long; 3799 let Inst{21-20} = 0b00; 3800 let Inst{11-8} = Rm; 3801 let Inst{7} = 0; 3802 let Inst{6} = sub; 3803 let Inst{5} = swap; 3804 let Inst{4} = 1; 3805 let Inst{3-0} = Rn; 3806} 3807class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 3808 InstrItinClass itin, string opc, string asm> 3809 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 3810 bits<4> Rd; 3811 let Inst{15-12} = 0b1111; 3812 let Inst{19-16} = Rd; 3813} 3814class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 3815 InstrItinClass itin, string opc, string asm> 3816 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 3817 bits<4> Ra; 3818 bits<4> Rd; 3819 let Inst{19-16} = Rd; 3820 let Inst{15-12} = Ra; 3821} 3822class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 3823 InstrItinClass itin, string opc, string asm> 3824 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 3825 bits<4> RdLo; 3826 bits<4> RdHi; 3827 let Inst{19-16} = RdHi; 3828 let Inst{15-12} = RdLo; 3829} 3830 3831multiclass AI_smld<bit sub, string opc> { 3832 3833 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 3834 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3835 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">; 3836 3837 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 3838 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3839 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">; 3840 3841 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3842 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, 3843 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">; 3844 3845 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3846 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, 3847 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">; 3848 3849} 3850 3851defm SMLA : AI_smld<0, "smla">; 3852defm SMLS : AI_smld<1, "smls">; 3853 3854multiclass AI_sdml<bit sub, string opc> { 3855 3856 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 3857 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">; 3858 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 3859 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">; 3860} 3861 3862defm SMUA : AI_sdml<0, "smua">; 3863defm SMUS : AI_sdml<1, "smus">; 3864 3865//===----------------------------------------------------------------------===// 3866// Division Instructions (ARMv7-A with virtualization extension) 3867// 3868def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 3869 "sdiv", "\t$Rd, $Rn, $Rm", 3870 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, 3871 Requires<[IsARM, HasDivideInARM]>; 3872 3873def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 3874 "udiv", "\t$Rd, $Rn, $Rm", 3875 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, 3876 Requires<[IsARM, HasDivideInARM]>; 3877 3878//===----------------------------------------------------------------------===// 3879// Misc. Arithmetic Instructions. 3880// 3881 3882def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 3883 IIC_iUNAr, "clz", "\t$Rd, $Rm", 3884 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>; 3885 3886def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 3887 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 3888 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>, 3889 Requires<[IsARM, HasV6T2]>; 3890 3891def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 3892 IIC_iUNAr, "rev", "\t$Rd, $Rm", 3893 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>; 3894 3895let AddedComplexity = 5 in 3896def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 3897 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 3898 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 3899 Requires<[IsARM, HasV6]>; 3900 3901let AddedComplexity = 5 in 3902def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 3903 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 3904 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 3905 Requires<[IsARM, HasV6]>; 3906 3907def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 3908 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 3909 (REVSH GPR:$Rm)>; 3910 3911def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 3912 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 3913 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 3914 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 3915 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 3916 0xFFFF0000)))]>, 3917 Requires<[IsARM, HasV6]>; 3918 3919// Alternate cases for PKHBT where identities eliminate some nodes. 3920def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 3921 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 3922def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 3923 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 3924 3925// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 3926// will match the pattern below. 3927def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 3928 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 3929 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 3930 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 3931 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 3932 0xFFFF)))]>, 3933 Requires<[IsARM, HasV6]>; 3934 3935// Alternate cases for PKHTB where identities eliminate some nodes. Note that 3936// a shift amount of 0 is *not legal* here, it is PKHBT instead. 3937def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 3938 (srl GPRnopc:$src2, imm16_31:$sh)), 3939 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 3940def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 3941 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 3942 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 3943 3944//===----------------------------------------------------------------------===// 3945// Comparison Instructions... 3946// 3947 3948defm CMP : AI1_cmp_irs<0b1010, "cmp", 3949 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, 3950 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 3951 3952// ARMcmpZ can re-use the above instruction definitions. 3953def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm), 3954 (CMPri GPR:$src, so_imm:$imm)>; 3955def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 3956 (CMPrr GPR:$src, GPR:$rhs)>; 3957def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 3958 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 3959def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 3960 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 3961 3962// CMN register-integer 3963let isCompare = 1, Defs = [CPSR] in { 3964def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi, 3965 "cmn", "\t$Rn, $imm", 3966 [(ARMcmn GPR:$Rn, so_imm:$imm)]> { 3967 bits<4> Rn; 3968 bits<12> imm; 3969 let Inst{25} = 1; 3970 let Inst{20} = 1; 3971 let Inst{19-16} = Rn; 3972 let Inst{15-12} = 0b0000; 3973 let Inst{11-0} = imm; 3974 3975 let Unpredictable{15-12} = 0b1111; 3976} 3977 3978// CMN register-register/shift 3979def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, 3980 "cmn", "\t$Rn, $Rm", 3981 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 3982 GPR:$Rn, GPR:$Rm)]> { 3983 bits<4> Rn; 3984 bits<4> Rm; 3985 let isCommutable = 1; 3986 let Inst{25} = 0; 3987 let Inst{20} = 1; 3988 let Inst{19-16} = Rn; 3989 let Inst{15-12} = 0b0000; 3990 let Inst{11-4} = 0b00000000; 3991 let Inst{3-0} = Rm; 3992 3993 let Unpredictable{15-12} = 0b1111; 3994} 3995 3996def CMNzrsi : AI1<0b1011, (outs), 3997 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, 3998 "cmn", "\t$Rn, $shift", 3999 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4000 GPR:$Rn, so_reg_imm:$shift)]> { 4001 bits<4> Rn; 4002 bits<12> shift; 4003 let Inst{25} = 0; 4004 let Inst{20} = 1; 4005 let Inst{19-16} = Rn; 4006 let Inst{15-12} = 0b0000; 4007 let Inst{11-5} = shift{11-5}; 4008 let Inst{4} = 0; 4009 let Inst{3-0} = shift{3-0}; 4010 4011 let Unpredictable{15-12} = 0b1111; 4012} 4013 4014def CMNzrsr : AI1<0b1011, (outs), 4015 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, 4016 "cmn", "\t$Rn, $shift", 4017 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4018 GPRnopc:$Rn, so_reg_reg:$shift)]> { 4019 bits<4> Rn; 4020 bits<12> shift; 4021 let Inst{25} = 0; 4022 let Inst{20} = 1; 4023 let Inst{19-16} = Rn; 4024 let Inst{15-12} = 0b0000; 4025 let Inst{11-8} = shift{11-8}; 4026 let Inst{7} = 0; 4027 let Inst{6-5} = shift{6-5}; 4028 let Inst{4} = 1; 4029 let Inst{3-0} = shift{3-0}; 4030 4031 let Unpredictable{15-12} = 0b1111; 4032} 4033 4034} 4035 4036def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm), 4037 (CMNri GPR:$src, so_imm_neg:$imm)>; 4038 4039def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm), 4040 (CMNri GPR:$src, so_imm_neg:$imm)>; 4041 4042// Note that TST/TEQ don't set all the same flags that CMP does! 4043defm TST : AI1_cmp_irs<0b1000, "tst", 4044 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4045 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>; 4046defm TEQ : AI1_cmp_irs<0b1001, "teq", 4047 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4048 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 4049 4050// Pseudo i64 compares for some floating point compares. 4051let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 4052 Defs = [CPSR] in { 4053def BCCi64 : PseudoInst<(outs), 4054 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 4055 IIC_Br, 4056 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>; 4057 4058def BCCZi64 : PseudoInst<(outs), 4059 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 4060 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>; 4061} // usesCustomInserter 4062 4063 4064// Conditional moves 4065// FIXME: should be able to write a pattern for ARMcmov, but can't use 4066// a two-value operand where a dag node expects two operands. :( 4067let neverHasSideEffects = 1 in { 4068 4069let isCommutable = 1, isSelect = 1 in 4070def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p), 4071 4, IIC_iCMOVr, 4072 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>, 4073 RegConstraint<"$false = $Rd">; 4074 4075def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 4076 (ins GPR:$false, so_reg_imm:$shift, pred:$p), 4077 4, IIC_iCMOVsr, 4078 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift, 4079 imm:$cc, CCR:$ccr))*/]>, 4080 RegConstraint<"$false = $Rd">; 4081def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 4082 (ins GPR:$false, so_reg_reg:$shift, pred:$p), 4083 4, IIC_iCMOVsr, 4084 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 4085 imm:$cc, CCR:$ccr))*/]>, 4086 RegConstraint<"$false = $Rd">; 4087 4088 4089let isMoveImm = 1 in 4090def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd), 4091 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p), 4092 4, IIC_iMOVi, 4093 []>, 4094 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 4095 4096let isMoveImm = 1 in 4097def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 4098 (ins GPR:$false, so_imm:$imm, pred:$p), 4099 4, IIC_iCMOVi, 4100 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>, 4101 RegConstraint<"$false = $Rd">; 4102 4103// Two instruction predicate mov immediate. 4104let isMoveImm = 1 in 4105def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd), 4106 (ins GPR:$false, i32imm:$src, pred:$p), 4107 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">; 4108 4109let isMoveImm = 1 in 4110def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 4111 (ins GPR:$false, so_imm:$imm, pred:$p), 4112 4, IIC_iCMOVi, 4113 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>, 4114 RegConstraint<"$false = $Rd">; 4115 4116} // neverHasSideEffects 4117 4118 4119//===----------------------------------------------------------------------===// 4120// Atomic operations intrinsics 4121// 4122 4123def MemBarrierOptOperand : AsmOperandClass { 4124 let Name = "MemBarrierOpt"; 4125 let ParserMethod = "parseMemBarrierOptOperand"; 4126} 4127def memb_opt : Operand<i32> { 4128 let PrintMethod = "printMemBOption"; 4129 let ParserMatchClass = MemBarrierOptOperand; 4130 let DecoderMethod = "DecodeMemBarrierOption"; 4131} 4132 4133// memory barriers protect the atomic sequences 4134let hasSideEffects = 1 in { 4135def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4136 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>, 4137 Requires<[IsARM, HasDB]> { 4138 bits<4> opt; 4139 let Inst{31-4} = 0xf57ff05; 4140 let Inst{3-0} = opt; 4141} 4142} 4143 4144def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4145 "dsb", "\t$opt", []>, 4146 Requires<[IsARM, HasDB]> { 4147 bits<4> opt; 4148 let Inst{31-4} = 0xf57ff04; 4149 let Inst{3-0} = opt; 4150} 4151 4152// ISB has only full system option 4153def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4154 "isb", "\t$opt", []>, 4155 Requires<[IsARM, HasDB]> { 4156 bits<4> opt; 4157 let Inst{31-4} = 0xf57ff06; 4158 let Inst{3-0} = opt; 4159} 4160 4161// Pseudo instruction that combines movs + predicated rsbmi 4162// to implement integer ABS 4163let usesCustomInserter = 1, Defs = [CPSR] in 4164def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; 4165 4166let usesCustomInserter = 1 in { 4167 let Defs = [CPSR] in { 4168 def ATOMIC_LOAD_ADD_I8 : PseudoInst< 4169 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4170 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>; 4171 def ATOMIC_LOAD_SUB_I8 : PseudoInst< 4172 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4173 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>; 4174 def ATOMIC_LOAD_AND_I8 : PseudoInst< 4175 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4176 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>; 4177 def ATOMIC_LOAD_OR_I8 : PseudoInst< 4178 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4179 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>; 4180 def ATOMIC_LOAD_XOR_I8 : PseudoInst< 4181 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4182 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>; 4183 def ATOMIC_LOAD_NAND_I8 : PseudoInst< 4184 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4185 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>; 4186 def ATOMIC_LOAD_MIN_I8 : PseudoInst< 4187 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4188 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>; 4189 def ATOMIC_LOAD_MAX_I8 : PseudoInst< 4190 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4191 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>; 4192 def ATOMIC_LOAD_UMIN_I8 : PseudoInst< 4193 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4194 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>; 4195 def ATOMIC_LOAD_UMAX_I8 : PseudoInst< 4196 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4197 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>; 4198 def ATOMIC_LOAD_ADD_I16 : PseudoInst< 4199 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4200 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>; 4201 def ATOMIC_LOAD_SUB_I16 : PseudoInst< 4202 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4203 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>; 4204 def ATOMIC_LOAD_AND_I16 : PseudoInst< 4205 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4206 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>; 4207 def ATOMIC_LOAD_OR_I16 : PseudoInst< 4208 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4209 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>; 4210 def ATOMIC_LOAD_XOR_I16 : PseudoInst< 4211 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4212 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>; 4213 def ATOMIC_LOAD_NAND_I16 : PseudoInst< 4214 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4215 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>; 4216 def ATOMIC_LOAD_MIN_I16 : PseudoInst< 4217 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4218 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>; 4219 def ATOMIC_LOAD_MAX_I16 : PseudoInst< 4220 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4221 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>; 4222 def ATOMIC_LOAD_UMIN_I16 : PseudoInst< 4223 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4224 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>; 4225 def ATOMIC_LOAD_UMAX_I16 : PseudoInst< 4226 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4227 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>; 4228 def ATOMIC_LOAD_ADD_I32 : PseudoInst< 4229 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4230 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>; 4231 def ATOMIC_LOAD_SUB_I32 : PseudoInst< 4232 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4233 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>; 4234 def ATOMIC_LOAD_AND_I32 : PseudoInst< 4235 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4236 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>; 4237 def ATOMIC_LOAD_OR_I32 : PseudoInst< 4238 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4239 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>; 4240 def ATOMIC_LOAD_XOR_I32 : PseudoInst< 4241 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4242 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>; 4243 def ATOMIC_LOAD_NAND_I32 : PseudoInst< 4244 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4245 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>; 4246 def ATOMIC_LOAD_MIN_I32 : PseudoInst< 4247 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4248 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>; 4249 def ATOMIC_LOAD_MAX_I32 : PseudoInst< 4250 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4251 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>; 4252 def ATOMIC_LOAD_UMIN_I32 : PseudoInst< 4253 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4254 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>; 4255 def ATOMIC_LOAD_UMAX_I32 : PseudoInst< 4256 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4257 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>; 4258 4259 def ATOMIC_SWAP_I8 : PseudoInst< 4260 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, 4261 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>; 4262 def ATOMIC_SWAP_I16 : PseudoInst< 4263 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, 4264 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>; 4265 def ATOMIC_SWAP_I32 : PseudoInst< 4266 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, 4267 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>; 4268 4269 def ATOMIC_CMP_SWAP_I8 : PseudoInst< 4270 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, 4271 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>; 4272 def ATOMIC_CMP_SWAP_I16 : PseudoInst< 4273 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, 4274 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>; 4275 def ATOMIC_CMP_SWAP_I32 : PseudoInst< 4276 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, 4277 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>; 4278} 4279} 4280 4281let usesCustomInserter = 1 in { 4282 def COPY_STRUCT_BYVAL_I32 : PseudoInst< 4283 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), 4284 NoItinerary, 4285 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; 4286} 4287 4288let mayLoad = 1 in { 4289def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4290 NoItinerary, 4291 "ldrexb", "\t$Rt, $addr", []>; 4292def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4293 NoItinerary, "ldrexh", "\t$Rt, $addr", []>; 4294def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4295 NoItinerary, "ldrex", "\t$Rt, $addr", []>; 4296let hasExtraDefRegAllocReq = 1 in 4297def LDREXD: AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4298 NoItinerary, "ldrexd", "\t$Rt, $addr", []> { 4299 let DecoderMethod = "DecodeDoubleRegLoad"; 4300} 4301} 4302 4303let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 4304def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4305 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>; 4306def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4307 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>; 4308def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4309 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>; 4310let hasExtraSrcRegAllocReq = 1 in 4311def STREXD : AIstrex<0b01, (outs GPR:$Rd), 4312 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 4313 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { 4314 let DecoderMethod = "DecodeDoubleRegStore"; 4315} 4316} 4317 4318 4319def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>, 4320 Requires<[IsARM, HasV7]> { 4321 let Inst{31-0} = 0b11110101011111111111000000011111; 4322} 4323 4324// SWP/SWPB are deprecated in V6/V7. 4325let mayLoad = 1, mayStore = 1 in { 4326def SWP : AIswp<0, (outs GPRnopc:$Rt), 4327 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>; 4328def SWPB: AIswp<1, (outs GPRnopc:$Rt), 4329 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>; 4330} 4331 4332//===----------------------------------------------------------------------===// 4333// Coprocessor Instructions. 4334// 4335 4336def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4337 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4338 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4339 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4340 imm:$CRm, imm:$opc2)]> { 4341 bits<4> opc1; 4342 bits<4> CRn; 4343 bits<4> CRd; 4344 bits<4> cop; 4345 bits<3> opc2; 4346 bits<4> CRm; 4347 4348 let Inst{3-0} = CRm; 4349 let Inst{4} = 0; 4350 let Inst{7-5} = opc2; 4351 let Inst{11-8} = cop; 4352 let Inst{15-12} = CRd; 4353 let Inst{19-16} = CRn; 4354 let Inst{23-20} = opc1; 4355} 4356 4357def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1, 4358 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4359 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4360 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4361 imm:$CRm, imm:$opc2)]> { 4362 let Inst{31-28} = 0b1111; 4363 bits<4> opc1; 4364 bits<4> CRn; 4365 bits<4> CRd; 4366 bits<4> cop; 4367 bits<3> opc2; 4368 bits<4> CRm; 4369 4370 let Inst{3-0} = CRm; 4371 let Inst{4} = 0; 4372 let Inst{7-5} = opc2; 4373 let Inst{11-8} = cop; 4374 let Inst{15-12} = CRd; 4375 let Inst{19-16} = CRn; 4376 let Inst{23-20} = opc1; 4377} 4378 4379class ACI<dag oops, dag iops, string opc, string asm, 4380 IndexMode im = IndexModeNone> 4381 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 4382 opc, asm, "", []> { 4383 let Inst{27-25} = 0b110; 4384} 4385class ACInoP<dag oops, dag iops, string opc, string asm, 4386 IndexMode im = IndexModeNone> 4387 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 4388 opc, asm, "", []> { 4389 let Inst{31-28} = 0b1111; 4390 let Inst{27-25} = 0b110; 4391} 4392multiclass LdStCop<bit load, bit Dbit, string asm> { 4393 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4394 asm, "\t$cop, $CRd, $addr"> { 4395 bits<13> addr; 4396 bits<4> cop; 4397 bits<4> CRd; 4398 let Inst{24} = 1; // P = 1 4399 let Inst{23} = addr{8}; 4400 let Inst{22} = Dbit; 4401 let Inst{21} = 0; // W = 0 4402 let Inst{20} = load; 4403 let Inst{19-16} = addr{12-9}; 4404 let Inst{15-12} = CRd; 4405 let Inst{11-8} = cop; 4406 let Inst{7-0} = addr{7-0}; 4407 let DecoderMethod = "DecodeCopMemInstruction"; 4408 } 4409 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4410 asm, "\t$cop, $CRd, $addr!", IndexModePre> { 4411 bits<13> addr; 4412 bits<4> cop; 4413 bits<4> CRd; 4414 let Inst{24} = 1; // P = 1 4415 let Inst{23} = addr{8}; 4416 let Inst{22} = Dbit; 4417 let Inst{21} = 1; // W = 1 4418 let Inst{20} = load; 4419 let Inst{19-16} = addr{12-9}; 4420 let Inst{15-12} = CRd; 4421 let Inst{11-8} = cop; 4422 let Inst{7-0} = addr{7-0}; 4423 let DecoderMethod = "DecodeCopMemInstruction"; 4424 } 4425 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4426 postidx_imm8s4:$offset), 4427 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> { 4428 bits<9> offset; 4429 bits<4> addr; 4430 bits<4> cop; 4431 bits<4> CRd; 4432 let Inst{24} = 0; // P = 0 4433 let Inst{23} = offset{8}; 4434 let Inst{22} = Dbit; 4435 let Inst{21} = 1; // W = 1 4436 let Inst{20} = load; 4437 let Inst{19-16} = addr; 4438 let Inst{15-12} = CRd; 4439 let Inst{11-8} = cop; 4440 let Inst{7-0} = offset{7-0}; 4441 let DecoderMethod = "DecodeCopMemInstruction"; 4442 } 4443 def _OPTION : ACI<(outs), 4444 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4445 coproc_option_imm:$option), 4446 asm, "\t$cop, $CRd, $addr, $option"> { 4447 bits<8> option; 4448 bits<4> addr; 4449 bits<4> cop; 4450 bits<4> CRd; 4451 let Inst{24} = 0; // P = 0 4452 let Inst{23} = 1; // U = 1 4453 let Inst{22} = Dbit; 4454 let Inst{21} = 0; // W = 0 4455 let Inst{20} = load; 4456 let Inst{19-16} = addr; 4457 let Inst{15-12} = CRd; 4458 let Inst{11-8} = cop; 4459 let Inst{7-0} = option; 4460 let DecoderMethod = "DecodeCopMemInstruction"; 4461 } 4462} 4463multiclass LdSt2Cop<bit load, bit Dbit, string asm> { 4464 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4465 asm, "\t$cop, $CRd, $addr"> { 4466 bits<13> addr; 4467 bits<4> cop; 4468 bits<4> CRd; 4469 let Inst{24} = 1; // P = 1 4470 let Inst{23} = addr{8}; 4471 let Inst{22} = Dbit; 4472 let Inst{21} = 0; // W = 0 4473 let Inst{20} = load; 4474 let Inst{19-16} = addr{12-9}; 4475 let Inst{15-12} = CRd; 4476 let Inst{11-8} = cop; 4477 let Inst{7-0} = addr{7-0}; 4478 let DecoderMethod = "DecodeCopMemInstruction"; 4479 } 4480 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4481 asm, "\t$cop, $CRd, $addr!", IndexModePre> { 4482 bits<13> addr; 4483 bits<4> cop; 4484 bits<4> CRd; 4485 let Inst{24} = 1; // P = 1 4486 let Inst{23} = addr{8}; 4487 let Inst{22} = Dbit; 4488 let Inst{21} = 1; // W = 1 4489 let Inst{20} = load; 4490 let Inst{19-16} = addr{12-9}; 4491 let Inst{15-12} = CRd; 4492 let Inst{11-8} = cop; 4493 let Inst{7-0} = addr{7-0}; 4494 let DecoderMethod = "DecodeCopMemInstruction"; 4495 } 4496 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4497 postidx_imm8s4:$offset), 4498 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> { 4499 bits<9> offset; 4500 bits<4> addr; 4501 bits<4> cop; 4502 bits<4> CRd; 4503 let Inst{24} = 0; // P = 0 4504 let Inst{23} = offset{8}; 4505 let Inst{22} = Dbit; 4506 let Inst{21} = 1; // W = 1 4507 let Inst{20} = load; 4508 let Inst{19-16} = addr; 4509 let Inst{15-12} = CRd; 4510 let Inst{11-8} = cop; 4511 let Inst{7-0} = offset{7-0}; 4512 let DecoderMethod = "DecodeCopMemInstruction"; 4513 } 4514 def _OPTION : ACInoP<(outs), 4515 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4516 coproc_option_imm:$option), 4517 asm, "\t$cop, $CRd, $addr, $option"> { 4518 bits<8> option; 4519 bits<4> addr; 4520 bits<4> cop; 4521 bits<4> CRd; 4522 let Inst{24} = 0; // P = 0 4523 let Inst{23} = 1; // U = 1 4524 let Inst{22} = Dbit; 4525 let Inst{21} = 0; // W = 0 4526 let Inst{20} = load; 4527 let Inst{19-16} = addr; 4528 let Inst{15-12} = CRd; 4529 let Inst{11-8} = cop; 4530 let Inst{7-0} = option; 4531 let DecoderMethod = "DecodeCopMemInstruction"; 4532 } 4533} 4534 4535defm LDC : LdStCop <1, 0, "ldc">; 4536defm LDCL : LdStCop <1, 1, "ldcl">; 4537defm STC : LdStCop <0, 0, "stc">; 4538defm STCL : LdStCop <0, 1, "stcl">; 4539defm LDC2 : LdSt2Cop<1, 0, "ldc2">; 4540defm LDC2L : LdSt2Cop<1, 1, "ldc2l">; 4541defm STC2 : LdSt2Cop<0, 0, "stc2">; 4542defm STC2L : LdSt2Cop<0, 1, "stc2l">; 4543 4544//===----------------------------------------------------------------------===// 4545// Move between coprocessor and ARM core register. 4546// 4547 4548class MovRCopro<string opc, bit direction, dag oops, dag iops, 4549 list<dag> pattern> 4550 : ABI<0b1110, oops, iops, NoItinerary, opc, 4551 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 4552 let Inst{20} = direction; 4553 let Inst{4} = 1; 4554 4555 bits<4> Rt; 4556 bits<4> cop; 4557 bits<3> opc1; 4558 bits<3> opc2; 4559 bits<4> CRm; 4560 bits<4> CRn; 4561 4562 let Inst{15-12} = Rt; 4563 let Inst{11-8} = cop; 4564 let Inst{23-21} = opc1; 4565 let Inst{7-5} = opc2; 4566 let Inst{3-0} = CRm; 4567 let Inst{19-16} = CRn; 4568} 4569 4570def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 4571 (outs), 4572 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4573 c_imm:$CRm, imm0_7:$opc2), 4574 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4575 imm:$CRm, imm:$opc2)]>; 4576def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 4577 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4578 c_imm:$CRm, 0, pred:$p)>; 4579def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 4580 (outs GPR:$Rt), 4581 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 4582 imm0_7:$opc2), []>; 4583def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 4584 (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4585 c_imm:$CRm, 0, pred:$p)>; 4586 4587def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 4588 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 4589 4590class MovRCopro2<string opc, bit direction, dag oops, dag iops, 4591 list<dag> pattern> 4592 : ABXI<0b1110, oops, iops, NoItinerary, 4593 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 4594 let Inst{31-28} = 0b1111; 4595 let Inst{20} = direction; 4596 let Inst{4} = 1; 4597 4598 bits<4> Rt; 4599 bits<4> cop; 4600 bits<3> opc1; 4601 bits<3> opc2; 4602 bits<4> CRm; 4603 bits<4> CRn; 4604 4605 let Inst{15-12} = Rt; 4606 let Inst{11-8} = cop; 4607 let Inst{23-21} = opc1; 4608 let Inst{7-5} = opc2; 4609 let Inst{3-0} = CRm; 4610 let Inst{19-16} = CRn; 4611} 4612 4613def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 4614 (outs), 4615 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4616 c_imm:$CRm, imm0_7:$opc2), 4617 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4618 imm:$CRm, imm:$opc2)]>; 4619def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm", 4620 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4621 c_imm:$CRm, 0)>; 4622def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 4623 (outs GPR:$Rt), 4624 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 4625 imm0_7:$opc2), []>; 4626def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm", 4627 (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4628 c_imm:$CRm, 0)>; 4629 4630def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, 4631 imm:$CRm, imm:$opc2), 4632 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 4633 4634class MovRRCopro<string opc, bit direction, list<dag> pattern = []> 4635 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4636 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), 4637 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> { 4638 let Inst{23-21} = 0b010; 4639 let Inst{20} = direction; 4640 4641 bits<4> Rt; 4642 bits<4> Rt2; 4643 bits<4> cop; 4644 bits<4> opc1; 4645 bits<4> CRm; 4646 4647 let Inst{15-12} = Rt; 4648 let Inst{19-16} = Rt2; 4649 let Inst{11-8} = cop; 4650 let Inst{7-4} = opc1; 4651 let Inst{3-0} = CRm; 4652} 4653 4654def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 4655 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt, 4656 GPRnopc:$Rt2, imm:$CRm)]>; 4657def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>; 4658 4659class MovRRCopro2<string opc, bit direction, list<dag> pattern = []> 4660 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4661 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary, 4662 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> { 4663 let Inst{31-28} = 0b1111; 4664 let Inst{23-21} = 0b010; 4665 let Inst{20} = direction; 4666 4667 bits<4> Rt; 4668 bits<4> Rt2; 4669 bits<4> cop; 4670 bits<4> opc1; 4671 bits<4> CRm; 4672 4673 let Inst{15-12} = Rt; 4674 let Inst{19-16} = Rt2; 4675 let Inst{11-8} = cop; 4676 let Inst{7-4} = opc1; 4677 let Inst{3-0} = CRm; 4678 4679 let DecoderMethod = "DecodeMRRC2"; 4680} 4681 4682def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 4683 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt, 4684 GPRnopc:$Rt2, imm:$CRm)]>; 4685def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>; 4686 4687//===----------------------------------------------------------------------===// 4688// Move between special register and ARM core register 4689// 4690 4691// Move to ARM core register from Special Register 4692def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 4693 "mrs", "\t$Rd, apsr", []> { 4694 bits<4> Rd; 4695 let Inst{23-16} = 0b00001111; 4696 let Unpredictable{19-17} = 0b111; 4697 4698 let Inst{15-12} = Rd; 4699 4700 let Inst{11-0} = 0b000000000000; 4701 let Unpredictable{11-0} = 0b110100001111; 4702} 4703 4704def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>, 4705 Requires<[IsARM]>; 4706 4707// The MRSsys instruction is the MRS instruction from the ARM ARM, 4708// section B9.3.9, with the R bit set to 1. 4709def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 4710 "mrs", "\t$Rd, spsr", []> { 4711 bits<4> Rd; 4712 let Inst{23-16} = 0b01001111; 4713 let Unpredictable{19-16} = 0b1111; 4714 4715 let Inst{15-12} = Rd; 4716 4717 let Inst{11-0} = 0b000000000000; 4718 let Unpredictable{11-0} = 0b110100001111; 4719} 4720 4721// Move from ARM core register to Special Register 4722// 4723// No need to have both system and application versions, the encodings are the 4724// same and the assembly parser has no way to distinguish between them. The mask 4725// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains 4726// the mask with the fields to be accessed in the special register. 4727def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 4728 "msr", "\t$mask, $Rn", []> { 4729 bits<5> mask; 4730 bits<4> Rn; 4731 4732 let Inst{23} = 0; 4733 let Inst{22} = mask{4}; // R bit 4734 let Inst{21-20} = 0b10; 4735 let Inst{19-16} = mask{3-0}; 4736 let Inst{15-12} = 0b1111; 4737 let Inst{11-4} = 0b00000000; 4738 let Inst{3-0} = Rn; 4739} 4740 4741def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary, 4742 "msr", "\t$mask, $a", []> { 4743 bits<5> mask; 4744 bits<12> a; 4745 4746 let Inst{23} = 0; 4747 let Inst{22} = mask{4}; // R bit 4748 let Inst{21-20} = 0b10; 4749 let Inst{19-16} = mask{3-0}; 4750 let Inst{15-12} = 0b1111; 4751 let Inst{11-0} = a; 4752} 4753 4754//===----------------------------------------------------------------------===// 4755// TLS Instructions 4756// 4757 4758// __aeabi_read_tp preserves the registers r1-r3. 4759// This is a pseudo inst so that we can get the encoding right, 4760// complete with fixup for the aeabi_read_tp function. 4761let isCall = 1, 4762 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 4763 def TPsoft : PseudoInst<(outs), (ins), IIC_Br, 4764 [(set R0, ARMthread_pointer)]>; 4765} 4766 4767//===----------------------------------------------------------------------===// 4768// SJLJ Exception handling intrinsics 4769// eh_sjlj_setjmp() is an instruction sequence to store the return 4770// address and save #0 in R0 for the non-longjmp case. 4771// Since by its nature we may be coming from some other function to get 4772// here, and we're using the stack frame for the containing function to 4773// save/restore registers, we can't keep anything live in regs across 4774// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 4775// when we get here from a longjmp(). We force everything out of registers 4776// except for our own input by listing the relevant registers in Defs. By 4777// doing so, we also cause the prologue/epilogue code to actively preserve 4778// all of the callee-saved resgisters, which is exactly what we want. 4779// A constant value is passed in $val, and we use the location as a scratch. 4780// 4781// These are pseudo-instructions and are lowered to individual MC-insts, so 4782// no encoding information is necessary. 4783let Defs = 4784 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 4785 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 4786 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 4787 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 4788 NoItinerary, 4789 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 4790 Requires<[IsARM, HasVFP2]>; 4791} 4792 4793let Defs = 4794 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 4795 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 4796 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 4797 NoItinerary, 4798 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 4799 Requires<[IsARM, NoVFP]>; 4800} 4801 4802// FIXME: Non-IOS version(s) 4803let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 4804 Defs = [ R7, LR, SP ] in { 4805def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 4806 NoItinerary, 4807 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 4808 Requires<[IsARM, IsIOS]>; 4809} 4810 4811// eh.sjlj.dispatchsetup pseudo-instruction. 4812// This pseudo is used for both ARM and Thumb. Any differences are handled when 4813// the pseudo is expanded (which happens before any passes that need the 4814// instruction size). 4815let isBarrier = 1 in 4816def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 4817 4818 4819//===----------------------------------------------------------------------===// 4820// Non-Instruction Patterns 4821// 4822 4823// ARMv4 indirect branch using (MOVr PC, dst) 4824let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 4825 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 4826 4, IIC_Br, [(brind GPR:$dst)], 4827 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 4828 Requires<[IsARM, NoV4T]>; 4829 4830// Large immediate handling. 4831 4832// 32-bit immediate using two piece so_imms or movw + movt. 4833// This is a single pseudo instruction, the benefit is that it can be remat'd 4834// as a single unit instead of having to handle reg inputs. 4835// FIXME: Remove this when we can do generalized remat. 4836let isReMaterializable = 1, isMoveImm = 1 in 4837def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 4838 [(set GPR:$dst, (arm_i32imm:$src))]>, 4839 Requires<[IsARM]>; 4840 4841// Pseudo instruction that combines movw + movt + add pc (if PIC). 4842// It also makes it possible to rematerialize the instructions. 4843// FIXME: Remove this when we can do generalized remat and when machine licm 4844// can properly the instructions. 4845let isReMaterializable = 1 in { 4846def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 4847 IIC_iMOVix2addpc, 4848 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 4849 Requires<[IsARM, UseMovt]>; 4850 4851def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 4852 IIC_iMOVix2, 4853 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>, 4854 Requires<[IsARM, UseMovt]>; 4855 4856let AddedComplexity = 10 in 4857def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 4858 IIC_iMOVix2ld, 4859 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 4860 Requires<[IsARM, UseMovt]>; 4861} // isReMaterializable 4862 4863// ConstantPool, GlobalAddress, and JumpTable 4864def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>, 4865 Requires<[IsARM, DontUseMovt]>; 4866def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 4867def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 4868 Requires<[IsARM, UseMovt]>; 4869def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id), 4870 (LEApcrelJT tjumptable:$dst, imm:$id)>; 4871 4872// TODO: add,sub,and, 3-instr forms? 4873 4874// Tail calls. These patterns also apply to Thumb mode. 4875def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; 4876def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; 4877def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; 4878 4879// Direct calls 4880def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 4881def : ARMPat<(ARMcall_nolink texternalsym:$func), 4882 (BMOVPCB_CALL texternalsym:$func)>; 4883 4884// zextload i1 -> zextload i8 4885def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 4886def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 4887 4888// extload -> zextload 4889def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 4890def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 4891def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 4892def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 4893 4894def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 4895 4896def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 4897def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 4898 4899// smul* and smla* 4900def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 4901 (sra (shl GPR:$b, (i32 16)), (i32 16))), 4902 (SMULBB GPR:$a, GPR:$b)>; 4903def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 4904 (SMULBB GPR:$a, GPR:$b)>; 4905def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 4906 (sra GPR:$b, (i32 16))), 4907 (SMULBT GPR:$a, GPR:$b)>; 4908def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))), 4909 (SMULBT GPR:$a, GPR:$b)>; 4910def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), 4911 (sra (shl GPR:$b, (i32 16)), (i32 16))), 4912 (SMULTB GPR:$a, GPR:$b)>; 4913def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b), 4914 (SMULTB GPR:$a, GPR:$b)>; 4915def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), 4916 (i32 16)), 4917 (SMULWB GPR:$a, GPR:$b)>; 4918def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)), 4919 (SMULWB GPR:$a, GPR:$b)>; 4920 4921def : ARMV5MOPat<(add GPR:$acc, 4922 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 4923 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 4924 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 4925def : ARMV5MOPat<(add GPR:$acc, 4926 (mul sext_16_node:$a, sext_16_node:$b)), 4927 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 4928def : ARMV5MOPat<(add GPR:$acc, 4929 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 4930 (sra GPR:$b, (i32 16)))), 4931 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 4932def : ARMV5MOPat<(add GPR:$acc, 4933 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))), 4934 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 4935def : ARMV5MOPat<(add GPR:$acc, 4936 (mul (sra GPR:$a, (i32 16)), 4937 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 4938 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 4939def : ARMV5MOPat<(add GPR:$acc, 4940 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)), 4941 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 4942def : ARMV5MOPat<(add GPR:$acc, 4943 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), 4944 (i32 16))), 4945 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 4946def : ARMV5MOPat<(add GPR:$acc, 4947 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))), 4948 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 4949 4950 4951// Pre-v7 uses MCR for synchronization barriers. 4952def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 4953 Requires<[IsARM, HasV6]>; 4954 4955// SXT/UXT with no rotate 4956let AddedComplexity = 16 in { 4957def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 4958def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 4959def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 4960def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 4961 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 4962def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 4963 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 4964} 4965 4966def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 4967def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 4968 4969def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 4970 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 4971def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 4972 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 4973 4974// Atomic load/store patterns 4975def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 4976 (LDRBrs ldst_so_reg:$src)>; 4977def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 4978 (LDRBi12 addrmode_imm12:$src)>; 4979def : ARMPat<(atomic_load_16 addrmode3:$src), 4980 (LDRH addrmode3:$src)>; 4981def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 4982 (LDRrs ldst_so_reg:$src)>; 4983def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 4984 (LDRi12 addrmode_imm12:$src)>; 4985def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 4986 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 4987def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 4988 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 4989def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 4990 (STRH GPR:$val, addrmode3:$ptr)>; 4991def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 4992 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 4993def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 4994 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 4995 4996 4997//===----------------------------------------------------------------------===// 4998// Thumb Support 4999// 5000 5001include "ARMInstrThumb.td" 5002 5003//===----------------------------------------------------------------------===// 5004// Thumb2 Support 5005// 5006 5007include "ARMInstrThumb2.td" 5008 5009//===----------------------------------------------------------------------===// 5010// Floating Point Support 5011// 5012 5013include "ARMInstrVFP.td" 5014 5015//===----------------------------------------------------------------------===// 5016// Advanced SIMD (NEON) Support 5017// 5018 5019include "ARMInstrNEON.td" 5020 5021//===----------------------------------------------------------------------===// 5022// Assembler aliases 5023// 5024 5025// Memory barriers 5026def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>; 5027def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>; 5028def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>; 5029 5030// System instructions 5031def : MnemonicAlias<"swi", "svc">; 5032 5033// Load / Store Multiple 5034def : MnemonicAlias<"ldmfd", "ldm">; 5035def : MnemonicAlias<"ldmia", "ldm">; 5036def : MnemonicAlias<"ldmea", "ldmdb">; 5037def : MnemonicAlias<"stmfd", "stmdb">; 5038def : MnemonicAlias<"stmia", "stm">; 5039def : MnemonicAlias<"stmea", "stm">; 5040 5041// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the 5042// shift amount is zero (i.e., unspecified). 5043def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 5044 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>, 5045 Requires<[IsARM, HasV6]>; 5046def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 5047 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>, 5048 Requires<[IsARM, HasV6]>; 5049 5050// PUSH/POP aliases for STM/LDM 5051def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 5052def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 5053 5054// SSAT/USAT optional shift operand. 5055def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 5056 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5057def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 5058 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5059 5060 5061// Extend instruction optional rotate operand. 5062def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 5063 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5064def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 5065 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5066def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 5067 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5068def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 5069 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5070def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 5071 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5072def : ARMInstAlias<"sxth${p} $Rd, $Rm", 5073 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5074 5075def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 5076 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5077def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 5078 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5079def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 5080 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5081def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 5082 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5083def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 5084 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5085def : ARMInstAlias<"uxth${p} $Rd, $Rm", 5086 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5087 5088 5089// RFE aliases 5090def : MnemonicAlias<"rfefa", "rfeda">; 5091def : MnemonicAlias<"rfeea", "rfedb">; 5092def : MnemonicAlias<"rfefd", "rfeia">; 5093def : MnemonicAlias<"rfeed", "rfeib">; 5094def : MnemonicAlias<"rfe", "rfeia">; 5095 5096// SRS aliases 5097def : MnemonicAlias<"srsfa", "srsda">; 5098def : MnemonicAlias<"srsea", "srsdb">; 5099def : MnemonicAlias<"srsfd", "srsia">; 5100def : MnemonicAlias<"srsed", "srsib">; 5101def : MnemonicAlias<"srs", "srsia">; 5102 5103// QSAX == QSUBADDX 5104def : MnemonicAlias<"qsubaddx", "qsax">; 5105// SASX == SADDSUBX 5106def : MnemonicAlias<"saddsubx", "sasx">; 5107// SHASX == SHADDSUBX 5108def : MnemonicAlias<"shaddsubx", "shasx">; 5109// SHSAX == SHSUBADDX 5110def : MnemonicAlias<"shsubaddx", "shsax">; 5111// SSAX == SSUBADDX 5112def : MnemonicAlias<"ssubaddx", "ssax">; 5113// UASX == UADDSUBX 5114def : MnemonicAlias<"uaddsubx", "uasx">; 5115// UHASX == UHADDSUBX 5116def : MnemonicAlias<"uhaddsubx", "uhasx">; 5117// UHSAX == UHSUBADDX 5118def : MnemonicAlias<"uhsubaddx", "uhsax">; 5119// UQASX == UQADDSUBX 5120def : MnemonicAlias<"uqaddsubx", "uqasx">; 5121// UQSAX == UQSUBADDX 5122def : MnemonicAlias<"uqsubaddx", "uqsax">; 5123// USAX == USUBADDX 5124def : MnemonicAlias<"usubaddx", "usax">; 5125 5126// "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like 5127// for isel. 5128def : ARMInstAlias<"mov${s}${p} $Rd, $imm", 5129 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>; 5130def : ARMInstAlias<"mvn${s}${p} $Rd, $imm", 5131 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>; 5132// Same for AND <--> BIC 5133def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm", 5134 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm, 5135 pred:$p, cc_out:$s)>; 5136def : ARMInstAlias<"bic${s}${p} $Rdn, $imm", 5137 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm, 5138 pred:$p, cc_out:$s)>; 5139def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm", 5140 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm, 5141 pred:$p, cc_out:$s)>; 5142def : ARMInstAlias<"and${s}${p} $Rdn, $imm", 5143 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm, 5144 pred:$p, cc_out:$s)>; 5145 5146// Likewise, "add Rd, so_imm_neg" -> sub 5147def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm", 5148 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>; 5149def : ARMInstAlias<"add${s}${p} $Rd, $imm", 5150 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>; 5151// Same for CMP <--> CMN via so_imm_neg 5152def : ARMInstAlias<"cmp${p} $Rd, $imm", 5153 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>; 5154def : ARMInstAlias<"cmn${p} $Rd, $imm", 5155 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>; 5156 5157// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 5158// LSR, ROR, and RRX instructions. 5159// FIXME: We need C++ parser hooks to map the alias to the MOV 5160// encoding. It seems we should be able to do that sort of thing 5161// in tblgen, but it could get ugly. 5162let TwoOperandAliasConstraint = "$Rm = $Rd" in { 5163def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 5164 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 5165 cc_out:$s)>; 5166def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 5167 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 5168 cc_out:$s)>; 5169def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 5170 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 5171 cc_out:$s)>; 5172def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 5173 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 5174 cc_out:$s)>; 5175} 5176def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 5177 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>; 5178let TwoOperandAliasConstraint = "$Rn = $Rd" in { 5179def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 5180 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5181 cc_out:$s)>; 5182def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 5183 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5184 cc_out:$s)>; 5185def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 5186 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5187 cc_out:$s)>; 5188def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 5189 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5190 cc_out:$s)>; 5191} 5192 5193// "neg" is and alias for "rsb rd, rn, #0" 5194def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 5195 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 5196 5197// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 5198def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 5199 Requires<[IsARM, NoV6]>; 5200 5201// UMULL/SMULL are available on all arches, but the instruction definitions 5202// need difference constraints pre-v6. Use these aliases for the assembly 5203// parsing on pre-v6. 5204def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5205 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5206 Requires<[IsARM, NoV6]>; 5207def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5208 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5209 Requires<[IsARM, NoV6]>; 5210 5211// 'it' blocks in ARM mode just validate the predicates. The IT itself 5212// is discarded. 5213def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>; 5214