ARMInstrInfo.td revision c1d30212e911d1e55ff6b25bffefb503708883c3
1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// ARM specific DAG Nodes. 16// 17 18// Type profiles. 19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 21 22def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 23 24def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 25 26def SDT_ARMCMov : SDTypeProfile<1, 3, 27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 28 SDTCisVT<3, i32>]>; 29 30def SDT_ARMBrcond : SDTypeProfile<0, 2, 31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 32 33def SDT_ARMBrJT : SDTypeProfile<0, 3, 34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 35 SDTCisVT<2, i32>]>; 36 37def SDT_ARMBr2JT : SDTypeProfile<0, 4, 38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 40 41def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 42 [SDTCisVT<0, i32>, 43 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 44 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 45 SDTCisVT<5, OtherVT>]>; 46 47def SDT_ARMAnd : SDTypeProfile<1, 2, 48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 49 SDTCisVT<2, i32>]>; 50 51def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 52 53def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 55 56def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 57def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 58 SDTCisInt<2>]>; 59def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 60 61def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 62 63def SDT_ARMMEMBARRIER : SDTypeProfile<0, 0, []>; 64def SDT_ARMSYNCBARRIER : SDTypeProfile<0, 0, []>; 65def SDT_ARMMEMBARRIERMCR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 66def SDT_ARMSYNCBARRIERMCR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 67 68def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 69 70def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 72 73// Node definitions. 74def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 75def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>; 76 77def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 78 [SDNPHasChain, SDNPOutFlag]>; 79def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 81 82def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag, 84 SDNPVariadic]>; 85def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 86 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag, 87 SDNPVariadic]>; 88def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 89 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag, 90 SDNPVariadic]>; 91 92def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 93 [SDNPHasChain, SDNPOptInFlag]>; 94 95def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 96 [SDNPInFlag]>; 97def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov, 98 [SDNPInFlag]>; 99 100def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 101 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; 102 103def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 104 [SDNPHasChain]>; 105def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 106 [SDNPHasChain]>; 107 108def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 109 [SDNPHasChain]>; 110 111def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 112 [SDNPOutFlag]>; 113 114def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 115 [SDNPOutFlag, SDNPCommutative]>; 116 117def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 118 119def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>; 120def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>; 121def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>; 122 123def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 124def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 125 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>; 126def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 127 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>; 128def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP", 129 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>; 130 131 132def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER, 133 [SDNPHasChain]>; 134def ARMSyncBarrier : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIER, 135 [SDNPHasChain]>; 136def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIERMCR, 137 [SDNPHasChain]>; 138def ARMSyncBarrierMCR : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERMCR, 139 [SDNPHasChain]>; 140 141def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>; 142 143def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 144 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>; 145 146 147def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 148 149//===----------------------------------------------------------------------===// 150// ARM Instruction Predicate Definitions. 151// 152def HasV4T : Predicate<"Subtarget->hasV4TOps()">; 153def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; 154def HasV5T : Predicate<"Subtarget->hasV5TOps()">; 155def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">; 156def HasV6 : Predicate<"Subtarget->hasV6Ops()">; 157def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">; 158def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; 159def HasV7 : Predicate<"Subtarget->hasV7Ops()">; 160def NoVFP : Predicate<"!Subtarget->hasVFP2()">; 161def HasVFP2 : Predicate<"Subtarget->hasVFP2()">; 162def HasVFP3 : Predicate<"Subtarget->hasVFP3()">; 163def HasNEON : Predicate<"Subtarget->hasNEON()">; 164def HasDivide : Predicate<"Subtarget->hasDivide()">; 165def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">; 166def HasDB : Predicate<"Subtarget->hasDataBarrier()">; 167def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; 168def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; 169def IsThumb : Predicate<"Subtarget->isThumb()">; 170def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; 171def IsThumb2 : Predicate<"Subtarget->isThumb2()">; 172def IsARM : Predicate<"!Subtarget->isThumb()">; 173def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; 174def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; 175 176// FIXME: Eventually this will be just "hasV6T2Ops". 177def UseMovt : Predicate<"Subtarget->useMovt()">; 178def DontUseMovt : Predicate<"!Subtarget->useMovt()">; 179def UseVMLx : Predicate<"Subtarget->useVMLx()">; 180 181//===----------------------------------------------------------------------===// 182// ARM Flag Definitions. 183 184class RegConstraint<string C> { 185 string Constraints = C; 186} 187 188//===----------------------------------------------------------------------===// 189// ARM specific transformation functions and pattern fragments. 190// 191 192// so_imm_neg_XFORM - Return a so_imm value packed into the format described for 193// so_imm_neg def below. 194def so_imm_neg_XFORM : SDNodeXForm<imm, [{ 195 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); 196}]>; 197 198// so_imm_not_XFORM - Return a so_imm value packed into the format described for 199// so_imm_not def below. 200def so_imm_not_XFORM : SDNodeXForm<imm, [{ 201 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32); 202}]>; 203 204/// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15]. 205def imm1_15 : PatLeaf<(i32 imm), [{ 206 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16; 207}]>; 208 209/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 210def imm16_31 : PatLeaf<(i32 imm), [{ 211 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32; 212}]>; 213 214def so_imm_neg : 215 PatLeaf<(imm), [{ 216 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1; 217 }], so_imm_neg_XFORM>; 218 219def so_imm_not : 220 PatLeaf<(imm), [{ 221 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1; 222 }], so_imm_not_XFORM>; 223 224// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 225def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 226 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 227}]>; 228 229/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 230/// e.g., 0xf000ffff 231def bf_inv_mask_imm : Operand<i32>, 232 PatLeaf<(imm), [{ 233 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 234}] > { 235 string EncoderMethod = "getBitfieldInvertedMaskOpValue"; 236 let PrintMethod = "printBitfieldInvMaskImmOperand"; 237} 238 239/// Split a 32-bit immediate into two 16 bit parts. 240def hi16 : SDNodeXForm<imm, [{ 241 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32); 242}]>; 243 244def lo16AllZero : PatLeaf<(i32 imm), [{ 245 // Returns true if all low 16-bits are 0. 246 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 247}], hi16>; 248 249/// imm0_65535 predicate - True if the 32-bit immediate is in the range 250/// [0.65535]. 251def imm0_65535 : PatLeaf<(i32 imm), [{ 252 return (uint32_t)N->getZExtValue() < 65536; 253}]>; 254 255class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 256class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 257 258/// adde and sube predicates - True based on whether the carry flag output 259/// will be needed or not. 260def adde_dead_carry : 261 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS), 262 [{return !N->hasAnyUseOfValue(1);}]>; 263def sube_dead_carry : 264 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS), 265 [{return !N->hasAnyUseOfValue(1);}]>; 266def adde_live_carry : 267 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS), 268 [{return N->hasAnyUseOfValue(1);}]>; 269def sube_live_carry : 270 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS), 271 [{return N->hasAnyUseOfValue(1);}]>; 272 273//===----------------------------------------------------------------------===// 274// Operand Definitions. 275// 276 277// Branch target. 278def brtarget : Operand<OtherVT>; 279 280// A list of registers separated by comma. Used by load/store multiple. 281def reglist : Operand<i32> { 282 let PrintMethod = "printRegisterList"; 283} 284 285// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 286def cpinst_operand : Operand<i32> { 287 let PrintMethod = "printCPInstOperand"; 288} 289 290def jtblock_operand : Operand<i32> { 291 let PrintMethod = "printJTBlockOperand"; 292} 293def jt2block_operand : Operand<i32> { 294 let PrintMethod = "printJT2BlockOperand"; 295} 296 297// Local PC labels. 298def pclabel : Operand<i32> { 299 let PrintMethod = "printPCLabel"; 300} 301 302// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 303def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 304 int32_t v = (int32_t)N->getZExtValue(); 305 return v == 8 || v == 16 || v == 24; }]> { 306 string EncoderMethod = "getRotImmOpValue"; 307} 308 309// shift_imm: An integer that encodes a shift amount and the type of shift 310// (currently either asr or lsl) using the same encoding used for the 311// immediates in so_reg operands. 312def shift_imm : Operand<i32> { 313 let PrintMethod = "printShiftImmOperand"; 314} 315 316// shifter_operand operands: so_reg and so_imm. 317def so_reg : Operand<i32>, // reg reg imm 318 ComplexPattern<i32, 3, "SelectShifterOperandReg", 319 [shl,srl,sra,rotr]> { 320 string EncoderMethod = "getSORegOpValue"; 321 let PrintMethod = "printSORegOperand"; 322 let MIOperandInfo = (ops GPR, GPR, i32imm); 323} 324 325// so_imm - Match a 32-bit shifter_operand immediate operand, which is an 326// 8-bit immediate rotated by an arbitrary number of bits. so_imm values are 327// represented in the imm field in the same 12-bit form that they are encoded 328// into so_imm instructions: the 8-bit immediate is the least significant bits 329// [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11]. 330def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> { 331 string EncoderMethod = "getSOImmOpValue"; 332 let PrintMethod = "printSOImmOperand"; 333} 334 335// Break so_imm's up into two pieces. This handles immediates with up to 16 336// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to 337// get the first/second pieces. 338def so_imm2part : Operand<i32>, 339 PatLeaf<(imm), [{ 340 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 341 }]> { 342 let PrintMethod = "printSOImm2PartOperand"; 343} 344 345def so_imm2part_1 : SDNodeXForm<imm, [{ 346 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue()); 347 return CurDAG->getTargetConstant(V, MVT::i32); 348}]>; 349 350def so_imm2part_2 : SDNodeXForm<imm, [{ 351 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue()); 352 return CurDAG->getTargetConstant(V, MVT::i32); 353}]>; 354 355def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{ 356 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue()); 357 }]> { 358 let PrintMethod = "printSOImm2PartOperand"; 359} 360 361def so_neg_imm2part_1 : SDNodeXForm<imm, [{ 362 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue()); 363 return CurDAG->getTargetConstant(V, MVT::i32); 364}]>; 365 366def so_neg_imm2part_2 : SDNodeXForm<imm, [{ 367 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue()); 368 return CurDAG->getTargetConstant(V, MVT::i32); 369}]>; 370 371/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 372def imm0_31 : Operand<i32>, PatLeaf<(imm), [{ 373 return (int32_t)N->getZExtValue() < 32; 374}]>; 375 376/// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'. 377def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{ 378 return (int32_t)N->getZExtValue() < 32; 379}]> { 380 string EncoderMethod = "getImmMinusOneOpValue"; 381} 382 383// Define ARM specific addressing modes. 384 385 386// addrmode_imm12 := reg +/- imm12 387// 388def addrmode_imm12 : Operand<i32>, 389 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 390 391 string EncoderMethod = "getAddrModeImm12OpValue"; 392 let PrintMethod = "printAddrModeImm12Operand"; 393 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 394} 395// ldst_so_reg := reg +/- reg shop imm 396// 397def ldst_so_reg : Operand<i32>, 398 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 399 // FIXME: Simplify the printer 400 let PrintMethod = "printAddrMode2Operand"; 401 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 402} 403 404// addrmode2 := reg +/- imm12 405// := reg +/- reg shop imm 406// 407def addrmode2 : Operand<i32>, 408 ComplexPattern<i32, 3, "SelectAddrMode2", []> { 409 let PrintMethod = "printAddrMode2Operand"; 410 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 411} 412 413def am2offset : Operand<i32>, 414 ComplexPattern<i32, 2, "SelectAddrMode2Offset", 415 [], [SDNPWantRoot]> { 416 let PrintMethod = "printAddrMode2OffsetOperand"; 417 let MIOperandInfo = (ops GPR, i32imm); 418} 419 420// addrmode3 := reg +/- reg 421// addrmode3 := reg +/- imm8 422// 423def addrmode3 : Operand<i32>, 424 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 425 let PrintMethod = "printAddrMode3Operand"; 426 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 427} 428 429def am3offset : Operand<i32>, 430 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 431 [], [SDNPWantRoot]> { 432 let PrintMethod = "printAddrMode3OffsetOperand"; 433 let MIOperandInfo = (ops GPR, i32imm); 434} 435 436// addrmode4 := reg, <mode|W> 437// 438def addrmode4 : Operand<i32>, 439 ComplexPattern<i32, 2, "SelectAddrMode4", []> { 440 let PrintMethod = "printAddrMode4Operand"; 441 let MIOperandInfo = (ops GPR:$addr, i32imm); 442} 443 444// addrmode5 := reg +/- imm8*4 445// 446def addrmode5 : Operand<i32>, 447 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 448 let PrintMethod = "printAddrMode5Operand"; 449 let MIOperandInfo = (ops GPR:$base, i32imm); 450} 451 452// addrmode6 := reg with optional writeback 453// 454def addrmode6 : Operand<i32>, 455 ComplexPattern<i32, 2, "SelectAddrMode6", []> { 456 let PrintMethod = "printAddrMode6Operand"; 457 let MIOperandInfo = (ops GPR:$addr, i32imm); 458} 459 460def am6offset : Operand<i32> { 461 let PrintMethod = "printAddrMode6OffsetOperand"; 462 let MIOperandInfo = (ops GPR); 463} 464 465// addrmodepc := pc + reg 466// 467def addrmodepc : Operand<i32>, 468 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 469 let PrintMethod = "printAddrModePCOperand"; 470 let MIOperandInfo = (ops GPR, i32imm); 471} 472 473def nohash_imm : Operand<i32> { 474 let PrintMethod = "printNoHashImmediate"; 475} 476 477//===----------------------------------------------------------------------===// 478 479include "ARMInstrFormats.td" 480 481//===----------------------------------------------------------------------===// 482// Multiclass helpers... 483// 484 485/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a 486/// binop that produces a value. 487multiclass AsI1_bin_irs<bits<4> opcod, string opc, 488 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 489 PatFrag opnode, bit Commutable = 0> { 490 // The register-immediate version is re-materializable. This is useful 491 // in particular for taking the address of a local. 492 let isReMaterializable = 1 in { 493 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, 494 iii, opc, "\t$Rd, $Rn, $imm", 495 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> { 496 bits<4> Rd; 497 bits<4> Rn; 498 bits<12> imm; 499 let Inst{25} = 1; 500 let Inst{15-12} = Rd; 501 let Inst{19-16} = Rn; 502 let Inst{11-0} = imm; 503 } 504 } 505 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 506 iir, opc, "\t$Rd, $Rn, $Rm", 507 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> { 508 bits<4> Rd; 509 bits<4> Rn; 510 bits<4> Rm; 511 let Inst{11-4} = 0b00000000; 512 let Inst{25} = 0; 513 let isCommutable = Commutable; 514 let Inst{3-0} = Rm; 515 let Inst{15-12} = Rd; 516 let Inst{19-16} = Rn; 517 } 518 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, 519 iis, opc, "\t$Rd, $Rn, $shift", 520 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> { 521 bits<4> Rd; 522 bits<4> Rn; 523 bits<12> shift; 524 let Inst{25} = 0; 525 let Inst{11-0} = shift; 526 let Inst{15-12} = Rd; 527 let Inst{19-16} = Rn; 528 } 529} 530 531/// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the 532/// instruction modifies the CPSR register. 533let Defs = [CPSR] in { 534multiclass AI1_bin_s_irs<bits<4> opcod, string opc, 535 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 536 PatFrag opnode, bit Commutable = 0> { 537 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, 538 iii, opc, "\t$Rd, $Rn, $imm", 539 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> { 540 bits<4> Rd; 541 bits<4> Rn; 542 bits<12> imm; 543 let Inst{25} = 1; 544 let Inst{15-12} = Rd; 545 let Inst{19-16} = Rn; 546 let Inst{11-0} = imm; 547 let Inst{20} = 1; 548 } 549 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 550 iir, opc, "\t$Rd, $Rn, $Rm", 551 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> { 552 bits<4> Rd; 553 bits<4> Rn; 554 bits<4> Rm; 555 let Inst{11-4} = 0b00000000; 556 let Inst{25} = 0; 557 let isCommutable = Commutable; 558 let Inst{3-0} = Rm; 559 let Inst{15-12} = Rd; 560 let Inst{19-16} = Rn; 561 let Inst{20} = 1; 562 } 563 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, 564 iis, opc, "\t$Rd, $Rn, $shift", 565 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> { 566 bits<4> Rd; 567 bits<4> Rn; 568 bits<12> shift; 569 let Inst{25} = 0; 570 let Inst{11-0} = shift; 571 let Inst{15-12} = Rd; 572 let Inst{19-16} = Rn; 573 let Inst{20} = 1; 574 } 575} 576} 577 578/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 579/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 580/// a explicit result, only implicitly set CPSR. 581let isCompare = 1, Defs = [CPSR] in { 582multiclass AI1_cmp_irs<bits<4> opcod, string opc, 583 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 584 PatFrag opnode, bit Commutable = 0> { 585 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii, 586 opc, "\t$Rn, $imm", 587 [(opnode GPR:$Rn, so_imm:$imm)]> { 588 bits<4> Rn; 589 bits<12> imm; 590 let Inst{25} = 1; 591 let Inst{15-12} = 0b0000; 592 let Inst{19-16} = Rn; 593 let Inst{11-0} = imm; 594 let Inst{20} = 1; 595 let Inst{20} = 1; 596 } 597 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 598 opc, "\t$Rn, $Rm", 599 [(opnode GPR:$Rn, GPR:$Rm)]> { 600 bits<4> Rn; 601 bits<4> Rm; 602 let Inst{11-4} = 0b00000000; 603 let Inst{25} = 0; 604 let isCommutable = Commutable; 605 let Inst{3-0} = Rm; 606 let Inst{15-12} = 0b0000; 607 let Inst{19-16} = Rn; 608 let Inst{20} = 1; 609 } 610 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis, 611 opc, "\t$Rn, $shift", 612 [(opnode GPR:$Rn, so_reg:$shift)]> { 613 bits<4> Rn; 614 bits<12> shift; 615 let Inst{25} = 0; 616 let Inst{11-0} = shift; 617 let Inst{15-12} = 0b0000; 618 let Inst{19-16} = Rn; 619 let Inst{20} = 1; 620 } 621} 622} 623 624/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 625/// register and one whose operand is a register rotated by 8/16/24. 626/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 627multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> { 628 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm), 629 IIC_iEXTr, opc, "\t$Rd, $Rm", 630 [(set GPR:$Rd, (opnode GPR:$Rm))]>, 631 Requires<[IsARM, HasV6]> { 632 bits<4> Rd; 633 bits<4> Rm; 634 let Inst{15-12} = Rd; 635 let Inst{3-0} = Rm; 636 let Inst{11-10} = 0b00; 637 let Inst{19-16} = 0b1111; 638 } 639 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot), 640 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot", 641 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>, 642 Requires<[IsARM, HasV6]> { 643 bits<4> Rd; 644 bits<4> Rm; 645 bits<2> rot; 646 let Inst{15-12} = Rd; 647 let Inst{11-10} = rot; 648 let Inst{3-0} = Rm; 649 let Inst{19-16} = 0b1111; 650 } 651} 652 653multiclass AI_ext_rrot_np<bits<8> opcod, string opc> { 654 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm), 655 IIC_iEXTr, opc, "\t$Rd, $Rm", 656 [/* For disassembly only; pattern left blank */]>, 657 Requires<[IsARM, HasV6]> { 658 let Inst{11-10} = 0b00; 659 let Inst{19-16} = 0b1111; 660 } 661 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot), 662 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot", 663 [/* For disassembly only; pattern left blank */]>, 664 Requires<[IsARM, HasV6]> { 665 bits<2> rot; 666 let Inst{11-10} = rot; 667 let Inst{19-16} = 0b1111; 668 } 669} 670 671/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 672/// register and one whose operand is a register rotated by 8/16/24. 673multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> { 674 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 675 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm", 676 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 677 Requires<[IsARM, HasV6]> { 678 let Inst{11-10} = 0b00; 679 } 680 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, 681 rot_imm:$rot), 682 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot", 683 [(set GPR:$Rd, (opnode GPR:$Rn, 684 (rotr GPR:$Rm, rot_imm:$rot)))]>, 685 Requires<[IsARM, HasV6]> { 686 bits<4> Rn; 687 bits<2> rot; 688 let Inst{19-16} = Rn; 689 let Inst{11-10} = rot; 690 } 691} 692 693// For disassembly only. 694multiclass AI_exta_rrot_np<bits<8> opcod, string opc> { 695 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 696 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm", 697 [/* For disassembly only; pattern left blank */]>, 698 Requires<[IsARM, HasV6]> { 699 let Inst{11-10} = 0b00; 700 } 701 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, 702 rot_imm:$rot), 703 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot", 704 [/* For disassembly only; pattern left blank */]>, 705 Requires<[IsARM, HasV6]> { 706 bits<4> Rn; 707 bits<2> rot; 708 let Inst{19-16} = Rn; 709 let Inst{11-10} = rot; 710 } 711} 712 713/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 714let Uses = [CPSR] in { 715multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, 716 bit Commutable = 0> { 717 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), 718 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 719 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>, 720 Requires<[IsARM]> { 721 bits<4> Rd; 722 bits<4> Rn; 723 bits<12> imm; 724 let Inst{25} = 1; 725 let Inst{15-12} = Rd; 726 let Inst{19-16} = Rn; 727 let Inst{11-0} = imm; 728 } 729 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 730 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 731 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 732 Requires<[IsARM]> { 733 bits<4> Rd; 734 bits<4> Rn; 735 bits<4> Rm; 736 let Inst{11-4} = 0b00000000; 737 let Inst{25} = 0; 738 let isCommutable = Commutable; 739 let Inst{3-0} = Rm; 740 let Inst{15-12} = Rd; 741 let Inst{19-16} = Rn; 742 } 743 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), 744 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 745 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>, 746 Requires<[IsARM]> { 747 bits<4> Rd; 748 bits<4> Rn; 749 bits<12> shift; 750 let Inst{25} = 0; 751 let Inst{11-0} = shift; 752 let Inst{15-12} = Rd; 753 let Inst{19-16} = Rn; 754 } 755} 756// Carry setting variants 757let Defs = [CPSR] in { 758multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode, 759 bit Commutable = 0> { 760 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), 761 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"), 762 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>, 763 Requires<[IsARM]> { 764 bits<4> Rd; 765 bits<4> Rn; 766 bits<12> imm; 767 let Inst{15-12} = Rd; 768 let Inst{19-16} = Rn; 769 let Inst{11-0} = imm; 770 let Inst{20} = 1; 771 let Inst{25} = 1; 772 } 773 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 774 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"), 775 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 776 Requires<[IsARM]> { 777 bits<4> Rd; 778 bits<4> Rn; 779 bits<4> Rm; 780 let Inst{11-4} = 0b00000000; 781 let isCommutable = Commutable; 782 let Inst{3-0} = Rm; 783 let Inst{15-12} = Rd; 784 let Inst{19-16} = Rn; 785 let Inst{20} = 1; 786 let Inst{25} = 0; 787 } 788 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), 789 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"), 790 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>, 791 Requires<[IsARM]> { 792 bits<4> Rd; 793 bits<4> Rn; 794 bits<12> shift; 795 let Inst{11-0} = shift; 796 let Inst{15-12} = Rd; 797 let Inst{19-16} = Rn; 798 let Inst{20} = 1; 799 let Inst{25} = 0; 800 } 801} 802} 803} 804 805let canFoldAsLoad = 1, isReMaterializable = 1 in { 806multiclass AI_ldr1<bit opc22, string opc, InstrItinClass iii, 807 InstrItinClass iir, PatFrag opnode> { 808 // Note: We use the complex addrmode_imm12 rather than just an input 809 // GPR and a constrained immediate so that we can use this to match 810 // frame index references and avoid matching constant pool references. 811 def i12 : AIldr1<0b010, opc22, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 812 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 813 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 814 bits<4> Rt; 815 bits<17> addr; 816 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 817 let Inst{19-16} = addr{16-13}; // Rn 818 let Inst{15-12} = Rt; 819 let Inst{11-0} = addr{11-0}; // imm12 820 } 821 def rs : AIldr1<0b011, opc22, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 822 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 823 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 824 bits<4> Rt; 825 bits<17> shift; 826 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 827 let Inst{19-16} = shift{16-13}; // Rn 828 let Inst{11-0} = shift{11-0}; 829 } 830} 831} 832 833//===----------------------------------------------------------------------===// 834// Instructions 835//===----------------------------------------------------------------------===// 836 837//===----------------------------------------------------------------------===// 838// Miscellaneous Instructions. 839// 840 841/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 842/// the function. The first operand is the ID# for this instruction, the second 843/// is the index into the MachineConstantPool that this is, the third is the 844/// size in bytes of this constant pool entry. 845let neverHasSideEffects = 1, isNotDuplicable = 1 in 846def CONSTPOOL_ENTRY : 847PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 848 i32imm:$size), NoItinerary, "", []>; 849 850// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 851// from removing one half of the matched pairs. That breaks PEI, which assumes 852// these will always be in pairs, and asserts if it finds otherwise. Better way? 853let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 854def ADJCALLSTACKUP : 855PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, "", 856 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 857 858def ADJCALLSTACKDOWN : 859PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, "", 860 [(ARMcallseq_start timm:$amt)]>; 861} 862 863def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", 864 [/* For disassembly only; pattern left blank */]>, 865 Requires<[IsARM, HasV6T2]> { 866 let Inst{27-16} = 0b001100100000; 867 let Inst{15-8} = 0b11110000; 868 let Inst{7-0} = 0b00000000; 869} 870 871def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", 872 [/* For disassembly only; pattern left blank */]>, 873 Requires<[IsARM, HasV6T2]> { 874 let Inst{27-16} = 0b001100100000; 875 let Inst{15-8} = 0b11110000; 876 let Inst{7-0} = 0b00000001; 877} 878 879def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", 880 [/* For disassembly only; pattern left blank */]>, 881 Requires<[IsARM, HasV6T2]> { 882 let Inst{27-16} = 0b001100100000; 883 let Inst{15-8} = 0b11110000; 884 let Inst{7-0} = 0b00000010; 885} 886 887def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", 888 [/* For disassembly only; pattern left blank */]>, 889 Requires<[IsARM, HasV6T2]> { 890 let Inst{27-16} = 0b001100100000; 891 let Inst{15-8} = 0b11110000; 892 let Inst{7-0} = 0b00000011; 893} 894 895def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel", 896 "\t$dst, $a, $b", 897 [/* For disassembly only; pattern left blank */]>, 898 Requires<[IsARM, HasV6]> { 899 bits<4> Rd; 900 bits<4> Rn; 901 bits<4> Rm; 902 let Inst{3-0} = Rm; 903 let Inst{15-12} = Rd; 904 let Inst{19-16} = Rn; 905 let Inst{27-20} = 0b01101000; 906 let Inst{7-4} = 0b1011; 907 let Inst{11-8} = 0b1111; 908} 909 910def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "", 911 [/* For disassembly only; pattern left blank */]>, 912 Requires<[IsARM, HasV6T2]> { 913 let Inst{27-16} = 0b001100100000; 914 let Inst{15-8} = 0b11110000; 915 let Inst{7-0} = 0b00000100; 916} 917 918// The i32imm operand $val can be used by a debugger to store more information 919// about the breakpoint. 920def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val", 921 [/* For disassembly only; pattern left blank */]>, 922 Requires<[IsARM]> { 923 bits<16> val; 924 let Inst{3-0} = val{3-0}; 925 let Inst{19-8} = val{15-4}; 926 let Inst{27-20} = 0b00010010; 927 let Inst{7-4} = 0b0111; 928} 929 930// Change Processor State is a system instruction -- for disassembly only. 931// The singleton $opt operand contains the following information: 932// opt{4-0} = mode from Inst{4-0} 933// opt{5} = changemode from Inst{17} 934// opt{8-6} = AIF from Inst{8-6} 935// opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable 936// FIXME: Integrated assembler will need these split out. 937def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt", 938 [/* For disassembly only; pattern left blank */]>, 939 Requires<[IsARM]> { 940 let Inst{31-28} = 0b1111; 941 let Inst{27-20} = 0b00010000; 942 let Inst{16} = 0; 943 let Inst{5} = 0; 944} 945 946// Preload signals the memory system of possible future data/instruction access. 947// These are for disassembly only. 948// 949// A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0. 950// The neg_zero operand translates -0 to -1, -1 to -2, ..., etc. 951multiclass APreLoad<bit data, bit read, string opc> { 952 953 def i : AXI<(outs), (ins GPR:$base, neg_zero:$imm), MiscFrm, NoItinerary, 954 !strconcat(opc, "\t[$base, $imm]"), []> { 955 let Inst{31-26} = 0b111101; 956 let Inst{25} = 0; // 0 for immediate form 957 let Inst{24} = data; 958 let Inst{22} = read; 959 let Inst{21-20} = 0b01; 960 } 961 962 def r : AXI<(outs), (ins addrmode2:$addr), MiscFrm, NoItinerary, 963 !strconcat(opc, "\t$addr"), []> { 964 let Inst{31-26} = 0b111101; 965 let Inst{25} = 1; // 1 for register form 966 let Inst{24} = data; 967 let Inst{22} = read; 968 let Inst{21-20} = 0b01; 969 let Inst{4} = 0; 970 } 971} 972 973defm PLD : APreLoad<1, 1, "pld">; 974defm PLDW : APreLoad<1, 0, "pldw">; 975defm PLI : APreLoad<0, 1, "pli">; 976 977def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary, 978 "setend\t$end", 979 [/* For disassembly only; pattern left blank */]>, 980 Requires<[IsARM]> { 981 bits<1> end; 982 let Inst{31-10} = 0b1111000100000001000000; 983 let Inst{9} = end; 984 let Inst{8-0} = 0; 985} 986 987def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 988 [/* For disassembly only; pattern left blank */]>, 989 Requires<[IsARM, HasV7]> { 990 bits<4> opt; 991 let Inst{27-4} = 0b001100100000111100001111; 992 let Inst{3-0} = opt; 993} 994 995// A5.4 Permanently UNDEFINED instructions. 996let isBarrier = 1, isTerminator = 1 in 997def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 998 "trap", [(trap)]>, 999 Requires<[IsARM]> { 1000 let Inst{27-25} = 0b011; 1001 let Inst{24-20} = 0b11111; 1002 let Inst{7-5} = 0b111; 1003 let Inst{4} = 0b1; 1004} 1005 1006// Address computation and loads and stores in PIC mode. 1007// FIXME: These PIC insn patterns are pseudos, but derive from the normal insn 1008// classes (AXI1, et.al.) and so have encoding information and such, 1009// which is suboptimal. Once the rest of the code emitter (including 1010// JIT) is MC-ized we should look at refactoring these into true 1011// pseudos. 1012let isNotDuplicable = 1 in { 1013def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 1014 Pseudo, IIC_iALUr, "", 1015 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; 1016 1017let AddedComplexity = 10 in { 1018def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 1019 Pseudo, IIC_iLoad_r, "", 1020 [(set GPR:$dst, (load addrmodepc:$addr))]>; 1021 1022def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 1023 Pseudo, IIC_iLoad_bh_r, "", 1024 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>; 1025 1026def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 1027 Pseudo, IIC_iLoad_bh_r, "", 1028 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>; 1029 1030def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 1031 Pseudo, IIC_iLoad_bh_r, "", 1032 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>; 1033 1034def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 1035 Pseudo, IIC_iLoad_bh_r, "", 1036 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>; 1037} 1038let AddedComplexity = 10 in { 1039def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 1040 Pseudo, IIC_iStore_r, "", 1041 [(store GPR:$src, addrmodepc:$addr)]>; 1042 1043def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 1044 Pseudo, IIC_iStore_bh_r, "", 1045 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>; 1046 1047def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 1048 Pseudo, IIC_iStore_bh_r, "", 1049 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 1050} 1051} // isNotDuplicable = 1 1052 1053 1054// LEApcrel - Load a pc-relative address into a register without offending the 1055// assembler. 1056// FIXME: These are marked as pseudos, but they're really not(?). They're just 1057// the ADR instruction. Is this the right way to handle that? They need 1058// encoding information regardless. 1059let neverHasSideEffects = 1 in { 1060let isReMaterializable = 1 in 1061def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), 1062 Pseudo, IIC_iALUi, 1063 "adr$p\t$dst, #$label", []>; 1064 1065} // neverHasSideEffects 1066def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), 1067 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1068 Pseudo, IIC_iALUi, 1069 "adr$p\t$dst, #${label}_${id}", []> { 1070 let Inst{25} = 1; 1071} 1072 1073//===----------------------------------------------------------------------===// 1074// Control Flow Instructions. 1075// 1076 1077let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 1078 // ARMV4T and above 1079 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 1080 "bx", "\tlr", [(ARMretflag)]>, 1081 Requires<[IsARM, HasV4T]> { 1082 let Inst{27-0} = 0b0001001011111111111100011110; 1083 } 1084 1085 // ARMV4 only 1086 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 1087 "mov", "\tpc, lr", [(ARMretflag)]>, 1088 Requires<[IsARM, NoV4T]> { 1089 let Inst{27-0} = 0b0001101000001111000000001110; 1090 } 1091} 1092 1093// Indirect branches 1094let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1095 // ARMV4T and above 1096 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 1097 [(brind GPR:$dst)]>, 1098 Requires<[IsARM, HasV4T]> { 1099 bits<4> dst; 1100 let Inst{31-4} = 0b1110000100101111111111110001; 1101 let Inst{3-0} = dst; 1102 } 1103 1104 // ARMV4 only 1105 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst", 1106 [(brind GPR:$dst)]>, 1107 Requires<[IsARM, NoV4T]> { 1108 bits<4> dst; 1109 let Inst{31-4} = 0b1110000110100000111100000000; 1110 let Inst{3-0} = dst; 1111 } 1112} 1113 1114// FIXME: remove when we have a way to marking a MI with these properties. 1115// FIXME: Should pc be an implicit operand like PICADD, etc? 1116let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1117 hasExtraDefRegAllocReq = 1 in 1118 def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, 1119 reglist:$dsts, variable_ops), 1120 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr, 1121 "ldm${addr:submode}${p}\t$addr!, $dsts", 1122 "$addr.addr = $wb", []>; 1123 1124// On non-Darwin platforms R9 is callee-saved. 1125let isCall = 1, 1126 Defs = [R0, R1, R2, R3, R12, LR, 1127 D0, D1, D2, D3, D4, D5, D6, D7, 1128 D16, D17, D18, D19, D20, D21, D22, D23, 1129 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { 1130 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), 1131 IIC_Br, "bl\t$func", 1132 [(ARMcall tglobaladdr:$func)]>, 1133 Requires<[IsARM, IsNotDarwin]> { 1134 let Inst{31-28} = 0b1110; 1135 // FIXME: Encoding info for $func. Needs fixups bits. 1136 } 1137 1138 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops), 1139 IIC_Br, "bl", "\t$func", 1140 [(ARMcall_pred tglobaladdr:$func)]>, 1141 Requires<[IsARM, IsNotDarwin]>; 1142 1143 // ARMv5T and above 1144 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, 1145 IIC_Br, "blx\t$func", 1146 [(ARMcall GPR:$func)]>, 1147 Requires<[IsARM, HasV5T, IsNotDarwin]> { 1148 bits<4> func; 1149 let Inst{27-4} = 0b000100101111111111110011; 1150 let Inst{3-0} = func; 1151 } 1152 1153 // ARMv4T 1154 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 1155 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops), 1156 IIC_Br, "mov\tlr, pc\n\tbx\t$func", 1157 [(ARMcall_nolink tGPR:$func)]>, 1158 Requires<[IsARM, HasV4T, IsNotDarwin]> { 1159 bits<4> func; 1160 let Inst{27-4} = 0b000100101111111111110001; 1161 let Inst{3-0} = func; 1162 } 1163 1164 // ARMv4 1165 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops), 1166 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func", 1167 [(ARMcall_nolink tGPR:$func)]>, 1168 Requires<[IsARM, NoV4T, IsNotDarwin]> { 1169 bits<4> func; 1170 let Inst{27-4} = 0b000110100000111100000000; 1171 let Inst{3-0} = func; 1172 } 1173} 1174 1175// On Darwin R9 is call-clobbered. 1176let isCall = 1, 1177 Defs = [R0, R1, R2, R3, R9, R12, LR, 1178 D0, D1, D2, D3, D4, D5, D6, D7, 1179 D16, D17, D18, D19, D20, D21, D22, D23, 1180 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { 1181 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), 1182 IIC_Br, "bl\t$func", 1183 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> { 1184 let Inst{31-28} = 0b1110; 1185 // FIXME: Encoding info for $func. Needs fixups bits. 1186 } 1187 1188 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops), 1189 IIC_Br, "bl", "\t$func", 1190 [(ARMcall_pred tglobaladdr:$func)]>, 1191 Requires<[IsARM, IsDarwin]>; 1192 1193 // ARMv5T and above 1194 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, 1195 IIC_Br, "blx\t$func", 1196 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> { 1197 bits<4> func; 1198 let Inst{27-4} = 0b000100101111111111110011; 1199 let Inst{3-0} = func; 1200 } 1201 1202 // ARMv4T 1203 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 1204 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops), 1205 IIC_Br, "mov\tlr, pc\n\tbx\t$func", 1206 [(ARMcall_nolink tGPR:$func)]>, 1207 Requires<[IsARM, HasV4T, IsDarwin]> { 1208 bits<4> func; 1209 let Inst{27-4} = 0b000100101111111111110001; 1210 let Inst{3-0} = func; 1211 } 1212 1213 // ARMv4 1214 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops), 1215 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func", 1216 [(ARMcall_nolink tGPR:$func)]>, 1217 Requires<[IsARM, NoV4T, IsDarwin]> { 1218 bits<4> func; 1219 let Inst{27-4} = 0b000110100000111100000000; 1220 let Inst{3-0} = func; 1221 } 1222} 1223 1224// Tail calls. 1225 1226// FIXME: These should probably be xformed into the non-TC versions of the 1227// instructions as part of MC lowering. 1228let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 1229 // Darwin versions. 1230 let Defs = [R0, R1, R2, R3, R9, R12, 1231 D0, D1, D2, D3, D4, D5, D6, D7, 1232 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, 1233 D27, D28, D29, D30, D31, PC], 1234 Uses = [SP] in { 1235 def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops), 1236 Pseudo, IIC_Br, 1237 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>; 1238 1239 def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops), 1240 Pseudo, IIC_Br, 1241 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>; 1242 1243 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops), 1244 IIC_Br, "b\t$dst @ TAILCALL", 1245 []>, Requires<[IsDarwin]>; 1246 1247 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops), 1248 IIC_Br, "b.w\t$dst @ TAILCALL", 1249 []>, Requires<[IsDarwin]>; 1250 1251 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops), 1252 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL", 1253 []>, Requires<[IsDarwin]> { 1254 bits<4> dst; 1255 let Inst{31-4} = 0b1110000100101111111111110001; 1256 let Inst{3-0} = dst; 1257 } 1258 } 1259 1260 // Non-Darwin versions (the difference is R9). 1261 let Defs = [R0, R1, R2, R3, R12, 1262 D0, D1, D2, D3, D4, D5, D6, D7, 1263 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, 1264 D27, D28, D29, D30, D31, PC], 1265 Uses = [SP] in { 1266 def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops), 1267 Pseudo, IIC_Br, 1268 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>; 1269 1270 def TCRETURNriND : AInoP<(outs), (ins tcGPR:$dst, variable_ops), 1271 Pseudo, IIC_Br, 1272 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>; 1273 1274 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops), 1275 IIC_Br, "b\t$dst @ TAILCALL", 1276 []>, Requires<[IsARM, IsNotDarwin]>; 1277 1278 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops), 1279 IIC_Br, "b.w\t$dst @ TAILCALL", 1280 []>, Requires<[IsThumb, IsNotDarwin]>; 1281 1282 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops), 1283 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL", 1284 []>, Requires<[IsNotDarwin]> { 1285 bits<4> dst; 1286 let Inst{31-4} = 0b1110000100101111111111110001; 1287 let Inst{3-0} = dst; 1288 } 1289 } 1290} 1291 1292let isBranch = 1, isTerminator = 1 in { 1293 // B is "predicable" since it can be xformed into a Bcc. 1294 let isBarrier = 1 in { 1295 let isPredicable = 1 in 1296 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br, 1297 "b\t$target", [(br bb:$target)]>; 1298 1299 let isNotDuplicable = 1, isIndirectBranch = 1 in { 1300 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), 1301 IIC_Br, "mov\tpc, $target$jt", 1302 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> { 1303 let Inst{11-4} = 0b00000000; 1304 let Inst{15-12} = 0b1111; 1305 let Inst{20} = 0; // S Bit 1306 let Inst{24-21} = 0b1101; 1307 let Inst{27-25} = 0b000; 1308 } 1309 def BR_JTm : JTI<(outs), 1310 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id), 1311 IIC_Br, "ldr\tpc, $target$jt", 1312 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, 1313 imm:$id)]> { 1314 let Inst{15-12} = 0b1111; 1315 let Inst{20} = 1; // L bit 1316 let Inst{21} = 0; // W bit 1317 let Inst{22} = 0; // B bit 1318 let Inst{24} = 1; // P bit 1319 let Inst{27-25} = 0b011; 1320 } 1321 def BR_JTadd : JTI<(outs), 1322 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id), 1323 IIC_Br, "add\tpc, $target, $idx$jt", 1324 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, 1325 imm:$id)]> { 1326 let Inst{15-12} = 0b1111; 1327 let Inst{20} = 0; // S bit 1328 let Inst{24-21} = 0b0100; 1329 let Inst{27-25} = 0b000; 1330 } 1331 } // isNotDuplicable = 1, isIndirectBranch = 1 1332 } // isBarrier = 1 1333 1334 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 1335 // a two-value operand where a dag node expects two operands. :( 1336 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target), 1337 IIC_Br, "b", "\t$target", 1338 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>; 1339} 1340 1341// Branch and Exchange Jazelle -- for disassembly only 1342def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 1343 [/* For disassembly only; pattern left blank */]> { 1344 let Inst{23-20} = 0b0010; 1345 //let Inst{19-8} = 0xfff; 1346 let Inst{7-4} = 0b0010; 1347} 1348 1349// Secure Monitor Call is a system instruction -- for disassembly only 1350def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt", 1351 [/* For disassembly only; pattern left blank */]> { 1352 bits<4> opt; 1353 let Inst{23-4} = 0b01100000000000000111; 1354 let Inst{3-0} = opt; 1355} 1356 1357// Supervisor Call (Software Interrupt) -- for disassembly only 1358let isCall = 1 in { 1359def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc", 1360 [/* For disassembly only; pattern left blank */]> { 1361 bits<24> svc; 1362 let Inst{23-0} = svc; 1363} 1364} 1365 1366// Store Return State is a system instruction -- for disassembly only 1367def SRSW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode), 1368 NoItinerary, "srs${addr:submode}\tsp!, $mode", 1369 [/* For disassembly only; pattern left blank */]> { 1370 let Inst{31-28} = 0b1111; 1371 let Inst{22-20} = 0b110; // W = 1 1372} 1373 1374def SRS : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode), 1375 NoItinerary, "srs${addr:submode}\tsp, $mode", 1376 [/* For disassembly only; pattern left blank */]> { 1377 let Inst{31-28} = 0b1111; 1378 let Inst{22-20} = 0b100; // W = 0 1379} 1380 1381// Return From Exception is a system instruction -- for disassembly only 1382def RFEW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base), 1383 NoItinerary, "rfe${addr:submode}\t$base!", 1384 [/* For disassembly only; pattern left blank */]> { 1385 let Inst{31-28} = 0b1111; 1386 let Inst{22-20} = 0b011; // W = 1 1387} 1388 1389def RFE : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base), 1390 NoItinerary, "rfe${addr:submode}\t$base", 1391 [/* For disassembly only; pattern left blank */]> { 1392 let Inst{31-28} = 0b1111; 1393 let Inst{22-20} = 0b001; // W = 0 1394} 1395 1396//===----------------------------------------------------------------------===// 1397// Load / store Instructions. 1398// 1399 1400// Load 1401 1402 1403defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_i, IIC_iLoad_r, 1404 UnOpFrag<(load node:$Src)>>; 1405defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_r, 1406 UnOpFrag<(zextloadi8 node:$Src)>>; 1407 1408// Special LDR for loads from non-pc-relative constpools. 1409let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1, 1410 isReMaterializable = 1 in 1411def LDRcp : AIldr1<0b010, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1412 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", []> { 1413 bits<4> Rt; 1414 bits<17> addr; 1415 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1416 let Inst{19-16} = 0b1111; 1417 let Inst{15-12} = Rt; 1418 let Inst{11-0} = addr{11-0}; // imm12 1419} 1420 1421// Loads with zero extension 1422def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, 1423 IIC_iLoad_bh_r, "ldrh", "\t$dst, $addr", 1424 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>; 1425 1426// Loads with sign extension 1427def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, 1428 IIC_iLoad_bh_r, "ldrsh", "\t$dst, $addr", 1429 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>; 1430 1431def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, 1432 IIC_iLoad_bh_r, "ldrsb", "\t$dst, $addr", 1433 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>; 1434 1435let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { 1436// Load doubleword 1437def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm, 1438 IIC_iLoad_d_r, "ldrd", "\t$dst1, $addr", 1439 []>, Requires<[IsARM, HasV5TE]>; 1440 1441// Indexed loads 1442def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb), 1443 (ins addrmode2:$addr), LdFrm, IIC_iLoad_ru, 1444 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>; 1445 1446def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb), 1447 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru, 1448 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>; 1449 1450def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb), 1451 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru, 1452 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>; 1453 1454def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb), 1455 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru, 1456 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>; 1457 1458def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb), 1459 (ins addrmode2:$addr), LdFrm, IIC_iLoad_bh_ru, 1460 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>; 1461 1462def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb), 1463 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru, 1464 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>; 1465 1466def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb), 1467 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru, 1468 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>; 1469 1470def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb), 1471 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru, 1472 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>; 1473 1474def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb), 1475 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru, 1476 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>; 1477 1478def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb), 1479 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_ru, 1480 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>; 1481 1482// For disassembly only 1483def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb), 1484 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_d_ru, 1485 "ldrd", "\t$dst1, $dst2, $addr!", "$addr.base = $base_wb", []>, 1486 Requires<[IsARM, HasV5TE]>; 1487 1488// For disassembly only 1489def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb), 1490 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_d_ru, 1491 "ldrd", "\t$dst1, $dst2, [$base], $offset", "$base = $base_wb", []>, 1492 Requires<[IsARM, HasV5TE]>; 1493 1494} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 1495 1496// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only. 1497 1498def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb), 1499 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru, 1500 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> { 1501 let Inst{21} = 1; // overwrite 1502} 1503 1504def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb), 1505 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru, 1506 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> { 1507 let Inst{21} = 1; // overwrite 1508} 1509 1510def LDRSBT : AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb), 1511 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru, 1512 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> { 1513 let Inst{21} = 1; // overwrite 1514} 1515 1516def LDRHT : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb), 1517 (ins GPR:$base, am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru, 1518 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> { 1519 let Inst{21} = 1; // overwrite 1520} 1521 1522def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb), 1523 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru, 1524 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> { 1525 let Inst{21} = 1; // overwrite 1526} 1527 1528// Store 1529def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStore_r, 1530 "str", "\t$src, $addr", 1531 [(store GPR:$src, addrmode2:$addr)]>; 1532 1533// Stores with truncate 1534def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, 1535 IIC_iStore_bh_r, "strh", "\t$src, $addr", 1536 [(truncstorei16 GPR:$src, addrmode3:$addr)]>; 1537 1538def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, 1539 IIC_iStore_bh_r, "strb", "\t$src, $addr", 1540 [(truncstorei8 GPR:$src, addrmode2:$addr)]>; 1541 1542// Store doubleword 1543let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in 1544def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr), 1545 StMiscFrm, IIC_iStore_d_r, 1546 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>; 1547 1548// Indexed stores 1549def STR_PRE : AI2stwpr<(outs GPR:$base_wb), 1550 (ins GPR:$src, GPR:$base, am2offset:$offset), 1551 StFrm, IIC_iStore_ru, 1552 "str", "\t$src, [$base, $offset]!", "$base = $base_wb", 1553 [(set GPR:$base_wb, 1554 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>; 1555 1556def STR_POST : AI2stwpo<(outs GPR:$base_wb), 1557 (ins GPR:$src, GPR:$base,am2offset:$offset), 1558 StFrm, IIC_iStore_ru, 1559 "str", "\t$src, [$base], $offset", "$base = $base_wb", 1560 [(set GPR:$base_wb, 1561 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>; 1562 1563def STRH_PRE : AI3sthpr<(outs GPR:$base_wb), 1564 (ins GPR:$src, GPR:$base,am3offset:$offset), 1565 StMiscFrm, IIC_iStore_ru, 1566 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb", 1567 [(set GPR:$base_wb, 1568 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>; 1569 1570def STRH_POST: AI3sthpo<(outs GPR:$base_wb), 1571 (ins GPR:$src, GPR:$base,am3offset:$offset), 1572 StMiscFrm, IIC_iStore_bh_ru, 1573 "strh", "\t$src, [$base], $offset", "$base = $base_wb", 1574 [(set GPR:$base_wb, (post_truncsti16 GPR:$src, 1575 GPR:$base, am3offset:$offset))]>; 1576 1577def STRB_PRE : AI2stbpr<(outs GPR:$base_wb), 1578 (ins GPR:$src, GPR:$base,am2offset:$offset), 1579 StFrm, IIC_iStore_bh_ru, 1580 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb", 1581 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src, 1582 GPR:$base, am2offset:$offset))]>; 1583 1584def STRB_POST: AI2stbpo<(outs GPR:$base_wb), 1585 (ins GPR:$src, GPR:$base,am2offset:$offset), 1586 StFrm, IIC_iStore_bh_ru, 1587 "strb", "\t$src, [$base], $offset", "$base = $base_wb", 1588 [(set GPR:$base_wb, (post_truncsti8 GPR:$src, 1589 GPR:$base, am2offset:$offset))]>; 1590 1591// For disassembly only 1592def STRD_PRE : AI3stdpr<(outs GPR:$base_wb), 1593 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset), 1594 StMiscFrm, IIC_iStore_d_ru, 1595 "strd", "\t$src1, $src2, [$base, $offset]!", 1596 "$base = $base_wb", []>; 1597 1598// For disassembly only 1599def STRD_POST: AI3stdpo<(outs GPR:$base_wb), 1600 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset), 1601 StMiscFrm, IIC_iStore_d_ru, 1602 "strd", "\t$src1, $src2, [$base], $offset", 1603 "$base = $base_wb", []>; 1604 1605// STRT, STRBT, and STRHT are for disassembly only. 1606 1607def STRT : AI2stwpo<(outs GPR:$base_wb), 1608 (ins GPR:$src, GPR:$base,am2offset:$offset), 1609 StFrm, IIC_iStore_ru, 1610 "strt", "\t$src, [$base], $offset", "$base = $base_wb", 1611 [/* For disassembly only; pattern left blank */]> { 1612 let Inst{21} = 1; // overwrite 1613} 1614 1615def STRBT : AI2stbpo<(outs GPR:$base_wb), 1616 (ins GPR:$src, GPR:$base,am2offset:$offset), 1617 StFrm, IIC_iStore_bh_ru, 1618 "strbt", "\t$src, [$base], $offset", "$base = $base_wb", 1619 [/* For disassembly only; pattern left blank */]> { 1620 let Inst{21} = 1; // overwrite 1621} 1622 1623def STRHT: AI3sthpo<(outs GPR:$base_wb), 1624 (ins GPR:$src, GPR:$base,am3offset:$offset), 1625 StMiscFrm, IIC_iStore_bh_ru, 1626 "strht", "\t$src, [$base], $offset", "$base = $base_wb", 1627 [/* For disassembly only; pattern left blank */]> { 1628 let Inst{21} = 1; // overwrite 1629} 1630 1631//===----------------------------------------------------------------------===// 1632// Load / store multiple Instructions. 1633// 1634 1635let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { 1636def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, 1637 reglist:$dsts, variable_ops), 1638 IndexModeNone, LdStMulFrm, IIC_iLoad_m, 1639 "ldm${addr:submode}${p}\t$addr, $dsts", "", []>; 1640 1641def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, 1642 reglist:$dsts, variable_ops), 1643 IndexModeUpd, LdStMulFrm, IIC_iLoad_mu, 1644 "ldm${addr:submode}${p}\t$addr!, $dsts", 1645 "$addr.addr = $wb", []>; 1646} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq 1647 1648let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { 1649def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p, 1650 reglist:$srcs, variable_ops), 1651 IndexModeNone, LdStMulFrm, IIC_iStore_m, 1652 "stm${addr:submode}${p}\t$addr, $srcs", "", []>; 1653 1654def STM_UPD : AXI4st<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, 1655 reglist:$srcs, variable_ops), 1656 IndexModeUpd, LdStMulFrm, IIC_iStore_mu, 1657 "stm${addr:submode}${p}\t$addr!, $srcs", 1658 "$addr.addr = $wb", []>; 1659} // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq 1660 1661//===----------------------------------------------------------------------===// 1662// Move Instructions. 1663// 1664 1665let neverHasSideEffects = 1 in 1666def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 1667 "mov", "\t$Rd, $Rm", []>, UnaryDP { 1668 bits<4> Rd; 1669 bits<4> Rm; 1670 1671 let Inst{11-4} = 0b00000000; 1672 let Inst{25} = 0; 1673 let Inst{3-0} = Rm; 1674 let Inst{15-12} = Rd; 1675} 1676 1677// A version for the smaller set of tail call registers. 1678let neverHasSideEffects = 1 in 1679def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 1680 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP { 1681 bits<4> Rd; 1682 bits<4> Rm; 1683 1684 let Inst{11-4} = 0b00000000; 1685 let Inst{25} = 0; 1686 let Inst{3-0} = Rm; 1687 let Inst{15-12} = Rd; 1688} 1689 1690def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins so_reg:$src), 1691 DPSoRegFrm, IIC_iMOVsr, 1692 "mov", "\t$Rd, $src", [(set GPR:$Rd, so_reg:$src)]>, UnaryDP { 1693 bits<4> Rd; 1694 bits<12> src; 1695 let Inst{15-12} = Rd; 1696 let Inst{11-0} = src; 1697 let Inst{25} = 0; 1698} 1699 1700let isReMaterializable = 1, isAsCheapAsAMove = 1 in 1701def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi, 1702 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP { 1703 bits<4> Rd; 1704 bits<12> imm; 1705 let Inst{25} = 1; 1706 let Inst{15-12} = Rd; 1707 let Inst{19-16} = 0b0000; 1708 let Inst{11-0} = imm; 1709} 1710 1711let isReMaterializable = 1, isAsCheapAsAMove = 1 in 1712def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm:$imm), 1713 DPFrm, IIC_iMOVi, 1714 "movw", "\t$Rd, $imm", 1715 [(set GPR:$Rd, imm0_65535:$imm)]>, 1716 Requires<[IsARM, HasV6T2]>, UnaryDP { 1717 bits<4> Rd; 1718 bits<16> imm; 1719 let Inst{15-12} = Rd; 1720 let Inst{11-0} = imm{11-0}; 1721 let Inst{19-16} = imm{15-12}; 1722 let Inst{20} = 0; 1723 let Inst{25} = 1; 1724} 1725 1726let Constraints = "$src = $Rd" in 1727def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm:$imm), 1728 DPFrm, IIC_iMOVi, 1729 "movt", "\t$Rd, $imm", 1730 [(set GPR:$Rd, 1731 (or (and GPR:$src, 0xffff), 1732 lo16AllZero:$imm))]>, UnaryDP, 1733 Requires<[IsARM, HasV6T2]> { 1734 bits<4> Rd; 1735 bits<16> imm; 1736 let Inst{15-12} = Rd; 1737 let Inst{11-0} = imm{11-0}; 1738 let Inst{19-16} = imm{15-12}; 1739 let Inst{20} = 0; 1740 let Inst{25} = 1; 1741} 1742 1743def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 1744 Requires<[IsARM, HasV6T2]>; 1745 1746let Uses = [CPSR] in 1747def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, "", 1748 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 1749 Requires<[IsARM]>; 1750 1751// These aren't really mov instructions, but we have to define them this way 1752// due to flag operands. 1753 1754let Defs = [CPSR] in { 1755def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, "", 1756 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 1757 Requires<[IsARM]>; 1758def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, "", 1759 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 1760 Requires<[IsARM]>; 1761} 1762 1763//===----------------------------------------------------------------------===// 1764// Extend Instructions. 1765// 1766 1767// Sign extenders 1768 1769defm SXTB : AI_ext_rrot<0b01101010, 1770 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 1771defm SXTH : AI_ext_rrot<0b01101011, 1772 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 1773 1774defm SXTAB : AI_exta_rrot<0b01101010, 1775 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 1776defm SXTAH : AI_exta_rrot<0b01101011, 1777 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 1778 1779// For disassembly only 1780defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 1781 1782// For disassembly only 1783defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 1784 1785// Zero extenders 1786 1787let AddedComplexity = 16 in { 1788defm UXTB : AI_ext_rrot<0b01101110, 1789 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 1790defm UXTH : AI_ext_rrot<0b01101111, 1791 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 1792defm UXTB16 : AI_ext_rrot<0b01101100, 1793 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 1794 1795// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 1796// The transformation should probably be done as a combiner action 1797// instead so we can include a check for masking back in the upper 1798// eight bits of the source into the lower eight bits of the result. 1799//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 1800// (UXTB16r_rot GPR:$Src, 24)>; 1801def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 1802 (UXTB16r_rot GPR:$Src, 8)>; 1803 1804defm UXTAB : AI_exta_rrot<0b01101110, "uxtab", 1805 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 1806defm UXTAH : AI_exta_rrot<0b01101111, "uxtah", 1807 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 1808} 1809 1810// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 1811// For disassembly only 1812defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 1813 1814 1815def SBFX : I<(outs GPR:$Rd), 1816 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width), 1817 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi, 1818 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 1819 Requires<[IsARM, HasV6T2]> { 1820 bits<4> Rd; 1821 bits<4> Rn; 1822 bits<5> lsb; 1823 bits<5> width; 1824 let Inst{27-21} = 0b0111101; 1825 let Inst{6-4} = 0b101; 1826 let Inst{20-16} = width; 1827 let Inst{15-12} = Rd; 1828 let Inst{11-7} = lsb; 1829 let Inst{3-0} = Rn; 1830} 1831 1832def UBFX : I<(outs GPR:$Rd), 1833 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width), 1834 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi, 1835 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 1836 Requires<[IsARM, HasV6T2]> { 1837 bits<4> Rd; 1838 bits<4> Rn; 1839 bits<5> lsb; 1840 bits<5> width; 1841 let Inst{27-21} = 0b0111111; 1842 let Inst{6-4} = 0b101; 1843 let Inst{20-16} = width; 1844 let Inst{15-12} = Rd; 1845 let Inst{11-7} = lsb; 1846 let Inst{3-0} = Rn; 1847} 1848 1849//===----------------------------------------------------------------------===// 1850// Arithmetic Instructions. 1851// 1852 1853defm ADD : AsI1_bin_irs<0b0100, "add", 1854 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 1855 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 1856defm SUB : AsI1_bin_irs<0b0010, "sub", 1857 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 1858 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 1859 1860// ADD and SUB with 's' bit set. 1861defm ADDS : AI1_bin_s_irs<0b0100, "adds", 1862 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 1863 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>; 1864defm SUBS : AI1_bin_s_irs<0b0010, "subs", 1865 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 1866 BinOpFrag<(subc node:$LHS, node:$RHS)>>; 1867 1868defm ADC : AI1_adde_sube_irs<0b0101, "adc", 1869 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>; 1870defm SBC : AI1_adde_sube_irs<0b0110, "sbc", 1871 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>; 1872defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs", 1873 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>; 1874defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs", 1875 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>; 1876 1877def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, 1878 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm", 1879 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> { 1880 bits<4> Rd; 1881 bits<4> Rn; 1882 bits<12> imm; 1883 let Inst{25} = 1; 1884 let Inst{15-12} = Rd; 1885 let Inst{19-16} = Rn; 1886 let Inst{11-0} = imm; 1887} 1888 1889// The reg/reg form is only defined for the disassembler; for codegen it is 1890// equivalent to SUBrr. 1891def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1892 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm", 1893 [/* For disassembly only; pattern left blank */]> { 1894 bits<4> Rd; 1895 bits<4> Rn; 1896 bits<4> Rm; 1897 let Inst{11-4} = 0b00000000; 1898 let Inst{25} = 0; 1899 let Inst{3-0} = Rm; 1900 let Inst{15-12} = Rd; 1901 let Inst{19-16} = Rn; 1902} 1903 1904def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), 1905 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift", 1906 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> { 1907 bits<4> Rd; 1908 bits<4> Rn; 1909 bits<12> shift; 1910 let Inst{25} = 0; 1911 let Inst{11-0} = shift; 1912 let Inst{15-12} = Rd; 1913 let Inst{19-16} = Rn; 1914} 1915 1916// RSB with 's' bit set. 1917let Defs = [CPSR] in { 1918def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, 1919 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm", 1920 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> { 1921 bits<4> Rd; 1922 bits<4> Rn; 1923 bits<12> imm; 1924 let Inst{25} = 1; 1925 let Inst{20} = 1; 1926 let Inst{15-12} = Rd; 1927 let Inst{19-16} = Rn; 1928 let Inst{11-0} = imm; 1929} 1930def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), 1931 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift", 1932 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> { 1933 bits<4> Rd; 1934 bits<4> Rn; 1935 bits<12> shift; 1936 let Inst{25} = 0; 1937 let Inst{20} = 1; 1938 let Inst{11-0} = shift; 1939 let Inst{15-12} = Rd; 1940 let Inst{19-16} = Rn; 1941} 1942} 1943 1944let Uses = [CPSR] in { 1945def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), 1946 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm", 1947 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>, 1948 Requires<[IsARM]> { 1949 bits<4> Rd; 1950 bits<4> Rn; 1951 bits<12> imm; 1952 let Inst{25} = 1; 1953 let Inst{15-12} = Rd; 1954 let Inst{19-16} = Rn; 1955 let Inst{11-0} = imm; 1956} 1957// The reg/reg form is only defined for the disassembler; for codegen it is 1958// equivalent to SUBrr. 1959def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1960 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm", 1961 [/* For disassembly only; pattern left blank */]> { 1962 bits<4> Rd; 1963 bits<4> Rn; 1964 bits<4> Rm; 1965 let Inst{11-4} = 0b00000000; 1966 let Inst{25} = 0; 1967 let Inst{3-0} = Rm; 1968 let Inst{15-12} = Rd; 1969 let Inst{19-16} = Rn; 1970} 1971def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), 1972 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift", 1973 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>, 1974 Requires<[IsARM]> { 1975 bits<4> Rd; 1976 bits<4> Rn; 1977 bits<12> shift; 1978 let Inst{25} = 0; 1979 let Inst{11-0} = shift; 1980 let Inst{15-12} = Rd; 1981 let Inst{19-16} = Rn; 1982} 1983} 1984 1985// FIXME: Allow these to be predicated. 1986let Defs = [CPSR], Uses = [CPSR] in { 1987def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), 1988 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm", 1989 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>, 1990 Requires<[IsARM]> { 1991 bits<4> Rd; 1992 bits<4> Rn; 1993 bits<12> imm; 1994 let Inst{25} = 1; 1995 let Inst{20} = 1; 1996 let Inst{15-12} = Rd; 1997 let Inst{19-16} = Rn; 1998 let Inst{11-0} = imm; 1999} 2000def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), 2001 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift", 2002 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>, 2003 Requires<[IsARM]> { 2004 bits<4> Rd; 2005 bits<4> Rn; 2006 bits<12> shift; 2007 let Inst{25} = 0; 2008 let Inst{20} = 1; 2009 let Inst{11-0} = shift; 2010 let Inst{15-12} = Rd; 2011 let Inst{19-16} = Rn; 2012} 2013} 2014 2015// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 2016// The assume-no-carry-in form uses the negation of the input since add/sub 2017// assume opposite meanings of the carry flag (i.e., carry == !borrow). 2018// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 2019// details. 2020def : ARMPat<(add GPR:$src, so_imm_neg:$imm), 2021 (SUBri GPR:$src, so_imm_neg:$imm)>; 2022def : ARMPat<(addc GPR:$src, so_imm_neg:$imm), 2023 (SUBSri GPR:$src, so_imm_neg:$imm)>; 2024// The with-carry-in form matches bitwise not instead of the negation. 2025// Effectively, the inverse interpretation of the carry flag already accounts 2026// for part of the negation. 2027def : ARMPat<(adde GPR:$src, so_imm_not:$imm), 2028 (SBCri GPR:$src, so_imm_not:$imm)>; 2029 2030// Note: These are implemented in C++ code, because they have to generate 2031// ADD/SUBrs instructions, which use a complex pattern that a xform function 2032// cannot produce. 2033// (mul X, 2^n+1) -> (add (X << n), X) 2034// (mul X, 2^n-1) -> (rsb X, (X << n)) 2035 2036// ARM Arithmetic Instruction -- for disassembly only 2037// GPR:$dst = GPR:$a op GPR:$b 2038class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 2039 list<dag> pattern = [/* For disassembly only; pattern left blank */]> 2040 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr, 2041 opc, "\t$Rd, $Rn, $Rm", pattern> { 2042 bits<4> Rd; 2043 bits<4> Rn; 2044 bits<4> Rm; 2045 let Inst{27-20} = op27_20; 2046 let Inst{11-4} = op11_4; 2047 let Inst{19-16} = Rn; 2048 let Inst{15-12} = Rd; 2049 let Inst{3-0} = Rm; 2050} 2051 2052// Saturating add/subtract -- for disassembly only 2053 2054def QADD : AAI<0b00010000, 0b00000101, "qadd", 2055 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>; 2056def QSUB : AAI<0b00010010, 0b00000101, "qsub", 2057 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>; 2058def QDADD : AAI<0b00010100, 0b00000101, "qdadd">; 2059def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">; 2060 2061def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">; 2062def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">; 2063def QASX : AAI<0b01100010, 0b11110011, "qasx">; 2064def QSAX : AAI<0b01100010, 0b11110101, "qsax">; 2065def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">; 2066def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">; 2067def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">; 2068def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">; 2069def UQASX : AAI<0b01100110, 0b11110011, "uqasx">; 2070def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">; 2071def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">; 2072def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">; 2073 2074// Signed/Unsigned add/subtract -- for disassembly only 2075 2076def SASX : AAI<0b01100001, 0b11110011, "sasx">; 2077def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">; 2078def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">; 2079def SSAX : AAI<0b01100001, 0b11110101, "ssax">; 2080def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">; 2081def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">; 2082def UASX : AAI<0b01100101, 0b11110011, "uasx">; 2083def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">; 2084def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">; 2085def USAX : AAI<0b01100101, 0b11110101, "usax">; 2086def USUB16 : AAI<0b01100101, 0b11110111, "usub16">; 2087def USUB8 : AAI<0b01100101, 0b11111111, "usub8">; 2088 2089// Signed/Unsigned halving add/subtract -- for disassembly only 2090 2091def SHASX : AAI<0b01100011, 0b11110011, "shasx">; 2092def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">; 2093def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">; 2094def SHSAX : AAI<0b01100011, 0b11110101, "shsax">; 2095def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">; 2096def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">; 2097def UHASX : AAI<0b01100111, 0b11110011, "uhasx">; 2098def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">; 2099def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">; 2100def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">; 2101def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">; 2102def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">; 2103 2104// Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only 2105 2106def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 2107 MulFrm /* for convenience */, NoItinerary, "usad8", 2108 "\t$Rd, $Rn, $Rm", []>, 2109 Requires<[IsARM, HasV6]> { 2110 bits<4> Rd; 2111 bits<4> Rn; 2112 bits<4> Rm; 2113 let Inst{27-20} = 0b01111000; 2114 let Inst{15-12} = 0b1111; 2115 let Inst{7-4} = 0b0001; 2116 let Inst{19-16} = Rd; 2117 let Inst{11-8} = Rm; 2118 let Inst{3-0} = Rn; 2119} 2120def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 2121 MulFrm /* for convenience */, NoItinerary, "usada8", 2122 "\t$Rd, $Rn, $Rm, $Ra", []>, 2123 Requires<[IsARM, HasV6]> { 2124 bits<4> Rd; 2125 bits<4> Rn; 2126 bits<4> Rm; 2127 bits<4> Ra; 2128 let Inst{27-20} = 0b01111000; 2129 let Inst{7-4} = 0b0001; 2130 let Inst{19-16} = Rd; 2131 let Inst{15-12} = Ra; 2132 let Inst{11-8} = Rm; 2133 let Inst{3-0} = Rn; 2134} 2135 2136// Signed/Unsigned saturate -- for disassembly only 2137 2138def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh), 2139 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh", 2140 [/* For disassembly only; pattern left blank */]> { 2141 bits<4> Rd; 2142 bits<5> sat_imm; 2143 bits<4> Rn; 2144 bits<8> sh; 2145 let Inst{27-21} = 0b0110101; 2146 let Inst{5-4} = 0b01; 2147 let Inst{20-16} = sat_imm; 2148 let Inst{15-12} = Rd; 2149 let Inst{11-7} = sh{7-3}; 2150 let Inst{6} = sh{0}; 2151 let Inst{3-0} = Rn; 2152} 2153 2154def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm, 2155 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", 2156 [/* For disassembly only; pattern left blank */]> { 2157 bits<4> Rd; 2158 bits<4> sat_imm; 2159 bits<4> Rn; 2160 let Inst{27-20} = 0b01101010; 2161 let Inst{11-4} = 0b11110011; 2162 let Inst{15-12} = Rd; 2163 let Inst{19-16} = sat_imm; 2164 let Inst{3-0} = Rn; 2165} 2166 2167def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh), 2168 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh", 2169 [/* For disassembly only; pattern left blank */]> { 2170 bits<4> Rd; 2171 bits<5> sat_imm; 2172 bits<4> Rn; 2173 bits<8> sh; 2174 let Inst{27-21} = 0b0110111; 2175 let Inst{5-4} = 0b01; 2176 let Inst{15-12} = Rd; 2177 let Inst{11-7} = sh{7-3}; 2178 let Inst{6} = sh{0}; 2179 let Inst{20-16} = sat_imm; 2180 let Inst{3-0} = Rn; 2181} 2182 2183def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm, 2184 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a", 2185 [/* For disassembly only; pattern left blank */]> { 2186 bits<4> Rd; 2187 bits<4> sat_imm; 2188 bits<4> Rn; 2189 let Inst{27-20} = 0b01101110; 2190 let Inst{11-4} = 0b11110011; 2191 let Inst{15-12} = Rd; 2192 let Inst{19-16} = sat_imm; 2193 let Inst{3-0} = Rn; 2194} 2195 2196def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>; 2197def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>; 2198 2199//===----------------------------------------------------------------------===// 2200// Bitwise Instructions. 2201// 2202 2203defm AND : AsI1_bin_irs<0b0000, "and", 2204 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 2205 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 2206defm ORR : AsI1_bin_irs<0b1100, "orr", 2207 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 2208 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 2209defm EOR : AsI1_bin_irs<0b0001, "eor", 2210 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 2211 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 2212defm BIC : AsI1_bin_irs<0b1110, "bic", 2213 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 2214 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 2215 2216def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 2217 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi, 2218 "bfc", "\t$Rd, $imm", "$src = $Rd", 2219 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 2220 Requires<[IsARM, HasV6T2]> { 2221 bits<4> Rd; 2222 bits<10> imm; 2223 let Inst{27-21} = 0b0111110; 2224 let Inst{6-0} = 0b0011111; 2225 let Inst{15-12} = Rd; 2226 let Inst{11-7} = imm{4-0}; // lsb 2227 let Inst{20-16} = imm{9-5}; // width 2228} 2229 2230// A8.6.18 BFI - Bitfield insert (Encoding A1) 2231def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 2232 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi, 2233 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 2234 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn, 2235 bf_inv_mask_imm:$imm))]>, 2236 Requires<[IsARM, HasV6T2]> { 2237 bits<4> Rd; 2238 bits<4> Rn; 2239 bits<10> imm; 2240 let Inst{27-21} = 0b0111110; 2241 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 2242 let Inst{15-12} = Rd; 2243 let Inst{11-7} = imm{4-0}; // lsb 2244 let Inst{20-16} = imm{9-5}; // width 2245 let Inst{3-0} = Rn; 2246} 2247 2248def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 2249 "mvn", "\t$Rd, $Rm", 2250 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP { 2251 bits<4> Rd; 2252 bits<4> Rm; 2253 let Inst{25} = 0; 2254 let Inst{19-16} = 0b0000; 2255 let Inst{11-4} = 0b00000000; 2256 let Inst{15-12} = Rd; 2257 let Inst{3-0} = Rm; 2258} 2259def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm, 2260 IIC_iMVNsr, "mvn", "\t$Rd, $shift", 2261 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP { 2262 bits<4> Rd; 2263 bits<4> Rm; 2264 bits<12> shift; 2265 let Inst{25} = 0; 2266 let Inst{19-16} = 0b0000; 2267 let Inst{15-12} = Rd; 2268 let Inst{11-0} = shift; 2269} 2270let isReMaterializable = 1, isAsCheapAsAMove = 1 in 2271def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, 2272 IIC_iMVNi, "mvn", "\t$Rd, $imm", 2273 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP { 2274 bits<4> Rd; 2275 bits<4> Rm; 2276 bits<12> imm; 2277 let Inst{25} = 1; 2278 let Inst{19-16} = 0b0000; 2279 let Inst{15-12} = Rd; 2280 let Inst{11-0} = imm; 2281} 2282 2283def : ARMPat<(and GPR:$src, so_imm_not:$imm), 2284 (BICri GPR:$src, so_imm_not:$imm)>; 2285 2286//===----------------------------------------------------------------------===// 2287// Multiply Instructions. 2288// 2289class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 2290 string opc, string asm, list<dag> pattern> 2291 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 2292 bits<4> Rd; 2293 bits<4> Rm; 2294 bits<4> Rn; 2295 let Inst{19-16} = Rd; 2296 let Inst{11-8} = Rm; 2297 let Inst{3-0} = Rn; 2298} 2299class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 2300 string opc, string asm, list<dag> pattern> 2301 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 2302 bits<4> RdLo; 2303 bits<4> RdHi; 2304 bits<4> Rm; 2305 bits<4> Rn; 2306 let Inst{19-16} = RdHi; 2307 let Inst{15-12} = RdLo; 2308 let Inst{11-8} = Rm; 2309 let Inst{3-0} = Rn; 2310} 2311 2312let isCommutable = 1 in 2313def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 2314 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 2315 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>; 2316 2317def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 2318 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 2319 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]> { 2320 bits<4> Ra; 2321 let Inst{15-12} = Ra; 2322} 2323 2324def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 2325 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c", 2326 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>, 2327 Requires<[IsARM, HasV6T2]> { 2328 bits<4> Rd; 2329 bits<4> Rm; 2330 bits<4> Rn; 2331 let Inst{19-16} = Rd; 2332 let Inst{11-8} = Rm; 2333 let Inst{3-0} = Rn; 2334} 2335 2336// Extra precision multiplies with low / high results 2337 2338let neverHasSideEffects = 1 in { 2339let isCommutable = 1 in { 2340def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 2341 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 2342 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>; 2343 2344def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 2345 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 2346 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>; 2347} 2348 2349// Multiply + accumulate 2350def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 2351 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64, 2352 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>; 2353 2354def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 2355 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64, 2356 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>; 2357 2358def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 2359 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64, 2360 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 2361 Requires<[IsARM, HasV6]> { 2362 bits<4> RdLo; 2363 bits<4> RdHi; 2364 bits<4> Rm; 2365 bits<4> Rn; 2366 let Inst{19-16} = RdLo; 2367 let Inst{15-12} = RdHi; 2368 let Inst{11-8} = Rm; 2369 let Inst{3-0} = Rn; 2370} 2371} // neverHasSideEffects 2372 2373// Most significant word multiply 2374def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 2375 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 2376 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 2377 Requires<[IsARM, HasV6]> { 2378 let Inst{15-12} = 0b1111; 2379} 2380 2381def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 2382 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", 2383 [/* For disassembly only; pattern left blank */]>, 2384 Requires<[IsARM, HasV6]> { 2385 let Inst{15-12} = 0b1111; 2386} 2387 2388def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 2389 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 2390 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 2391 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 2392 Requires<[IsARM, HasV6]>; 2393 2394def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 2395 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 2396 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", 2397 [/* For disassembly only; pattern left blank */]>, 2398 Requires<[IsARM, HasV6]>; 2399 2400def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 2401 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 2402 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", 2403 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>, 2404 Requires<[IsARM, HasV6]>; 2405 2406def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 2407 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 2408 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", 2409 [/* For disassembly only; pattern left blank */]>, 2410 Requires<[IsARM, HasV6]>; 2411 2412multiclass AI_smul<string opc, PatFrag opnode> { 2413 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 2414 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 2415 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16), 2416 (sext_inreg GPR:$Rm, i16)))]>, 2417 Requires<[IsARM, HasV5TE]>; 2418 2419 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 2420 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 2421 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16), 2422 (sra GPR:$Rm, (i32 16))))]>, 2423 Requires<[IsARM, HasV5TE]>; 2424 2425 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 2426 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 2427 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)), 2428 (sext_inreg GPR:$Rm, i16)))]>, 2429 Requires<[IsARM, HasV5TE]>; 2430 2431 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 2432 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 2433 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)), 2434 (sra GPR:$Rm, (i32 16))))]>, 2435 Requires<[IsARM, HasV5TE]>; 2436 2437 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 2438 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 2439 [(set GPR:$Rd, (sra (opnode GPR:$Rn, 2440 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>, 2441 Requires<[IsARM, HasV5TE]>; 2442 2443 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 2444 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 2445 [(set GPR:$Rd, (sra (opnode GPR:$Rn, 2446 (sra GPR:$Rm, (i32 16))), (i32 16)))]>, 2447 Requires<[IsARM, HasV5TE]>; 2448} 2449 2450 2451multiclass AI_smla<string opc, PatFrag opnode> { 2452 def BB : AMulxyI<0b0001000, 0b00, (outs GPR:$Rd), 2453 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 2454 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 2455 [(set GPR:$Rd, (add GPR:$Ra, 2456 (opnode (sext_inreg GPR:$Rn, i16), 2457 (sext_inreg GPR:$Rm, i16))))]>, 2458 Requires<[IsARM, HasV5TE]>; 2459 2460 def BT : AMulxyI<0b0001000, 0b10, (outs GPR:$Rd), 2461 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 2462 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 2463 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16), 2464 (sra GPR:$Rm, (i32 16)))))]>, 2465 Requires<[IsARM, HasV5TE]>; 2466 2467 def TB : AMulxyI<0b0001000, 0b01, (outs GPR:$Rd), 2468 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 2469 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 2470 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)), 2471 (sext_inreg GPR:$Rm, i16))))]>, 2472 Requires<[IsARM, HasV5TE]>; 2473 2474 def TT : AMulxyI<0b0001000, 0b11, (outs GPR:$Rd), 2475 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 2476 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 2477 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)), 2478 (sra GPR:$Rm, (i32 16)))))]>, 2479 Requires<[IsARM, HasV5TE]>; 2480 2481 def WB : AMulxyI<0b0001001, 0b00, (outs GPR:$Rd), 2482 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 2483 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 2484 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn, 2485 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>, 2486 Requires<[IsARM, HasV5TE]>; 2487 2488 def WT : AMulxyI<0b0001001, 0b10, (outs GPR:$Rd), 2489 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 2490 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 2491 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn, 2492 (sra GPR:$Rm, (i32 16))), (i32 16))))]>, 2493 Requires<[IsARM, HasV5TE]>; 2494} 2495 2496defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 2497defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 2498 2499// Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only 2500def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi), 2501 (ins GPR:$Rn, GPR:$Rm), 2502 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", 2503 [/* For disassembly only; pattern left blank */]>, 2504 Requires<[IsARM, HasV5TE]>; 2505 2506def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi), 2507 (ins GPR:$Rn, GPR:$Rm), 2508 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", 2509 [/* For disassembly only; pattern left blank */]>, 2510 Requires<[IsARM, HasV5TE]>; 2511 2512def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi), 2513 (ins GPR:$Rn, GPR:$Rm), 2514 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", 2515 [/* For disassembly only; pattern left blank */]>, 2516 Requires<[IsARM, HasV5TE]>; 2517 2518def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi), 2519 (ins GPR:$Rn, GPR:$Rm), 2520 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", 2521 [/* For disassembly only; pattern left blank */]>, 2522 Requires<[IsARM, HasV5TE]>; 2523 2524// Helper class for AI_smld -- for disassembly only 2525class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 2526 InstrItinClass itin, string opc, string asm> 2527 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> { 2528 bits<4> Rn; 2529 bits<4> Rm; 2530 let Inst{4} = 1; 2531 let Inst{5} = swap; 2532 let Inst{6} = sub; 2533 let Inst{7} = 0; 2534 let Inst{21-20} = 0b00; 2535 let Inst{22} = long; 2536 let Inst{27-23} = 0b01110; 2537 let Inst{11-8} = Rm; 2538 let Inst{3-0} = Rn; 2539} 2540class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 2541 InstrItinClass itin, string opc, string asm> 2542 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 2543 bits<4> Rd; 2544 let Inst{15-12} = 0b1111; 2545 let Inst{19-16} = Rd; 2546} 2547class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 2548 InstrItinClass itin, string opc, string asm> 2549 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 2550 bits<4> Ra; 2551 let Inst{15-12} = Ra; 2552} 2553class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 2554 InstrItinClass itin, string opc, string asm> 2555 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 2556 bits<4> RdLo; 2557 bits<4> RdHi; 2558 let Inst{19-16} = RdHi; 2559 let Inst{15-12} = RdLo; 2560} 2561 2562multiclass AI_smld<bit sub, string opc> { 2563 2564 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 2565 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">; 2566 2567 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 2568 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">; 2569 2570 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi), 2571 (ins GPR:$Rn, GPR:$Rm), NoItinerary, 2572 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">; 2573 2574 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi), 2575 (ins GPR:$Rn, GPR:$Rm), NoItinerary, 2576 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">; 2577 2578} 2579 2580defm SMLA : AI_smld<0, "smla">; 2581defm SMLS : AI_smld<1, "smls">; 2582 2583multiclass AI_sdml<bit sub, string opc> { 2584 2585 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 2586 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">; 2587 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 2588 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">; 2589} 2590 2591defm SMUA : AI_sdml<0, "smua">; 2592defm SMUS : AI_sdml<1, "smus">; 2593 2594//===----------------------------------------------------------------------===// 2595// Misc. Arithmetic Instructions. 2596// 2597 2598def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 2599 IIC_iUNAr, "clz", "\t$Rd, $Rm", 2600 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>; 2601 2602def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 2603 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 2604 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>, 2605 Requires<[IsARM, HasV6T2]>; 2606 2607def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 2608 IIC_iUNAr, "rev", "\t$Rd, $Rm", 2609 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>; 2610 2611def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 2612 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 2613 [(set GPR:$Rd, 2614 (or (and (srl GPR:$Rm, (i32 8)), 0xFF), 2615 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00), 2616 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000), 2617 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>, 2618 Requires<[IsARM, HasV6]>; 2619 2620def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 2621 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 2622 [(set GPR:$Rd, 2623 (sext_inreg 2624 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)), 2625 (shl GPR:$Rm, (i32 8))), i16))]>, 2626 Requires<[IsARM, HasV6]>; 2627 2628def lsl_shift_imm : SDNodeXForm<imm, [{ 2629 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue()); 2630 return CurDAG->getTargetConstant(Sh, MVT::i32); 2631}]>; 2632 2633def lsl_amt : PatLeaf<(i32 imm), [{ 2634 return (N->getZExtValue() < 32); 2635}], lsl_shift_imm>; 2636 2637def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd), 2638 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh), 2639 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 2640 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF), 2641 (and (shl GPR:$Rm, lsl_amt:$sh), 2642 0xFFFF0000)))]>, 2643 Requires<[IsARM, HasV6]>; 2644 2645// Alternate cases for PKHBT where identities eliminate some nodes. 2646def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)), 2647 (PKHBT GPR:$Rn, GPR:$Rm, 0)>; 2648def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)), 2649 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>; 2650 2651def asr_shift_imm : SDNodeXForm<imm, [{ 2652 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue()); 2653 return CurDAG->getTargetConstant(Sh, MVT::i32); 2654}]>; 2655 2656def asr_amt : PatLeaf<(i32 imm), [{ 2657 return (N->getZExtValue() <= 32); 2658}], asr_shift_imm>; 2659 2660// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 2661// will match the pattern below. 2662def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd), 2663 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh), 2664 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 2665 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000), 2666 (and (sra GPR:$Rm, asr_amt:$sh), 2667 0xFFFF)))]>, 2668 Requires<[IsARM, HasV6]>; 2669 2670// Alternate cases for PKHTB where identities eliminate some nodes. Note that 2671// a shift amount of 0 is *not legal* here, it is PKHBT instead. 2672def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)), 2673 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>; 2674def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), 2675 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)), 2676 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>; 2677 2678//===----------------------------------------------------------------------===// 2679// Comparison Instructions... 2680// 2681 2682defm CMP : AI1_cmp_irs<0b1010, "cmp", 2683 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, 2684 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 2685 2686// FIXME: We have to be careful when using the CMN instruction and comparison 2687// with 0. One would expect these two pieces of code should give identical 2688// results: 2689// 2690// rsbs r1, r1, 0 2691// cmp r0, r1 2692// mov r0, #0 2693// it ls 2694// mov r0, #1 2695// 2696// and: 2697// 2698// cmn r0, r1 2699// mov r0, #0 2700// it ls 2701// mov r0, #1 2702// 2703// However, the CMN gives the *opposite* result when r1 is 0. This is because 2704// the carry flag is set in the CMP case but not in the CMN case. In short, the 2705// CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the 2706// value of r0 and the carry bit (because the "carry bit" parameter to 2707// AddWithCarry is defined as 1 in this case, the carry flag will always be set 2708// when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is 2709// never a "carry" when this AddWithCarry is performed (because the "carry bit" 2710// parameter to AddWithCarry is defined as 0). 2711// 2712// When x is 0 and unsigned: 2713// 2714// x = 0 2715// ~x = 0xFFFF FFFF 2716// ~x + 1 = 0x1 0000 0000 2717// (-x = 0) != (0x1 0000 0000 = ~x + 1) 2718// 2719// Therefore, we should disable CMN when comparing against zero, until we can 2720// limit when the CMN instruction is used (when we know that the RHS is not 0 or 2721// when it's a comparison which doesn't look at the 'carry' flag). 2722// 2723// (See the ARM docs for the "AddWithCarry" pseudo-code.) 2724// 2725// This is related to <rdar://problem/7569620>. 2726// 2727//defm CMN : AI1_cmp_irs<0b1011, "cmn", 2728// BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; 2729 2730// Note that TST/TEQ don't set all the same flags that CMP does! 2731defm TST : AI1_cmp_irs<0b1000, "tst", 2732 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 2733 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>; 2734defm TEQ : AI1_cmp_irs<0b1001, "teq", 2735 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 2736 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>; 2737 2738defm CMPz : AI1_cmp_irs<0b1010, "cmp", 2739 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, 2740 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>; 2741defm CMNz : AI1_cmp_irs<0b1011, "cmn", 2742 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, 2743 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>; 2744 2745//def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm), 2746// (CMNri GPR:$src, so_imm_neg:$imm)>; 2747 2748def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm), 2749 (CMNzri GPR:$src, so_imm_neg:$imm)>; 2750 2751// Pseudo i64 compares for some floating point compares. 2752let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 2753 Defs = [CPSR] in { 2754def BCCi64 : PseudoInst<(outs), 2755 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 2756 IIC_Br, "", 2757 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>; 2758 2759def BCCZi64 : PseudoInst<(outs), 2760 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, "", 2761 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>; 2762} // usesCustomInserter 2763 2764 2765// Conditional moves 2766// FIXME: should be able to write a pattern for ARMcmov, but can't use 2767// a two-value operand where a dag node expects two operands. :( 2768// FIXME: These should all be pseudo-instructions that get expanded to 2769// the normal MOV instructions. That would fix the dependency on 2770// special casing them in tblgen. 2771let neverHasSideEffects = 1 in { 2772def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm, 2773 IIC_iCMOVr, "mov", "\t$Rd, $Rm", 2774 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>, 2775 RegConstraint<"$false = $Rd">, UnaryDP { 2776 bits<4> Rd; 2777 bits<4> Rm; 2778 2779 let Inst{11-4} = 0b00000000; 2780 let Inst{25} = 0; 2781 let Inst{3-0} = Rm; 2782 let Inst{15-12} = Rd; 2783 let Inst{11-4} = 0b00000000; 2784 let Inst{25} = 0; 2785} 2786 2787def MOVCCs : AI1<0b1101, (outs GPR:$dst), 2788 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr, 2789 "mov", "\t$dst, $true", 2790 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>, 2791 RegConstraint<"$false = $dst">, UnaryDP { 2792 let Inst{25} = 0; 2793} 2794 2795def MOVCCi16 : AI1<0b1000, (outs GPR:$dst), (ins GPR:$false, i32imm:$src), 2796 DPFrm, IIC_iMOVi, 2797 "movw", "\t$dst, $src", 2798 []>, 2799 RegConstraint<"$false = $dst">, Requires<[IsARM, HasV6T2]>, 2800 UnaryDP { 2801 let Inst{20} = 0; 2802 let Inst{25} = 1; 2803} 2804 2805def MOVCCi : AI1<0b1101, (outs GPR:$dst), 2806 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi, 2807 "mov", "\t$dst, $true", 2808 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>, 2809 RegConstraint<"$false = $dst">, UnaryDP { 2810 let Inst{25} = 1; 2811} 2812} // neverHasSideEffects 2813 2814//===----------------------------------------------------------------------===// 2815// Atomic operations intrinsics 2816// 2817 2818// memory barriers protect the atomic sequences 2819let hasSideEffects = 1 in { 2820def DMBsy : AInoP<(outs), (ins), MiscFrm, NoItinerary, "dmb", "", 2821 [(ARMMemBarrier)]>, Requires<[IsARM, HasDB]> { 2822 let Inst{31-4} = 0xf57ff05; 2823 // FIXME: add support for options other than a full system DMB 2824 // See DMB disassembly-only variants below. 2825 let Inst{3-0} = 0b1111; 2826} 2827 2828def DSBsy : AInoP<(outs), (ins), MiscFrm, NoItinerary, "dsb", "", 2829 [(ARMSyncBarrier)]>, Requires<[IsARM, HasDB]> { 2830 let Inst{31-4} = 0xf57ff04; 2831 // FIXME: add support for options other than a full system DSB 2832 // See DSB disassembly-only variants below. 2833 let Inst{3-0} = 0b1111; 2834} 2835 2836def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary, 2837 "mcr", "\tp15, 0, $zero, c7, c10, 5", 2838 [(ARMMemBarrierMCR GPR:$zero)]>, 2839 Requires<[IsARM, HasV6]> { 2840 // FIXME: add support for options other than a full system DMB 2841 // FIXME: add encoding 2842} 2843 2844def DSB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary, 2845 "mcr", "\tp15, 0, $zero, c7, c10, 4", 2846 [(ARMSyncBarrierMCR GPR:$zero)]>, 2847 Requires<[IsARM, HasV6]> { 2848 // FIXME: add support for options other than a full system DSB 2849 // FIXME: add encoding 2850} 2851} 2852 2853// Memory Barrier Operations Variants -- for disassembly only 2854 2855def memb_opt : Operand<i32> { 2856 let PrintMethod = "printMemBOption"; 2857} 2858 2859class AMBI<bits<4> op7_4, string opc> 2860 : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, opc, "\t$opt", 2861 [/* For disassembly only; pattern left blank */]>, 2862 Requires<[IsARM, HasDB]> { 2863 let Inst{31-8} = 0xf57ff0; 2864 let Inst{7-4} = op7_4; 2865} 2866 2867// These DMB variants are for disassembly only. 2868def DMBvar : AMBI<0b0101, "dmb">; 2869 2870// These DSB variants are for disassembly only. 2871def DSBvar : AMBI<0b0100, "dsb">; 2872 2873// ISB has only full system option -- for disassembly only 2874def ISBsy : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>, 2875 Requires<[IsARM, HasDB]> { 2876 let Inst{31-4} = 0xf57ff06; 2877 let Inst{3-0} = 0b1111; 2878} 2879 2880let usesCustomInserter = 1 in { 2881 let Uses = [CPSR] in { 2882 def ATOMIC_LOAD_ADD_I8 : PseudoInst< 2883 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", 2884 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>; 2885 def ATOMIC_LOAD_SUB_I8 : PseudoInst< 2886 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", 2887 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>; 2888 def ATOMIC_LOAD_AND_I8 : PseudoInst< 2889 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", 2890 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>; 2891 def ATOMIC_LOAD_OR_I8 : PseudoInst< 2892 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", 2893 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>; 2894 def ATOMIC_LOAD_XOR_I8 : PseudoInst< 2895 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", 2896 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>; 2897 def ATOMIC_LOAD_NAND_I8 : PseudoInst< 2898 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", 2899 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>; 2900 def ATOMIC_LOAD_ADD_I16 : PseudoInst< 2901 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", 2902 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>; 2903 def ATOMIC_LOAD_SUB_I16 : PseudoInst< 2904 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", 2905 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>; 2906 def ATOMIC_LOAD_AND_I16 : PseudoInst< 2907 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", 2908 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>; 2909 def ATOMIC_LOAD_OR_I16 : PseudoInst< 2910 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", 2911 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>; 2912 def ATOMIC_LOAD_XOR_I16 : PseudoInst< 2913 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", 2914 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>; 2915 def ATOMIC_LOAD_NAND_I16 : PseudoInst< 2916 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", 2917 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>; 2918 def ATOMIC_LOAD_ADD_I32 : PseudoInst< 2919 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", 2920 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>; 2921 def ATOMIC_LOAD_SUB_I32 : PseudoInst< 2922 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", 2923 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>; 2924 def ATOMIC_LOAD_AND_I32 : PseudoInst< 2925 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", 2926 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>; 2927 def ATOMIC_LOAD_OR_I32 : PseudoInst< 2928 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", 2929 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>; 2930 def ATOMIC_LOAD_XOR_I32 : PseudoInst< 2931 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", 2932 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>; 2933 def ATOMIC_LOAD_NAND_I32 : PseudoInst< 2934 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "", 2935 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>; 2936 2937 def ATOMIC_SWAP_I8 : PseudoInst< 2938 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "", 2939 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>; 2940 def ATOMIC_SWAP_I16 : PseudoInst< 2941 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "", 2942 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>; 2943 def ATOMIC_SWAP_I32 : PseudoInst< 2944 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "", 2945 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>; 2946 2947 def ATOMIC_CMP_SWAP_I8 : PseudoInst< 2948 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "", 2949 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>; 2950 def ATOMIC_CMP_SWAP_I16 : PseudoInst< 2951 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "", 2952 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>; 2953 def ATOMIC_CMP_SWAP_I32 : PseudoInst< 2954 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "", 2955 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>; 2956} 2957} 2958 2959let mayLoad = 1 in { 2960def LDREXB : AIldrex<0b10, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary, 2961 "ldrexb", "\t$dest, [$ptr]", 2962 []>; 2963def LDREXH : AIldrex<0b11, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary, 2964 "ldrexh", "\t$dest, [$ptr]", 2965 []>; 2966def LDREX : AIldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary, 2967 "ldrex", "\t$dest, [$ptr]", 2968 []>; 2969def LDREXD : AIldrex<0b01, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr), 2970 NoItinerary, 2971 "ldrexd", "\t$dest, $dest2, [$ptr]", 2972 []>; 2973} 2974 2975let mayStore = 1, Constraints = "@earlyclobber $success" in { 2976def STREXB : AIstrex<0b10, (outs GPR:$success), (ins GPR:$src, GPR:$ptr), 2977 NoItinerary, 2978 "strexb", "\t$success, $src, [$ptr]", 2979 []>; 2980def STREXH : AIstrex<0b11, (outs GPR:$success), (ins GPR:$src, GPR:$ptr), 2981 NoItinerary, 2982 "strexh", "\t$success, $src, [$ptr]", 2983 []>; 2984def STREX : AIstrex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr), 2985 NoItinerary, 2986 "strex", "\t$success, $src, [$ptr]", 2987 []>; 2988def STREXD : AIstrex<0b01, (outs GPR:$success), 2989 (ins GPR:$src, GPR:$src2, GPR:$ptr), 2990 NoItinerary, 2991 "strexd", "\t$success, $src, $src2, [$ptr]", 2992 []>; 2993} 2994 2995// Clear-Exclusive is for disassembly only. 2996def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 2997 [/* For disassembly only; pattern left blank */]>, 2998 Requires<[IsARM, HasV7]> { 2999 let Inst{31-20} = 0xf57; 3000 let Inst{7-4} = 0b0001; 3001} 3002 3003// SWP/SWPB are deprecated in V6/V7 and for disassembly only. 3004let mayLoad = 1 in { 3005def SWP : AI<(outs GPR:$dst), (ins GPR:$src, GPR:$ptr), LdStExFrm, NoItinerary, 3006 "swp", "\t$dst, $src, [$ptr]", 3007 [/* For disassembly only; pattern left blank */]> { 3008 let Inst{27-23} = 0b00010; 3009 let Inst{22} = 0; // B = 0 3010 let Inst{21-20} = 0b00; 3011 let Inst{7-4} = 0b1001; 3012} 3013 3014def SWPB : AI<(outs GPR:$dst), (ins GPR:$src, GPR:$ptr), LdStExFrm, NoItinerary, 3015 "swpb", "\t$dst, $src, [$ptr]", 3016 [/* For disassembly only; pattern left blank */]> { 3017 let Inst{27-23} = 0b00010; 3018 let Inst{22} = 1; // B = 1 3019 let Inst{21-20} = 0b00; 3020 let Inst{7-4} = 0b1001; 3021} 3022} 3023 3024//===----------------------------------------------------------------------===// 3025// TLS Instructions 3026// 3027 3028// __aeabi_read_tp preserves the registers r1-r3. 3029let isCall = 1, 3030 Defs = [R0, R12, LR, CPSR] in { 3031 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br, 3032 "bl\t__aeabi_read_tp", 3033 [(set R0, ARMthread_pointer)]>; 3034} 3035 3036//===----------------------------------------------------------------------===// 3037// SJLJ Exception handling intrinsics 3038// eh_sjlj_setjmp() is an instruction sequence to store the return 3039// address and save #0 in R0 for the non-longjmp case. 3040// Since by its nature we may be coming from some other function to get 3041// here, and we're using the stack frame for the containing function to 3042// save/restore registers, we can't keep anything live in regs across 3043// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 3044// when we get here from a longjmp(). We force everthing out of registers 3045// except for our own input by listing the relevant registers in Defs. By 3046// doing so, we also cause the prologue/epilogue code to actively preserve 3047// all of the callee-saved resgisters, which is exactly what we want. 3048// A constant value is passed in $val, and we use the location as a scratch. 3049let Defs = 3050 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0, 3051 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, 3052 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, 3053 D31 ], hasSideEffects = 1, isBarrier = 1 in { 3054 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val), 3055 AddrModeNone, SizeSpecial, IndexModeNone, 3056 Pseudo, NoItinerary, "", "", 3057 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 3058 Requires<[IsARM, HasVFP2]>; 3059} 3060 3061let Defs = 3062 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ], 3063 hasSideEffects = 1, isBarrier = 1 in { 3064 def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val), 3065 AddrModeNone, SizeSpecial, IndexModeNone, 3066 Pseudo, NoItinerary, "", "", 3067 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 3068 Requires<[IsARM, NoVFP]>; 3069} 3070 3071// FIXME: Non-Darwin version(s) 3072let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 3073 Defs = [ R7, LR, SP ] in { 3074def Int_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), 3075 AddrModeNone, SizeSpecial, IndexModeNone, 3076 Pseudo, NoItinerary, "", "", 3077 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 3078 Requires<[IsARM, IsDarwin]>; 3079} 3080 3081// eh.sjlj.dispatchsetup pseudo-instruction. 3082// This pseudo is usef for ARM, Thumb1 and Thumb2. Any differences are 3083// handled when the pseudo is expanded (which happens before any passes 3084// that need the instruction size). 3085let isBarrier = 1, hasSideEffects = 1 in 3086def Int_eh_sjlj_dispatchsetup : 3087 PseudoInst<(outs), (ins GPR:$src), NoItinerary, "", 3088 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>, 3089 Requires<[IsDarwin]>; 3090 3091//===----------------------------------------------------------------------===// 3092// Non-Instruction Patterns 3093// 3094 3095// Large immediate handling. 3096 3097// Two piece so_imms. 3098// FIXME: Expand this in ARMExpandPseudoInsts. 3099// FIXME: Remove this when we can do generalized remat. 3100let isReMaterializable = 1 in 3101def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), 3102 Pseudo, IIC_iMOVix2, 3103 "mov", "\t$dst, $src", 3104 [(set GPR:$dst, so_imm2part:$src)]>, 3105 Requires<[IsARM, NoV6T2]>; 3106 3107def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS), 3108 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)), 3109 (so_imm2part_2 imm:$RHS))>; 3110def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS), 3111 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)), 3112 (so_imm2part_2 imm:$RHS))>; 3113def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS), 3114 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)), 3115 (so_imm2part_2 imm:$RHS))>; 3116def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS), 3117 (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)), 3118 (so_neg_imm2part_2 imm:$RHS))>; 3119 3120// 32-bit immediate using movw + movt. 3121// This is a single pseudo instruction, the benefit is that it can be remat'd 3122// as a single unit instead of having to handle reg inputs. 3123// FIXME: Remove this when we can do generalized remat. 3124let isReMaterializable = 1 in 3125def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, "", 3126 [(set GPR:$dst, (i32 imm:$src))]>, 3127 Requires<[IsARM, HasV6T2]>; 3128 3129// ConstantPool, GlobalAddress, and JumpTable 3130def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>, 3131 Requires<[IsARM, DontUseMovt]>; 3132def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 3133def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 3134 Requires<[IsARM, UseMovt]>; 3135def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id), 3136 (LEApcrelJT tjumptable:$dst, imm:$id)>; 3137 3138// TODO: add,sub,and, 3-instr forms? 3139 3140// Tail calls 3141def : ARMPat<(ARMtcret tcGPR:$dst), 3142 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>; 3143 3144def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)), 3145 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>; 3146 3147def : ARMPat<(ARMtcret (i32 texternalsym:$dst)), 3148 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>; 3149 3150def : ARMPat<(ARMtcret tcGPR:$dst), 3151 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>; 3152 3153def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)), 3154 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>; 3155 3156def : ARMPat<(ARMtcret (i32 texternalsym:$dst)), 3157 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>; 3158 3159// Direct calls 3160def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>, 3161 Requires<[IsARM, IsNotDarwin]>; 3162def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>, 3163 Requires<[IsARM, IsDarwin]>; 3164 3165// zextload i1 -> zextload i8 3166//def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>; 3167def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 3168def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 3169 3170// extload -> zextload 3171def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 3172def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 3173def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 3174def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 3175 3176def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 3177 3178def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 3179def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 3180 3181// smul* and smla* 3182def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 3183 (sra (shl GPR:$b, (i32 16)), (i32 16))), 3184 (SMULBB GPR:$a, GPR:$b)>; 3185def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 3186 (SMULBB GPR:$a, GPR:$b)>; 3187def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 3188 (sra GPR:$b, (i32 16))), 3189 (SMULBT GPR:$a, GPR:$b)>; 3190def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))), 3191 (SMULBT GPR:$a, GPR:$b)>; 3192def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), 3193 (sra (shl GPR:$b, (i32 16)), (i32 16))), 3194 (SMULTB GPR:$a, GPR:$b)>; 3195def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b), 3196 (SMULTB GPR:$a, GPR:$b)>; 3197def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), 3198 (i32 16)), 3199 (SMULWB GPR:$a, GPR:$b)>; 3200def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)), 3201 (SMULWB GPR:$a, GPR:$b)>; 3202 3203def : ARMV5TEPat<(add GPR:$acc, 3204 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 3205 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 3206 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 3207def : ARMV5TEPat<(add GPR:$acc, 3208 (mul sext_16_node:$a, sext_16_node:$b)), 3209 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 3210def : ARMV5TEPat<(add GPR:$acc, 3211 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 3212 (sra GPR:$b, (i32 16)))), 3213 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 3214def : ARMV5TEPat<(add GPR:$acc, 3215 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))), 3216 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 3217def : ARMV5TEPat<(add GPR:$acc, 3218 (mul (sra GPR:$a, (i32 16)), 3219 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 3220 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 3221def : ARMV5TEPat<(add GPR:$acc, 3222 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)), 3223 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 3224def : ARMV5TEPat<(add GPR:$acc, 3225 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), 3226 (i32 16))), 3227 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 3228def : ARMV5TEPat<(add GPR:$acc, 3229 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))), 3230 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 3231 3232//===----------------------------------------------------------------------===// 3233// Thumb Support 3234// 3235 3236include "ARMInstrThumb.td" 3237 3238//===----------------------------------------------------------------------===// 3239// Thumb2 Support 3240// 3241 3242include "ARMInstrThumb2.td" 3243 3244//===----------------------------------------------------------------------===// 3245// Floating Point Support 3246// 3247 3248include "ARMInstrVFP.td" 3249 3250//===----------------------------------------------------------------------===// 3251// Advanced SIMD (NEON) Support 3252// 3253 3254include "ARMInstrNEON.td" 3255 3256//===----------------------------------------------------------------------===// 3257// Coprocessor Instructions. For disassembly only. 3258// 3259 3260def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, 3261 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), 3262 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2", 3263 [/* For disassembly only; pattern left blank */]> { 3264 let Inst{4} = 0; 3265} 3266 3267def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, 3268 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), 3269 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2", 3270 [/* For disassembly only; pattern left blank */]> { 3271 let Inst{31-28} = 0b1111; 3272 let Inst{4} = 0; 3273} 3274 3275class ACI<dag oops, dag iops, string opc, string asm> 3276 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary, 3277 opc, asm, "", [/* For disassembly only; pattern left blank */]> { 3278 let Inst{27-25} = 0b110; 3279} 3280 3281multiclass LdStCop<bits<4> op31_28, bit load, string opc> { 3282 3283 def _OFFSET : ACI<(outs), 3284 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), 3285 opc, "\tp$cop, cr$CRd, $addr"> { 3286 let Inst{31-28} = op31_28; 3287 let Inst{24} = 1; // P = 1 3288 let Inst{21} = 0; // W = 0 3289 let Inst{22} = 0; // D = 0 3290 let Inst{20} = load; 3291 } 3292 3293 def _PRE : ACI<(outs), 3294 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), 3295 opc, "\tp$cop, cr$CRd, $addr!"> { 3296 let Inst{31-28} = op31_28; 3297 let Inst{24} = 1; // P = 1 3298 let Inst{21} = 1; // W = 1 3299 let Inst{22} = 0; // D = 0 3300 let Inst{20} = load; 3301 } 3302 3303 def _POST : ACI<(outs), 3304 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset), 3305 opc, "\tp$cop, cr$CRd, [$base], $offset"> { 3306 let Inst{31-28} = op31_28; 3307 let Inst{24} = 0; // P = 0 3308 let Inst{21} = 1; // W = 1 3309 let Inst{22} = 0; // D = 0 3310 let Inst{20} = load; 3311 } 3312 3313 def _OPTION : ACI<(outs), 3314 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option), 3315 opc, "\tp$cop, cr$CRd, [$base], $option"> { 3316 let Inst{31-28} = op31_28; 3317 let Inst{24} = 0; // P = 0 3318 let Inst{23} = 1; // U = 1 3319 let Inst{21} = 0; // W = 0 3320 let Inst{22} = 0; // D = 0 3321 let Inst{20} = load; 3322 } 3323 3324 def L_OFFSET : ACI<(outs), 3325 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), 3326 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> { 3327 let Inst{31-28} = op31_28; 3328 let Inst{24} = 1; // P = 1 3329 let Inst{21} = 0; // W = 0 3330 let Inst{22} = 1; // D = 1 3331 let Inst{20} = load; 3332 } 3333 3334 def L_PRE : ACI<(outs), 3335 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), 3336 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> { 3337 let Inst{31-28} = op31_28; 3338 let Inst{24} = 1; // P = 1 3339 let Inst{21} = 1; // W = 1 3340 let Inst{22} = 1; // D = 1 3341 let Inst{20} = load; 3342 } 3343 3344 def L_POST : ACI<(outs), 3345 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset), 3346 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> { 3347 let Inst{31-28} = op31_28; 3348 let Inst{24} = 0; // P = 0 3349 let Inst{21} = 1; // W = 1 3350 let Inst{22} = 1; // D = 1 3351 let Inst{20} = load; 3352 } 3353 3354 def L_OPTION : ACI<(outs), 3355 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option), 3356 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> { 3357 let Inst{31-28} = op31_28; 3358 let Inst{24} = 0; // P = 0 3359 let Inst{23} = 1; // U = 1 3360 let Inst{21} = 0; // W = 0 3361 let Inst{22} = 1; // D = 1 3362 let Inst{20} = load; 3363 } 3364} 3365 3366defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">; 3367defm LDC2 : LdStCop<0b1111, 1, "ldc2">; 3368defm STC : LdStCop<{?,?,?,?}, 0, "stc">; 3369defm STC2 : LdStCop<0b1111, 0, "stc2">; 3370 3371def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, 3372 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), 3373 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2", 3374 [/* For disassembly only; pattern left blank */]> { 3375 let Inst{20} = 0; 3376 let Inst{4} = 1; 3377} 3378 3379def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, 3380 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), 3381 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2", 3382 [/* For disassembly only; pattern left blank */]> { 3383 let Inst{31-28} = 0b1111; 3384 let Inst{20} = 0; 3385 let Inst{4} = 1; 3386} 3387 3388def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, 3389 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), 3390 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2", 3391 [/* For disassembly only; pattern left blank */]> { 3392 let Inst{20} = 1; 3393 let Inst{4} = 1; 3394} 3395 3396def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, 3397 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), 3398 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2", 3399 [/* For disassembly only; pattern left blank */]> { 3400 let Inst{31-28} = 0b1111; 3401 let Inst{20} = 1; 3402 let Inst{4} = 1; 3403} 3404 3405def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc, 3406 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm), 3407 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm", 3408 [/* For disassembly only; pattern left blank */]> { 3409 let Inst{23-20} = 0b0100; 3410} 3411 3412def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc, 3413 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm), 3414 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm", 3415 [/* For disassembly only; pattern left blank */]> { 3416 let Inst{31-28} = 0b1111; 3417 let Inst{23-20} = 0b0100; 3418} 3419 3420def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc, 3421 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm), 3422 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm", 3423 [/* For disassembly only; pattern left blank */]> { 3424 let Inst{23-20} = 0b0101; 3425} 3426 3427def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc, 3428 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm), 3429 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm", 3430 [/* For disassembly only; pattern left blank */]> { 3431 let Inst{31-28} = 0b1111; 3432 let Inst{23-20} = 0b0101; 3433} 3434 3435//===----------------------------------------------------------------------===// 3436// Move between special register and ARM core register -- for disassembly only 3437// 3438 3439def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr", 3440 [/* For disassembly only; pattern left blank */]> { 3441 let Inst{23-20} = 0b0000; 3442 let Inst{7-4} = 0b0000; 3443} 3444 3445def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr", 3446 [/* For disassembly only; pattern left blank */]> { 3447 let Inst{23-20} = 0b0100; 3448 let Inst{7-4} = 0b0000; 3449} 3450 3451def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, 3452 "msr", "\tcpsr$mask, $src", 3453 [/* For disassembly only; pattern left blank */]> { 3454 let Inst{23-20} = 0b0010; 3455 let Inst{7-4} = 0b0000; 3456} 3457 3458def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary, 3459 "msr", "\tcpsr$mask, $a", 3460 [/* For disassembly only; pattern left blank */]> { 3461 let Inst{23-20} = 0b0010; 3462 let Inst{7-4} = 0b0000; 3463} 3464 3465def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, 3466 "msr", "\tspsr$mask, $src", 3467 [/* For disassembly only; pattern left blank */]> { 3468 let Inst{23-20} = 0b0110; 3469 let Inst{7-4} = 0b0000; 3470} 3471 3472def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary, 3473 "msr", "\tspsr$mask, $a", 3474 [/* For disassembly only; pattern left blank */]> { 3475 let Inst{23-20} = 0b0110; 3476 let Inst{7-4} = 0b0000; 3477} 3478