ARMScheduleV6.td revision e459ad4380c5eed48471d4dac025f732c909f6d3
1//===- ARMScheduleV6.td - ARM v6 Scheduling Definitions ----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the itinerary class data for the ARM v6 processors. 11// 12//===----------------------------------------------------------------------===// 13 14// Model based on ARM1176 15// 16// Functional Units 17def V6_Pipe : FuncUnit; // pipeline 18 19// Scheduling information derived from "ARM1176JZF-S Technical Reference Manual" 20// 21def ARMV6Itineraries : ProcessorItineraries< 22 [V6_Pipe], [ 23 // 24 // No operand cycles 25 InstrItinData<IIC_iALUx , [InstrStage<1, [V6_Pipe]>]>, 26 // 27 // Binary Instructions that produce a result 28 InstrItinData<IIC_iALUi , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 29 InstrItinData<IIC_iALUr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 30 InstrItinData<IIC_iALUsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 31 InstrItinData<IIC_iALUsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>, 32 // 33 // Unary Instructions that produce a result 34 InstrItinData<IIC_iUNAr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 35 InstrItinData<IIC_iUNAsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 36 InstrItinData<IIC_iUNAsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>, 37 // 38 // Zero and sign extension instructions 39 InstrItinData<IIC_iEXTr , [InstrStage<1, [V6_Pipe]>], [1, 1]>, 40 InstrItinData<IIC_iEXTAr , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 41 // 42 // Compare instructions 43 InstrItinData<IIC_iCMPi , [InstrStage<1, [V6_Pipe]>], [2]>, 44 InstrItinData<IIC_iCMPr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 45 InstrItinData<IIC_iCMPsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 46 InstrItinData<IIC_iCMPsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>, 47 // 48 // Move instructions, unconditional 49 InstrItinData<IIC_iMOVi , [InstrStage<1, [V6_Pipe]>], [2]>, 50 InstrItinData<IIC_iMOVr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 51 InstrItinData<IIC_iMOVsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 52 InstrItinData<IIC_iMOVsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>, 53 InstrItinData<IIC_iMOVix2 , [InstrStage<1, [V6_Pipe]>, 54 InstrStage<1, [V6_Pipe]>], [2]>, 55 // 56 // Move instructions, conditional 57 InstrItinData<IIC_iCMOVi , [InstrStage<1, [V6_Pipe]>], [3]>, 58 InstrItinData<IIC_iCMOVr , [InstrStage<1, [V6_Pipe]>], [3, 2]>, 59 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [V6_Pipe]>], [3, 1]>, 60 InstrItinData<IIC_iCMOVsr , [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>, 61 62 // Integer multiply pipeline 63 // 64 InstrItinData<IIC_iMUL16 , [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>, 65 InstrItinData<IIC_iMAC16 , [InstrStage<1, [V6_Pipe]>], [4, 1, 1, 2]>, 66 InstrItinData<IIC_iMUL32 , [InstrStage<2, [V6_Pipe]>], [5, 1, 1]>, 67 InstrItinData<IIC_iMAC32 , [InstrStage<2, [V6_Pipe]>], [5, 1, 1, 2]>, 68 InstrItinData<IIC_iMUL64 , [InstrStage<3, [V6_Pipe]>], [6, 1, 1]>, 69 InstrItinData<IIC_iMAC64 , [InstrStage<3, [V6_Pipe]>], [6, 1, 1, 2]>, 70 71 // Integer load pipeline 72 // 73 // Immediate offset 74 InstrItinData<IIC_iLoadi , [InstrStage<1, [V6_Pipe]>], [4, 1]>, 75 // 76 // Register offset 77 InstrItinData<IIC_iLoadr , [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>, 78 // 79 // Scaled register offset, issues over 2 cycles 80 InstrItinData<IIC_iLoadsi , [InstrStage<2, [V6_Pipe]>], [5, 2, 1]>, 81 // 82 // Immediate offset with update 83 InstrItinData<IIC_iLoadiu , [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>, 84 // 85 // Register offset with update 86 InstrItinData<IIC_iLoadru , [InstrStage<1, [V6_Pipe]>], [4, 2, 1, 1]>, 87 // 88 // Scaled register offset with update, issues over 2 cycles 89 InstrItinData<IIC_iLoadsiu , [InstrStage<2, [V6_Pipe]>], [5, 2, 2, 1]>, 90 91 // 92 // Load multiple 93 InstrItinData<IIC_iLoadm , [InstrStage<3, [V6_Pipe]>]>, 94 95 // 96 // Load multiple plus branch 97 InstrItinData<IIC_iLoadmBr , [InstrStage<3, [V6_Pipe]>, 98 InstrStage<1, [V6_Pipe]>]>, 99 100 // 101 // iLoadi + iALUr for t2LDRpci_pic. 102 InstrItinData<IIC_iLoadiALU, [InstrStage<1, [V6_Pipe]>, 103 InstrStage<1, [V6_Pipe]>], [3, 1]>, 104 105 // Integer store pipeline 106 // 107 // Immediate offset 108 InstrItinData<IIC_iStorei , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 109 // 110 // Register offset 111 InstrItinData<IIC_iStorer , [InstrStage<1, [V6_Pipe]>], [2, 1, 1]>, 112 113 // 114 // Scaled register offset, issues over 2 cycles 115 InstrItinData<IIC_iStoresi , [InstrStage<2, [V6_Pipe]>], [2, 2, 1]>, 116 // 117 // Immediate offset with update 118 InstrItinData<IIC_iStoreiu , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 119 // 120 // Register offset with update 121 InstrItinData<IIC_iStoreru , [InstrStage<1, [V6_Pipe]>], [2, 2, 1, 1]>, 122 // 123 // Scaled register offset with update, issues over 2 cycles 124 InstrItinData<IIC_iStoresiu, [InstrStage<2, [V6_Pipe]>], [2, 2, 2, 1]>, 125 // 126 // Store multiple 127 InstrItinData<IIC_iStorem , [InstrStage<3, [V6_Pipe]>]>, 128 129 // Branch 130 // 131 // no delay slots, so the latency of a branch is unimportant 132 InstrItinData<IIC_Br , [InstrStage<1, [V6_Pipe]>]>, 133 134 // VFP 135 // Issue through integer pipeline, and execute in NEON unit. We assume 136 // RunFast mode so that NFP pipeline is used for single-precision when 137 // possible. 138 // 139 // FP Special Register to Integer Register File Move 140 InstrItinData<IIC_fpSTAT , [InstrStage<1, [V6_Pipe]>], [3]>, 141 // 142 // Single-precision FP Unary 143 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [V6_Pipe]>], [5, 2]>, 144 // 145 // Double-precision FP Unary 146 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [V6_Pipe]>], [5, 2]>, 147 // 148 // Single-precision FP Compare 149 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 150 // 151 // Double-precision FP Compare 152 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 153 // 154 // Single to Double FP Convert 155 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [V6_Pipe]>], [5, 2]>, 156 // 157 // Double to Single FP Convert 158 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [V6_Pipe]>], [5, 2]>, 159 // 160 // Single-Precision FP to Integer Convert 161 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [V6_Pipe]>], [9, 2]>, 162 // 163 // Double-Precision FP to Integer Convert 164 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [V6_Pipe]>], [9, 2]>, 165 // 166 // Integer to Single-Precision FP Convert 167 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [V6_Pipe]>], [9, 2]>, 168 // 169 // Integer to Double-Precision FP Convert 170 InstrItinData<IIC_fpCVTID , [InstrStage<1, [V6_Pipe]>], [9, 2]>, 171 // 172 // Single-precision FP ALU 173 InstrItinData<IIC_fpALU32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>, 174 // 175 // Double-precision FP ALU 176 InstrItinData<IIC_fpALU64 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>, 177 // 178 // Single-precision FP Multiply 179 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>, 180 // 181 // Double-precision FP Multiply 182 InstrItinData<IIC_fpMUL64 , [InstrStage<2, [V6_Pipe]>], [9, 2, 2]>, 183 // 184 // Single-precision FP MAC 185 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2, 2]>, 186 // 187 // Double-precision FP MAC 188 InstrItinData<IIC_fpMAC64 , [InstrStage<2, [V6_Pipe]>], [9, 2, 2, 2]>, 189 // 190 // Single-precision FP DIV 191 InstrItinData<IIC_fpDIV32 , [InstrStage<15, [V6_Pipe]>], [20, 2, 2]>, 192 // 193 // Double-precision FP DIV 194 InstrItinData<IIC_fpDIV64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>, 195 // 196 // Single-precision FP SQRT 197 InstrItinData<IIC_fpSQRT32 , [InstrStage<15, [V6_Pipe]>], [20, 2, 2]>, 198 // 199 // Double-precision FP SQRT 200 InstrItinData<IIC_fpSQRT64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>, 201 // 202 // Single-precision FP Load 203 InstrItinData<IIC_fpLoad32 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>, 204 // 205 // Double-precision FP Load 206 InstrItinData<IIC_fpLoad64 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>, 207 // 208 // FP Load Multiple 209 InstrItinData<IIC_fpLoadm , [InstrStage<3, [V6_Pipe]>]>, 210 // 211 // Single-precision FP Store 212 InstrItinData<IIC_fpStore32 , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 213 // 214 // Double-precision FP Store 215 // use FU_Issue to enforce the 1 load/store per cycle limit 216 InstrItinData<IIC_fpStore64 , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 217 // 218 // FP Store Multiple 219 InstrItinData<IIC_fpStorem , [InstrStage<3, [V6_Pipe]>]> 220]>; 221