| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 82509e5c62a99912c636b22e227b810eaf6eda78 |
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11-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Fix a number of problems with ARM fused multiply add/subtract instructions.
1. The new instruction itinerary entries are not properly described.
2. The asm parser can't handle vfms and vfnms.
3. There were no assembler, disassembler test cases.
4. HasNEON2 has the wrong assembler predicate.
rdar://10139676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154456 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
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18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 9fe2009956fc40f3aea46fb3c38dcfb61c4aca46 |
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20-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sorry, several patches in one.
TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.
Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.
ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
to re-materialize the instruction, allow machine LICM to hoist the set of
instructions out of the loop and make it possible to CSE them. It's a bit
hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.
With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| c47f7d643eee54c087bbe4c9964aa4d5afb7f6fe |
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13-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Conditional moves are slightly more expensive than moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118985 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 5b7a825ec5551fd1dff8c9f280cc203da3fdedd9 |
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21-Oct-2010 |
Andrew Trick <atrick@apple.com> |
putback r116983 and fix simple-fp-encoding.ll tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116992 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| d9707e3d852622197133a73dcb788a7fcd364015 |
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21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Revert r116983, which is breaking all the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116987 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| d6865de2d205d501e20d312ac66463be57dc44a1 |
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21-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add missing scheduling itineraries for transfers between core registers and VFP registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116983 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 5a50ceeaea980962c1982ad535226c7ab06c971c |
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07-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| a0792de66c8364d47b0a688c7f408efb7b10f31b |
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06-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 0e55fd61ae9ab88cf76b30f7e69d168bd7be87d0 |
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30-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
ARM instruction itinerary fixes:
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 5d42c567c901508e80ab10ddba1bb30a5007d742 |
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29-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 7e1bf305cfecbaee859405468b769650efe68f1a |
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29-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115008 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 63d66eed16a6ee4e838f2f7a4c8299def0722c20 |
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29-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add support to model pipeline bypass / forwarding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115005 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 27fdcd1c95fb1ded32d5e3876fed3c0f0641ab30 |
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25-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove a unused instruction itinerary class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 576a3968a2c1607d0ca0d87b28f8509b633e4bf0 |
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25-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix zero and sign extension instructions scheduling itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114780 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| bd30ce4311e158f1bfc6c95987ffbbad2193fef3 |
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25-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
More pseudo instruction scheduling itinerary fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 5f54ce347368105260be2cec497b6a4199dc5789 |
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09-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
For each instruction itinerary class, specify the number of micro-ops each
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 18f30e6f5e80787808fe1455742452a5210afe07 |
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02-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up 80 column violations. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 928eb49cae286c95dceecf4442997dd561c6e3b7 |
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18-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make processor FUs unique for given itinerary. This extends the limit of 32
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| ebb5cb92169a04dd94fa65ae18aead271db3a4e5 |
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18-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Add ARMv6 itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 127221fbdceba333f5e243f5278a691a7d182898 |
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23-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Checkpoint NEON scheduling itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| b2bb7db9e242c54a4a84448ab503015a148e9286 |
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21-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Add Cortex-A8 VFP model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82483 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 5d598aaf3de7f506749f4a0a142fe0121854e1a6 |
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19-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Update Cortex-A8 instruction itineraries for integer instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79436 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| bc9b754091ea281e769e487f396b40f6675b9edb |
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15-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Turn on if-conversion for thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79084 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 6d3d9c3fc3b98e9c12ca38acaffa77cf02deffe6 |
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13-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Finalize itineraries for cortex-a8 integer multiply
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78908 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 546952fd600ddba3f1eb6d4f93ff4eb42821a962 |
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12-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78736 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| bcf81629b85218ba86d9a4b4fdd06d4c182ba9a0 |
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10-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Checkpoint scheduling itinerary changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 7fdf962e5c8c58650b08e25ba2443f3252674b3d |
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22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
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| 8557c2bcb8002169d890eb8485e9a1d7219e4343 |
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19-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMScheduleV6.td
|