ARMDisassembler.cpp revision 8e1e60b5f8fd9c6233bdb8814ee40887555a0594 
1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#define DEBUG_TYPE "arm-disassembler"
11
12#include "ARMDisassembler.h"
13#include "ARM.h"
14#include "ARMRegisterInfo.h"
15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
17#include "llvm/MC/EDInstInfo.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCContext.h"
21#include "llvm/Target/TargetRegistry.h"
22#include "llvm/Support/Debug.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/raw_ostream.h"
26
27// Pull DecodeStatus and its enum values into the global namespace.
28typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
29#define Success llvm::MCDisassembler::Success
30#define Unpredictable llvm::MCDisassembler::SoftFail
31#define Fail llvm::MCDisassembler::Fail
32
33// Helper macro to perform setwise reduction of the current running status
34// and another status, and return if the new status is Fail.
35#define CHECK(S,X) do {                           \
36    S = (DecodeStatus) ((int)S & (X));            \
37    if (S == Fail) return Fail;                   \
38  } while(0)
39
40// Forward declare these because the autogenerated code will reference them.
41// Definitions are further down.
42static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
43                                   uint64_t Address, const void *Decoder);
44static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
45                                               unsigned RegNo, uint64_t Address,
46                                               const void *Decoder);
47static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
48                                   uint64_t Address, const void *Decoder);
49static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
50                                   uint64_t Address, const void *Decoder);
51static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
52                                   uint64_t Address, const void *Decoder);
53static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
54                                   uint64_t Address, const void *Decoder);
55static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
56                                   uint64_t Address, const void *Decoder);
57static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
58                                   uint64_t Address, const void *Decoder);
59static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
60                                                unsigned RegNo,
61                                                uint64_t Address,
62                                                const void *Decoder);
63static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
64                                   uint64_t Address, const void *Decoder);
65
66static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
67                               uint64_t Address, const void *Decoder);
68static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
69                               uint64_t Address, const void *Decoder);
70static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
71                               uint64_t Address, const void *Decoder);
72static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
73                               uint64_t Address, const void *Decoder);
74static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
75                               uint64_t Address, const void *Decoder);
76static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
77                               uint64_t Address, const void *Decoder);
78static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
79                               uint64_t Address, const void *Decoder);
80
81static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
82                               uint64_t Address, const void *Decoder);
83static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
84                               uint64_t Address, const void *Decoder);
85static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
86                                                  unsigned Insn,
87                                                  uint64_t Address,
88                                                  const void *Decoder);
89static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
90                               uint64_t Address, const void *Decoder);
91static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
92                               uint64_t Address, const void *Decoder);
93static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
94                               uint64_t Address, const void *Decoder);
95static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
96                               uint64_t Address, const void *Decoder);
97
98static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
99                                                  unsigned Insn,
100                                                  uint64_t Adddress,
101                                                  const void *Decoder);
102static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
103                               uint64_t Address, const void *Decoder);
104static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
105                               uint64_t Address, const void *Decoder);
106static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
107                               uint64_t Address, const void *Decoder);
108static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
109                               uint64_t Address, const void *Decoder);
110static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
111                               uint64_t Address, const void *Decoder);
112static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
113                               uint64_t Address, const void *Decoder);
114static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
115                               uint64_t Address, const void *Decoder);
116static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
117                               uint64_t Address, const void *Decoder);
118static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
119                               uint64_t Address, const void *Decoder);
120static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
121                               uint64_t Address, const void *Decoder);
122static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
123                               uint64_t Address, const void *Decoder);
124static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
125                               uint64_t Address, const void *Decoder);
126static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
127                               uint64_t Address, const void *Decoder);
128static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
129                               uint64_t Address, const void *Decoder);
130static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
131                               uint64_t Address, const void *Decoder);
132static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
133                               uint64_t Address, const void *Decoder);
134static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
135                               uint64_t Address, const void *Decoder);
136static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
137                               uint64_t Address, const void *Decoder);
138static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
139                               uint64_t Address, const void *Decoder);
140static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
141                               uint64_t Address, const void *Decoder);
142static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
143                               uint64_t Address, const void *Decoder);
144static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
145                               uint64_t Address, const void *Decoder);
146static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
147                               uint64_t Address, const void *Decoder);
148static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
149                               uint64_t Address, const void *Decoder);
150static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
151                               uint64_t Address, const void *Decoder);
152static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
153                               uint64_t Address, const void *Decoder);
154static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
155                               uint64_t Address, const void *Decoder);
156static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
157                               uint64_t Address, const void *Decoder);
158static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
159                               uint64_t Address, const void *Decoder);
160static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
161                               uint64_t Address, const void *Decoder);
162static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
163                               uint64_t Address, const void *Decoder);
164static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
165                               uint64_t Address, const void *Decoder);
166static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
167                               uint64_t Address, const void *Decoder);
168static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
169                               uint64_t Address, const void *Decoder);
170static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
171                               uint64_t Address, const void *Decoder);
172static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
173                               uint64_t Address, const void *Decoder);
174static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
175                               uint64_t Address, const void *Decoder);
176static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
177                               uint64_t Address, const void *Decoder);
178static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
179                               uint64_t Address, const void *Decoder);
180static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
181                               uint64_t Address, const void *Decoder);
182static DecodeStatus DecodeCPSIMod(llvm::MCInst &Inst, unsigned Insn,
183                               uint64_t Address, const void *Decoder);
184
185static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
186                               uint64_t Address, const void *Decoder);
187static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
188                               uint64_t Address, const void *Decoder);
189static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
190                               uint64_t Address, const void *Decoder);
191static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
192                               uint64_t Address, const void *Decoder);
193static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
194                               uint64_t Address, const void *Decoder);
195static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
196                               uint64_t Address, const void *Decoder);
197static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
198                               uint64_t Address, const void *Decoder);
199static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
200                               uint64_t Address, const void *Decoder);
201static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
202                               uint64_t Address, const void *Decoder);
203static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
204                               uint64_t Address, const void *Decoder);
205static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
206                               uint64_t Address, const void *Decoder);
207static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
208                               uint64_t Address, const void *Decoder);
209static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
210                               uint64_t Address, const void *Decoder);
211static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
212                               uint64_t Address, const void *Decoder);
213static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
214                               uint64_t Address, const void *Decoder);
215static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
216                                uint64_t Address, const void *Decoder);
217static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
218                                uint64_t Address, const void *Decoder);
219static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
220                                uint64_t Address, const void *Decoder);
221static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
222                                uint64_t Address, const void *Decoder);
223static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
224                                uint64_t Address, const void *Decoder);
225static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
226                                uint64_t Address, const void *Decoder);
227static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
228                                uint64_t Address, const void *Decoder);
229static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
230                                uint64_t Address, const void *Decoder);
231
232#include "ARMGenDisassemblerTables.inc"
233#include "ARMGenInstrInfo.inc"
234#include "ARMGenEDInfo.inc"
235
236using namespace llvm;
237
238static MCDisassembler *createARMDisassembler(const Target &T) {
239  return new ARMDisassembler;
240}
241
242static MCDisassembler *createThumbDisassembler(const Target &T) {
243  return new ThumbDisassembler;
244}
245
246EDInstInfo *ARMDisassembler::getEDInfo() const {
247  return instInfoARM;
248}
249
250EDInstInfo *ThumbDisassembler::getEDInfo() const {
251  return instInfoARM;
252}
253
254DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
255                                             const MemoryObject &Region,
256                                             uint64_t Address,
257                                             raw_ostream &os) const {
258  uint8_t bytes[4];
259
260  // We want to read exactly 4 bytes of data.
261  if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
262    return Fail;
263
264  // Encoded as a small-endian 32-bit word in the stream.
265  uint32_t insn = (bytes[3] << 24) |
266                  (bytes[2] << 16) |
267                  (bytes[1] <<  8) |
268                  (bytes[0] <<  0);
269
270  // Calling the auto-generated decoder function.
271  DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this);
272  if (result != Fail) {
273    Size = 4;
274    return result;
275  }
276
277  // Instructions that are shared between ARM and Thumb modes.
278  // FIXME: This shouldn't really exist.  It's an artifact of the
279  // fact that we fail to encode a few instructions properly for Thumb.
280  MI.clear();
281  result = decodeCommonInstruction32(MI, insn, Address, this);
282  if (result != Fail) {
283    Size = 4;
284    return result;
285  }
286
287  // VFP and NEON instructions, similarly, are shared between ARM
288  // and Thumb modes.
289  MI.clear();
290  result = decodeVFPInstruction32(MI, insn, Address, this);
291  if (result != Fail) {
292    Size = 4;
293    return result;
294  }
295
296  MI.clear();
297  result = decodeNEONDataInstruction32(MI, insn, Address, this);
298  if (result != Fail) {
299    Size = 4;
300    // Add a fake predicate operand, because we share these instruction
301    // definitions with Thumb2 where these instructions are predicable.
302    if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
303    return result;
304  }
305
306  MI.clear();
307  result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this);
308  if (result != Fail) {
309    Size = 4;
310    // Add a fake predicate operand, because we share these instruction
311    // definitions with Thumb2 where these instructions are predicable.
312    if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
313    return result;
314  }
315
316  MI.clear();
317  result = decodeNEONDupInstruction32(MI, insn, Address, this);
318  if (result != Fail) {
319    Size = 4;
320    // Add a fake predicate operand, because we share these instruction
321    // definitions with Thumb2 where these instructions are predicable.
322    if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
323    return result;
324  }
325
326  MI.clear();
327
328  return Fail;
329}
330
331namespace llvm {
332extern MCInstrDesc ARMInsts[];
333}
334
335// Thumb1 instructions don't have explicit S bits.  Rather, they
336// implicitly set CPSR.  Since it's not represented in the encoding, the
337// auto-generated decoder won't inject the CPSR operand.  We need to fix
338// that as a post-pass.
339static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
340  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
341  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
342  MCInst::iterator I = MI.begin();
343  for (unsigned i = 0; i < NumOps; ++i, ++I) {
344    if (I == MI.end()) break;
345    if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
346      if (i > 0 && OpInfo[i-1].isPredicate()) continue;
347      MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
348      return;
349    }
350  }
351
352  MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
353}
354
355// Most Thumb instructions don't have explicit predicates in the
356// encoding, but rather get their predicates from IT context.  We need
357// to fix up the predicate operands using this context information as a
358// post-pass.
359void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
360  // A few instructions actually have predicates encoded in them.  Don't
361  // try to overwrite it if we're seeing one of those.
362  switch (MI.getOpcode()) {
363    case ARM::tBcc:
364    case ARM::t2Bcc:
365      return;
366    default:
367      break;
368  }
369
370  // If we're in an IT block, base the predicate on that.  Otherwise,
371  // assume a predicate of AL.
372  unsigned CC;
373  if (!ITBlock.empty()) {
374    CC = ITBlock.back();
375    ITBlock.pop_back();
376  } else
377    CC = ARMCC::AL;
378
379  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
380  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
381  MCInst::iterator I = MI.begin();
382  for (unsigned i = 0; i < NumOps; ++i, ++I) {
383    if (I == MI.end()) break;
384    if (OpInfo[i].isPredicate()) {
385      I = MI.insert(I, MCOperand::CreateImm(CC));
386      ++I;
387      if (CC == ARMCC::AL)
388        MI.insert(I, MCOperand::CreateReg(0));
389      else
390        MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
391      return;
392    }
393  }
394
395  I = MI.insert(I, MCOperand::CreateImm(CC));
396  ++I;
397  if (CC == ARMCC::AL)
398    MI.insert(I, MCOperand::CreateReg(0));
399  else
400    MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
401}
402
403// Thumb VFP instructions are a special case.  Because we share their
404// encodings between ARM and Thumb modes, and they are predicable in ARM
405// mode, the auto-generated decoder will give them an (incorrect)
406// predicate operand.  We need to rewrite these operands based on the IT
407// context as a post-pass.
408void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
409  unsigned CC;
410  if (!ITBlock.empty()) {
411    CC = ITBlock.back();
412    ITBlock.pop_back();
413  } else
414    CC = ARMCC::AL;
415
416  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
417  MCInst::iterator I = MI.begin();
418  for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) {
419    if (OpInfo[i].isPredicate() ) {
420      I->setImm(CC);
421      ++I;
422      if (CC == ARMCC::AL)
423        I->setReg(0);
424      else
425        I->setReg(ARM::CPSR);
426      return;
427    }
428  }
429}
430
431DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
432                                               const MemoryObject &Region,
433                                               uint64_t Address,
434                                               raw_ostream &os) const {
435  uint8_t bytes[4];
436
437  // We want to read exactly 2 bytes of data.
438  if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1)
439    return Fail;
440
441  uint16_t insn16 = (bytes[1] << 8) | bytes[0];
442  DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this);
443  if (result != Fail) {
444    Size = 2;
445    AddThumbPredicate(MI);
446    return result;
447  }
448
449  MI.clear();
450  result = decodeThumbSBitInstruction16(MI, insn16, Address, this);
451  if (result) {
452    Size = 2;
453    bool InITBlock = !ITBlock.empty();
454    AddThumbPredicate(MI);
455    AddThumb1SBit(MI, InITBlock);
456    return result;
457  }
458
459  MI.clear();
460  result = decodeThumb2Instruction16(MI, insn16, Address, this);
461  if (result != Fail) {
462    Size = 2;
463    AddThumbPredicate(MI);
464
465    // If we find an IT instruction, we need to parse its condition
466    // code and mask operands so that we can apply them correctly
467    // to the subsequent instructions.
468    if (MI.getOpcode() == ARM::t2IT) {
469      unsigned firstcond = MI.getOperand(0).getImm();
470      uint32_t mask = MI.getOperand(1).getImm();
471      unsigned zeros = CountTrailingZeros_32(mask);
472      mask >>= zeros+1;
473
474      for (unsigned i = 0; i < 4 - (zeros+1); ++i) {
475        if (firstcond ^ (mask & 1))
476          ITBlock.push_back(firstcond ^ 1);
477        else
478          ITBlock.push_back(firstcond);
479        mask >>= 1;
480      }
481      ITBlock.push_back(firstcond);
482    }
483
484    return result;
485  }
486
487  // We want to read exactly 4 bytes of data.
488  if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
489    return Fail;
490
491  uint32_t insn32 = (bytes[3] <<  8) |
492                    (bytes[2] <<  0) |
493                    (bytes[1] << 24) |
494                    (bytes[0] << 16);
495  MI.clear();
496  result = decodeThumbInstruction32(MI, insn32, Address, this);
497  if (result != Fail) {
498    Size = 4;
499    bool InITBlock = ITBlock.size();
500    AddThumbPredicate(MI);
501    AddThumb1SBit(MI, InITBlock);
502    return result;
503  }
504
505  MI.clear();
506  result = decodeThumb2Instruction32(MI, insn32, Address, this);
507  if (result != Fail) {
508    Size = 4;
509    AddThumbPredicate(MI);
510    return result;
511  }
512
513  MI.clear();
514  result = decodeCommonInstruction32(MI, insn32, Address, this);
515  if (result != Fail) {
516    Size = 4;
517    AddThumbPredicate(MI);
518    return result;
519  }
520
521  MI.clear();
522  result = decodeVFPInstruction32(MI, insn32, Address, this);
523  if (result != Fail) {
524    Size = 4;
525    UpdateThumbVFPPredicate(MI);
526    return result;
527  }
528
529  MI.clear();
530  result = decodeNEONDupInstruction32(MI, insn32, Address, this);
531  if (result != Fail) {
532    Size = 4;
533    AddThumbPredicate(MI);
534    return result;
535  }
536
537  if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
538    MI.clear();
539    uint32_t NEONLdStInsn = insn32;
540    NEONLdStInsn &= 0xF0FFFFFF;
541    NEONLdStInsn |= 0x04000000;
542    result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this);
543    if (result != Fail) {
544      Size = 4;
545      AddThumbPredicate(MI);
546      return result;
547    }
548  }
549
550  if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
551    MI.clear();
552    uint32_t NEONDataInsn = insn32;
553    NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
554    NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
555    NEONDataInsn |= 0x12000000; // Set bits 28 and 25
556    result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this);
557    if (result != Fail) {
558      Size = 4;
559      AddThumbPredicate(MI);
560      return result;
561    }
562  }
563
564  return Fail;
565}
566
567
568extern "C" void LLVMInitializeARMDisassembler() {
569  TargetRegistry::RegisterMCDisassembler(TheARMTarget,
570                                         createARMDisassembler);
571  TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
572                                         createThumbDisassembler);
573}
574
575static const unsigned GPRDecoderTable[] = {
576  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
577  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
578  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
579  ARM::R12, ARM::SP, ARM::LR, ARM::PC
580};
581
582static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
583                                   uint64_t Address, const void *Decoder) {
584  if (RegNo > 15)
585    return Fail;
586
587  unsigned Register = GPRDecoderTable[RegNo];
588  Inst.addOperand(MCOperand::CreateReg(Register));
589  return Success;
590}
591
592static DecodeStatus
593DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
594                           uint64_t Address, const void *Decoder) {
595  if (RegNo == 15) return Fail;
596  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
597}
598
599static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
600                                   uint64_t Address, const void *Decoder) {
601  if (RegNo > 7)
602    return Fail;
603  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
604}
605
606static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
607                                   uint64_t Address, const void *Decoder) {
608  unsigned Register = 0;
609  switch (RegNo) {
610    case 0:
611      Register = ARM::R0;
612      break;
613    case 1:
614      Register = ARM::R1;
615      break;
616    case 2:
617      Register = ARM::R2;
618      break;
619    case 3:
620      Register = ARM::R3;
621      break;
622    case 9:
623      Register = ARM::R9;
624      break;
625    case 12:
626      Register = ARM::R12;
627      break;
628    default:
629      return Fail;
630    }
631
632  Inst.addOperand(MCOperand::CreateReg(Register));
633  return Success;
634}
635
636static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
637                                   uint64_t Address, const void *Decoder) {
638  if (RegNo == 13 || RegNo == 15) return Fail;
639  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
640}
641
642static const unsigned SPRDecoderTable[] = {
643     ARM::S0,  ARM::S1,  ARM::S2,  ARM::S3,
644     ARM::S4,  ARM::S5,  ARM::S6,  ARM::S7,
645     ARM::S8,  ARM::S9, ARM::S10, ARM::S11,
646    ARM::S12, ARM::S13, ARM::S14, ARM::S15,
647    ARM::S16, ARM::S17, ARM::S18, ARM::S19,
648    ARM::S20, ARM::S21, ARM::S22, ARM::S23,
649    ARM::S24, ARM::S25, ARM::S26, ARM::S27,
650    ARM::S28, ARM::S29, ARM::S30, ARM::S31
651};
652
653static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
654                                   uint64_t Address, const void *Decoder) {
655  if (RegNo > 31)
656    return Fail;
657
658  unsigned Register = SPRDecoderTable[RegNo];
659  Inst.addOperand(MCOperand::CreateReg(Register));
660  return Success;
661}
662
663static const unsigned DPRDecoderTable[] = {
664     ARM::D0,  ARM::D1,  ARM::D2,  ARM::D3,
665     ARM::D4,  ARM::D5,  ARM::D6,  ARM::D7,
666     ARM::D8,  ARM::D9, ARM::D10, ARM::D11,
667    ARM::D12, ARM::D13, ARM::D14, ARM::D15,
668    ARM::D16, ARM::D17, ARM::D18, ARM::D19,
669    ARM::D20, ARM::D21, ARM::D22, ARM::D23,
670    ARM::D24, ARM::D25, ARM::D26, ARM::D27,
671    ARM::D28, ARM::D29, ARM::D30, ARM::D31
672};
673
674static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
675                                   uint64_t Address, const void *Decoder) {
676  if (RegNo > 31)
677    return Fail;
678
679  unsigned Register = DPRDecoderTable[RegNo];
680  Inst.addOperand(MCOperand::CreateReg(Register));
681  return Success;
682}
683
684static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
685                                   uint64_t Address, const void *Decoder) {
686  if (RegNo > 7)
687    return Fail;
688  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
689}
690
691static DecodeStatus
692DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
693                            uint64_t Address, const void *Decoder) {
694  if (RegNo > 15)
695    return Fail;
696  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
697}
698
699static const unsigned QPRDecoderTable[] = {
700     ARM::Q0,  ARM::Q1,  ARM::Q2,  ARM::Q3,
701     ARM::Q4,  ARM::Q5,  ARM::Q6,  ARM::Q7,
702     ARM::Q8,  ARM::Q9, ARM::Q10, ARM::Q11,
703    ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
704};
705
706
707static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
708                                   uint64_t Address, const void *Decoder) {
709  if (RegNo > 31)
710    return Fail;
711  RegNo >>= 1;
712
713  unsigned Register = QPRDecoderTable[RegNo];
714  Inst.addOperand(MCOperand::CreateReg(Register));
715  return Success;
716}
717
718static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
719                               uint64_t Address, const void *Decoder) {
720  if (Val == 0xF) return Fail;
721  // AL predicate is not allowed on Thumb1 branches.
722  if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
723    return Fail;
724  Inst.addOperand(MCOperand::CreateImm(Val));
725  if (Val == ARMCC::AL) {
726    Inst.addOperand(MCOperand::CreateReg(0));
727  } else
728    Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
729  return Success;
730}
731
732static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
733                               uint64_t Address, const void *Decoder) {
734  if (Val)
735    Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
736  else
737    Inst.addOperand(MCOperand::CreateReg(0));
738  return Success;
739}
740
741static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
742                               uint64_t Address, const void *Decoder) {
743  uint32_t imm = Val & 0xFF;
744  uint32_t rot = (Val & 0xF00) >> 7;
745  uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
746  Inst.addOperand(MCOperand::CreateImm(rot_imm));
747  return Success;
748}
749
750static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
751                               uint64_t Address, const void *Decoder) {
752  Val <<= 2;
753  Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val)));
754  return Success;
755}
756
757static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
758                               uint64_t Address, const void *Decoder) {
759  DecodeStatus S = Success;
760
761  unsigned Rm = fieldFromInstruction32(Val, 0, 4);
762  unsigned type = fieldFromInstruction32(Val, 5, 2);
763  unsigned imm = fieldFromInstruction32(Val, 7, 5);
764
765  // Register-immediate
766  CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
767
768  ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
769  switch (type) {
770    case 0:
771      Shift = ARM_AM::lsl;
772      break;
773    case 1:
774      Shift = ARM_AM::lsr;
775      break;
776    case 2:
777      Shift = ARM_AM::asr;
778      break;
779    case 3:
780      Shift = ARM_AM::ror;
781      break;
782  }
783
784  if (Shift == ARM_AM::ror && imm == 0)
785    Shift = ARM_AM::rrx;
786
787  unsigned Op = Shift | (imm << 3);
788  Inst.addOperand(MCOperand::CreateImm(Op));
789
790  return S;
791}
792
793static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
794                               uint64_t Address, const void *Decoder) {
795  DecodeStatus S = Success;
796
797  unsigned Rm = fieldFromInstruction32(Val, 0, 4);
798  unsigned type = fieldFromInstruction32(Val, 5, 2);
799  unsigned Rs = fieldFromInstruction32(Val, 8, 4);
800
801  // Register-register
802  CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
803  CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder));
804
805  ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
806  switch (type) {
807    case 0:
808      Shift = ARM_AM::lsl;
809      break;
810    case 1:
811      Shift = ARM_AM::lsr;
812      break;
813    case 2:
814      Shift = ARM_AM::asr;
815      break;
816    case 3:
817      Shift = ARM_AM::ror;
818      break;
819  }
820
821  Inst.addOperand(MCOperand::CreateImm(Shift));
822
823  return S;
824}
825
826static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
827                                 uint64_t Address, const void *Decoder) {
828  DecodeStatus S = Success;
829
830  // Empty register lists are not allowed.
831  if (CountPopulation_32(Val) == 0) return Fail;
832  for (unsigned i = 0; i < 16; ++i) {
833    if (Val & (1 << i)) {
834      CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder));
835    }
836  }
837
838  return S;
839}
840
841static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
842                                 uint64_t Address, const void *Decoder) {
843  DecodeStatus S = Success;
844
845  unsigned Vd = fieldFromInstruction32(Val, 8, 4);
846  unsigned regs = Val & 0xFF;
847
848  CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder));
849  for (unsigned i = 0; i < (regs - 1); ++i) {
850    CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder));
851  }
852
853  return S;
854}
855
856static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
857                                 uint64_t Address, const void *Decoder) {
858  DecodeStatus S = Success;
859
860  unsigned Vd = fieldFromInstruction32(Val, 8, 4);
861  unsigned regs = (Val & 0xFF) / 2;
862
863  CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder));
864  for (unsigned i = 0; i < (regs - 1); ++i) {
865    CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder));
866  }
867
868  return S;
869}
870
871static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
872                                      uint64_t Address, const void *Decoder) {
873  // This operand encodes a mask of contiguous zeros between a specified MSB
874  // and LSB.  To decode it, we create the mask of all bits MSB-and-lower,
875  // the mask of all bits LSB-and-lower, and then xor them to create
876  // the mask of that's all ones on [msb, lsb].  Finally we not it to
877  // create the final mask.
878  unsigned msb = fieldFromInstruction32(Val, 5, 5);
879  unsigned lsb = fieldFromInstruction32(Val, 0, 5);
880  uint32_t msb_mask = (1 << (msb+1)) - 1;
881  uint32_t lsb_mask = (1 << lsb) - 1;
882  Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
883  return Success;
884}
885
886static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
887                                  uint64_t Address, const void *Decoder) {
888  DecodeStatus S = Success;
889
890  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
891  unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
892  unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
893  unsigned imm = fieldFromInstruction32(Insn, 0, 8);
894  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
895  unsigned U = fieldFromInstruction32(Insn, 23, 1);
896
897  switch (Inst.getOpcode()) {
898    case ARM::LDC_OFFSET:
899    case ARM::LDC_PRE:
900    case ARM::LDC_POST:
901    case ARM::LDC_OPTION:
902    case ARM::LDCL_OFFSET:
903    case ARM::LDCL_PRE:
904    case ARM::LDCL_POST:
905    case ARM::LDCL_OPTION:
906    case ARM::STC_OFFSET:
907    case ARM::STC_PRE:
908    case ARM::STC_POST:
909    case ARM::STC_OPTION:
910    case ARM::STCL_OFFSET:
911    case ARM::STCL_PRE:
912    case ARM::STCL_POST:
913    case ARM::STCL_OPTION:
914      if (coproc == 0xA || coproc == 0xB)
915        return Fail;
916      break;
917    default:
918      break;
919  }
920
921  Inst.addOperand(MCOperand::CreateImm(coproc));
922  Inst.addOperand(MCOperand::CreateImm(CRd));
923  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
924  switch (Inst.getOpcode()) {
925    case ARM::LDC_OPTION:
926    case ARM::LDCL_OPTION:
927    case ARM::LDC2_OPTION:
928    case ARM::LDC2L_OPTION:
929    case ARM::STC_OPTION:
930    case ARM::STCL_OPTION:
931    case ARM::STC2_OPTION:
932    case ARM::STC2L_OPTION:
933    case ARM::LDCL_POST:
934    case ARM::STCL_POST:
935    case ARM::LDC2L_POST:
936    case ARM::STC2L_POST:
937      break;
938    default:
939      Inst.addOperand(MCOperand::CreateReg(0));
940      break;
941  }
942
943  unsigned P = fieldFromInstruction32(Insn, 24, 1);
944  unsigned W = fieldFromInstruction32(Insn, 21, 1);
945
946  bool writeback = (P == 0) || (W == 1);
947  unsigned idx_mode = 0;
948  if (P && writeback)
949    idx_mode = ARMII::IndexModePre;
950  else if (!P && writeback)
951    idx_mode = ARMII::IndexModePost;
952
953  switch (Inst.getOpcode()) {
954    case ARM::LDCL_POST:
955    case ARM::STCL_POST:
956    case ARM::LDC2L_POST:
957    case ARM::STC2L_POST:
958      imm |= U << 8;
959    case ARM::LDC_OPTION:
960    case ARM::LDCL_OPTION:
961    case ARM::LDC2_OPTION:
962    case ARM::LDC2L_OPTION:
963    case ARM::STC_OPTION:
964    case ARM::STCL_OPTION:
965    case ARM::STC2_OPTION:
966    case ARM::STC2L_OPTION:
967      Inst.addOperand(MCOperand::CreateImm(imm));
968      break;
969    default:
970      if (U)
971        Inst.addOperand(MCOperand::CreateImm(
972            ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
973      else
974        Inst.addOperand(MCOperand::CreateImm(
975            ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
976      break;
977  }
978
979  switch (Inst.getOpcode()) {
980    case ARM::LDC_OFFSET:
981    case ARM::LDC_PRE:
982    case ARM::LDC_POST:
983    case ARM::LDC_OPTION:
984    case ARM::LDCL_OFFSET:
985    case ARM::LDCL_PRE:
986    case ARM::LDCL_POST:
987    case ARM::LDCL_OPTION:
988    case ARM::STC_OFFSET:
989    case ARM::STC_PRE:
990    case ARM::STC_POST:
991    case ARM::STC_OPTION:
992    case ARM::STCL_OFFSET:
993    case ARM::STCL_PRE:
994    case ARM::STCL_POST:
995    case ARM::STCL_OPTION:
996      CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
997      break;
998    default:
999      break;
1000  }
1001
1002  return S;
1003}
1004
1005static DecodeStatus
1006DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1007                              uint64_t Address, const void *Decoder) {
1008  DecodeStatus S = Success;
1009
1010  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1011  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1012  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1013  unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1014  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1015  unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1016  unsigned P = fieldFromInstruction32(Insn, 24, 1);
1017  unsigned W = fieldFromInstruction32(Insn, 21, 1);
1018
1019  // On stores, the writeback operand precedes Rt.
1020  switch (Inst.getOpcode()) {
1021    case ARM::STR_POST_IMM:
1022    case ARM::STR_POST_REG:
1023    case ARM::STRB_POST_IMM:
1024    case ARM::STRB_POST_REG:
1025    case ARM::STRT_POST_REG:
1026    case ARM::STRT_POST_IMM:
1027    case ARM::STRBT_POST_REG:
1028    case ARM::STRBT_POST_IMM:
1029      CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1030      break;
1031    default:
1032      break;
1033  }
1034
1035  CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
1036
1037  // On loads, the writeback operand comes after Rt.
1038  switch (Inst.getOpcode()) {
1039    case ARM::LDR_POST_IMM:
1040    case ARM::LDR_POST_REG:
1041    case ARM::LDRB_POST_IMM:
1042    case ARM::LDRB_POST_REG:
1043    case ARM::LDR_PRE:
1044    case ARM::LDRB_PRE:
1045    case ARM::LDRBT_POST_REG:
1046    case ARM::LDRBT_POST_IMM:
1047    case ARM::LDRT_POST_REG:
1048    case ARM::LDRT_POST_IMM:
1049      CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1050      break;
1051    default:
1052      break;
1053  }
1054
1055  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1056
1057  ARM_AM::AddrOpc Op = ARM_AM::add;
1058  if (!fieldFromInstruction32(Insn, 23, 1))
1059    Op = ARM_AM::sub;
1060
1061  bool writeback = (P == 0) || (W == 1);
1062  unsigned idx_mode = 0;
1063  if (P && writeback)
1064    idx_mode = ARMII::IndexModePre;
1065  else if (!P && writeback)
1066    idx_mode = ARMII::IndexModePost;
1067
1068  if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE
1069
1070  if (reg) {
1071    CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
1072    ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1073    switch( fieldFromInstruction32(Insn, 5, 2)) {
1074      case 0:
1075        Opc = ARM_AM::lsl;
1076        break;
1077      case 1:
1078        Opc = ARM_AM::lsr;
1079        break;
1080      case 2:
1081        Opc = ARM_AM::asr;
1082        break;
1083      case 3:
1084        Opc = ARM_AM::ror;
1085        break;
1086      default:
1087        return Fail;
1088    }
1089    unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1090    unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1091
1092    Inst.addOperand(MCOperand::CreateImm(imm));
1093  } else {
1094    Inst.addOperand(MCOperand::CreateReg(0));
1095    unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1096    Inst.addOperand(MCOperand::CreateImm(tmp));
1097  }
1098
1099  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1100
1101  return S;
1102}
1103
1104static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
1105                                  uint64_t Address, const void *Decoder) {
1106  DecodeStatus S = Success;
1107
1108  unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1109  unsigned Rm = fieldFromInstruction32(Val,  0, 4);
1110  unsigned type = fieldFromInstruction32(Val, 5, 2);
1111  unsigned imm = fieldFromInstruction32(Val, 7, 5);
1112  unsigned U = fieldFromInstruction32(Val, 12, 1);
1113
1114  ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1115  switch (type) {
1116    case 0:
1117      ShOp = ARM_AM::lsl;
1118      break;
1119    case 1:
1120      ShOp = ARM_AM::lsr;
1121      break;
1122    case 2:
1123      ShOp = ARM_AM::asr;
1124      break;
1125    case 3:
1126      ShOp = ARM_AM::ror;
1127      break;
1128  }
1129
1130  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1131  CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1132  unsigned shift;
1133  if (U)
1134    shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1135  else
1136    shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1137  Inst.addOperand(MCOperand::CreateImm(shift));
1138
1139  return S;
1140}
1141
1142static DecodeStatus
1143DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1144                           uint64_t Address, const void *Decoder) {
1145  DecodeStatus S = Success;
1146
1147  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1148  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1149  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1150  unsigned type = fieldFromInstruction32(Insn, 22, 1);
1151  unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1152  unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1153  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1154  unsigned W = fieldFromInstruction32(Insn, 21, 1);
1155  unsigned P = fieldFromInstruction32(Insn, 24, 1);
1156
1157  bool writeback = (W == 1) | (P == 0);
1158
1159  // For {LD,ST}RD, Rt must be even, else undefined.
1160  switch (Inst.getOpcode()) {
1161    case ARM::STRD:
1162    case ARM::STRD_PRE:
1163    case ARM::STRD_POST:
1164    case ARM::LDRD:
1165    case ARM::LDRD_PRE:
1166    case ARM::LDRD_POST:
1167      if (Rt & 0x1) return Fail;
1168      break;
1169  default:
1170    break;
1171  }
1172
1173  if (writeback) { // Writeback
1174    if (P)
1175      U |= ARMII::IndexModePre << 9;
1176    else
1177      U |= ARMII::IndexModePost << 9;
1178
1179    // On stores, the writeback operand precedes Rt.
1180    switch (Inst.getOpcode()) {
1181    case ARM::STRD:
1182    case ARM::STRD_PRE:
1183    case ARM::STRD_POST:
1184    case ARM::STRH:
1185    case ARM::STRH_PRE:
1186    case ARM::STRH_POST:
1187      CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1188      break;
1189    default:
1190      break;
1191    }
1192  }
1193
1194  CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
1195  switch (Inst.getOpcode()) {
1196    case ARM::STRD:
1197    case ARM::STRD_PRE:
1198    case ARM::STRD_POST:
1199    case ARM::LDRD:
1200    case ARM::LDRD_PRE:
1201    case ARM::LDRD_POST:
1202      CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
1203      break;
1204    default:
1205      break;
1206  }
1207
1208  if (writeback) {
1209    // On loads, the writeback operand comes after Rt.
1210    switch (Inst.getOpcode()) {
1211    case ARM::LDRD:
1212    case ARM::LDRD_PRE:
1213    case ARM::LDRD_POST:
1214    case ARM::LDRH:
1215    case ARM::LDRH_PRE:
1216    case ARM::LDRH_POST:
1217    case ARM::LDRSH:
1218    case ARM::LDRSH_PRE:
1219    case ARM::LDRSH_POST:
1220    case ARM::LDRSB:
1221    case ARM::LDRSB_PRE:
1222    case ARM::LDRSB_POST:
1223    case ARM::LDRHTr:
1224    case ARM::LDRSBTr:
1225      CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1226      break;
1227    default:
1228      break;
1229    }
1230  }
1231
1232  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1233
1234  if (type) {
1235    Inst.addOperand(MCOperand::CreateReg(0));
1236    Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1237  } else {
1238    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1239    Inst.addOperand(MCOperand::CreateImm(U));
1240  }
1241
1242  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1243
1244  return S;
1245}
1246
1247static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
1248                                 uint64_t Address, const void *Decoder) {
1249  DecodeStatus S = Success;
1250
1251  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1252  unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1253
1254  switch (mode) {
1255    case 0:
1256      mode = ARM_AM::da;
1257      break;
1258    case 1:
1259      mode = ARM_AM::ia;
1260      break;
1261    case 2:
1262      mode = ARM_AM::db;
1263      break;
1264    case 3:
1265      mode = ARM_AM::ib;
1266      break;
1267  }
1268
1269  Inst.addOperand(MCOperand::CreateImm(mode));
1270  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1271
1272  return S;
1273}
1274
1275static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
1276                                  unsigned Insn,
1277                                  uint64_t Address, const void *Decoder) {
1278  DecodeStatus S = Success;
1279
1280  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1281  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1282  unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1283
1284  if (pred == 0xF) {
1285    switch (Inst.getOpcode()) {
1286      case ARM::LDMDA:
1287        Inst.setOpcode(ARM::RFEDA);
1288        break;
1289      case ARM::LDMDA_UPD:
1290        Inst.setOpcode(ARM::RFEDA_UPD);
1291        break;
1292      case ARM::LDMDB:
1293        Inst.setOpcode(ARM::RFEDB);
1294        break;
1295      case ARM::LDMDB_UPD:
1296        Inst.setOpcode(ARM::RFEDB_UPD);
1297        break;
1298      case ARM::LDMIA:
1299        Inst.setOpcode(ARM::RFEIA);
1300        break;
1301      case ARM::LDMIA_UPD:
1302        Inst.setOpcode(ARM::RFEIA_UPD);
1303        break;
1304      case ARM::LDMIB:
1305        Inst.setOpcode(ARM::RFEIB);
1306        break;
1307      case ARM::LDMIB_UPD:
1308        Inst.setOpcode(ARM::RFEIB_UPD);
1309        break;
1310      case ARM::STMDA:
1311        Inst.setOpcode(ARM::SRSDA);
1312        break;
1313      case ARM::STMDA_UPD:
1314        Inst.setOpcode(ARM::SRSDA_UPD);
1315        break;
1316      case ARM::STMDB:
1317        Inst.setOpcode(ARM::SRSDB);
1318        break;
1319      case ARM::STMDB_UPD:
1320        Inst.setOpcode(ARM::SRSDB_UPD);
1321        break;
1322      case ARM::STMIA:
1323        Inst.setOpcode(ARM::SRSIA);
1324        break;
1325      case ARM::STMIA_UPD:
1326        Inst.setOpcode(ARM::SRSIA_UPD);
1327        break;
1328      case ARM::STMIB:
1329        Inst.setOpcode(ARM::SRSIB);
1330        break;
1331      case ARM::STMIB_UPD:
1332        Inst.setOpcode(ARM::SRSIB_UPD);
1333        break;
1334      default:
1335        CHECK(S, Fail);
1336    }
1337
1338    // For stores (which become SRS's, the only operand is the mode.
1339    if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1340      Inst.addOperand(
1341          MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1342      return S;
1343    }
1344
1345    return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1346  }
1347
1348  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1349  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied
1350  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1351  CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder));
1352
1353  return S;
1354}
1355
1356static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1357                                 uint64_t Address, const void *Decoder) {
1358  unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1359  unsigned M = fieldFromInstruction32(Insn, 17, 1);
1360  unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1361  unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1362
1363  DecodeStatus S = Success;
1364
1365  // imod == '01' --> UNPREDICTABLE
1366  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1367  // return failure here.  The '01' imod value is unprintable, so there's
1368  // nothing useful we could do even if we returned UNPREDICTABLE.
1369
1370  if (imod == 1) CHECK(S, Fail);
1371
1372  if (imod && M) {
1373    Inst.setOpcode(ARM::CPS3p);
1374    Inst.addOperand(MCOperand::CreateImm(imod));
1375    Inst.addOperand(MCOperand::CreateImm(iflags));
1376    Inst.addOperand(MCOperand::CreateImm(mode));
1377  } else if (imod && !M) {
1378    Inst.setOpcode(ARM::CPS2p);
1379    Inst.addOperand(MCOperand::CreateImm(imod));
1380    Inst.addOperand(MCOperand::CreateImm(iflags));
1381    if (mode) CHECK(S, Unpredictable);
1382  } else if (!imod && M) {
1383    Inst.setOpcode(ARM::CPS1p);
1384    Inst.addOperand(MCOperand::CreateImm(mode));
1385    if (iflags) CHECK(S, Unpredictable);
1386  } else {
1387    // imod == '00' && M == '0' --> UNPREDICTABLE
1388    Inst.setOpcode(ARM::CPS1p);
1389    Inst.addOperand(MCOperand::CreateImm(mode));
1390    CHECK(S, Unpredictable);
1391  }
1392
1393  return S;
1394}
1395
1396static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
1397                                 uint64_t Address, const void *Decoder) {
1398  DecodeStatus S = Success;
1399
1400  unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1401  unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1402  unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1403  unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1404  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1405
1406  if (pred == 0xF)
1407    return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1408
1409  CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder));
1410  CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder));
1411  CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
1412  CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder));
1413
1414  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1415
1416  return S;
1417}
1418
1419static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
1420                           uint64_t Address, const void *Decoder) {
1421  DecodeStatus S = Success;
1422
1423  unsigned add = fieldFromInstruction32(Val, 12, 1);
1424  unsigned imm = fieldFromInstruction32(Val, 0, 12);
1425  unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1426
1427  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1428
1429  if (!add) imm *= -1;
1430  if (imm == 0 && !add) imm = INT32_MIN;
1431  Inst.addOperand(MCOperand::CreateImm(imm));
1432
1433  return S;
1434}
1435
1436static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
1437                                   uint64_t Address, const void *Decoder) {
1438  DecodeStatus S = Success;
1439
1440  unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1441  unsigned U = fieldFromInstruction32(Val, 8, 1);
1442  unsigned imm = fieldFromInstruction32(Val, 0, 8);
1443
1444  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1445
1446  if (U)
1447    Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1448  else
1449    Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1450
1451  return S;
1452}
1453
1454static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
1455                                   uint64_t Address, const void *Decoder) {
1456  return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1457}
1458
1459static DecodeStatus
1460DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1461                           uint64_t Address, const void *Decoder) {
1462  DecodeStatus S = Success;
1463
1464  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1465  unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1466
1467  if (pred == 0xF) {
1468    Inst.setOpcode(ARM::BLXi);
1469    imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
1470    Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1471    return S;
1472  }
1473
1474  Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1475  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1476
1477  return S;
1478}
1479
1480
1481static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
1482                                 uint64_t Address, const void *Decoder) {
1483  Inst.addOperand(MCOperand::CreateImm(64 - Val));
1484  return Success;
1485}
1486
1487static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
1488                                   uint64_t Address, const void *Decoder) {
1489  DecodeStatus S = Success;
1490
1491  unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1492  unsigned align = fieldFromInstruction32(Val, 4, 2);
1493
1494  CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1495  if (!align)
1496    Inst.addOperand(MCOperand::CreateImm(0));
1497  else
1498    Inst.addOperand(MCOperand::CreateImm(4 << align));
1499
1500  return S;
1501}
1502
1503static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
1504                                   uint64_t Address, const void *Decoder) {
1505  DecodeStatus S = Success;
1506
1507  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1508  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1509  unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1510  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1511  Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1512  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1513
1514  // First output register
1515  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
1516
1517  // Second output register
1518  switch (Inst.getOpcode()) {
1519    case ARM::VLD1q8:
1520    case ARM::VLD1q16:
1521    case ARM::VLD1q32:
1522    case ARM::VLD1q64:
1523    case ARM::VLD1q8_UPD:
1524    case ARM::VLD1q16_UPD:
1525    case ARM::VLD1q32_UPD:
1526    case ARM::VLD1q64_UPD:
1527    case ARM::VLD1d8T:
1528    case ARM::VLD1d16T:
1529    case ARM::VLD1d32T:
1530    case ARM::VLD1d64T:
1531    case ARM::VLD1d8T_UPD:
1532    case ARM::VLD1d16T_UPD:
1533    case ARM::VLD1d32T_UPD:
1534    case ARM::VLD1d64T_UPD:
1535    case ARM::VLD1d8Q:
1536    case ARM::VLD1d16Q:
1537    case ARM::VLD1d32Q:
1538    case ARM::VLD1d64Q:
1539    case ARM::VLD1d8Q_UPD:
1540    case ARM::VLD1d16Q_UPD:
1541    case ARM::VLD1d32Q_UPD:
1542    case ARM::VLD1d64Q_UPD:
1543    case ARM::VLD2d8:
1544    case ARM::VLD2d16:
1545    case ARM::VLD2d32:
1546    case ARM::VLD2d8_UPD:
1547    case ARM::VLD2d16_UPD:
1548    case ARM::VLD2d32_UPD:
1549    case ARM::VLD2q8:
1550    case ARM::VLD2q16:
1551    case ARM::VLD2q32:
1552    case ARM::VLD2q8_UPD:
1553    case ARM::VLD2q16_UPD:
1554    case ARM::VLD2q32_UPD:
1555    case ARM::VLD3d8:
1556    case ARM::VLD3d16:
1557    case ARM::VLD3d32:
1558    case ARM::VLD3d8_UPD:
1559    case ARM::VLD3d16_UPD:
1560    case ARM::VLD3d32_UPD:
1561    case ARM::VLD4d8:
1562    case ARM::VLD4d16:
1563    case ARM::VLD4d32:
1564    case ARM::VLD4d8_UPD:
1565    case ARM::VLD4d16_UPD:
1566    case ARM::VLD4d32_UPD:
1567      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
1568      break;
1569    case ARM::VLD2b8:
1570    case ARM::VLD2b16:
1571    case ARM::VLD2b32:
1572    case ARM::VLD2b8_UPD:
1573    case ARM::VLD2b16_UPD:
1574    case ARM::VLD2b32_UPD:
1575    case ARM::VLD3q8:
1576    case ARM::VLD3q16:
1577    case ARM::VLD3q32:
1578    case ARM::VLD3q8_UPD:
1579    case ARM::VLD3q16_UPD:
1580    case ARM::VLD3q32_UPD:
1581    case ARM::VLD4q8:
1582    case ARM::VLD4q16:
1583    case ARM::VLD4q32:
1584    case ARM::VLD4q8_UPD:
1585    case ARM::VLD4q16_UPD:
1586    case ARM::VLD4q32_UPD:
1587      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1588    default:
1589      break;
1590  }
1591
1592  // Third output register
1593  switch(Inst.getOpcode()) {
1594    case ARM::VLD1d8T:
1595    case ARM::VLD1d16T:
1596    case ARM::VLD1d32T:
1597    case ARM::VLD1d64T:
1598    case ARM::VLD1d8T_UPD:
1599    case ARM::VLD1d16T_UPD:
1600    case ARM::VLD1d32T_UPD:
1601    case ARM::VLD1d64T_UPD:
1602    case ARM::VLD1d8Q:
1603    case ARM::VLD1d16Q:
1604    case ARM::VLD1d32Q:
1605    case ARM::VLD1d64Q:
1606    case ARM::VLD1d8Q_UPD:
1607    case ARM::VLD1d16Q_UPD:
1608    case ARM::VLD1d32Q_UPD:
1609    case ARM::VLD1d64Q_UPD:
1610    case ARM::VLD2q8:
1611    case ARM::VLD2q16:
1612    case ARM::VLD2q32:
1613    case ARM::VLD2q8_UPD:
1614    case ARM::VLD2q16_UPD:
1615    case ARM::VLD2q32_UPD:
1616    case ARM::VLD3d8:
1617    case ARM::VLD3d16:
1618    case ARM::VLD3d32:
1619    case ARM::VLD3d8_UPD:
1620    case ARM::VLD3d16_UPD:
1621    case ARM::VLD3d32_UPD:
1622    case ARM::VLD4d8:
1623    case ARM::VLD4d16:
1624    case ARM::VLD4d32:
1625    case ARM::VLD4d8_UPD:
1626    case ARM::VLD4d16_UPD:
1627    case ARM::VLD4d32_UPD:
1628      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1629      break;
1630    case ARM::VLD3q8:
1631    case ARM::VLD3q16:
1632    case ARM::VLD3q32:
1633    case ARM::VLD3q8_UPD:
1634    case ARM::VLD3q16_UPD:
1635    case ARM::VLD3q32_UPD:
1636    case ARM::VLD4q8:
1637    case ARM::VLD4q16:
1638    case ARM::VLD4q32:
1639    case ARM::VLD4q8_UPD:
1640    case ARM::VLD4q16_UPD:
1641    case ARM::VLD4q32_UPD:
1642      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
1643      break;
1644    default:
1645      break;
1646  }
1647
1648  // Fourth output register
1649  switch (Inst.getOpcode()) {
1650    case ARM::VLD1d8Q:
1651    case ARM::VLD1d16Q:
1652    case ARM::VLD1d32Q:
1653    case ARM::VLD1d64Q:
1654    case ARM::VLD1d8Q_UPD:
1655    case ARM::VLD1d16Q_UPD:
1656    case ARM::VLD1d32Q_UPD:
1657    case ARM::VLD1d64Q_UPD:
1658    case ARM::VLD2q8:
1659    case ARM::VLD2q16:
1660    case ARM::VLD2q32:
1661    case ARM::VLD2q8_UPD:
1662    case ARM::VLD2q16_UPD:
1663    case ARM::VLD2q32_UPD:
1664    case ARM::VLD4d8:
1665    case ARM::VLD4d16:
1666    case ARM::VLD4d32:
1667    case ARM::VLD4d8_UPD:
1668    case ARM::VLD4d16_UPD:
1669    case ARM::VLD4d32_UPD:
1670      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
1671      break;
1672    case ARM::VLD4q8:
1673    case ARM::VLD4q16:
1674    case ARM::VLD4q32:
1675    case ARM::VLD4q8_UPD:
1676    case ARM::VLD4q16_UPD:
1677    case ARM::VLD4q32_UPD:
1678      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
1679      break;
1680    default:
1681      break;
1682  }
1683
1684  // Writeback operand
1685  switch (Inst.getOpcode()) {
1686    case ARM::VLD1d8_UPD:
1687    case ARM::VLD1d16_UPD:
1688    case ARM::VLD1d32_UPD:
1689    case ARM::VLD1d64_UPD:
1690    case ARM::VLD1q8_UPD:
1691    case ARM::VLD1q16_UPD:
1692    case ARM::VLD1q32_UPD:
1693    case ARM::VLD1q64_UPD:
1694    case ARM::VLD1d8T_UPD:
1695    case ARM::VLD1d16T_UPD:
1696    case ARM::VLD1d32T_UPD:
1697    case ARM::VLD1d64T_UPD:
1698    case ARM::VLD1d8Q_UPD:
1699    case ARM::VLD1d16Q_UPD:
1700    case ARM::VLD1d32Q_UPD:
1701    case ARM::VLD1d64Q_UPD:
1702    case ARM::VLD2d8_UPD:
1703    case ARM::VLD2d16_UPD:
1704    case ARM::VLD2d32_UPD:
1705    case ARM::VLD2q8_UPD:
1706    case ARM::VLD2q16_UPD:
1707    case ARM::VLD2q32_UPD:
1708    case ARM::VLD2b8_UPD:
1709    case ARM::VLD2b16_UPD:
1710    case ARM::VLD2b32_UPD:
1711    case ARM::VLD3d8_UPD:
1712    case ARM::VLD3d16_UPD:
1713    case ARM::VLD3d32_UPD:
1714    case ARM::VLD3q8_UPD:
1715    case ARM::VLD3q16_UPD:
1716    case ARM::VLD3q32_UPD:
1717    case ARM::VLD4d8_UPD:
1718    case ARM::VLD4d16_UPD:
1719    case ARM::VLD4d32_UPD:
1720    case ARM::VLD4q8_UPD:
1721    case ARM::VLD4q16_UPD:
1722    case ARM::VLD4q32_UPD:
1723      CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
1724      break;
1725    default:
1726      break;
1727  }
1728
1729  // AddrMode6 Base (register+alignment)
1730  CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
1731
1732  // AddrMode6 Offset (register)
1733  if (Rm == 0xD)
1734    Inst.addOperand(MCOperand::CreateReg(0));
1735  else if (Rm != 0xF) {
1736    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1737  }
1738
1739  return S;
1740}
1741
1742static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
1743                                 uint64_t Address, const void *Decoder) {
1744  DecodeStatus S = Success;
1745
1746  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1747  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1748  unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1749  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1750  Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1751  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1752
1753  // Writeback Operand
1754  switch (Inst.getOpcode()) {
1755    case ARM::VST1d8_UPD:
1756    case ARM::VST1d16_UPD:
1757    case ARM::VST1d32_UPD:
1758    case ARM::VST1d64_UPD:
1759    case ARM::VST1q8_UPD:
1760    case ARM::VST1q16_UPD:
1761    case ARM::VST1q32_UPD:
1762    case ARM::VST1q64_UPD:
1763    case ARM::VST1d8T_UPD:
1764    case ARM::VST1d16T_UPD:
1765    case ARM::VST1d32T_UPD:
1766    case ARM::VST1d64T_UPD:
1767    case ARM::VST1d8Q_UPD:
1768    case ARM::VST1d16Q_UPD:
1769    case ARM::VST1d32Q_UPD:
1770    case ARM::VST1d64Q_UPD:
1771    case ARM::VST2d8_UPD:
1772    case ARM::VST2d16_UPD:
1773    case ARM::VST2d32_UPD:
1774    case ARM::VST2q8_UPD:
1775    case ARM::VST2q16_UPD:
1776    case ARM::VST2q32_UPD:
1777    case ARM::VST2b8_UPD:
1778    case ARM::VST2b16_UPD:
1779    case ARM::VST2b32_UPD:
1780    case ARM::VST3d8_UPD:
1781    case ARM::VST3d16_UPD:
1782    case ARM::VST3d32_UPD:
1783    case ARM::VST3q8_UPD:
1784    case ARM::VST3q16_UPD:
1785    case ARM::VST3q32_UPD:
1786    case ARM::VST4d8_UPD:
1787    case ARM::VST4d16_UPD:
1788    case ARM::VST4d32_UPD:
1789    case ARM::VST4q8_UPD:
1790    case ARM::VST4q16_UPD:
1791    case ARM::VST4q32_UPD:
1792      CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
1793      break;
1794    default:
1795      break;
1796  }
1797
1798  // AddrMode6 Base (register+alignment)
1799  CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
1800
1801  // AddrMode6 Offset (register)
1802  if (Rm == 0xD)
1803    Inst.addOperand(MCOperand::CreateReg(0));
1804  else if (Rm != 0xF) {
1805    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1806  }
1807
1808  // First input register
1809  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
1810
1811  // Second input register
1812  switch (Inst.getOpcode()) {
1813    case ARM::VST1q8:
1814    case ARM::VST1q16:
1815    case ARM::VST1q32:
1816    case ARM::VST1q64:
1817    case ARM::VST1q8_UPD:
1818    case ARM::VST1q16_UPD:
1819    case ARM::VST1q32_UPD:
1820    case ARM::VST1q64_UPD:
1821    case ARM::VST1d8T:
1822    case ARM::VST1d16T:
1823    case ARM::VST1d32T:
1824    case ARM::VST1d64T:
1825    case ARM::VST1d8T_UPD:
1826    case ARM::VST1d16T_UPD:
1827    case ARM::VST1d32T_UPD:
1828    case ARM::VST1d64T_UPD:
1829    case ARM::VST1d8Q:
1830    case ARM::VST1d16Q:
1831    case ARM::VST1d32Q:
1832    case ARM::VST1d64Q:
1833    case ARM::VST1d8Q_UPD:
1834    case ARM::VST1d16Q_UPD:
1835    case ARM::VST1d32Q_UPD:
1836    case ARM::VST1d64Q_UPD:
1837    case ARM::VST2d8:
1838    case ARM::VST2d16:
1839    case ARM::VST2d32:
1840    case ARM::VST2d8_UPD:
1841    case ARM::VST2d16_UPD:
1842    case ARM::VST2d32_UPD:
1843    case ARM::VST2q8:
1844    case ARM::VST2q16:
1845    case ARM::VST2q32:
1846    case ARM::VST2q8_UPD:
1847    case ARM::VST2q16_UPD:
1848    case ARM::VST2q32_UPD:
1849    case ARM::VST3d8:
1850    case ARM::VST3d16:
1851    case ARM::VST3d32:
1852    case ARM::VST3d8_UPD:
1853    case ARM::VST3d16_UPD:
1854    case ARM::VST3d32_UPD:
1855    case ARM::VST4d8:
1856    case ARM::VST4d16:
1857    case ARM::VST4d32:
1858    case ARM::VST4d8_UPD:
1859    case ARM::VST4d16_UPD:
1860    case ARM::VST4d32_UPD:
1861      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
1862      break;
1863    case ARM::VST2b8:
1864    case ARM::VST2b16:
1865    case ARM::VST2b32:
1866    case ARM::VST2b8_UPD:
1867    case ARM::VST2b16_UPD:
1868    case ARM::VST2b32_UPD:
1869    case ARM::VST3q8:
1870    case ARM::VST3q16:
1871    case ARM::VST3q32:
1872    case ARM::VST3q8_UPD:
1873    case ARM::VST3q16_UPD:
1874    case ARM::VST3q32_UPD:
1875    case ARM::VST4q8:
1876    case ARM::VST4q16:
1877    case ARM::VST4q32:
1878    case ARM::VST4q8_UPD:
1879    case ARM::VST4q16_UPD:
1880    case ARM::VST4q32_UPD:
1881      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1882      break;
1883    default:
1884      break;
1885  }
1886
1887  // Third input register
1888  switch (Inst.getOpcode()) {
1889    case ARM::VST1d8T:
1890    case ARM::VST1d16T:
1891    case ARM::VST1d32T:
1892    case ARM::VST1d64T:
1893    case ARM::VST1d8T_UPD:
1894    case ARM::VST1d16T_UPD:
1895    case ARM::VST1d32T_UPD:
1896    case ARM::VST1d64T_UPD:
1897    case ARM::VST1d8Q:
1898    case ARM::VST1d16Q:
1899    case ARM::VST1d32Q:
1900    case ARM::VST1d64Q:
1901    case ARM::VST1d8Q_UPD:
1902    case ARM::VST1d16Q_UPD:
1903    case ARM::VST1d32Q_UPD:
1904    case ARM::VST1d64Q_UPD:
1905    case ARM::VST2q8:
1906    case ARM::VST2q16:
1907    case ARM::VST2q32:
1908    case ARM::VST2q8_UPD:
1909    case ARM::VST2q16_UPD:
1910    case ARM::VST2q32_UPD:
1911    case ARM::VST3d8:
1912    case ARM::VST3d16:
1913    case ARM::VST3d32:
1914    case ARM::VST3d8_UPD:
1915    case ARM::VST3d16_UPD:
1916    case ARM::VST3d32_UPD:
1917    case ARM::VST4d8:
1918    case ARM::VST4d16:
1919    case ARM::VST4d32:
1920    case ARM::VST4d8_UPD:
1921    case ARM::VST4d16_UPD:
1922    case ARM::VST4d32_UPD:
1923      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1924      break;
1925    case ARM::VST3q8:
1926    case ARM::VST3q16:
1927    case ARM::VST3q32:
1928    case ARM::VST3q8_UPD:
1929    case ARM::VST3q16_UPD:
1930    case ARM::VST3q32_UPD:
1931    case ARM::VST4q8:
1932    case ARM::VST4q16:
1933    case ARM::VST4q32:
1934    case ARM::VST4q8_UPD:
1935    case ARM::VST4q16_UPD:
1936    case ARM::VST4q32_UPD:
1937      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
1938      break;
1939    default:
1940      break;
1941  }
1942
1943  // Fourth input register
1944  switch (Inst.getOpcode()) {
1945    case ARM::VST1d8Q:
1946    case ARM::VST1d16Q:
1947    case ARM::VST1d32Q:
1948    case ARM::VST1d64Q:
1949    case ARM::VST1d8Q_UPD:
1950    case ARM::VST1d16Q_UPD:
1951    case ARM::VST1d32Q_UPD:
1952    case ARM::VST1d64Q_UPD:
1953    case ARM::VST2q8:
1954    case ARM::VST2q16:
1955    case ARM::VST2q32:
1956    case ARM::VST2q8_UPD:
1957    case ARM::VST2q16_UPD:
1958    case ARM::VST2q32_UPD:
1959    case ARM::VST4d8:
1960    case ARM::VST4d16:
1961    case ARM::VST4d32:
1962    case ARM::VST4d8_UPD:
1963    case ARM::VST4d16_UPD:
1964    case ARM::VST4d32_UPD:
1965      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
1966      break;
1967    case ARM::VST4q8:
1968    case ARM::VST4q16:
1969    case ARM::VST4q32:
1970    case ARM::VST4q8_UPD:
1971    case ARM::VST4q16_UPD:
1972    case ARM::VST4q32_UPD:
1973      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
1974      break;
1975    default:
1976      break;
1977  }
1978
1979  return S;
1980}
1981
1982static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
1983                                    uint64_t Address, const void *Decoder) {
1984  DecodeStatus S = Success;
1985
1986  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1987  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1988  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1989  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1990  unsigned align = fieldFromInstruction32(Insn, 4, 1);
1991  unsigned size = fieldFromInstruction32(Insn, 6, 2);
1992  unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
1993
1994  align *= (1 << size);
1995
1996  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
1997  if (regs == 2) {
1998    CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
1999  }
2000  if (Rm != 0xF) {
2001    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2002  }
2003
2004  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2005  Inst.addOperand(MCOperand::CreateImm(align));
2006
2007  if (Rm == 0xD)
2008    Inst.addOperand(MCOperand::CreateReg(0));
2009  else if (Rm != 0xF) {
2010    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2011  }
2012
2013  return S;
2014}
2015
2016static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2017                                    uint64_t Address, const void *Decoder) {
2018  DecodeStatus S = Success;
2019
2020  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2021  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2022  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2023  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2024  unsigned align = fieldFromInstruction32(Insn, 4, 1);
2025  unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2026  unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2027  align *= 2*size;
2028
2029  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2030  CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
2031  if (Rm != 0xF) {
2032    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2033  }
2034
2035  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2036  Inst.addOperand(MCOperand::CreateImm(align));
2037
2038  if (Rm == 0xD)
2039    Inst.addOperand(MCOperand::CreateReg(0));
2040  else if (Rm != 0xF) {
2041    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2042  }
2043
2044  return S;
2045}
2046
2047static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2048                                    uint64_t Address, const void *Decoder) {
2049  DecodeStatus S = Success;
2050
2051  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2052  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2053  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2054  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2055  unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2056
2057  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2058  CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
2059  CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
2060  if (Rm != 0xF) {
2061    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2062  }
2063
2064  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2065  Inst.addOperand(MCOperand::CreateImm(0));
2066
2067  if (Rm == 0xD)
2068    Inst.addOperand(MCOperand::CreateReg(0));
2069  else if (Rm != 0xF) {
2070    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2071  }
2072
2073  return S;
2074}
2075
2076static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2077                                    uint64_t Address, const void *Decoder) {
2078  DecodeStatus S = Success;
2079
2080  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2081  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2082  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2083  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2084  unsigned size = fieldFromInstruction32(Insn, 6, 2);
2085  unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2086  unsigned align = fieldFromInstruction32(Insn, 4, 1);
2087
2088  if (size == 0x3) {
2089    size = 4;
2090    align = 16;
2091  } else {
2092    if (size == 2) {
2093      size = 1 << size;
2094      align *= 8;
2095    } else {
2096      size = 1 << size;
2097      align *= 4*size;
2098    }
2099  }
2100
2101  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2102  CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
2103  CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
2104  CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder));
2105  if (Rm != 0xF) {
2106    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2107  }
2108
2109  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2110  Inst.addOperand(MCOperand::CreateImm(align));
2111
2112  if (Rm == 0xD)
2113    Inst.addOperand(MCOperand::CreateReg(0));
2114  else if (Rm != 0xF) {
2115    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2116  }
2117
2118  return S;
2119}
2120
2121static DecodeStatus
2122DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2123                            uint64_t Address, const void *Decoder) {
2124  DecodeStatus S = Success;
2125
2126  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2127  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2128  unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2129  imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2130  imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2131  imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2132  imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2133  unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2134
2135  if (Q) {
2136    CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
2137  } else {
2138    CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2139  }
2140
2141  Inst.addOperand(MCOperand::CreateImm(imm));
2142
2143  switch (Inst.getOpcode()) {
2144    case ARM::VORRiv4i16:
2145    case ARM::VORRiv2i32:
2146    case ARM::VBICiv4i16:
2147    case ARM::VBICiv2i32:
2148      CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2149      break;
2150    case ARM::VORRiv8i16:
2151    case ARM::VORRiv4i32:
2152    case ARM::VBICiv8i16:
2153    case ARM::VBICiv4i32:
2154      CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
2155      break;
2156    default:
2157      break;
2158  }
2159
2160  return S;
2161}
2162
2163static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
2164                                        uint64_t Address, const void *Decoder) {
2165  DecodeStatus S = Success;
2166
2167  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2168  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2169  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2170  Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2171  unsigned size = fieldFromInstruction32(Insn, 18, 2);
2172
2173  CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
2174  CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
2175  Inst.addOperand(MCOperand::CreateImm(8 << size));
2176
2177  return S;
2178}
2179
2180static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
2181                               uint64_t Address, const void *Decoder) {
2182  Inst.addOperand(MCOperand::CreateImm(8 - Val));
2183  return Success;
2184}
2185
2186static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
2187                               uint64_t Address, const void *Decoder) {
2188  Inst.addOperand(MCOperand::CreateImm(16 - Val));
2189  return Success;
2190}
2191
2192static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
2193                               uint64_t Address, const void *Decoder) {
2194  Inst.addOperand(MCOperand::CreateImm(32 - Val));
2195  return Success;
2196}
2197
2198static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
2199                               uint64_t Address, const void *Decoder) {
2200  Inst.addOperand(MCOperand::CreateImm(64 - Val));
2201  return Success;
2202}
2203
2204static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
2205                               uint64_t Address, const void *Decoder) {
2206  DecodeStatus S = Success;
2207
2208  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2209  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2210  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2211  Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2212  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2213  Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2214  unsigned op = fieldFromInstruction32(Insn, 6, 1);
2215  unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2216
2217  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2218  if (op) {
2219    CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback
2220  }
2221
2222  for (unsigned i = 0; i < length; ++i) {
2223    CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder));
2224  }
2225
2226  CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
2227
2228  return S;
2229}
2230
2231static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
2232                            uint64_t Address, const void *Decoder) {
2233  // The immediate needs to be a fully instantiated float.  However, the
2234  // auto-generated decoder is only able to fill in some of the bits
2235  // necessary.  For instance, the 'b' bit is replicated multiple times,
2236  // and is even present in inverted form in one bit.  We do a little
2237  // binary parsing here to fill in those missing bits, and then
2238  // reinterpret it all as a float.
2239  union {
2240    uint32_t integer;
2241    float fp;
2242  } fp_conv;
2243
2244  fp_conv.integer = Val;
2245  uint32_t b = fieldFromInstruction32(Val, 25, 1);
2246  fp_conv.integer |= b << 26;
2247  fp_conv.integer |= b << 27;
2248  fp_conv.integer |= b << 28;
2249  fp_conv.integer |= b << 29;
2250  fp_conv.integer |= (~b & 0x1) << 30;
2251
2252  Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
2253  return Success;
2254}
2255
2256static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
2257                                     uint64_t Address, const void *Decoder) {
2258  DecodeStatus S = Success;
2259
2260  unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2261  unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2262
2263  CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder));
2264
2265  if (Inst.getOpcode() == ARM::tADR)
2266    Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2267  else if (Inst.getOpcode() == ARM::tADDrSPi)
2268    Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2269  else
2270    return Fail;
2271
2272  Inst.addOperand(MCOperand::CreateImm(imm));
2273  return S;
2274}
2275
2276static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
2277                                 uint64_t Address, const void *Decoder) {
2278  Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
2279  return Success;
2280}
2281
2282static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
2283                                 uint64_t Address, const void *Decoder) {
2284  Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
2285  return Success;
2286}
2287
2288static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
2289                                 uint64_t Address, const void *Decoder) {
2290  Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
2291  return Success;
2292}
2293
2294static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
2295                                 uint64_t Address, const void *Decoder) {
2296  DecodeStatus S = Success;
2297
2298  unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2299  unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2300
2301  CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
2302  CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder));
2303
2304  return S;
2305}
2306
2307static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
2308                                  uint64_t Address, const void *Decoder) {
2309  DecodeStatus S = Success;
2310
2311  unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2312  unsigned imm = fieldFromInstruction32(Val, 3, 5);
2313
2314  CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
2315  Inst.addOperand(MCOperand::CreateImm(imm));
2316
2317  return S;
2318}
2319
2320static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
2321                                  uint64_t Address, const void *Decoder) {
2322  Inst.addOperand(MCOperand::CreateImm(Val << 2));
2323
2324  return Success;
2325}
2326
2327static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
2328                                  uint64_t Address, const void *Decoder) {
2329  Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2330  Inst.addOperand(MCOperand::CreateImm(Val));
2331
2332  return Success;
2333}
2334
2335static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
2336                                  uint64_t Address, const void *Decoder) {
2337  DecodeStatus S = Success;
2338
2339  unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2340  unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2341  unsigned imm = fieldFromInstruction32(Val, 0, 2);
2342
2343  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2344  CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder));
2345  Inst.addOperand(MCOperand::CreateImm(imm));
2346
2347  return S;
2348}
2349
2350static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
2351                              uint64_t Address, const void *Decoder) {
2352  DecodeStatus S = Success;
2353
2354  if (Inst.getOpcode() != ARM::t2PLDs) {
2355    unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2356    CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2357  }
2358
2359  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2360  if (Rn == 0xF) {
2361    switch (Inst.getOpcode()) {
2362      case ARM::t2LDRBs:
2363        Inst.setOpcode(ARM::t2LDRBpci);
2364        break;
2365      case ARM::t2LDRHs:
2366        Inst.setOpcode(ARM::t2LDRHpci);
2367        break;
2368      case ARM::t2LDRSHs:
2369        Inst.setOpcode(ARM::t2LDRSHpci);
2370        break;
2371      case ARM::t2LDRSBs:
2372        Inst.setOpcode(ARM::t2LDRSBpci);
2373        break;
2374      case ARM::t2PLDs:
2375        Inst.setOpcode(ARM::t2PLDi12);
2376        Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2377        break;
2378      default:
2379        return Fail;
2380    }
2381
2382    int imm = fieldFromInstruction32(Insn, 0, 12);
2383    if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2384    Inst.addOperand(MCOperand::CreateImm(imm));
2385
2386    return S;
2387  }
2388
2389  unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2390  addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2391  addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
2392  CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder));
2393
2394  return S;
2395}
2396
2397static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
2398                           uint64_t Address, const void *Decoder) {
2399  int imm = Val & 0xFF;
2400  if (!(Val & 0x100)) imm *= -1;
2401  Inst.addOperand(MCOperand::CreateImm(imm << 2));
2402
2403  return Success;
2404}
2405
2406static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
2407                                   uint64_t Address, const void *Decoder) {
2408  DecodeStatus S = Success;
2409
2410  unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2411  unsigned imm = fieldFromInstruction32(Val, 0, 9);
2412
2413  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2414  CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder));
2415
2416  return S;
2417}
2418
2419static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
2420                         uint64_t Address, const void *Decoder) {
2421  int imm = Val & 0xFF;
2422  if (!(Val & 0x100)) imm *= -1;
2423  Inst.addOperand(MCOperand::CreateImm(imm));
2424
2425  return Success;
2426}
2427
2428
2429static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
2430                                 uint64_t Address, const void *Decoder) {
2431  DecodeStatus S = Success;
2432
2433  unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2434  unsigned imm = fieldFromInstruction32(Val, 0, 9);
2435
2436  // Some instructions always use an additive offset.
2437  switch (Inst.getOpcode()) {
2438    case ARM::t2LDRT:
2439    case ARM::t2LDRBT:
2440    case ARM::t2LDRHT:
2441    case ARM::t2LDRSBT:
2442    case ARM::t2LDRSHT:
2443      imm |= 0x100;
2444      break;
2445    default:
2446      break;
2447  }
2448
2449  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2450  CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder));
2451
2452  return S;
2453}
2454
2455
2456static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
2457                                  uint64_t Address, const void *Decoder) {
2458  DecodeStatus S = Success;
2459
2460  unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2461  unsigned imm = fieldFromInstruction32(Val, 0, 12);
2462
2463  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2464  Inst.addOperand(MCOperand::CreateImm(imm));
2465
2466  return S;
2467}
2468
2469
2470static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
2471                                uint64_t Address, const void *Decoder) {
2472  unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2473
2474  Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2475  Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2476  Inst.addOperand(MCOperand::CreateImm(imm));
2477
2478  return Success;
2479}
2480
2481static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
2482                                uint64_t Address, const void *Decoder) {
2483  DecodeStatus S = Success;
2484
2485  if (Inst.getOpcode() == ARM::tADDrSP) {
2486    unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2487    Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2488
2489    CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
2490    Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2491    CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
2492  } else if (Inst.getOpcode() == ARM::tADDspr) {
2493    unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2494
2495    Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2496    Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2497    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2498  }
2499
2500  return S;
2501}
2502
2503static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
2504                           uint64_t Address, const void *Decoder) {
2505  unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2506  unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2507
2508  Inst.addOperand(MCOperand::CreateImm(imod));
2509  Inst.addOperand(MCOperand::CreateImm(flags));
2510
2511  return Success;
2512}
2513
2514static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
2515                             uint64_t Address, const void *Decoder) {
2516  DecodeStatus S = Success;
2517  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2518  unsigned add = fieldFromInstruction32(Insn, 4, 1);
2519
2520  CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ;
2521  Inst.addOperand(MCOperand::CreateImm(add));
2522
2523  return S;
2524}
2525
2526static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
2527                                 uint64_t Address, const void *Decoder) {
2528  Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
2529  return Success;
2530}
2531
2532static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
2533                              uint64_t Address, const void *Decoder) {
2534  if (Val == 0xA || Val == 0xB)
2535    return Fail;
2536
2537  Inst.addOperand(MCOperand::CreateImm(Val));
2538  return Success;
2539}
2540
2541static DecodeStatus
2542DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2543                           uint64_t Address, const void *Decoder) {
2544  DecodeStatus S = Success;
2545
2546  unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2547  if (pred == 0xE || pred == 0xF) {
2548    unsigned opc = fieldFromInstruction32(Insn, 4, 2);
2549    switch (opc) {
2550      default:
2551        return Fail;
2552      case 0:
2553        Inst.setOpcode(ARM::t2DSB);
2554        break;
2555      case 1:
2556        Inst.setOpcode(ARM::t2DMB);
2557        break;
2558      case 2:
2559        Inst.setOpcode(ARM::t2ISB);
2560        return Success;
2561    }
2562
2563    unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2564    return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
2565  }
2566
2567  unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2568  brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2569  brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2570  brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2571  brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2572
2573  CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder));
2574  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2575
2576  return S;
2577}
2578
2579// Decode a shifted immediate operand.  These basically consist
2580// of an 8-bit value, and a 4-bit directive that specifies either
2581// a splat operation or a rotation.
2582static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
2583                          uint64_t Address, const void *Decoder) {
2584  unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2585  if (ctrl == 0) {
2586    unsigned byte = fieldFromInstruction32(Val, 8, 2);
2587    unsigned imm = fieldFromInstruction32(Val, 0, 8);
2588    switch (byte) {
2589      case 0:
2590        Inst.addOperand(MCOperand::CreateImm(imm));
2591        break;
2592      case 1:
2593        Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2594        break;
2595      case 2:
2596        Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2597        break;
2598      case 3:
2599        Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2600                                             (imm << 8)  |  imm));
2601        break;
2602    }
2603  } else {
2604    unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2605    unsigned rot = fieldFromInstruction32(Val, 7, 5);
2606    unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2607    Inst.addOperand(MCOperand::CreateImm(imm));
2608  }
2609
2610  return Success;
2611}
2612
2613static DecodeStatus
2614DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2615                            uint64_t Address, const void *Decoder){
2616  Inst.addOperand(MCOperand::CreateImm(Val << 1));
2617  return Success;
2618}
2619
2620static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
2621                                       uint64_t Address, const void *Decoder){
2622  Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
2623  return Success;
2624}
2625
2626static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
2627                                   uint64_t Address, const void *Decoder) {
2628  switch (Val) {
2629  default:
2630    return Fail;
2631  case 0xF: // SY
2632  case 0xE: // ST
2633  case 0xB: // ISH
2634  case 0xA: // ISHST
2635  case 0x7: // NSH
2636  case 0x6: // NSHST
2637  case 0x3: // OSH
2638  case 0x2: // OSHST
2639    break;
2640  }
2641
2642  Inst.addOperand(MCOperand::CreateImm(Val));
2643  return Success;
2644}
2645
2646static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
2647                          uint64_t Address, const void *Decoder) {
2648  if (!Val) return Fail;
2649  Inst.addOperand(MCOperand::CreateImm(Val));
2650  return Success;
2651}
2652
2653static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
2654                                        uint64_t Address, const void *Decoder) {
2655  DecodeStatus S = Success;
2656
2657  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2658  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2659  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2660
2661  if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
2662
2663  CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2664  CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
2665  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2666  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2667
2668  return S;
2669}
2670
2671
2672static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
2673                                         uint64_t Address, const void *Decoder){
2674  DecodeStatus S = Success;
2675
2676  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2677  unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
2678  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2679  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2680
2681  CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder));
2682
2683  if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
2684  if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail;
2685
2686  CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2687  CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
2688  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2689  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2690
2691  return S;
2692}
2693
2694static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
2695                            uint64_t Address, const void *Decoder) {
2696  DecodeStatus S = Success;
2697
2698  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2699  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2700  unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2701  imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2702  imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2703  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2704
2705  if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
2706
2707  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2708  CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2709  CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder));
2710  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2711
2712  return S;
2713}
2714
2715static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
2716                            uint64_t Address, const void *Decoder) {
2717  DecodeStatus S = Success;
2718
2719  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2720  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2721  unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2722  imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2723  imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2724  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2725
2726  if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
2727
2728  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2729  CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2730  CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder));
2731  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2732
2733  return S;
2734}
2735
2736static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
2737                         uint64_t Address, const void *Decoder) {
2738  DecodeStatus S = Success;
2739
2740  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2741  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2742  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2743  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2744  unsigned size = fieldFromInstruction32(Insn, 10, 2);
2745
2746  unsigned align = 0;
2747  unsigned index = 0;
2748  switch (size) {
2749    default:
2750      return Fail;
2751    case 0:
2752      if (fieldFromInstruction32(Insn, 4, 1))
2753        return Fail; // UNDEFINED
2754      index = fieldFromInstruction32(Insn, 5, 3);
2755      break;
2756    case 1:
2757      if (fieldFromInstruction32(Insn, 5, 1))
2758        return Fail; // UNDEFINED
2759      index = fieldFromInstruction32(Insn, 6, 2);
2760      if (fieldFromInstruction32(Insn, 4, 1))
2761        align = 2;
2762      break;
2763    case 2:
2764      if (fieldFromInstruction32(Insn, 6, 1))
2765        return Fail; // UNDEFINED
2766      index = fieldFromInstruction32(Insn, 7, 1);
2767      if (fieldFromInstruction32(Insn, 4, 2) != 0)
2768        align = 4;
2769  }
2770
2771  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2772  if (Rm != 0xF) { // Writeback
2773    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2774  }
2775  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2776  Inst.addOperand(MCOperand::CreateImm(align));
2777  if (Rm != 0xF) {
2778    if (Rm != 0xD)
2779      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2780    else
2781      Inst.addOperand(MCOperand::CreateReg(0));
2782  }
2783
2784  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2785  Inst.addOperand(MCOperand::CreateImm(index));
2786
2787  return S;
2788}
2789
2790static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
2791                         uint64_t Address, const void *Decoder) {
2792  DecodeStatus S = Success;
2793
2794  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2795  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2796  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2797  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2798  unsigned size = fieldFromInstruction32(Insn, 10, 2);
2799
2800  unsigned align = 0;
2801  unsigned index = 0;
2802  switch (size) {
2803    default:
2804      return Fail;
2805    case 0:
2806      if (fieldFromInstruction32(Insn, 4, 1))
2807        return Fail; // UNDEFINED
2808      index = fieldFromInstruction32(Insn, 5, 3);
2809      break;
2810    case 1:
2811      if (fieldFromInstruction32(Insn, 5, 1))
2812        return Fail; // UNDEFINED
2813      index = fieldFromInstruction32(Insn, 6, 2);
2814      if (fieldFromInstruction32(Insn, 4, 1))
2815        align = 2;
2816      break;
2817    case 2:
2818      if (fieldFromInstruction32(Insn, 6, 1))
2819        return Fail; // UNDEFINED
2820      index = fieldFromInstruction32(Insn, 7, 1);
2821      if (fieldFromInstruction32(Insn, 4, 2) != 0)
2822        align = 4;
2823  }
2824
2825  if (Rm != 0xF) { // Writeback
2826    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2827  }
2828  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2829  Inst.addOperand(MCOperand::CreateImm(align));
2830  if (Rm != 0xF) {
2831    if (Rm != 0xD)
2832      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2833    else
2834      Inst.addOperand(MCOperand::CreateReg(0));
2835  }
2836
2837  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2838  Inst.addOperand(MCOperand::CreateImm(index));
2839
2840  return S;
2841}
2842
2843
2844static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
2845                         uint64_t Address, const void *Decoder) {
2846  DecodeStatus S = Success;
2847
2848  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2849  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2850  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2851  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2852  unsigned size = fieldFromInstruction32(Insn, 10, 2);
2853
2854  unsigned align = 0;
2855  unsigned index = 0;
2856  unsigned inc = 1;
2857  switch (size) {
2858    default:
2859      return Fail;
2860    case 0:
2861      index = fieldFromInstruction32(Insn, 5, 3);
2862      if (fieldFromInstruction32(Insn, 4, 1))
2863        align = 2;
2864      break;
2865    case 1:
2866      index = fieldFromInstruction32(Insn, 6, 2);
2867      if (fieldFromInstruction32(Insn, 4, 1))
2868        align = 4;
2869      if (fieldFromInstruction32(Insn, 5, 1))
2870        inc = 2;
2871      break;
2872    case 2:
2873      if (fieldFromInstruction32(Insn, 5, 1))
2874        return Fail; // UNDEFINED
2875      index = fieldFromInstruction32(Insn, 7, 1);
2876      if (fieldFromInstruction32(Insn, 4, 1) != 0)
2877        align = 8;
2878      if (fieldFromInstruction32(Insn, 6, 1))
2879        inc = 2;
2880      break;
2881  }
2882
2883  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2884  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
2885  if (Rm != 0xF) { // Writeback
2886    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2887  }
2888  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2889  Inst.addOperand(MCOperand::CreateImm(align));
2890  if (Rm != 0xF) {
2891    if (Rm != 0xD)
2892      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2893    else
2894      Inst.addOperand(MCOperand::CreateReg(0));
2895  }
2896
2897  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2898  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
2899  Inst.addOperand(MCOperand::CreateImm(index));
2900
2901  return S;
2902}
2903
2904static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
2905                         uint64_t Address, const void *Decoder) {
2906  DecodeStatus S = Success;
2907
2908  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2909  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2910  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2911  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2912  unsigned size = fieldFromInstruction32(Insn, 10, 2);
2913
2914  unsigned align = 0;
2915  unsigned index = 0;
2916  unsigned inc = 1;
2917  switch (size) {
2918    default:
2919      return Fail;
2920    case 0:
2921      index = fieldFromInstruction32(Insn, 5, 3);
2922      if (fieldFromInstruction32(Insn, 4, 1))
2923        align = 2;
2924      break;
2925    case 1:
2926      index = fieldFromInstruction32(Insn, 6, 2);
2927      if (fieldFromInstruction32(Insn, 4, 1))
2928        align = 4;
2929      if (fieldFromInstruction32(Insn, 5, 1))
2930        inc = 2;
2931      break;
2932    case 2:
2933      if (fieldFromInstruction32(Insn, 5, 1))
2934        return Fail; // UNDEFINED
2935      index = fieldFromInstruction32(Insn, 7, 1);
2936      if (fieldFromInstruction32(Insn, 4, 1) != 0)
2937        align = 8;
2938      if (fieldFromInstruction32(Insn, 6, 1))
2939        inc = 2;
2940      break;
2941  }
2942
2943  if (Rm != 0xF) { // Writeback
2944    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2945  }
2946  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2947  Inst.addOperand(MCOperand::CreateImm(align));
2948  if (Rm != 0xF) {
2949    if (Rm != 0xD)
2950      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2951    else
2952      Inst.addOperand(MCOperand::CreateReg(0));
2953  }
2954
2955  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2956  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
2957  Inst.addOperand(MCOperand::CreateImm(index));
2958
2959  return S;
2960}
2961
2962
2963static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
2964                         uint64_t Address, const void *Decoder) {
2965  DecodeStatus S = Success;
2966
2967  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2968  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2969  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2970  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2971  unsigned size = fieldFromInstruction32(Insn, 10, 2);
2972
2973  unsigned align = 0;
2974  unsigned index = 0;
2975  unsigned inc = 1;
2976  switch (size) {
2977    default:
2978      return Fail;
2979    case 0:
2980      if (fieldFromInstruction32(Insn, 4, 1))
2981        return Fail; // UNDEFINED
2982      index = fieldFromInstruction32(Insn, 5, 3);
2983      break;
2984    case 1:
2985      if (fieldFromInstruction32(Insn, 4, 1))
2986        return Fail; // UNDEFINED
2987      index = fieldFromInstruction32(Insn, 6, 2);
2988      if (fieldFromInstruction32(Insn, 5, 1))
2989        inc = 2;
2990      break;
2991    case 2:
2992      if (fieldFromInstruction32(Insn, 4, 2))
2993        return Fail; // UNDEFINED
2994      index = fieldFromInstruction32(Insn, 7, 1);
2995      if (fieldFromInstruction32(Insn, 6, 1))
2996        inc = 2;
2997      break;
2998  }
2999
3000  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3001  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3002  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3003
3004  if (Rm != 0xF) { // Writeback
3005    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3006  }
3007  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3008  Inst.addOperand(MCOperand::CreateImm(align));
3009  if (Rm != 0xF) {
3010    if (Rm != 0xD)
3011      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3012    else
3013      Inst.addOperand(MCOperand::CreateReg(0));
3014  }
3015
3016  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3017  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3018  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3019  Inst.addOperand(MCOperand::CreateImm(index));
3020
3021  return S;
3022}
3023
3024static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
3025                         uint64_t Address, const void *Decoder) {
3026  DecodeStatus S = Success;
3027
3028  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3029  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3030  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3031  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3032  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3033
3034  unsigned align = 0;
3035  unsigned index = 0;
3036  unsigned inc = 1;
3037  switch (size) {
3038    default:
3039      return Fail;
3040    case 0:
3041      if (fieldFromInstruction32(Insn, 4, 1))
3042        return Fail; // UNDEFINED
3043      index = fieldFromInstruction32(Insn, 5, 3);
3044      break;
3045    case 1:
3046      if (fieldFromInstruction32(Insn, 4, 1))
3047        return Fail; // UNDEFINED
3048      index = fieldFromInstruction32(Insn, 6, 2);
3049      if (fieldFromInstruction32(Insn, 5, 1))
3050        inc = 2;
3051      break;
3052    case 2:
3053      if (fieldFromInstruction32(Insn, 4, 2))
3054        return Fail; // UNDEFINED
3055      index = fieldFromInstruction32(Insn, 7, 1);
3056      if (fieldFromInstruction32(Insn, 6, 1))
3057        inc = 2;
3058      break;
3059  }
3060
3061  if (Rm != 0xF) { // Writeback
3062    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3063  }
3064  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3065  Inst.addOperand(MCOperand::CreateImm(align));
3066  if (Rm != 0xF) {
3067    if (Rm != 0xD)
3068      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3069    else
3070      Inst.addOperand(MCOperand::CreateReg(0));
3071  }
3072
3073  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3074  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3075  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3076  Inst.addOperand(MCOperand::CreateImm(index));
3077
3078  return S;
3079}
3080
3081
3082static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
3083                         uint64_t Address, const void *Decoder) {
3084  DecodeStatus S = Success;
3085
3086  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3087  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3088  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3089  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3090  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3091
3092  unsigned align = 0;
3093  unsigned index = 0;
3094  unsigned inc = 1;
3095  switch (size) {
3096    default:
3097      return Fail;
3098    case 0:
3099      if (fieldFromInstruction32(Insn, 4, 1))
3100        align = 4;
3101      index = fieldFromInstruction32(Insn, 5, 3);
3102      break;
3103    case 1:
3104      if (fieldFromInstruction32(Insn, 4, 1))
3105        align = 8;
3106      index = fieldFromInstruction32(Insn, 6, 2);
3107      if (fieldFromInstruction32(Insn, 5, 1))
3108        inc = 2;
3109      break;
3110    case 2:
3111      if (fieldFromInstruction32(Insn, 4, 2))
3112        align = 4 << fieldFromInstruction32(Insn, 4, 2);
3113      index = fieldFromInstruction32(Insn, 7, 1);
3114      if (fieldFromInstruction32(Insn, 6, 1))
3115        inc = 2;
3116      break;
3117  }
3118
3119  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3120  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3121  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3122  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
3123
3124  if (Rm != 0xF) { // Writeback
3125    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3126  }
3127  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3128  Inst.addOperand(MCOperand::CreateImm(align));
3129  if (Rm != 0xF) {
3130    if (Rm != 0xD)
3131      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3132    else
3133      Inst.addOperand(MCOperand::CreateReg(0));
3134  }
3135
3136  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3137  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3138  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3139  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
3140  Inst.addOperand(MCOperand::CreateImm(index));
3141
3142  return S;
3143}
3144
3145static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
3146                         uint64_t Address, const void *Decoder) {
3147  DecodeStatus S = Success;
3148
3149  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3150  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3151  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3152  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3153  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3154
3155  unsigned align = 0;
3156  unsigned index = 0;
3157  unsigned inc = 1;
3158  switch (size) {
3159    default:
3160      return Fail;
3161    case 0:
3162      if (fieldFromInstruction32(Insn, 4, 1))
3163        align = 4;
3164      index = fieldFromInstruction32(Insn, 5, 3);
3165      break;
3166    case 1:
3167      if (fieldFromInstruction32(Insn, 4, 1))
3168        align = 8;
3169      index = fieldFromInstruction32(Insn, 6, 2);
3170      if (fieldFromInstruction32(Insn, 5, 1))
3171        inc = 2;
3172      break;
3173    case 2:
3174      if (fieldFromInstruction32(Insn, 4, 2))
3175        align = 4 << fieldFromInstruction32(Insn, 4, 2);
3176      index = fieldFromInstruction32(Insn, 7, 1);
3177      if (fieldFromInstruction32(Insn, 6, 1))
3178        inc = 2;
3179      break;
3180  }
3181
3182  if (Rm != 0xF) { // Writeback
3183    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3184  }
3185  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3186  Inst.addOperand(MCOperand::CreateImm(align));
3187  if (Rm != 0xF) {
3188    if (Rm != 0xD)
3189      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3190    else
3191      Inst.addOperand(MCOperand::CreateReg(0));
3192  }
3193
3194  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3195  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3196  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3197  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
3198  Inst.addOperand(MCOperand::CreateImm(index));
3199
3200  return S;
3201}
3202
3203static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
3204                                  uint64_t Address, const void *Decoder) {
3205  DecodeStatus S = Success;
3206  unsigned Rt  = fieldFromInstruction32(Insn, 12, 4);
3207  unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3208  unsigned Rm  = fieldFromInstruction32(Insn,  0, 4);
3209  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3210  Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3211
3212  if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3213    CHECK(S, Unpredictable);
3214
3215  CHECK(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder));
3216  CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));
3217  CHECK(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder));
3218  CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));
3219  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
3220
3221  return S;
3222}
3223
3224static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
3225                                  uint64_t Address, const void *Decoder) {
3226  DecodeStatus S = Success;
3227  unsigned Rt  = fieldFromInstruction32(Insn, 12, 4);
3228  unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3229  unsigned Rm  = fieldFromInstruction32(Insn,  0, 4);
3230  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3231  Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3232
3233  if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3234    CHECK(S, Unpredictable);
3235
3236  CHECK(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder));
3237  CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));
3238  CHECK(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder));
3239  CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));
3240  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
3241
3242  return S;
3243}
3244
3245static DecodeStatus DecodeCPSIMod(llvm::MCInst &Inst, unsigned Val,
3246                                 uint64_t Address, const void *Decoder) {
3247  if (Val == 0x1) return Fail;
3248  Inst.addOperand(MCOperand::CreateImm(Val));
3249  return Success;
3250}
3251
3252