| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| fa840ba402806d978c18401c6bea1c808607d944 |
|
08-Nov-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194261 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 3f04b5068619ca0411521c9871f4bfc6b04f951f |
|
30-Oct-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
[ARM] NEON instructions were erroneously decoded from certain invalid encodings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193705 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 01b0e94bb731310e72f66977e4b57cd3f3280ba4 |
|
22-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: provide diagnostics on more writeback LDM/STM instructions
The set of circumstances where the writeback register is allowed to be in the
list of registers is rather baroque, but I think this implements them all on
the assembly parsing side.
For disassembly, we still warn about an ARM-mode LDM even if the architecture
revision is < v7 (the required architecture information isn't available). It's
a silly instruction anyway, so hopefully no-one will mind.
rdar://problem/15223374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193185 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 441aeddd56d000ff77460586961a523e41edd205 |
|
01-Oct-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARM] Remove an unused function from the disassembler.
Pointed out by Joerg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191749 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 5df37dab763ce377095389c4ea1cff88db369954 |
|
19-Sep-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARMv8] Add support for the v8 cryptography extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 4f7092176c3d3eaae0ea7af26aec2d77b3e4035f |
|
06-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci,
as pldw does not have a literal variant (i.e. pc relative version)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187804 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 19c14abf1c4ccebfa7d07bdd6ea8462a15c0b749 |
|
17-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add support for the NEON instructions vmaxnm/vminnm.
This adds a new class for non-predicable NEON instructions and a
new DecoderNamespace for v8 NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 1e9ddc229f3d837a79eed1d7ac43743db148f8d1 |
|
04-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Remove an unneeded call to 'UpdateThumbVFPPredicate', spotted by Amaury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185651 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 4ea250524f77a67102118747dad6ee69f9f3b3aa |
|
04-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions.
This adds a new decoder table/namespace 'VFPV8', as these instructions have their
top 4 bits as 0b1111, while other Thumb instructions have 0b1110.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| ebc3938ae717d7352de800344c3ad5a1bceb74e5 |
|
24-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: check predicate bits for thumb instructions
When encoded to thumb, VFP instruction and VMOV/VDUP between scalar and
core registers, must have their predicate bit to 0b1110.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184707 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 07c3e159d8fffc8b16bcd52cc395a78007c62910 |
|
24-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: rGPR is meant to be unpredictable, not undefined
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184706 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| ff08da15cf3d0412ee9cc325fc5a720bcad178f2 |
|
24-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix IT decoding
mask == 0 -> UNPRED
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184702 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 0c9f0c047dfba91bc7c0fb66f7e868e917d37c4c |
|
24-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: enable decoding of pc-relative PLD/PLI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| ce046b98ed6c351779fc43599a80d588752bc1ca |
|
18-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix thumb literal loads decoding
This fixes two previous issues:
- Negative offsets were not correctly disassembled
- The decoded opcodes were not the right one
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| cea0032f73a56a62b692b25ca4084850cd51763b |
|
18-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: thumb stores cannot use PC as dest register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 8117ac555d06b23f61ddd06aa54d3dfa3e5b8e56 |
|
13-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix B decoding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183914 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| aa8003712e8b28bc4f263aeb79d8851146273a05 |
|
11-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: Enforce decoding rules for VLDn instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183731 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 3862709058ecfe809c9d4b32e3bff0efe8ebe646 |
|
11-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: Fix STREX/LDREX reecoding
The decoded MCInst wasn't reencoded as the same instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183729 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 4e9a96d810eb0cc126ebe6f18e536b474c84940c |
|
10-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: ISB cannot be passed the same options as DMB
ISB should only accepts full system sync, other options are reserved
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 9eefea009fb559cf441254f7022a2824386852c6 |
|
08-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix VMOVvnf32 decoding when ambiguous with VCVT
Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183612 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| ae50ddb2aeaec7dd91ef8db3918688c104a6baed |
|
08-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: enforce SRS decoding constraints
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 46e136c952e0242308db2682ba2ec4020cdcd006 |
|
08-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix CPS decoding when ambiguous with QADD
Handle the case when the disassembler table can't tell
the difference between some encodings of QADD and CPS.
Add some necessary safe guards in CPS decoding as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| c64835b0c57913b11abd648b76913390e62af8d6 |
|
08-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix VCVT decoding
UNPRED was reported instead of UNDEF
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 242c9f4615feeee2fbdd1f29cd9a8e8ffd43c075 |
|
31-May-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: add fstmx and fldmx instructions for assembly
These instructions are deprecated oddities, but we still need to be able to
disassemble (and reassemble) them if and when they're encountered.
Patch by Amaury de la Vieuville.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| c6af2432c802d241c8fffbe0371c023e6c58844e |
|
25-May-2013 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 49a6a8d8f2994249c81b7914b07015714748a55c |
|
24-May-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove the Copied parameter from MemoryObject::readBytes.
There was exactly one caller using this API right, the others were relying on
specific behavior of the default implementation. Since it's too hard to use it
right just remove it and standardize on the default behavior.
Defines away PR16132.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 2c94d0faa0e1c268893d5e04dc77e8a35889db00 |
|
24-May-2013 |
Ahmed Bougacha <ahmed.bougacha@gmail.com> |
Add MCSymbolizer for symbolic/annotated disassembly.
This is a basic first step towards symbolization of disassembled
instructions. This used to be done using externally provided (C API)
callbacks. This patch introduces:
- the MCSymbolizer class, that mimics the same functions that were used
in the X86 and ARM disassemblers to symbolize immediate operands and
to annotate loads based off PC (for things like c string literals).
- the MCExternalSymbolizer class, which implements the old C API.
- the MCRelocationInfo class, which provides a way for targets to
translate relocations (either object::RelocationRef, or disassembler
C API VariantKinds) to MCExprs.
- the MCObjectSymbolizer class, which does symbolization using what it
finds in an object::ObjectFile. This makes simple symbolization (with
no fancy relocation stuff) work for all object formats!
- x86-64 Mach-O and ELF MCRelocationInfos.
- A basic ARM Mach-O MCRelocationInfo, that provides just enough to
support the C API VariantKinds.
Most of what works in otool (the only user of the old symbolization API
that I know of) for x86-64 symbolic disassembly (-tvV) works, namely:
- symbol references: call _foo; jmp 15 <_foo+50>
- relocations: call _foo-_bar; call _foo-4
- __cf?string: leaq 193(%rip), %rax ## literal pool for "hello"
Stub support is the main missing part (because libObject doesn't know,
among other things, about mach-o indirect symbols).
As for the MCSymbolizer API, instead of relying on the disassemblers
to call the tryAdding* methods, maybe this could be done automagically
using InstrInfo? For instance, even though PC-relative LEAs are used
to get the address of string literals in a typical Mach-O file, a MOV
would be used in an ELF file. And right now, the explicit symbolization
only recognizes PC-relative LEAs. InstrInfo should have already have
most of what is needed to know what to symbolize, so this can
definitely be improved.
I'd also like to remove object::RelocationRef::getValueString (it seems
only used by relocation printing in objdump), as simply printing the
created MCExpr is definitely enough (and cleaner than string concats).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 30a7a7c1fdbd2607345dd1554e3436749fd75c6e |
|
20-May-2013 |
Mihai Popa <mihail.popa@gmail.com> |
VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| bac932e9c3c4305a3c73598f3d0dc55de53d4c68 |
|
20-May-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 4dc8bdf87d402ad8c91d9a72777d9576c5461e40 |
|
20-May-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Replace some bit operations with simpler ones. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| f86e436fb95670ed110818fefa403f21ae104639 |
|
13-May-2013 |
Mihai Popa <mihail.popa@gmail.com> |
The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181705 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 1ad3a410beff11913db0573942fb51b651d01a13 |
|
26-Apr-2013 |
Quentin Colombet <qcolombet@apple.com> |
ARM: Fix encoding of hint instruction for Thumb.
"hint" space for Thumb actually overlaps the encoding space of the CPS
instruction. In actuality, hints can be defined as CPS instructions where imod
and M bits are all nil.
Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe,
sev) in DecodeT2CPSInstruction.
This commit adds a proper diagnostic message for Imm0_4 and updates all tests.
Patch by Mihail Popa <Mihail.Popa@arm.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180617 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| d3af696c08923d4d376641b52c3b2cb5baa00487 |
|
19-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
ARM: Permit "sp" in ARM variant of STREXD instructions
Patch from Mihail Popa
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 4521019c6fd23680c583abe086067fc1c569bad1 |
|
19-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
ARM: permit "sp" in ARM variants of MOVW/MOVT instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 7c4cf030a898b5b4e0d2c66adf8dc068b1f1f070 |
|
17-Apr-2013 |
Quentin Colombet <qcolombet@apple.com> |
Fix treatment of ARM unallocated hint instructions.
The reference manual defines only 5 permitted values for the immediate field of the "hint" instruction:
1. nop (imm == 0)
2. yield (imm == 1)
3. wfe (imm == 2)
4. wfi (imm == 3)
5. sev (imm == 4)
Therefore, restrict the permitted values for the "hint" instruction to 0 through 4.
Patch by Mihail Popa <Mihail.Popa@arm.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179707 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| ce888351106a72825e2a107cb08d7130f3dce0ee |
|
28-Mar-2013 |
Gordon Keiser <gkeiser@arxan.com> |
Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when the upper bit is set.
They should always be zero-extended, not sign extended. Added test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| b78821d380b6f9514bd3b56b1c27ba367660228b |
|
26-Mar-2013 |
Joe Abbey <jabbey@arxan.com> |
Patch by Gordon Keiser!
If PC or SP is the destination, the disassembler erroneously failed with the
invalid encoding, despite the manual saying that both are fine.
This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a
postindexed load, where the offset 0xc is applied to SP after the load occurs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 759e3fa641d0ad01012d16d913015c9f69c8d2ab |
|
19-Dec-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Remove edis - the enhanced disassembler. Fixes PR14654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 1c83093cd5f4f6d33e732c817bb5afd033531beb |
|
30-Nov-2012 |
Kevin Enderby <enderby@apple.com> |
Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInst
which would then cause an assert when printed. rdar://11437956
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 445ba85b8d7bc8fb4689ca22131cadc80a034705 |
|
30-Oct-2012 |
Kevin Enderby <enderby@apple.com> |
Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target
is 24 bits not 20 and the decoding needed to correctly handle converting the
J1 and J2 bits to their I1 and I2 values to reconstruct the displacement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166982 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 88d12663abdac344f312b09edfe4934143436132 |
|
18-Oct-2012 |
Kevin Enderby <enderby@apple.com> |
Fix a bug where a 32-bit address with the high bit does not get symbolicated
because the value is incorrectly being signed extended when passed to
SymbolLookUp().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166234 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 93c7c449a1351542fa5a275587187154dbedb8e0 |
|
22-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Fix the handling of edge cases in ARM shifted operands.
This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164455 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 24b9f258f194c5e472bf133f9bbf5ca26ad500d3 |
|
06-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Diagnose invalid alignments on duplicating VLDn instructions.
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| eae1d34029c159306ce4a0472294de6cf9baedac |
|
06-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions.
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 1144af3c9b4da48cd581156e05b24261c8de366a |
|
25-Aug-2012 |
Richard Smith <richard-llvm@metafoo.co.uk> |
Fix integer undefined behavior due to signed left shift overflow in LLVM.
Reviewed offline by chandlerc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 960fb7437003dcb96c6af093e2d55e06e4c8bd43 |
|
17-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unnecessary include of ARMGenInstrInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162086 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| fc1a161d76f5cc0204bed3bce3e27cf36ac76d22 |
|
14-Aug-2012 |
Jim Grosbach <grosbach@apple.com> |
Switch the fixed-length disassembler to be table-driven.
Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() statements.
As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more
quickly and generates a smaller end result. For a Release+Asserts build on
a 16GB 3.4GHz i7 iMac w/ SSD:
Time to compile at -O2 (averaged w/ hot caches):
Previous: 35.5s
New: 8.9s
TEXT size:
Previous: 447,251
New: 297,661
Builds in 25% of the time previously required and generates code 66% of
the size.
Execution time of the disassembler is only slightly slower (7% disassembling
10 million ARM instructions, 19.6s vs 21.0s). The new implementation has
not yet been tuned, however, so the performance should almost certainly
be recoverable should it become a concern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaa |
|
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| c1b7ca5ba28ded2d83ae534c8e072c2538d43295 |
|
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161161 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| c8e41c591741b3da1077f7000274ad040bef8002 |
|
23-Jul-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Fix a typo (the the => the)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| fae96f17b4b022fccd94a143698112a17d8ddf05 |
|
10-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 270e3625b23174688aa5b6f1e1d0cd42086541de |
|
09-Jul-2012 |
Chad Rosier <mcrosier@apple.com> |
Revert r159938 (and r159945) to appease the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 83cfff6229c4afe9af9d48d4109df9a503233a7c |
|
09-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Oops - correct broken disassembly for VMOV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159945 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 2e7e34ba5485320a84ca69c83d242e24433f7acd |
|
09-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| c8f2fcc9a381f1e024656568f2face2f600e0328 |
|
06-Jun-2012 |
Richard Barton <richard.barton@arm.com> |
Correct decoder for T1 conditional B encoding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| dd051a0414d0c807388bdc9584b71729b3158571 |
|
22-May-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
ARMDisassembler.cpp: Fix utf8 char in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 3610a15c3581dee713820f72d8ffe2e2a632b057 |
|
05-May-2012 |
Kevin Enderby <enderby@apple.com> |
Tweak to the fix in r156212, as with the change in removing the shift the
SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156213 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| ce734d5ffe53273caa7df762f70803050b0ce929 |
|
05-May-2012 |
Kevin Enderby <enderby@apple.com> |
Fix a bug in the ARM disassembler for wide branch conditional instructions
where the symbolic operand's displacement was incorrectly shifted left by 1.
rdar://11387046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156212 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 2d524b0765145f1c7888166c985a25452f16b2bc |
|
04-May-2012 |
Kevin Enderby <enderby@apple.com> |
Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
for the assembler and disassembler. Which were not being set/read correctly
for offsets greater than 22 bits in some cases.
Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| b422d0b65e15435b6aef4a92f5663db9ec6659d4 |
|
03-May-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Fixed disassembler for vstm/vldm ARM VFP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| bb32f1d545241ab957f402165cec359d4473c0ca |
|
28-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Tweak tADDrSP definition for consistent operand order.
Make the operand order of the instruction match that of the asm syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 4d2f077df1b46a126b5595d983f233ec896b757e |
|
27-Apr-2012 |
Richard Barton <richard.barton@arm.com> |
Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155700 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| f4478f99dd63503bf0f0e763bc6d684e738bfe3d |
|
24-Apr-2012 |
Richard Barton <richard.barton@arm.com> |
Refactor Thumb ITState handling in ARM Disassembler to more efficiently use its vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 35ee7d28a69173ca0c11fb6b3271518bf4c5bff6 |
|
18-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added support for disassembling unpredictable swp/swpb ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| fa1ebc6abe95b79b7f82030eea53586a8704eb7e |
|
18-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| c5a2a33938182ccc5a1a94f7e1e2b3fdaff6a8b1 |
|
17-Apr-2012 |
Kevin Enderby <enderby@apple.com> |
Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)
instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 2a7d3a93735f97c2a4cabcc08a88d702c28cb0d4 |
|
13-Apr-2012 |
Kevin Enderby <enderby@apple.com> |
Fix a few more places in the ARM disassembler so that branches get
symbolic operands added when using the C disassembler API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154628 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| b318cc16c9e959adb96294b3aa4940e74f68dde3 |
|
12-Apr-2012 |
Kevin Enderby <enderby@apple.com> |
Fixed a case of ARM disassembly getting an assert on a bad encoding
of a VST instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154544 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| a69da35c127dd7e35ae6216d965670643dc55bb6 |
|
11-Apr-2012 |
Kevin Enderby <enderby@apple.com> |
Fix ARM disassembly of VLD instructions with writebacks. Â And add test a case
for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 75e3b7fb8fdf069b6f9f1e1db9634ca5701cbe96 |
|
03-Apr-2012 |
Dylan Noblesmith <nobled@dreamwidth.org> |
ARMDisassembler: drop bogus dependency on ARMCodeGen
And indirectly, a dependency on most of the core LLVM optimization
libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153957 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| c89c744b69cecac576317a98322fd295e36e9886 |
|
27-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unnecessary llvm:: qualifications
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 6fe310e1555dedba2b36dedae9a88eb900ad1804 |
|
22-Mar-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153252 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| b7c2ed66642b141a768b3074c465eba9d98665d8 |
|
22-Mar-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| f0586f08dfd5bf1889c15849e9c603b3985fce4a |
|
21-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test
case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 5c062ad92672f22e61a4b20a9954af3db3b72bd6 |
|
20-Mar-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| b78ca423844f19f4a838abb49b4b4fa7ae499707 |
|
11-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store registers and opcode in static tables in the target specific backends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| ff3164a1893c61dc0b7169dba9705c2d8e80dfec |
|
07-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Remove dead code that slipped into previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 4d0983a4d734280d481bb56472fe44ad0ddc447d |
|
07-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM more NEON VLD/VST composite physical register refactoring.
Register pair, all lanes subscripting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| c0fc450f0754508871bc70f21e528bf2f1520da1 |
|
06-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor more NEON VLD/VST instructions to use composite physregs
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 158c8a49c23d01297e7913c03c1fdb0760aee3a8 |
|
06-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| c3384c93c0e4c50da4ad093f08997507f9281c75 |
|
05-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM Refactor VLD/VST spaced pair instructions.
Use the new composite physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 28f08c93e75d291695ea89b9004145103292e85b |
|
05-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor away a bunch of VLD/VST pseudo instructions.
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| adef06a71458ded0716935a61b3d43d164d4df12 |
|
29-Feb-2012 |
Derek Schuff <dschuff@google.com> |
Make MemoryObject accessor members const again
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 0943303d31b1d1f2111725e2fa6906c0a785b96e |
|
27-Feb-2012 |
Kevin Enderby <enderby@apple.com> |
Fix the symbolic operand added for the C disassmbler API for the ARM bl
thumb instruction. The PC adjustment is +4 in Thumb mode and +8 in ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151530 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| b80d571ea85db5d52fafed0523cf59e693502198 |
|
23-Feb-2012 |
Kevin Enderby <enderby@apple.com> |
Updated the llvm-mc disassembler C API to support for the X86 target.
rdar://10873652
As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back. If there is a
getOpInfo call back that is tried first and then if that gets no information
then the SymbolLookUp is called. I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo. And also don't use any
values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683
For the X86 target also fixed bugs so the annotations get printed.
Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions. rdar://10878166
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151267 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
|
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 88b6fc06db667bd26d6ef661597affaa6abfdd0d |
|
11-Feb-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Make the EDis tables const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| bc2198133a1836598b54b943420748e75d5dea94 |
|
07-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 2ea93875b2f2900b9d244dfd7649c9ed02a34cd7 |
|
06-Feb-2012 |
Derek Schuff <dschuff@google.com> |
Enable streaming of bitcode
This CL delays reading of function bodies from initial parse until
materialization, allowing overlap of compilation with bitcode download.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 |
|
20-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
More dead code removal (using -Wunreachable-code)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 60d99a5278e4a0e7116a05c01cececb07ca1362a |
|
15-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VTBL/VTBX assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| bb3a2e4d0defc6854d37384d80858037dbbc5f20 |
|
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON refactor VST2 w/ writeback instructions.
In addition to improving the representation, this adds support for assembly
parsing of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| e90ac9bce9aa6de288568df9bf6133c08534ae2f |
|
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VST2 assembly parsing and encoding.
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| a4e3c7fc4ba2d55695b0484480685698132eba20 |
|
09-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD2 with writeback.
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 7b8e12152011ee21b1781113805a68cd3dc3d46b |
|
30-Nov-2011 |
Matt Beaumont-Gay <matthewbg@google.com> |
Remove unused variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 096334e25ea68ac970942ecb680a82fbb8ad206c |
|
30-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing for VLD1 all lanes, with writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 4c7edb3ad8bd513c59190f6ebee9bee34af7d247 |
|
29-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for four-register VST1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| d5ca201891d238ca2185831524a1e3f2670224df |
|
29-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for three-register VST1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145442 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 22925d93e9c5d6159f24853457c858be5f08af04 |
|
15-Nov-2011 |
Owen Anderson <resistor@mac.com> |
Fix a misplaced paren bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| b589be9334ee5352dd263c406b99a90d413c0b2f |
|
15-Nov-2011 |
Owen Anderson <resistor@mac.com> |
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144683 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 742c4bac07e2800275a69259296fba7c3e3f651b |
|
12-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Re-apply 144430, this time with the associated isel and disassmbler bits.
Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144437 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| eea66f63d98771a2772f5173debf954a81f3f782 |
|
11-Nov-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144384 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 244006db5c4d48878dc5fdc86976acdaff96cfaa |
|
02-Nov-2011 |
Owen Anderson <resistor@mac.com> |
The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143553 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| e31b42a6f5598691498808673648211916bf4d0f |
|
02-Nov-2011 |
Owen Anderson <resistor@mac.com> |
Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 60cb643f7561e5be7a3b5fe705535e96de72cbf5 |
|
01-Nov-2011 |
Owen Anderson <resistor@mac.com> |
Fix disassembly of some VST1 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143507 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 4334e032525d6c9038605f3871b945e8cbe6fab7 |
|
31-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VST1 w/ writeback assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143369 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| fb6ab2b30e822d292c557bda32f7eb0acd1004e2 |
|
31-Oct-2011 |
Owen Anderson <resistor@mac.com> |
More not-crashing NEON disassembly updates for the vld refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143351 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| cb9fed665550376b7c65c7e1157a58911193e2e2 |
|
28-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143208 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 04b12a4cfb74ac65ea86d57bde5999ef6ab09ad4 |
|
28-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Add some NEON stores to the VLD decoding hook that were accidentally omitted previously.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 399cdca4d201f7232126c3a0643669971ede780a |
|
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 with writeback.
Four entry register lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 5921675ff5ea632ab1e6d7aa5d1f263b858bbafa |
|
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 w/ writeback.
Three entry register list variation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 10b90a9bbf7dcae1568c03a03f9606f5395f2144 |
|
24-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor am6offset usage for VLD1.
Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| a7c98f58ea939e1dfe40bba725fbac698f36c0bb |
|
24-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142817 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 1a2f9886a2a60dbd41216468a240446bbfed3e76 |
|
22-Oct-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move various generated tables into read-only memory, fixing up const correctness along the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 224180e81b34c99d15e35a4d4de6729357c6d372 |
|
22-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 4-register sequential variant of VLD2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 4661d4cac3ba7f480a91d0ccd35fb2d22d9692d3 |
|
22-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 2-register sequential variant of VLD2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| b6310316dbaf8716003531d7ed245f77f1a76a11 |
|
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 4-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| cdcfa280568d5d48ebeba2dcfc87915105e090d1 |
|
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 3-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 280dfad48940a0a51726308dd3daa3b1b0d18705 |
|
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD parsing and encoding.
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 01817c39a9d7ff864d0b5de4941eec93d2f9e3a8 |
|
20-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| c378015d1cc073e5e8027491514f50e2c7413f9e |
|
17-Oct-2011 |
Chad Rosier <mcrosier@apple.com> |
Removed set, but unused variables.
Patch by Joe Abbey <jabbey@arxan.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142223 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 8223e45dff0f368ee40242f9e81f09b40e081756 |
|
14-Oct-2011 |
Richard Trieu <rtrieu@google.com> |
Fix a non-firing assert. Change:
assert("bad SymbolicOp.VariantKind");
To:
assert(0 && "bad SymbolicOp.VariantKind");
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142000 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| ecb830e45c216209f4a8b95d687f1ef4e9185bee |
|
14-Oct-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Fix undefined shift. Patch by Ahmed Charles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141914 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| c18e940c5a1c050701594ee2b356cd40249505a3 |
|
13-Oct-2011 |
Owen Anderson <resistor@mac.com> |
SETEND is not allowed in an IT block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141874 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 81b2928d80047cb6c8ae0048185742abae1d9dfa |
|
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM addrmode5 represents the 'U' bit of the encoding backwards.
The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141819 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| c66e7afcf2810a2c1ebf08514eaf45c478e5ff67 |
|
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDC/STC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| b0786b33fa9090adee9a30796ead7969f948f4cd |
|
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
addrmode2 is gone from these, so no need for the reg0 operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 7011eee9b509f3a0f95a75f68787384f31ea3e01 |
|
07-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 9e5887b17e634b98f7c1cf0ee4f25c218097d08e |
|
05-Oct-2011 |
Kevin Enderby <enderby@apple.com> |
Adding back support for printing operands symbolically to ARM's new disassembler
using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141129 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 4ebbf7b8a8e80532bd2ddf7209e62689c1698a96 |
|
30-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140834 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 0afa0094afdfe589f407feb76948f273b414b278 |
|
26-Sep-2011 |
Owen Anderson <resistor@mac.com> |
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 31d485ec9a2afcf83c5354061568b4280d61b574 |
|
23-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| df0caeb6eca5c3424b4ccef5f489708392450982 |
|
23-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Revert r140412. This affects more instructions than intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| d2560565810d40afea87f2dfbe51e125d0dc80ab |
|
23-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Thumb2 register-shifted-register loads cannot target the PC or the SP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140412 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| d9346fbb06d64266c2fe46edef7a15cb9af7e7e8 |
|
20-Sep-2011 |
Owen Anderson <resistor@mac.com> |
tMOVSr is not allowed in an IT block either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 9f666b5f2e4a5e94cd667e5be0c5d513dd64ea67 |
|
20-Sep-2011 |
Owen Anderson <resistor@mac.com> |
CPS instructions are UNPREDICTABLE inside IT blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 04c7877894492d6e8aa45567988cd7de100589d8 |
|
20-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140079 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 7f739bee261debdf56bd89ac922b57eca53e91dc |
|
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for TBB/TBH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| ecd1c557904815e568258fc5420de479589b0a93 |
|
19-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140032 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| cb775519279cd1471c490eb5bf4e3ce663fcdc7d |
|
17-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139972 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 8b22778431cdeb112366ed5dc6283b3a7af19018 |
|
17-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix bitfield decoding based on Eli's feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| e4f2df945a69e70f8e045baea3a14f3cdc076554 |
|
17-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139965 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 89db0f690c3238544e59ea3bf2b7a0d6bc8a6544 |
|
17-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139964 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 705b48ff860e7484f0adee88362dbe1936ae936b |
|
16-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 98c5ddabca1debf935a07d14d0cbc9732374bdb8 |
|
16-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139876 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 34626acf7fb042c3a831e2f7dfb653ea79c7adec |
|
14-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139736 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| a3157b402695ef9d5f6a03e8e3afc5bddf3a3df7 |
|
12-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 921d01ae1ff4e1dad2daeed22f8259a7a520412f |
|
10-Sep-2011 |
Owen Anderson <resistor@mac.com> |
LDM writeback is not allowed if Rn is in the target register list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 08fef885eb39339a47e3be7f0842b1db33683003 |
|
10-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 51f6a7abf27fc92c3d8904c2334feab8b498e8e9 |
|
09-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| b6aed508e310e31dcb080e761ca856127cec0773 |
|
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 441462f9328cc7fb86af74c9568a7f70b7bd1fbc |
|
09-Sep-2011 |
Owen Anderson <resistor@mac.com> |
All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| d2fc31b3f75700dc89305cb161f3bca7f1a39bef |
|
09-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| a77295db19527503d6b290e4f34f273d0a789365 |
|
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRD(immediate).
Refactor operand handling for STRD as well. Tests for that forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 170580e8f413271f665d78f349237c4bcaf9d8c4 |
|
08-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139268 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 8a83f71301fdf0e2cea8ecdf413f192ac48ddc5c |
|
07-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| a5d585685493d85d5cb72b831a68ec747ae55a86 |
|
07-Sep-2011 |
James Molloy <james.molloy@arm.com> |
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139250 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 6de3c6f1a926f49cca2fd207ab4eeb6c35e0e068 |
|
07-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139240 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| b950585cc5a0d665e9accfe5ce490cd269756f2e |
|
07-Sep-2011 |
James Molloy <james.molloy@arm.com> |
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139237 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| a1c110045a284190955f28b8f308ffb365cc2eda |
|
02-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Merge the ARM disassembler header into the implementation file, since it is not externally exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138982 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| a6804444e874b27aee5921d4c6049df573c5e249 |
|
02-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix 80 columns violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138980 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| c047dcade506a5acaccb1548cb83a3f85f52d71d |
|
01-Sep-2011 |
James Molloy <james.molloy@arm.com> |
Fix up r137380 based on post-commit review by Jim Grosbach.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| b45b11bce1fd79b0973d2df8db295583b5477c62 |
|
01-Sep-2011 |
Owen Anderson <resistor@mac.com> |
The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| eaca928a3798e1fa7072457b94eccdd5b53b5d5f |
|
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| f1eab597b2316c6cfcabfcee98895fedb2071722 |
|
27-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 9f7e8319947c65d9aef2a0f0984557c3b3a20656 |
|
26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Spelling fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 9ab0f25fc194b4315db1b87d38d4024054120bf6 |
|
26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 1af7f7291d0689e2d58f900c9b5ecaddec56caa1 |
|
26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Update for feedback from Jim.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 86ce852a15f0c66601dcaf55644d8c4ec268906f |
|
26-Aug-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
ARMDisassembler: Always return a size, even when disassembling fails.
This should fix PR10772.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 96425c846494c1c20a4c931f4783571295ab170c |
|
26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 9bd655dcde1cfa1b97014e2d8e4f9845f7d474bb |
|
26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 99906830e82cf70dbcbed22237c7bd24f9d9ffdb |
|
25-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| f44082091c5517a3275c57a8b58e36987c8227f0 |
|
25-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138507 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 12a1e3bbcbd4e8f740c8304379001d1e6731561c |
|
24-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Be careful not to walk off the end of the operand info list while updating VFP predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138492 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 3e74d6fdd248e20a280f1dff3da9a6c689c2c4c3 |
|
24-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move TargetRegistry and TargetSelect from Target to Support where they belong.
These are strictly utilities for registering targets and components.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| e234d02204e0e546c3555e7e894b8521d22a2121 |
|
24-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138443 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 82265a2c72b0f2d0daeab4985c9509d8405f51ef |
|
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138341 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 6153a036f544beb03dfc4d58edc28cf42712743d |
|
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 8e1e60b5f8fd9c6233bdb8814ee40887555a0594 |
|
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Reject invalid imod values in t2CPS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138306 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 357ec6850be0dff0038ea3a14f16066705284c0b |
|
22-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138269 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 2cbf2104507c855850b610ed910536058aa0c6ee |
|
22-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| f1c8e3e70e222365b84f4cb7e87396ee85820711 |
|
22-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| b113ec55e897c85fda606409c1eedec4f89ec53f |
|
22-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 78affc9ea1978d707b376180ec559b62fbf9ea05 |
|
19-Aug-2011 |
Owen Anderson <resistor@mac.com> |
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
Found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138003 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 846dd95f87f62e2faa6092f99b521ecd9790121a |
|
19-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138000 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 1dd56f05e1bc3e7f66f2b0de4b5ea3692136a77f |
|
19-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 14090bf2636edf5e46a2c12a312b1889f5335d7d |
|
19-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
Fixes a large class of disassembler crashes found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| c40578250d391069d2d81ecaab58a83f2667e96e |
|
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137881 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 70939ee1415722d7f39f13faf9b3644b96007996 |
|
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM clean up the imm_sr operand class representation.
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 0aa38ab1fb53c457ce90390aed2659eb085709f0 |
|
17-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 83e3f67fb68d497b600da83a62f000fcce7868a9 |
|
17-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137830 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 16280308ac6f20d9da06eafcc19e4a6777f49750 |
|
17-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137787 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| ef2865a8eadffd7e346b9bc70c647578010b6afd |
|
16-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137686 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| c537f3be0c4ff7030afcdcd9f55133ce68eef773 |
|
15-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137647 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 7a2e1770ead7c2e3b7292ae466a41b560f3d272c |
|
15-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 0d09499cf3e2d927cdc53ec79895303ac12808ac |
|
12-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 79628e92e1f903d50340d4cd3d1ea8c5fff63a87 |
|
12-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding of ARM-mode STRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137499 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 7cdbf086e4676494fc6a5b26c169285ae0bb740b |
|
12-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding of pre-indexed stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137487 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 3f3570a38be37ca18c545bd1b4c89604ecaf7e31 |
|
12-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Separate decoding for STREXD and LDREXD to make each work better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 342ebd5f380637d965504dcc350f9d0d79bbe599 |
|
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137372 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| adf2b094cb66e6b3ca318cf5b92d0b5232a7d420 |
|
12-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add another accidentally omitted predicate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 1fb6673bc2f0a404f4f914bf381c627402ac7c6b |
|
12-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add missing predicate operand on SMLA and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| cbfc044acd722d14d0687c9cf099f3dca45e26d5 |
|
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding support for STREXD and LDREXD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137356 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 508e1d3db536b736063385eb1f885b446a1385ca |
|
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137347 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 26d2f0ac919f6ae868fe901fd4ad64af6f92da4d |
|
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Continue to tighten decoding by performing more operand validation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 10348e70d567fb61f6c762d99e91e215c720ebd1 |
|
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRBT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 71156a6e00d3dc4c531a421a76b3b6ee0ae7d0ab |
|
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137325 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 2b7b238e843cbbe0682a3cc001fe514f4270a984 |
|
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| ae0bc5deaa30f1e20a6189e42ca412ba27ec7153 |
|
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve error checking in the new ARM disassembler. Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 59999264e6cfc7f5d59c9a92c8cd9baaa53434f4 |
|
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDRT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137282 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 8533ebad6f6e407215497ca50771f323058f5576 |
|
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add initial support for decoding NEON instructions in Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 10cbaab7b774e187c99790292dc1ed64dee2b0f3 |
|
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Cleanups based on Nick Lewycky's feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 33e57515b173baf572398fafeffcf4644c2a7381 |
|
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| de317f40f7a9962372adea162a12ec35a628efa1 |
|
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tighten operand checking of register-shifted-register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| c36481c4744cdbddec91dc3eca9245acaf2982da |
|
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tighten operand checking on memory barrier instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137176 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 35008c2f8dcfe55960fe4efea3a26e526d437ad6 |
|
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tighten operand checking on CPS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 51c9805c4bcca635bc6a854e4a246ebd4258f512 |
|
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 793b811c5057365d847b7f9ae326358e76facfe2 |
|
10-Aug-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
ARM Disassembler: sign extend branch immediates.
Not sure about BLXi, but this is what the old disassembler did.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137156 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 51157d22348fdbd4b7975877d5b58e53a6d5d3a2 |
|
09-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Silence an false-positive warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137154 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| bd9091c18d85d6649763165c4951d7b5ff2e31a9 |
|
09-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Tighten Thumb1 branch predicate decoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137146 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 8d7d2e1238fac58c01ccfb719d0cc5680a079561 |
|
09-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 7ce057983ea7b8ad42d5cca1bb5d3f6941662269 |
|
04-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 4aaf3465f71afa4e156eb15df12095ebde1b0f6f |
|
20-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix typo in the comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129837 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| bd3327654b5708f1ba92aff3ab25b1bbf5034797 |
|
11-Apr-2011 |
Kevin Enderby <enderby@apple.com> |
Adding support for printing operands symbolically to llvm's public 'C'
disassembler API. Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
blx _puts
instead of this:
blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| eca915fb5242442756a80bad7f285cb54d7b8ea4 |
|
26-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fixed the t2PLD and friends disassembly and add two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 8cb988686d4d55eace0cb4aac408d790c02a120b |
|
24-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 83ccbff84fd38d8680ae39b3b629aee339478855 |
|
24-Mar-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Plug a leak in the arm disassembler and put the tests back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| c59c87c3228b471140fb219dc9118ab9321486f2 |
|
23-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
For ARM Disassembler, start a newline to dump the opcode and friends for an instruction.
Change inspired by llvm-bug 9530 submitted by Jyun-Yan You.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 18b475f95478f130667faa8c74bea4efdf68b1ed |
|
09-Mar-2011 |
Johnny Chen <johnny.chen@apple.com> |
LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.
The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16. Add extra logic to recover from that.
Fixed an assert reported by Sean Callanan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 971b83b67a9812556cdb97bb58aa96fb37af458d |
|
08-Feb-2011 |
Owen Anderson <resistor@mac.com> |
Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| eb6779c5b98383e33542207f062102e79263df16 |
|
07-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121082 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|
| 9d63d90de5e57ad96f467b270544443a9284eb2b |
|
01-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120589 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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| 80dd3e06129e2b570cbd65cba850571981df693a |
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30-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the
Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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| bc7deb0f758d2544fc4c36433668340cbf4835cf |
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03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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| 55561d188246e128e6c452d2e254cfd9fd359f2e |
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14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Detabify and clean up 80 column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116454 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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| 38e1390c29c024d5bbff3063c2a86bceb7bd3e60 |
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28-Sep-2010 |
Oscar Fuentes <ofv@wanadoo.es> |
Add ARM Disassembler to the CMake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114949 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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| 186acea74646c9f3909b1968920bed8c7ab6148b |
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08-Sep-2010 |
NAKAMURA Takumi <geek4civic@gmail.com> |
ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to Cygwin-1.5, following up to r113255.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113345 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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| 270159fcc21e06c67aa571d10d2b22d41d9a751a |
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12-Aug-2010 |
Johnny Chen <johnny.chen@apple.com> |
The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.
Added a "usat" test case to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110894 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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| eaf1c98a7c38444d41d1c6dc2074736eec7d452f |
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12-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Move the ARM SSAT and USAT optional shift amount operand out of the
instruction opcode. This also fixes part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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| ef37e3abb7fdcdb773163e4e48743b2f7b2141b3 |
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20-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111',
transform the Opcode to the corresponding t2LDR*pci counterpart.
Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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| 6bcf52f00a4fc352e90ff11681a0e69f9757eb37 |
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20-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
More IT instruction error-handling improvements from fuzzing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101839 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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| d0f3c46d166b5d0ab4573987011cab7bd1ec28e0 |
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20-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Better error handling of invalid IT mask '0000', instead of just asserting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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| af5b0e851e42d7de1247c4084ba75a76c4497ca6 |
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17-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed logic error. Should check Builder for validity before calling SetSession
on it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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| d907d2566af966333cf170fae27b3e7847a855a4 |
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14-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fixed another assert exposed by fuzzing. The utility function getRegisterEnum()
was asserting because the (RegClass, RegNum) combination doesn't make sense from
an encoding point of view.
Since getRegisterEnum() is used all over the place, to change the code to check
for encoding error after each call would not only bloat the code, but also make
it less readable. An Err flag is added to the ARMBasicMCBuilder where a client
can set a non-zero value to indicate some kind of error condition while building
up the MCInst. ARMBasicMCBuilder::BuildIt() checks this flag and returns false
if a non-zero value is detected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101290 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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| 9899f70a7406d632c82849978bf6981f1ee4ccb5 |
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13-Apr-2010 |
Sean Callanan <scallanan@apple.com> |
Fixed a nasty layering violation in the edis source
code. It used to #include the enhanced disassembly
information for the targets it supported straight
out of lib/Target/{X86,ARM,...} but now it uses a
new interface provided by MCDisassembler, and (so
far) implemented by X86 and ARM.
Also removed hacky #define-controlled initialization
of targets in edis. If clients only want edis to
initialize a limited set of targets, they can set
--enable-targets on the configure command line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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| 7fb053dd45f7754b0a359a9de1a7445aefcca318 |
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05-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Get rid of traling whitespaces. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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| 9d563b676cc9f3bcd9a9806ea5e9a791f35e3d70 |
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05-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
The disassembler impl. of MCDisassembler::getInstruction() was using the pattern
uint32_t insn;
MemoryObject.readBytes(Address, 4, (uint8_t*)&insn, NULL)
to read 4 bytes of memory contents into a 32-bit uint variable. This leaves the
interpretation of byte order up to the host machine and causes PPC test cases of
arm-tests, neon-tests, and thumb-tests to fail. Fixed to use a byte array for
reading the memory contents and shift the bytes into place for the 32-bit uint
variable in the ARM case and 16-bit halfword in the Thumb case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100403 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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| b68a3ee82a8a34f7bae1d68d76f574e76a5535ef |
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03-Apr-2010 |
Johnny Chen <johnny.chen@apple.com> |
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.
Reviewed by Chris Latter and Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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| 49d9dc4dd205b615beb7af160ef974eaabe4d1cf |
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16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
--- Reverse-merging r98637 into '.':
U test/CodeGen/ARM/tls2.ll
U test/CodeGen/ARM/arm-negative-stride.ll
U test/CodeGen/ARM/2009-10-30.ll
U test/CodeGen/ARM/globals.ll
U test/CodeGen/ARM/str_pre-2.ll
U test/CodeGen/ARM/ldrd.ll
U test/CodeGen/ARM/2009-10-27-double-align.ll
U test/CodeGen/Thumb2/thumb2-strb.ll
U test/CodeGen/Thumb2/ldr-str-imm12.ll
U test/CodeGen/Thumb2/thumb2-strh.ll
U test/CodeGen/Thumb2/thumb2-ldr.ll
U test/CodeGen/Thumb2/thumb2-str_pre.ll
U test/CodeGen/Thumb2/thumb2-str.ll
U test/CodeGen/Thumb2/thumb2-ldrh.ll
U utils/TableGen/TableGen.cpp
U utils/TableGen/DisassemblerEmitter.cpp
D utils/TableGen/RISCDisassemblerEmitter.h
D utils/TableGen/RISCDisassemblerEmitter.cpp
U Makefile.rules
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/Makefile
U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
D lib/Target/ARM/Disassembler
U lib/Target/ARM/ARMInstrFormats.td
U lib/Target/ARM/ARMAddressingModes.h
U lib/Target/ARM/Thumb2ITBlockPass.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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| d30a98e43ae18e1fc70a7dc748edf669d809c685 |
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16-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Initial ARM/Thumb disassembler check-in. It consists of a tablgen backend
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.
We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60.
And modified test cases to not expect '+' in +reg or #+num. For example,
; CHECK: ldr.w r9, [r7, #28]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98637 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
|