HexagonISelLowering.cpp revision 4c1ea552c54eefceeb7489a794a6d18b01c29900 
1//===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the interfaces that Hexagon uses to lower LLVM code
11// into a selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "HexagonISelLowering.h"
16#include "HexagonTargetMachine.h"
17#include "HexagonMachineFunctionInfo.h"
18#include "HexagonTargetObjectFile.h"
19#include "HexagonSubtarget.h"
20#include "llvm/DerivedTypes.h"
21#include "llvm/Function.h"
22#include "llvm/InlineAsm.h"
23#include "llvm/GlobalVariable.h"
24#include "llvm/GlobalAlias.h"
25#include "llvm/Intrinsics.h"
26#include "llvm/CallingConv.h"
27#include "llvm/CodeGen/CallingConvLower.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/CodeGen/MachineJumpTableInfo.h"
37#include "HexagonMachineFunctionInfo.h"
38#include "llvm/Support/CommandLine.h"
39
40const unsigned Hexagon_MAX_RET_SIZE = 64;
41using namespace llvm;
42
43static cl::opt<bool>
44EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden,
45               cl::desc("Control jump table emission on Hexagon target"));
46
47int NumNamedVarArgParams = -1;
48
49// Implement calling convention for Hexagon.
50static bool
51CC_Hexagon(unsigned ValNo, MVT ValVT,
52           MVT LocVT, CCValAssign::LocInfo LocInfo,
53           ISD::ArgFlagsTy ArgFlags, CCState &State);
54
55static bool
56CC_Hexagon32(unsigned ValNo, MVT ValVT,
57             MVT LocVT, CCValAssign::LocInfo LocInfo,
58             ISD::ArgFlagsTy ArgFlags, CCState &State);
59
60static bool
61CC_Hexagon64(unsigned ValNo, MVT ValVT,
62             MVT LocVT, CCValAssign::LocInfo LocInfo,
63             ISD::ArgFlagsTy ArgFlags, CCState &State);
64
65static bool
66RetCC_Hexagon(unsigned ValNo, MVT ValVT,
67              MVT LocVT, CCValAssign::LocInfo LocInfo,
68              ISD::ArgFlagsTy ArgFlags, CCState &State);
69
70static bool
71RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
72                MVT LocVT, CCValAssign::LocInfo LocInfo,
73                ISD::ArgFlagsTy ArgFlags, CCState &State);
74
75static bool
76RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
77                MVT LocVT, CCValAssign::LocInfo LocInfo,
78                ISD::ArgFlagsTy ArgFlags, CCState &State);
79
80static bool
81CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
82            MVT LocVT, CCValAssign::LocInfo LocInfo,
83            ISD::ArgFlagsTy ArgFlags, CCState &State) {
84
85  // NumNamedVarArgParams can not be zero for a VarArg function.
86  assert ( (NumNamedVarArgParams > 0) &&
87           "NumNamedVarArgParams is not bigger than zero.");
88
89  if ( (int)ValNo < NumNamedVarArgParams ) {
90    // Deal with named arguments.
91    return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
92  }
93
94  // Deal with un-named arguments.
95  unsigned ofst;
96  if (ArgFlags.isByVal()) {
97    // If pass-by-value, the size allocated on stack is decided
98    // by ArgFlags.getByValSize(), not by the size of LocVT.
99    assert ((ArgFlags.getByValSize() > 8) &&
100            "ByValSize must be bigger than 8 bytes");
101    ofst = State.AllocateStack(ArgFlags.getByValSize(), 4);
102    State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
103    return false;
104  }
105  if (LocVT == MVT::i32) {
106    ofst = State.AllocateStack(4, 4);
107    State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
108    return false;
109  }
110  if (LocVT == MVT::i64) {
111    ofst = State.AllocateStack(8, 8);
112    State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
113    return false;
114  }
115  llvm_unreachable(0);
116
117  return true;
118}
119
120
121static bool
122CC_Hexagon (unsigned ValNo, MVT ValVT,
123            MVT LocVT, CCValAssign::LocInfo LocInfo,
124            ISD::ArgFlagsTy ArgFlags, CCState &State) {
125
126  if (ArgFlags.isByVal()) {
127    // Passed on stack.
128    assert ((ArgFlags.getByValSize() > 8) &&
129            "ByValSize must be bigger than 8 bytes");
130    unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 4);
131    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
132    return false;
133  }
134
135  if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
136    LocVT = MVT::i32;
137    ValVT = MVT::i32;
138    if (ArgFlags.isSExt())
139      LocInfo = CCValAssign::SExt;
140    else if (ArgFlags.isZExt())
141      LocInfo = CCValAssign::ZExt;
142    else
143      LocInfo = CCValAssign::AExt;
144  }
145
146  if (LocVT == MVT::i32) {
147    if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
148      return false;
149  }
150
151  if (LocVT == MVT::i64) {
152    if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
153      return false;
154  }
155
156  return true;  // CC didn't match.
157}
158
159
160static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
161                         MVT LocVT, CCValAssign::LocInfo LocInfo,
162                         ISD::ArgFlagsTy ArgFlags, CCState &State) {
163
164  static const unsigned RegList[] = {
165    Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
166    Hexagon::R5
167  };
168  if (unsigned Reg = State.AllocateReg(RegList, 6)) {
169    State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
170    return false;
171  }
172
173  unsigned Offset = State.AllocateStack(4, 4);
174  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
175  return false;
176}
177
178static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
179                         MVT LocVT, CCValAssign::LocInfo LocInfo,
180                         ISD::ArgFlagsTy ArgFlags, CCState &State) {
181
182  if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
183    State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
184    return false;
185  }
186
187  static const unsigned RegList1[] = {
188    Hexagon::D1, Hexagon::D2
189  };
190  static const unsigned RegList2[] = {
191    Hexagon::R1, Hexagon::R3
192  };
193  if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) {
194    State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
195    return false;
196  }
197
198  unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
199  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
200  return false;
201}
202
203static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
204                          MVT LocVT, CCValAssign::LocInfo LocInfo,
205                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
206
207
208  if (LocVT == MVT::i1 ||
209      LocVT == MVT::i8 ||
210      LocVT == MVT::i16) {
211    LocVT = MVT::i32;
212    ValVT = MVT::i32;
213    if (ArgFlags.isSExt())
214      LocInfo = CCValAssign::SExt;
215    else if (ArgFlags.isZExt())
216      LocInfo = CCValAssign::ZExt;
217    else
218      LocInfo = CCValAssign::AExt;
219  }
220
221  if (LocVT == MVT::i32) {
222    if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
223    return false;
224  }
225
226  if (LocVT == MVT::i64) {
227    if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
228    return false;
229  }
230
231  return true;  // CC didn't match.
232}
233
234static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
235                            MVT LocVT, CCValAssign::LocInfo LocInfo,
236                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
237
238  if (LocVT == MVT::i32) {
239    if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
240      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
241      return false;
242    }
243  }
244
245  unsigned Offset = State.AllocateStack(4, 4);
246  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
247  return false;
248}
249
250static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
251                            MVT LocVT, CCValAssign::LocInfo LocInfo,
252                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
253  if (LocVT == MVT::i64) {
254    if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
255      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
256      return false;
257    }
258  }
259
260  unsigned Offset = State.AllocateStack(8, 8);
261  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
262  return false;
263}
264
265SDValue
266HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
267const {
268  return SDValue();
269}
270
271/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
272/// by "Src" to address "Dst" of size "Size".  Alignment information is
273/// specified by the specific parameter attribute. The copy will be passed as
274/// a byval function parameter.  Sometimes what we are copying is the end of a
275/// larger object, the part that does not fit in registers.
276static SDValue
277CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
278                          ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
279                          DebugLoc dl) {
280
281  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
282  return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
283                       /*isVolatile=*/false, /*AlwaysInline=*/false,
284                       MachinePointerInfo(), MachinePointerInfo());
285}
286
287
288// LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
289// passed by value, the function prototype is modified to return void and
290// the value is stored in memory pointed by a pointer passed by caller.
291SDValue
292HexagonTargetLowering::LowerReturn(SDValue Chain,
293                                   CallingConv::ID CallConv, bool isVarArg,
294                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
295                                   const SmallVectorImpl<SDValue> &OutVals,
296                                   DebugLoc dl, SelectionDAG &DAG) const {
297
298  // CCValAssign - represent the assignment of the return value to locations.
299  SmallVector<CCValAssign, 16> RVLocs;
300
301  // CCState - Info about the registers and stack slot.
302  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
303		 getTargetMachine(), RVLocs, *DAG.getContext());
304
305  // Analyze return values of ISD::RET
306  CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
307
308  // If this is the first return lowered for this function, add the regs to the
309  // liveout set for the function.
310  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
311    for (unsigned i = 0; i != RVLocs.size(); ++i)
312      if (RVLocs[i].isRegLoc())
313        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
314  }
315
316  SDValue Flag;
317  // Copy the result values into the output registers.
318  for (unsigned i = 0; i != RVLocs.size(); ++i) {
319    CCValAssign &VA = RVLocs[i];
320
321    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
322
323    // Guarantee that all emitted copies are stuck together with flags.
324    Flag = Chain.getValue(1);
325  }
326
327  if (Flag.getNode())
328    return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
329
330  return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, Chain);
331}
332
333
334
335
336/// LowerCallResult - Lower the result values of an ISD::CALL into the
337/// appropriate copies out of appropriate physical registers.  This assumes that
338/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
339/// being lowered. Returns a SDNode with the same number of values as the
340/// ISD::CALL.
341SDValue
342HexagonTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
343                                       CallingConv::ID CallConv, bool isVarArg,
344                                       const
345                                       SmallVectorImpl<ISD::InputArg> &Ins,
346                                       DebugLoc dl, SelectionDAG &DAG,
347                                       SmallVectorImpl<SDValue> &InVals,
348                                       const SmallVectorImpl<SDValue> &OutVals,
349                                       SDValue Callee) const {
350
351  // Assign locations to each value returned by this call.
352  SmallVector<CCValAssign, 16> RVLocs;
353
354  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
355		 getTargetMachine(), RVLocs, *DAG.getContext());
356
357  CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
358
359  // Copy all of the result registers out of their specified physreg.
360  for (unsigned i = 0; i != RVLocs.size(); ++i) {
361    Chain = DAG.getCopyFromReg(Chain, dl,
362                               RVLocs[i].getLocReg(),
363                               RVLocs[i].getValVT(), InFlag).getValue(1);
364    InFlag = Chain.getValue(2);
365    InVals.push_back(Chain.getValue(0));
366  }
367
368  return Chain;
369}
370
371/// LowerCall - Functions arguments are copied from virtual regs to
372/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
373SDValue
374HexagonTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
375                                 CallingConv::ID CallConv, bool isVarArg,
376                                 bool &isTailCall,
377                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
378                                 const SmallVectorImpl<SDValue> &OutVals,
379                                 const SmallVectorImpl<ISD::InputArg> &Ins,
380                                 DebugLoc dl, SelectionDAG &DAG,
381                                 SmallVectorImpl<SDValue> &InVals) const {
382
383  bool IsStructRet    = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
384
385  // Analyze operands of the call, assigning locations to each operand.
386  SmallVector<CCValAssign, 16> ArgLocs;
387  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
388		 getTargetMachine(), ArgLocs, *DAG.getContext());
389
390  // Check for varargs.
391  NumNamedVarArgParams = -1;
392  if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Callee))
393  {
394    const Function* CalleeFn = NULL;
395    Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, MVT::i32);
396    if ((CalleeFn = dyn_cast<Function>(GA->getGlobal())))
397    {
398      // If a function has zero args and is a vararg function, that's
399      // disallowed so it must be an undeclared function.  Do not assume
400      // varargs if the callee is undefined.
401      if (CalleeFn->isVarArg() &&
402          CalleeFn->getFunctionType()->getNumParams() != 0) {
403        NumNamedVarArgParams = CalleeFn->getFunctionType()->getNumParams();
404      }
405    }
406  }
407
408  if (NumNamedVarArgParams > 0)
409    CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
410  else
411    CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
412
413
414  if(isTailCall) {
415    bool StructAttrFlag =
416      DAG.getMachineFunction().getFunction()->hasStructRetAttr();
417    isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
418                                                   isVarArg, IsStructRet,
419                                                   StructAttrFlag,
420                                                   Outs, OutVals, Ins, DAG);
421    for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i){
422      CCValAssign &VA = ArgLocs[i];
423      if (VA.isMemLoc()) {
424        isTailCall = false;
425        break;
426      }
427    }
428    if (isTailCall) {
429      DEBUG(dbgs () << "Eligible for Tail Call\n");
430    } else {
431      DEBUG(dbgs () <<
432            "Argument must be passed on stack. Not eligible for Tail Call\n");
433    }
434  }
435  // Get a count of how many bytes are to be pushed on the stack.
436  unsigned NumBytes = CCInfo.getNextStackOffset();
437  SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
438  SmallVector<SDValue, 8> MemOpChains;
439
440  SDValue StackPtr =
441    DAG.getCopyFromReg(Chain, dl, TM.getRegisterInfo()->getStackRegister(),
442                       getPointerTy());
443
444  // Walk the register/memloc assignments, inserting copies/loads.
445  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
446    CCValAssign &VA = ArgLocs[i];
447    SDValue Arg = OutVals[i];
448    ISD::ArgFlagsTy Flags = Outs[i].Flags;
449
450    // Promote the value if needed.
451    switch (VA.getLocInfo()) {
452      default:
453        // Loc info must be one of Full, SExt, ZExt, or AExt.
454        assert(0 && "Unknown loc info!");
455      case CCValAssign::Full:
456        break;
457      case CCValAssign::SExt:
458        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
459        break;
460      case CCValAssign::ZExt:
461        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
462        break;
463      case CCValAssign::AExt:
464        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
465        break;
466    }
467
468    if (VA.isMemLoc()) {
469      unsigned LocMemOffset = VA.getLocMemOffset();
470      SDValue PtrOff = DAG.getConstant(LocMemOffset, StackPtr.getValueType());
471      PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
472
473      if (Flags.isByVal()) {
474        // The argument is a struct passed by value. According to LLVM, "Arg"
475        // is is pointer.
476        MemOpChains.push_back(CreateCopyOfByValArgument(Arg, PtrOff, Chain,
477                                                        Flags, DAG, dl));
478      } else {
479        // The argument is not passed by value. "Arg" is a buildin type. It is
480        // not a pointer.
481        MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
482                                           MachinePointerInfo(),false, false,
483                                           0));
484      }
485      continue;
486    }
487
488    // Arguments that can be passed on register must be kept at RegsToPass
489    // vector.
490    if (VA.isRegLoc()) {
491      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
492    }
493  }
494
495  // Transform all store nodes into one single node because all store
496  // nodes are independent of each other.
497  if (!MemOpChains.empty()) {
498    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0],
499                        MemOpChains.size());
500  }
501
502  if (!isTailCall)
503    Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes,
504                                                        getPointerTy(), true));
505
506  // Build a sequence of copy-to-reg nodes chained together with token
507  // chain and flag operands which copy the outgoing args into registers.
508  // The InFlag in necessary since all emited instructions must be
509  // stuck together.
510  SDValue InFlag;
511  if (!isTailCall) {
512    for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
513      Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
514                               RegsToPass[i].second, InFlag);
515      InFlag = Chain.getValue(1);
516    }
517  }
518
519  // For tail calls lower the arguments to the 'real' stack slot.
520  if (isTailCall) {
521    // Force all the incoming stack arguments to be loaded from the stack
522    // before any new outgoing arguments are stored to the stack, because the
523    // outgoing stack slots may alias the incoming argument stack slots, and
524    // the alias isn't otherwise explicit. This is slightly more conservative
525    // than necessary, because it means that each store effectively depends
526    // on every argument instead of just those arguments it would clobber.
527    //
528    // Do not flag preceeding copytoreg stuff together with the following stuff.
529    InFlag = SDValue();
530    for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
531      Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
532                               RegsToPass[i].second, InFlag);
533      InFlag = Chain.getValue(1);
534    }
535    InFlag =SDValue();
536  }
537
538  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
539  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
540  // node so that legalize doesn't hack it.
541  if (flag_aligned_memcpy) {
542    const char *MemcpyName =
543      "__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes";
544    Callee =
545      DAG.getTargetExternalSymbol(MemcpyName, getPointerTy());
546    flag_aligned_memcpy = false;
547  } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
548    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy());
549  } else if (ExternalSymbolSDNode *S =
550             dyn_cast<ExternalSymbolSDNode>(Callee)) {
551    Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
552  }
553
554  // Returns a chain & a flag for retval copy to use.
555  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
556  SmallVector<SDValue, 8> Ops;
557  Ops.push_back(Chain);
558  Ops.push_back(Callee);
559
560  // Add argument registers to the end of the list so that they are
561  // known live into the call.
562  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
563    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
564                                  RegsToPass[i].second.getValueType()));
565  }
566
567  if (InFlag.getNode()) {
568    Ops.push_back(InFlag);
569  }
570
571  if (isTailCall)
572    return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
573
574  Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
575  InFlag = Chain.getValue(1);
576
577  // Create the CALLSEQ_END node.
578  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
579                             DAG.getIntPtrConstant(0, true), InFlag);
580  InFlag = Chain.getValue(1);
581
582  // Handle result values, copying them out of physregs into vregs that we
583  // return.
584  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
585                         InVals, OutVals, Callee);
586}
587
588static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
589                                   bool isSEXTLoad, SDValue &Base,
590                                   SDValue &Offset, bool &isInc,
591                                   SelectionDAG &DAG) {
592  if (Ptr->getOpcode() != ISD::ADD)
593  return false;
594
595  if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
596    isInc = (Ptr->getOpcode() == ISD::ADD);
597    Base = Ptr->getOperand(0);
598    Offset = Ptr->getOperand(1);
599    // Ensure that Offset is a constant.
600    return (isa<ConstantSDNode>(Offset));
601  }
602
603  return false;
604}
605
606// TODO: Put this function along with the other isS* functions in
607// HexagonISelDAGToDAG.cpp into a common file. Or better still, use the
608// functions defined in HexagonImmediates.td.
609static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) {
610  ConstantSDNode *N = cast<ConstantSDNode>(S);
611
612  // immS4 predicate - True if the immediate fits in a 4-bit sign extended.
613  // field.
614  int64_t v = (int64_t)N->getSExtValue();
615  int64_t m = 0;
616  if (ShiftAmount > 0) {
617    m = v % ShiftAmount;
618    v = v >> ShiftAmount;
619  }
620  return (v <= 7) && (v >= -8) && (m == 0);
621}
622
623/// getPostIndexedAddressParts - returns true by value, base pointer and
624/// offset pointer and addressing mode by reference if this node can be
625/// combined with a load / store to form a post-indexed load / store.
626bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
627                                                       SDValue &Base,
628                                                       SDValue &Offset,
629                                                       ISD::MemIndexedMode &AM,
630                                                       SelectionDAG &DAG) const
631{
632  EVT VT;
633  SDValue Ptr;
634  bool isSEXTLoad = false;
635
636  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
637    VT  = LD->getMemoryVT();
638    isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
639  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
640    VT  = ST->getMemoryVT();
641    if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) {
642      return false;
643    }
644  } else {
645    return false;
646  }
647
648  bool isInc;
649  bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
650                                        isInc, DAG);
651  // ShiftAmount = number of left-shifted bits in the Hexagon instruction.
652  int ShiftAmount = VT.getSizeInBits() / 16;
653  if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) {
654    AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
655    return true;
656  }
657
658  return false;
659}
660
661SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op,
662                                              SelectionDAG &DAG) const {
663  SDNode *Node = Op.getNode();
664  MachineFunction &MF = DAG.getMachineFunction();
665  HexagonMachineFunctionInfo *FuncInfo =
666    MF.getInfo<HexagonMachineFunctionInfo>();
667  switch (Node->getOpcode()) {
668    case ISD::INLINEASM: {
669      unsigned NumOps = Node->getNumOperands();
670      if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
671        --NumOps;  // Ignore the flag operand.
672
673      for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
674        if (FuncInfo->hasClobberLR())
675          break;
676        unsigned Flags =
677          cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
678        unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
679        ++i;  // Skip the ID value.
680
681        switch (InlineAsm::getKind(Flags)) {
682        default: llvm_unreachable("Bad flags!");
683          case InlineAsm::Kind_RegDef:
684          case InlineAsm::Kind_RegUse:
685          case InlineAsm::Kind_Imm:
686          case InlineAsm::Kind_Clobber:
687          case InlineAsm::Kind_Mem: {
688            for (; NumVals; --NumVals, ++i) {}
689            break;
690          }
691          case InlineAsm::Kind_RegDefEarlyClobber: {
692            for (; NumVals; --NumVals, ++i) {
693              unsigned Reg =
694                cast<RegisterSDNode>(Node->getOperand(i))->getReg();
695
696              // Check it to be lr
697              if (Reg == TM.getRegisterInfo()->getRARegister()) {
698                FuncInfo->setHasClobberLR(true);
699                break;
700              }
701            }
702            break;
703          }
704        }
705      }
706    }
707  } // Node->getOpcode
708  return Op;
709}
710
711
712//
713// Taken from the XCore backend.
714//
715SDValue HexagonTargetLowering::
716LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
717{
718  SDValue Chain = Op.getOperand(0);
719  SDValue Table = Op.getOperand(1);
720  SDValue Index = Op.getOperand(2);
721  DebugLoc dl = Op.getDebugLoc();
722  JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
723  unsigned JTI = JT->getIndex();
724  MachineFunction &MF = DAG.getMachineFunction();
725  const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
726  SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
727
728  // Mark all jump table targets as address taken.
729  const std::vector<MachineJumpTableEntry> &JTE = MJTI->getJumpTables();
730  const std::vector<MachineBasicBlock*> &JTBBs = JTE[JTI].MBBs;
731  for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
732    MachineBasicBlock *MBB = JTBBs[i];
733    MBB->setHasAddressTaken();
734    // This line is needed to set the hasAddressTaken flag on the BasicBlock
735    // object.
736    BlockAddress::get(const_cast<BasicBlock *>(MBB->getBasicBlock()));
737  }
738
739  SDValue JumpTableBase = DAG.getNode(HexagonISD::WrapperJT, dl,
740                                      getPointerTy(), TargetJT);
741  SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
742                                   DAG.getConstant(2, MVT::i32));
743  SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase,
744                                  ShiftIndex);
745  SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress,
746                                   MachinePointerInfo(), false, false, false,
747                                   0);
748  return DAG.getNode(HexagonISD::BR_JT, dl, MVT::Other, Chain, LoadTarget);
749}
750
751
752SDValue
753HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
754                                               SelectionDAG &DAG) const {
755  SDValue Chain = Op.getOperand(0);
756  SDValue Size = Op.getOperand(1);
757  DebugLoc dl = Op.getDebugLoc();
758
759  unsigned SPReg = getStackPointerRegisterToSaveRestore();
760
761  // Get a reference to the stack pointer.
762  SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
763
764  // Subtract the dynamic size from the actual stack size to
765  // obtain the new stack size.
766  SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
767
768  //
769  // For Hexagon, the outgoing memory arguments area should be on top of the
770  // alloca area on the stack i.e., the outgoing memory arguments should be
771  // at a lower address than the alloca area. Move the alloca area down the
772  // stack by adding back the space reserved for outgoing arguments to SP
773  // here.
774  //
775  // We do not know what the size of the outgoing args is at this point.
776  // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
777  // stack pointer. We patch this instruction with the correct, known
778  // offset in emitPrologue().
779  //
780  // Use a placeholder immediate (zero) for now. This will be patched up
781  // by emitPrologue().
782  SDValue ArgAdjust = DAG.getNode(HexagonISD::ADJDYNALLOC, dl,
783                                  MVT::i32,
784                                  Sub,
785                                  DAG.getConstant(0, MVT::i32));
786
787  // The Sub result contains the new stack start address, so it
788  // must be placed in the stack pointer register.
789  SDValue CopyChain = DAG.getCopyToReg(Chain, dl,
790                                       TM.getRegisterInfo()->getStackRegister(),
791                                       Sub);
792
793  SDValue Ops[2] = { ArgAdjust, CopyChain };
794  return DAG.getMergeValues(Ops, 2, dl);
795}
796
797SDValue
798HexagonTargetLowering::LowerFormalArguments(SDValue Chain,
799                                            CallingConv::ID CallConv,
800                                            bool isVarArg,
801                                            const
802                                            SmallVectorImpl<ISD::InputArg> &Ins,
803                                            DebugLoc dl, SelectionDAG &DAG,
804                                            SmallVectorImpl<SDValue> &InVals)
805const {
806
807  MachineFunction &MF = DAG.getMachineFunction();
808  MachineFrameInfo *MFI = MF.getFrameInfo();
809  MachineRegisterInfo &RegInfo = MF.getRegInfo();
810  HexagonMachineFunctionInfo *FuncInfo =
811    MF.getInfo<HexagonMachineFunctionInfo>();
812
813
814  // Assign locations to all of the incoming arguments.
815  SmallVector<CCValAssign, 16> ArgLocs;
816  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
817		 getTargetMachine(), ArgLocs, *DAG.getContext());
818
819  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
820
821  // For LLVM, in the case when returning a struct by value (>8byte),
822  // the first argument is a pointer that points to the location on caller's
823  // stack where the return value will be stored. For Hexagon, the location on
824  // caller's stack is passed only when the struct size is smaller than (and
825  // equal to) 8 bytes. If not, no address will be passed into callee and
826  // callee return the result direclty through R0/R1.
827
828  SmallVector<SDValue, 4> MemOps;
829
830  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
831    CCValAssign &VA = ArgLocs[i];
832    ISD::ArgFlagsTy Flags = Ins[i].Flags;
833    unsigned ObjSize;
834    unsigned StackLocation;
835    int FI;
836
837    if (   (VA.isRegLoc() && !Flags.isByVal())
838        || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) {
839      // Arguments passed in registers
840      // 1. int, long long, ptr args that get allocated in register.
841      // 2. Large struct that gets an register to put its address in.
842      EVT RegVT = VA.getLocVT();
843      if (RegVT == MVT::i8 || RegVT == MVT::i16 || RegVT == MVT::i32) {
844        unsigned VReg =
845          RegInfo.createVirtualRegister(Hexagon::IntRegsRegisterClass);
846        RegInfo.addLiveIn(VA.getLocReg(), VReg);
847        InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
848      } else if (RegVT == MVT::i64) {
849        unsigned VReg =
850          RegInfo.createVirtualRegister(Hexagon::DoubleRegsRegisterClass);
851        RegInfo.addLiveIn(VA.getLocReg(), VReg);
852        InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
853      } else {
854        assert (0);
855      }
856    } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) {
857      assert (0 && "ByValSize must be bigger than 8 bytes");
858    } else {
859      // Sanity check.
860      assert(VA.isMemLoc());
861
862      if (Flags.isByVal()) {
863        // If it's a byval parameter, then we need to compute the
864        // "real" size, not the size of the pointer.
865        ObjSize = Flags.getByValSize();
866      } else {
867        ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3;
868      }
869
870      StackLocation = HEXAGON_LRFP_SIZE + VA.getLocMemOffset();
871      // Create the frame index object for this incoming parameter...
872      FI = MFI->CreateFixedObject(ObjSize, StackLocation, true);
873
874      // Create the SelectionDAG nodes cordl, responding to a load
875      // from this parameter.
876      SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
877
878      if (Flags.isByVal()) {
879        // If it's a pass-by-value aggregate, then do not dereference the stack
880        // location. Instead, we should generate a reference to the stack
881        // location.
882        InVals.push_back(FIN);
883      } else {
884        InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
885                                     MachinePointerInfo(), false, false,
886                                     false, 0));
887      }
888    }
889  }
890
891  if (!MemOps.empty())
892    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0],
893                        MemOps.size());
894
895  if (isVarArg) {
896    // This will point to the next argument passed via stack.
897    int FrameIndex = MFI->CreateFixedObject(Hexagon_PointerSize,
898                                            HEXAGON_LRFP_SIZE +
899                                            CCInfo.getNextStackOffset(),
900                                            true);
901    FuncInfo->setVarArgsFrameIndex(FrameIndex);
902  }
903
904  return Chain;
905}
906
907SDValue
908HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
909  // VASTART stores the address of the VarArgsFrameIndex slot into the
910  // memory location argument.
911  MachineFunction &MF = DAG.getMachineFunction();
912  HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>();
913  SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
914  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
915  return DAG.getStore(Op.getOperand(0), Op.getDebugLoc(), Addr,
916                      Op.getOperand(1), MachinePointerInfo(SV), false,
917                      false, 0);
918}
919
920SDValue
921HexagonTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
922  SDNode* OpNode = Op.getNode();
923
924  SDValue Cond = DAG.getNode(ISD::SETCC, Op.getDebugLoc(), MVT::i1,
925                             Op.getOperand(2), Op.getOperand(3),
926                             Op.getOperand(4));
927  return DAG.getNode(ISD::SELECT, Op.getDebugLoc(), OpNode->getValueType(0),
928                     Cond, Op.getOperand(0),
929                     Op.getOperand(1));
930}
931
932SDValue
933HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
934  const TargetRegisterInfo *TRI = TM.getRegisterInfo();
935  MachineFunction &MF = DAG.getMachineFunction();
936  MachineFrameInfo *MFI = MF.getFrameInfo();
937  MFI->setReturnAddressIsTaken(true);
938
939  EVT VT = Op.getValueType();
940  DebugLoc dl = Op.getDebugLoc();
941  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
942  if (Depth) {
943    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
944    SDValue Offset = DAG.getConstant(4, MVT::i32);
945    return DAG.getLoad(VT, dl, DAG.getEntryNode(),
946                       DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
947                       MachinePointerInfo(), false, false, false, 0);
948  }
949
950  // Return LR, which contains the return address. Mark it an implicit live-in.
951  unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
952  return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
953}
954
955SDValue
956HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
957  const HexagonRegisterInfo  *TRI = TM.getRegisterInfo();
958  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
959  MFI->setFrameAddressIsTaken(true);
960
961  EVT VT = Op.getValueType();
962  DebugLoc dl = Op.getDebugLoc();
963  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
964  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
965                                         TRI->getFrameRegister(), VT);
966  while (Depth--)
967    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
968                            MachinePointerInfo(),
969                            false, false, false, 0);
970  return FrameAddr;
971}
972
973
974SDValue HexagonTargetLowering::LowerMEMBARRIER(SDValue Op,
975                                               SelectionDAG& DAG) const {
976  DebugLoc dl = Op.getDebugLoc();
977  return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other,  Op.getOperand(0));
978}
979
980
981SDValue HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op,
982                                                 SelectionDAG& DAG) const {
983  DebugLoc dl = Op.getDebugLoc();
984  return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
985}
986
987
988SDValue HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op,
989                                                  SelectionDAG &DAG) const {
990  SDValue Result;
991  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
992  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
993  DebugLoc dl = Op.getDebugLoc();
994  Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
995
996  HexagonTargetObjectFile &TLOF =
997    (HexagonTargetObjectFile&)getObjFileLowering();
998  if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
999    return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), Result);
1000  }
1001
1002  return DAG.getNode(HexagonISD::CONST32, dl, getPointerTy(), Result);
1003}
1004
1005//===----------------------------------------------------------------------===//
1006// TargetLowering Implementation
1007//===----------------------------------------------------------------------===//
1008
1009HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine
1010                                             &targetmachine)
1011  : TargetLowering(targetmachine, new HexagonTargetObjectFile()),
1012    TM(targetmachine) {
1013
1014    // Set up the register classes.
1015    addRegisterClass(MVT::i32, Hexagon::IntRegsRegisterClass);
1016    addRegisterClass(MVT::i64, Hexagon::DoubleRegsRegisterClass);
1017
1018    addRegisterClass(MVT::i1, Hexagon::PredRegsRegisterClass);
1019
1020    computeRegisterProperties();
1021
1022    // Align loop entry
1023    setPrefLoopAlignment(4);
1024
1025    // Limits for inline expansion of memcpy/memmove
1026    maxStoresPerMemcpy = 6;
1027    maxStoresPerMemmove = 6;
1028
1029    //
1030    // Library calls for unsupported operations
1031    //
1032    setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
1033
1034    setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
1035    setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1036    setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1037    setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
1038    setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
1039    setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
1040    setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
1041
1042    setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
1043    setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
1044    setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1045
1046    setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
1047    setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
1048    setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1049
1050    setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
1051    setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
1052    setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1053    setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
1054    setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1055
1056    setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
1057
1058    setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1059    setOperationAction(ISD::SDIV,  MVT::i32, Expand);
1060    setLibcallName(RTLIB::SREM_I32, "__hexagon_umodsi3");
1061    setOperationAction(ISD::SREM,  MVT::i32, Expand);
1062
1063    setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1064    setOperationAction(ISD::SDIV,  MVT::i64, Expand);
1065    setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1066    setOperationAction(ISD::SREM,  MVT::i64, Expand);
1067
1068    setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1069    setOperationAction(ISD::UDIV,  MVT::i32, Expand);
1070
1071    setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1072    setOperationAction(ISD::UDIV,  MVT::i64, Expand);
1073
1074    setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1075    setOperationAction(ISD::UREM,  MVT::i32, Expand);
1076
1077    setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1078    setOperationAction(ISD::UREM,  MVT::i64, Expand);
1079
1080    setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1081    setOperationAction(ISD::FDIV,  MVT::f32, Expand);
1082
1083    setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1084    setOperationAction(ISD::FDIV,  MVT::f64, Expand);
1085
1086    setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
1087    setOperationAction(ISD::FP_EXTEND,  MVT::f32, Expand);
1088
1089    setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
1090    setOperationAction(ISD::SINT_TO_FP,  MVT::i32, Expand);
1091
1092    setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1093    setOperationAction(ISD::FADD,  MVT::f64, Expand);
1094
1095    setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
1096    setOperationAction(ISD::FADD,  MVT::f32, Expand);
1097
1098    setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
1099    setOperationAction(ISD::FADD,  MVT::f32, Expand);
1100
1101    setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
1102    setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
1103
1104    setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
1105    setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
1106
1107    setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
1108    setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
1109
1110    setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
1111    setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
1112
1113    setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
1114    setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
1115
1116    setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
1117    setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
1118
1119    setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
1120    setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
1121
1122    setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
1123    setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
1124
1125    setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
1126    setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
1127
1128    setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
1129    setCondCodeAction(ISD::SETOLT, MVT::f64, Expand);
1130
1131    setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
1132    setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
1133
1134    setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1135    setOperationAction(ISD::SREM, MVT::i32, Expand);
1136
1137    setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1138    setOperationAction(ISD::FMUL, MVT::f64, Expand);
1139
1140    setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
1141    setOperationAction(ISD::MUL, MVT::f32, Expand);
1142
1143    setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
1144    setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
1145
1146    setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
1147
1148
1149    setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1150    setOperationAction(ISD::SUB, MVT::f64, Expand);
1151
1152    setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
1153    setOperationAction(ISD::SUB, MVT::f32, Expand);
1154
1155    setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
1156    setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
1157
1158    setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
1159    setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
1160
1161    setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
1162    setCondCodeAction(ISD::SETO, MVT::f64, Expand);
1163
1164    setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
1165    setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
1166
1167    setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
1168    setCondCodeAction(ISD::SETO, MVT::f32, Expand);
1169
1170    setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
1171    setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
1172
1173    setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
1174    setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
1175    setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1176    setIndexedLoadAction(ISD::POST_INC, MVT::i64, Legal);
1177
1178    setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal);
1179    setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal);
1180    setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1181    setIndexedStoreAction(ISD::POST_INC, MVT::i64, Legal);
1182
1183    setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1184
1185    // Turn FP extload into load/fextend.
1186    setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
1187    // Hexagon has a i1 sign extending load.
1188    setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
1189    // Turn FP truncstore into trunc + store.
1190    setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1191
1192    // Custom legalize GlobalAddress nodes into CONST32.
1193    setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1194    setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1195    // Truncate action?
1196    setOperationAction(ISD::TRUNCATE, MVT::i64, Expand);
1197
1198    // Hexagon doesn't have sext_inreg, replace them with shl/sra.
1199    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1200
1201    // Hexagon has no REM or DIVREM operations.
1202    setOperationAction(ISD::UREM, MVT::i32, Expand);
1203    setOperationAction(ISD::SREM, MVT::i32, Expand);
1204    setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1205    setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1206    setOperationAction(ISD::SREM, MVT::i64, Expand);
1207    setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1208    setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1209
1210    setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1211
1212    // Expand fp<->uint.
1213    setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
1214    setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
1215
1216    // Hexagon has no select or setcc: expand to SELECT_CC.
1217    setOperationAction(ISD::SELECT, MVT::f32, Expand);
1218    setOperationAction(ISD::SELECT, MVT::f64, Expand);
1219
1220    // Lower SELECT_CC to SETCC and SELECT.
1221    setOperationAction(ISD::SELECT_CC, MVT::i32,   Custom);
1222    setOperationAction(ISD::SELECT_CC, MVT::i64,   Custom);
1223    // This is a workaround documented in DAGCombiner.cpp:2892 We don't
1224    // support SELECT_CC on every type.
1225    setOperationAction(ISD::SELECT_CC, MVT::Other,   Expand);
1226
1227    setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1228    setOperationAction(ISD::BRIND, MVT::Other, Expand);
1229    if (EmitJumpTables) {
1230      setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1231    } else {
1232      setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1233    }
1234
1235    setOperationAction(ISD::BR_CC, MVT::i32, Expand);
1236
1237    setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
1238    setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1239
1240    setOperationAction(ISD::FSIN , MVT::f64, Expand);
1241    setOperationAction(ISD::FCOS , MVT::f64, Expand);
1242    setOperationAction(ISD::FREM , MVT::f64, Expand);
1243    setOperationAction(ISD::FSIN , MVT::f32, Expand);
1244    setOperationAction(ISD::FCOS , MVT::f32, Expand);
1245    setOperationAction(ISD::FREM , MVT::f32, Expand);
1246    setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1247    setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1248    setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1249    setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1250    setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1251    setOperationAction(ISD::ROTL , MVT::i32, Expand);
1252    setOperationAction(ISD::ROTR , MVT::i32, Expand);
1253    setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1254    setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1255    setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1256    setOperationAction(ISD::FPOW , MVT::f64, Expand);
1257    setOperationAction(ISD::FPOW , MVT::f32, Expand);
1258
1259    setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1260    setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1261    setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1262
1263    setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1264    setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1265
1266    setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1267    setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
1268
1269    setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
1270    setOperationAction(ISD::EHSELECTION,   MVT::i64, Expand);
1271    setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
1272    setOperationAction(ISD::EHSELECTION,   MVT::i32, Expand);
1273
1274    setOperationAction(ISD::EH_RETURN,     MVT::Other, Expand);
1275
1276    if (TM.getSubtargetImpl()->isSubtargetV2()) {
1277      setExceptionPointerRegister(Hexagon::R20);
1278      setExceptionSelectorRegister(Hexagon::R21);
1279    } else {
1280      setExceptionPointerRegister(Hexagon::R0);
1281      setExceptionSelectorRegister(Hexagon::R1);
1282    }
1283
1284    // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1285    setOperationAction(ISD::VASTART           , MVT::Other, Custom);
1286
1287    // Use the default implementation.
1288    setOperationAction(ISD::VAARG             , MVT::Other, Expand);
1289    setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
1290    setOperationAction(ISD::VAEND             , MVT::Other, Expand);
1291    setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand);
1292    setOperationAction(ISD::STACKRESTORE      , MVT::Other, Expand);
1293
1294
1295    setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
1296    setOperationAction(ISD::INLINEASM         , MVT::Other, Custom);
1297
1298    setMinFunctionAlignment(2);
1299
1300    // Needed for DYNAMIC_STACKALLOC expansion.
1301    unsigned StackRegister = TM.getRegisterInfo()->getStackRegister();
1302    setStackPointerRegisterToSaveRestore(StackRegister);
1303}
1304
1305
1306const char*
1307HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1308  switch (Opcode) {
1309    default: return 0;
1310    case HexagonISD::CONST32:    return "HexagonISD::CONST32";
1311    case HexagonISD::ADJDYNALLOC: return "HexagonISD::ADJDYNALLOC";
1312    case HexagonISD::CMPICC:     return "HexagonISD::CMPICC";
1313    case HexagonISD::CMPFCC:     return "HexagonISD::CMPFCC";
1314    case HexagonISD::BRICC:      return "HexagonISD::BRICC";
1315    case HexagonISD::BRFCC:      return "HexagonISD::BRFCC";
1316    case HexagonISD::SELECT_ICC: return "HexagonISD::SELECT_ICC";
1317    case HexagonISD::SELECT_FCC: return "HexagonISD::SELECT_FCC";
1318    case HexagonISD::Hi:         return "HexagonISD::Hi";
1319    case HexagonISD::Lo:         return "HexagonISD::Lo";
1320    case HexagonISD::FTOI:       return "HexagonISD::FTOI";
1321    case HexagonISD::ITOF:       return "HexagonISD::ITOF";
1322    case HexagonISD::CALL:       return "HexagonISD::CALL";
1323    case HexagonISD::RET_FLAG:   return "HexagonISD::RET_FLAG";
1324    case HexagonISD::BR_JT:      return "HexagonISD::BR_JT";
1325    case HexagonISD::TC_RETURN:  return "HexagonISD::TC_RETURN";
1326  }
1327}
1328
1329bool
1330HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
1331  EVT MTy1 = EVT::getEVT(Ty1);
1332  EVT MTy2 = EVT::getEVT(Ty2);
1333  if (!MTy1.isSimple() || !MTy2.isSimple()) {
1334    return false;
1335  }
1336  return ((MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32));
1337}
1338
1339bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1340  if (!VT1.isSimple() || !VT2.isSimple()) {
1341    return false;
1342  }
1343  return ((VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32));
1344}
1345
1346SDValue
1347HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1348  switch (Op.getOpcode()) {
1349    default: assert(0 && "Should not custom lower this!");
1350      // Frame & Return address.  Currently unimplemented.
1351    case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
1352    case ISD::FRAMEADDR:  return LowerFRAMEADDR(Op, DAG);
1353    case ISD::GlobalTLSAddress:
1354                          assert(0 && "TLS not implemented for Hexagon.");
1355    case ISD::MEMBARRIER:         return LowerMEMBARRIER(Op, DAG);
1356    case ISD::ATOMIC_FENCE:       return LowerATOMIC_FENCE(Op, DAG);
1357    case ISD::GlobalAddress:      return LowerGLOBALADDRESS(Op, DAG);
1358    case ISD::VASTART:            return LowerVASTART(Op, DAG);
1359    case ISD::BR_JT:              return LowerBR_JT(Op, DAG);
1360
1361    case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
1362    case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
1363    case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1364  case ISD::INLINEASM:          return LowerINLINEASM(Op, DAG);
1365
1366  }
1367}
1368
1369
1370
1371//===----------------------------------------------------------------------===//
1372//                           Hexagon Scheduler Hooks
1373//===----------------------------------------------------------------------===//
1374MachineBasicBlock *
1375HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1376                                                   MachineBasicBlock *BB)
1377const {
1378  switch (MI->getOpcode()) {
1379    case Hexagon::ADJDYNALLOC: {
1380      MachineFunction *MF = BB->getParent();
1381      HexagonMachineFunctionInfo *FuncInfo =
1382        MF->getInfo<HexagonMachineFunctionInfo>();
1383      FuncInfo->addAllocaAdjustInst(MI);
1384      return BB;
1385    }
1386    default:
1387      assert(false && "Unexpected instr type to insert");
1388  } // switch
1389  return NULL;
1390}
1391
1392//===----------------------------------------------------------------------===//
1393// Inline Assembly Support
1394//===----------------------------------------------------------------------===//
1395
1396std::pair<unsigned, const TargetRegisterClass*>
1397HexagonTargetLowering::getRegForInlineAsmConstraint(const
1398                                                    std::string &Constraint,
1399                                                    EVT VT) const {
1400  if (Constraint.size() == 1) {
1401    switch (Constraint[0]) {
1402    case 'r':   // R0-R31
1403       switch (VT.getSimpleVT().SimpleTy) {
1404       default:
1405         assert(0 && "getRegForInlineAsmConstraint Unhandled data type");
1406       case MVT::i32:
1407       case MVT::i16:
1408       case MVT::i8:
1409         return std::make_pair(0U, Hexagon::IntRegsRegisterClass);
1410       case MVT::i64:
1411         return std::make_pair(0U, Hexagon::DoubleRegsRegisterClass);
1412      }
1413    default:
1414      assert(0 && "Unknown asm register class");
1415    }
1416  }
1417
1418  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1419}
1420
1421/// isLegalAddressingMode - Return true if the addressing mode represented by
1422/// AM is legal for this target, for a load/store of the specified type.
1423bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1424                                                  Type *Ty) const {
1425  // Allows a signed-extended 11-bit immediate field.
1426  if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) {
1427    return false;
1428  }
1429
1430  // No global is ever allowed as a base.
1431  if (AM.BaseGV) {
1432    return false;
1433  }
1434
1435  int Scale = AM.Scale;
1436  if (Scale < 0) Scale = -Scale;
1437  switch (Scale) {
1438  case 0:  // No scale reg, "r+i", "r", or just "i".
1439    break;
1440  default: // No scaled addressing mode.
1441    return false;
1442  }
1443  return true;
1444}
1445
1446/// isLegalICmpImmediate - Return true if the specified immediate is legal
1447/// icmp immediate, that is the target has icmp instructions which can compare
1448/// a register against the immediate without having to materialize the
1449/// immediate into a register.
1450bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
1451  return Imm >= -512 && Imm <= 511;
1452}
1453
1454/// IsEligibleForTailCallOptimization - Check whether the call is eligible
1455/// for tail call optimization. Targets which want to do tail call
1456/// optimization should implement this function.
1457bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
1458                                 SDValue Callee,
1459                                 CallingConv::ID CalleeCC,
1460                                 bool isVarArg,
1461                                 bool isCalleeStructRet,
1462                                 bool isCallerStructRet,
1463                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
1464                                 const SmallVectorImpl<SDValue> &OutVals,
1465                                 const SmallVectorImpl<ISD::InputArg> &Ins,
1466                                 SelectionDAG& DAG) const {
1467  const Function *CallerF = DAG.getMachineFunction().getFunction();
1468  CallingConv::ID CallerCC = CallerF->getCallingConv();
1469  bool CCMatch = CallerCC == CalleeCC;
1470
1471  // ***************************************************************************
1472  //  Look for obvious safe cases to perform tail call optimization that do not
1473  //  require ABI changes.
1474  // ***************************************************************************
1475
1476  // If this is a tail call via a function pointer, then don't do it!
1477  if (!(dyn_cast<GlobalAddressSDNode>(Callee))
1478      && !(dyn_cast<ExternalSymbolSDNode>(Callee))) {
1479    return false;
1480  }
1481
1482  // Do not optimize if the calling conventions do not match.
1483  if (!CCMatch)
1484    return false;
1485
1486  // Do not tail call optimize vararg calls.
1487  if (isVarArg)
1488    return false;
1489
1490  // Also avoid tail call optimization if either caller or callee uses struct
1491  // return semantics.
1492  if (isCalleeStructRet || isCallerStructRet)
1493    return false;
1494
1495  // In addition to the cases above, we also disable Tail Call Optimization if
1496  // the calling convention code that at least one outgoing argument needs to
1497  // go on the stack. We cannot check that here because at this point that
1498  // information is not available.
1499  return true;
1500}
1501