1//===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements NewValueJump pass in Hexagon. 11// Ideally, we should merge this as a Peephole pass prior to register 12// allocation, but because we have a spill in between the feeder and new value 13// jump instructions, we are forced to write after register allocation. 14// Having said that, we should re-attempt to pull this earlier at some point 15// in future. 16 17// The basic approach looks for sequence of predicated jump, compare instruciton 18// that genereates the predicate and, the feeder to the predicate. Once it finds 19// all, it collapses compare and jump instruction into a new valu jump 20// intstructions. 21// 22// 23//===----------------------------------------------------------------------===// 24#include "llvm/PassSupport.h" 25#include "Hexagon.h" 26#include "HexagonInstrInfo.h" 27#include "HexagonMachineFunctionInfo.h" 28#include "HexagonRegisterInfo.h" 29#include "HexagonSubtarget.h" 30#include "HexagonTargetMachine.h" 31#include "llvm/ADT/DenseMap.h" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/CodeGen/LiveVariables.h" 34#include "llvm/CodeGen/MachineFunctionAnalysis.h" 35#include "llvm/CodeGen/MachineFunctionPass.h" 36#include "llvm/CodeGen/MachineInstrBuilder.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/CodeGen/Passes.h" 39#include "llvm/CodeGen/ScheduleDAGInstrs.h" 40#include "llvm/Support/CommandLine.h" 41#include "llvm/Support/Compiler.h" 42#include "llvm/Support/Debug.h" 43#include "llvm/Target/TargetInstrInfo.h" 44#include "llvm/Target/TargetMachine.h" 45#include "llvm/Target/TargetRegisterInfo.h" 46#include <map> 47using namespace llvm; 48 49#define DEBUG_TYPE "hexagon-nvj" 50 51STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created"); 52 53static cl::opt<int> 54DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc( 55 "Maximum number of predicated jumps to be converted to New Value Jump")); 56 57static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden, 58 cl::ZeroOrMore, cl::init(false), 59 cl::desc("Disable New Value Jumps")); 60 61namespace llvm { 62 void initializeHexagonNewValueJumpPass(PassRegistry&); 63} 64 65 66namespace { 67 struct HexagonNewValueJump : public MachineFunctionPass { 68 const HexagonInstrInfo *QII; 69 const HexagonRegisterInfo *QRI; 70 71 public: 72 static char ID; 73 74 HexagonNewValueJump() : MachineFunctionPass(ID) { 75 initializeHexagonNewValueJumpPass(*PassRegistry::getPassRegistry()); 76 } 77 78 void getAnalysisUsage(AnalysisUsage &AU) const override { 79 AU.addRequired<MachineBranchProbabilityInfo>(); 80 MachineFunctionPass::getAnalysisUsage(AU); 81 } 82 83 const char *getPassName() const override { 84 return "Hexagon NewValueJump"; 85 } 86 87 bool runOnMachineFunction(MachineFunction &Fn) override; 88 89 private: 90 /// \brief A handle to the branch probability pass. 91 const MachineBranchProbabilityInfo *MBPI; 92 93 }; 94 95} // end of anonymous namespace 96 97char HexagonNewValueJump::ID = 0; 98 99INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj", 100 "Hexagon NewValueJump", false, false) 101INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo) 102INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj", 103 "Hexagon NewValueJump", false, false) 104 105 106// We have identified this II could be feeder to NVJ, 107// verify that it can be. 108static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, 109 const TargetRegisterInfo *TRI, 110 MachineBasicBlock::iterator II, 111 MachineBasicBlock::iterator end, 112 MachineBasicBlock::iterator skip, 113 MachineFunction &MF) { 114 115 // Predicated instruction can not be feeder to NVJ. 116 if (QII->isPredicated(II)) 117 return false; 118 119 // Bail out if feederReg is a paired register (double regs in 120 // our case). One would think that we can check to see if a given 121 // register cmpReg1 or cmpReg2 is a sub register of feederReg 122 // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic 123 // before the callsite of this function 124 // But we can not as it comes in the following fashion. 125 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill> 126 // %R0<def> = KILL %R0, %D0<imp-use,kill> 127 // %P0<def> = CMPEQri %R0<kill>, 0 128 // Hence, we need to check if it's a KILL instruction. 129 if (II->getOpcode() == TargetOpcode::KILL) 130 return false; 131 132 133 // Make sure there there is no 'def' or 'use' of any of the uses of 134 // feeder insn between it's definition, this MI and jump, jmpInst 135 // skipping compare, cmpInst. 136 // Here's the example. 137 // r21=memub(r22+r24<<#0) 138 // p0 = cmp.eq(r21, #0) 139 // r4=memub(r3+r21<<#0) 140 // if (p0.new) jump:t .LBB29_45 141 // Without this check, it will be converted into 142 // r4=memub(r3+r21<<#0) 143 // r21=memub(r22+r24<<#0) 144 // p0 = cmp.eq(r21, #0) 145 // if (p0.new) jump:t .LBB29_45 146 // and result WAR hazards if converted to New Value Jump. 147 148 for (unsigned i = 0; i < II->getNumOperands(); ++i) { 149 if (II->getOperand(i).isReg() && 150 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { 151 MachineBasicBlock::iterator localII = II; 152 ++localII; 153 unsigned Reg = II->getOperand(i).getReg(); 154 for (MachineBasicBlock::iterator localBegin = localII; 155 localBegin != end; ++localBegin) { 156 if (localBegin == skip ) continue; 157 // Check for Subregisters too. 158 if (localBegin->modifiesRegister(Reg, TRI) || 159 localBegin->readsRegister(Reg, TRI)) 160 return false; 161 } 162 } 163 } 164 return true; 165} 166 167// These are the common checks that need to performed 168// to determine if 169// 1. compare instruction can be moved before jump. 170// 2. feeder to the compare instruction can be moved before jump. 171static bool commonChecksToProhibitNewValueJump(bool afterRA, 172 MachineBasicBlock::iterator MII) { 173 174 // If store in path, bail out. 175 if (MII->getDesc().mayStore()) 176 return false; 177 178 // if call in path, bail out. 179 if (MII->getOpcode() == Hexagon::CALLv3) 180 return false; 181 182 // if NVJ is running prior to RA, do the following checks. 183 if (!afterRA) { 184 // The following Target Opcode instructions are spurious 185 // to new value jump. If they are in the path, bail out. 186 // KILL sets kill flag on the opcode. It also sets up a 187 // single register, out of pair. 188 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill> 189 // %R0<def> = KILL %R0, %D0<imp-use,kill> 190 // %P0<def> = CMPEQri %R0<kill>, 0 191 // PHI can be anything after RA. 192 // COPY can remateriaze things in between feeder, compare and nvj. 193 if (MII->getOpcode() == TargetOpcode::KILL || 194 MII->getOpcode() == TargetOpcode::PHI || 195 MII->getOpcode() == TargetOpcode::COPY) 196 return false; 197 198 // The following pseudo Hexagon instructions sets "use" and "def" 199 // of registers by individual passes in the backend. At this time, 200 // we don't know the scope of usage and definitions of these 201 // instructions. 202 if (MII->getOpcode() == Hexagon::TFR_condset_rr || 203 MII->getOpcode() == Hexagon::TFR_condset_ii || 204 MII->getOpcode() == Hexagon::TFR_condset_ri || 205 MII->getOpcode() == Hexagon::TFR_condset_ir || 206 MII->getOpcode() == Hexagon::LDriw_pred || 207 MII->getOpcode() == Hexagon::STriw_pred) 208 return false; 209 } 210 211 return true; 212} 213 214static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, 215 const TargetRegisterInfo *TRI, 216 MachineBasicBlock::iterator II, 217 unsigned pReg, 218 bool secondReg, 219 bool optLocation, 220 MachineBasicBlock::iterator end, 221 MachineFunction &MF) { 222 223 MachineInstr *MI = II; 224 225 // If the second operand of the compare is an imm, make sure it's in the 226 // range specified by the arch. 227 if (!secondReg) { 228 int64_t v = MI->getOperand(2).getImm(); 229 230 if (!(isUInt<5>(v) || 231 ((MI->getOpcode() == Hexagon::CMPEQri || 232 MI->getOpcode() == Hexagon::CMPGTri) && 233 (v == -1)))) 234 return false; 235 } 236 237 unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning. 238 cmpReg1 = MI->getOperand(1).getReg(); 239 240 if (secondReg) { 241 cmpOp2 = MI->getOperand(2).getReg(); 242 243 // Make sure that that second register is not from COPY 244 // At machine code level, we don't need this, but if we decide 245 // to move new value jump prior to RA, we would be needing this. 246 MachineRegisterInfo &MRI = MF.getRegInfo(); 247 if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) { 248 MachineInstr *def = MRI.getVRegDef(cmpOp2); 249 if (def->getOpcode() == TargetOpcode::COPY) 250 return false; 251 } 252 } 253 254 // Walk the instructions after the compare (predicate def) to the jump, 255 // and satisfy the following conditions. 256 ++II ; 257 for (MachineBasicBlock::iterator localII = II; localII != end; 258 ++localII) { 259 260 // Check 1. 261 // If "common" checks fail, bail out. 262 if (!commonChecksToProhibitNewValueJump(optLocation, localII)) 263 return false; 264 265 // Check 2. 266 // If there is a def or use of predicate (result of compare), bail out. 267 if (localII->modifiesRegister(pReg, TRI) || 268 localII->readsRegister(pReg, TRI)) 269 return false; 270 271 // Check 3. 272 // If there is a def of any of the use of the compare (operands of compare), 273 // bail out. 274 // Eg. 275 // p0 = cmp.eq(r2, r0) 276 // r2 = r4 277 // if (p0.new) jump:t .LBB28_3 278 if (localII->modifiesRegister(cmpReg1, TRI) || 279 (secondReg && localII->modifiesRegister(cmpOp2, TRI))) 280 return false; 281 } 282 return true; 283} 284 285// Given a compare operator, return a matching New Value Jump 286// compare operator. Make sure that MI here is included in 287// HexagonInstrInfo.cpp::isNewValueJumpCandidate 288static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg, 289 bool secondRegNewified, 290 MachineBasicBlock *jmpTarget, 291 const MachineBranchProbabilityInfo 292 *MBPI) { 293 bool taken = false; 294 MachineBasicBlock *Src = MI->getParent(); 295 const BranchProbability Prediction = 296 MBPI->getEdgeProbability(Src, jmpTarget); 297 298 if (Prediction >= BranchProbability(1,2)) 299 taken = true; 300 301 switch (MI->getOpcode()) { 302 case Hexagon::CMPEQrr: 303 return taken ? Hexagon::CMPEQrr_t_Jumpnv_t_V4 304 : Hexagon::CMPEQrr_t_Jumpnv_nt_V4; 305 306 case Hexagon::CMPEQri: { 307 if (reg >= 0) 308 return taken ? Hexagon::CMPEQri_t_Jumpnv_t_V4 309 : Hexagon::CMPEQri_t_Jumpnv_nt_V4; 310 else 311 return taken ? Hexagon::CMPEQn1_t_Jumpnv_t_V4 312 : Hexagon::CMPEQn1_t_Jumpnv_nt_V4; 313 } 314 315 case Hexagon::CMPGTrr: { 316 if (secondRegNewified) 317 return taken ? Hexagon::CMPLTrr_t_Jumpnv_t_V4 318 : Hexagon::CMPLTrr_t_Jumpnv_nt_V4; 319 else 320 return taken ? Hexagon::CMPGTrr_t_Jumpnv_t_V4 321 : Hexagon::CMPGTrr_t_Jumpnv_nt_V4; 322 } 323 324 case Hexagon::CMPGTri: { 325 if (reg >= 0) 326 return taken ? Hexagon::CMPGTri_t_Jumpnv_t_V4 327 : Hexagon::CMPGTri_t_Jumpnv_nt_V4; 328 else 329 return taken ? Hexagon::CMPGTn1_t_Jumpnv_t_V4 330 : Hexagon::CMPGTn1_t_Jumpnv_nt_V4; 331 } 332 333 case Hexagon::CMPGTUrr: { 334 if (secondRegNewified) 335 return taken ? Hexagon::CMPLTUrr_t_Jumpnv_t_V4 336 : Hexagon::CMPLTUrr_t_Jumpnv_nt_V4; 337 else 338 return taken ? Hexagon::CMPGTUrr_t_Jumpnv_t_V4 339 : Hexagon::CMPGTUrr_t_Jumpnv_nt_V4; 340 } 341 342 case Hexagon::CMPGTUri: 343 return taken ? Hexagon::CMPGTUri_t_Jumpnv_t_V4 344 : Hexagon::CMPGTUri_t_Jumpnv_nt_V4; 345 346 default: 347 llvm_unreachable("Could not find matching New Value Jump instruction."); 348 } 349 // return *some value* to avoid compiler warning 350 return 0; 351} 352 353bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { 354 355 DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n" 356 << "********** Function: " 357 << MF.getName() << "\n"); 358 359#if 0 360 // for now disable this, if we move NewValueJump before register 361 // allocation we need this information. 362 LiveVariables &LVs = getAnalysis<LiveVariables>(); 363#endif 364 365 QII = static_cast<const HexagonInstrInfo *>(MF.getTarget().getInstrInfo()); 366 QRI = 367 static_cast<const HexagonRegisterInfo *>(MF.getTarget().getRegisterInfo()); 368 MBPI = &getAnalysis<MachineBranchProbabilityInfo>(); 369 370 if (!QRI->Subtarget.hasV4TOps() || 371 DisableNewValueJumps) { 372 return false; 373 } 374 375 int nvjCount = DbgNVJCount; 376 int nvjGenerated = 0; 377 378 // Loop through all the bb's of the function 379 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end(); 380 MBBb != MBBe; ++MBBb) { 381 MachineBasicBlock* MBB = MBBb; 382 383 DEBUG(dbgs() << "** dumping bb ** " 384 << MBB->getNumber() << "\n"); 385 DEBUG(MBB->dump()); 386 DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n"); 387 bool foundJump = false; 388 bool foundCompare = false; 389 bool invertPredicate = false; 390 unsigned predReg = 0; // predicate reg of the jump. 391 unsigned cmpReg1 = 0; 392 int cmpOp2 = 0; 393 bool MO1IsKill = false; 394 bool MO2IsKill = false; 395 MachineBasicBlock::iterator jmpPos; 396 MachineBasicBlock::iterator cmpPos; 397 MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr; 398 MachineBasicBlock *jmpTarget = nullptr; 399 bool afterRA = false; 400 bool isSecondOpReg = false; 401 bool isSecondOpNewified = false; 402 // Traverse the basic block - bottom up 403 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin(); 404 MII != E;) { 405 MachineInstr *MI = --MII; 406 if (MI->isDebugValue()) { 407 continue; 408 } 409 410 if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated)) 411 break; 412 413 DEBUG(dbgs() << "Instr: "; MI->dump(); dbgs() << "\n"); 414 415 if (!foundJump && 416 (MI->getOpcode() == Hexagon::JMP_t || 417 MI->getOpcode() == Hexagon::JMP_f || 418 MI->getOpcode() == Hexagon::JMP_tnew_t || 419 MI->getOpcode() == Hexagon::JMP_tnew_nt || 420 MI->getOpcode() == Hexagon::JMP_fnew_t || 421 MI->getOpcode() == Hexagon::JMP_fnew_nt)) { 422 // This is where you would insert your compare and 423 // instr that feeds compare 424 jmpPos = MII; 425 jmpInstr = MI; 426 predReg = MI->getOperand(0).getReg(); 427 afterRA = TargetRegisterInfo::isPhysicalRegister(predReg); 428 429 // If ifconverter had not messed up with the kill flags of the 430 // operands, the following check on the kill flag would suffice. 431 // if(!jmpInstr->getOperand(0).isKill()) break; 432 433 // This predicate register is live out out of BB 434 // this would only work if we can actually use Live 435 // variable analysis on phy regs - but LLVM does not 436 // provide LV analysis on phys regs. 437 //if(LVs.isLiveOut(predReg, *MBB)) break; 438 439 // Get all the successors of this block - which will always 440 // be 2. Check if the predicate register is live in in those 441 // successor. If yes, we can not delete the predicate - 442 // I am doing this only because LLVM does not provide LiveOut 443 // at the BB level. 444 bool predLive = false; 445 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(), 446 SIE = MBB->succ_end(); SI != SIE; ++SI) { 447 MachineBasicBlock* succMBB = *SI; 448 if (succMBB->isLiveIn(predReg)) { 449 predLive = true; 450 } 451 } 452 if (predLive) 453 break; 454 455 jmpTarget = MI->getOperand(1).getMBB(); 456 foundJump = true; 457 if (MI->getOpcode() == Hexagon::JMP_f || 458 MI->getOpcode() == Hexagon::JMP_fnew_t || 459 MI->getOpcode() == Hexagon::JMP_fnew_nt) { 460 invertPredicate = true; 461 } 462 continue; 463 } 464 465 // No new value jump if there is a barrier. A barrier has to be in its 466 // own packet. A barrier has zero operands. We conservatively bail out 467 // here if we see any instruction with zero operands. 468 if (foundJump && MI->getNumOperands() == 0) 469 break; 470 471 if (foundJump && 472 !foundCompare && 473 MI->getOperand(0).isReg() && 474 MI->getOperand(0).getReg() == predReg) { 475 476 // Not all compares can be new value compare. Arch Spec: 7.6.1.1 477 if (QII->isNewValueJumpCandidate(MI)) { 478 479 assert((MI->getDesc().isCompare()) && 480 "Only compare instruction can be collapsed into New Value Jump"); 481 isSecondOpReg = MI->getOperand(2).isReg(); 482 483 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg, 484 afterRA, jmpPos, MF)) 485 break; 486 487 cmpInstr = MI; 488 cmpPos = MII; 489 foundCompare = true; 490 491 // We need cmpReg1 and cmpOp2(imm or reg) while building 492 // new value jump instruction. 493 cmpReg1 = MI->getOperand(1).getReg(); 494 if (MI->getOperand(1).isKill()) 495 MO1IsKill = true; 496 497 if (isSecondOpReg) { 498 cmpOp2 = MI->getOperand(2).getReg(); 499 if (MI->getOperand(2).isKill()) 500 MO2IsKill = true; 501 } else 502 cmpOp2 = MI->getOperand(2).getImm(); 503 continue; 504 } 505 } 506 507 if (foundCompare && foundJump) { 508 509 // If "common" checks fail, bail out on this BB. 510 if (!commonChecksToProhibitNewValueJump(afterRA, MII)) 511 break; 512 513 bool foundFeeder = false; 514 MachineBasicBlock::iterator feederPos = MII; 515 if (MI->getOperand(0).isReg() && 516 MI->getOperand(0).isDef() && 517 (MI->getOperand(0).getReg() == cmpReg1 || 518 (isSecondOpReg && 519 MI->getOperand(0).getReg() == (unsigned) cmpOp2))) { 520 521 unsigned feederReg = MI->getOperand(0).getReg(); 522 523 // First try to see if we can get the feeder from the first operand 524 // of the compare. If we can not, and if secondOpReg is true 525 // (second operand of the compare is also register), try that one. 526 // TODO: Try to come up with some heuristic to figure out which 527 // feeder would benefit. 528 529 if (feederReg == cmpReg1) { 530 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) { 531 if (!isSecondOpReg) 532 break; 533 else 534 continue; 535 } else 536 foundFeeder = true; 537 } 538 539 if (!foundFeeder && 540 isSecondOpReg && 541 feederReg == (unsigned) cmpOp2) 542 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) 543 break; 544 545 if (isSecondOpReg) { 546 // In case of CMPLT, or CMPLTU, or EQ with the second register 547 // to newify, swap the operands. 548 if (cmpInstr->getOpcode() == Hexagon::CMPEQrr && 549 feederReg == (unsigned) cmpOp2) { 550 unsigned tmp = cmpReg1; 551 bool tmpIsKill = MO1IsKill; 552 cmpReg1 = cmpOp2; 553 MO1IsKill = MO2IsKill; 554 cmpOp2 = tmp; 555 MO2IsKill = tmpIsKill; 556 } 557 558 // Now we have swapped the operands, all we need to check is, 559 // if the second operand (after swap) is the feeder. 560 // And if it is, make a note. 561 if (feederReg == (unsigned)cmpOp2) 562 isSecondOpNewified = true; 563 } 564 565 // Now that we are moving feeder close the jump, 566 // make sure we are respecting the kill values of 567 // the operands of the feeder. 568 569 bool updatedIsKill = false; 570 for (unsigned i = 0; i < MI->getNumOperands(); i++) { 571 MachineOperand &MO = MI->getOperand(i); 572 if (MO.isReg() && MO.isUse()) { 573 unsigned feederReg = MO.getReg(); 574 for (MachineBasicBlock::iterator localII = feederPos, 575 end = jmpPos; localII != end; localII++) { 576 MachineInstr *localMI = localII; 577 for (unsigned j = 0; j < localMI->getNumOperands(); j++) { 578 MachineOperand &localMO = localMI->getOperand(j); 579 if (localMO.isReg() && localMO.isUse() && 580 localMO.isKill() && feederReg == localMO.getReg()) { 581 // We found that there is kill of a use register 582 // Set up a kill flag on the register 583 localMO.setIsKill(false); 584 MO.setIsKill(); 585 updatedIsKill = true; 586 break; 587 } 588 } 589 if (updatedIsKill) break; 590 } 591 } 592 if (updatedIsKill) break; 593 } 594 595 MBB->splice(jmpPos, MI->getParent(), MI); 596 MBB->splice(jmpPos, MI->getParent(), cmpInstr); 597 DebugLoc dl = MI->getDebugLoc(); 598 MachineInstr *NewMI; 599 600 assert((QII->isNewValueJumpCandidate(cmpInstr)) && 601 "This compare is not a New Value Jump candidate."); 602 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2, 603 isSecondOpNewified, 604 jmpTarget, MBPI); 605 if (invertPredicate) 606 opc = QII->getInvertedPredicatedOpcode(opc); 607 608 if (isSecondOpReg) 609 NewMI = BuildMI(*MBB, jmpPos, dl, 610 QII->get(opc)) 611 .addReg(cmpReg1, getKillRegState(MO1IsKill)) 612 .addReg(cmpOp2, getKillRegState(MO2IsKill)) 613 .addMBB(jmpTarget); 614 615 else if ((cmpInstr->getOpcode() == Hexagon::CMPEQri || 616 cmpInstr->getOpcode() == Hexagon::CMPGTri) && 617 cmpOp2 == -1 ) 618 // Corresponding new-value compare jump instructions don't have the 619 // operand for -1 immediate value. 620 NewMI = BuildMI(*MBB, jmpPos, dl, 621 QII->get(opc)) 622 .addReg(cmpReg1, getKillRegState(MO1IsKill)) 623 .addMBB(jmpTarget); 624 625 else 626 NewMI = BuildMI(*MBB, jmpPos, dl, 627 QII->get(opc)) 628 .addReg(cmpReg1, getKillRegState(MO1IsKill)) 629 .addImm(cmpOp2) 630 .addMBB(jmpTarget); 631 632 assert(NewMI && "New Value Jump Instruction Not created!"); 633 (void)NewMI; 634 if (cmpInstr->getOperand(0).isReg() && 635 cmpInstr->getOperand(0).isKill()) 636 cmpInstr->getOperand(0).setIsKill(false); 637 if (cmpInstr->getOperand(1).isReg() && 638 cmpInstr->getOperand(1).isKill()) 639 cmpInstr->getOperand(1).setIsKill(false); 640 cmpInstr->eraseFromParent(); 641 jmpInstr->eraseFromParent(); 642 ++nvjGenerated; 643 ++NumNVJGenerated; 644 break; 645 } 646 } 647 } 648 } 649 650 return true; 651 652} 653 654FunctionPass *llvm::createHexagonNewValueJump() { 655 return new HexagonNewValueJump(); 656} 657