MSP430InstrInfo.td revision 51c31d6888a6c2a7cea74e210a1e1c8551535f28 
1//===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source 
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the MSP430 instructions in TableGen format.
11//
12//===----------------------------------------------------------------------===//
13
14include "MSP430InstrFormats.td"
15
16//===----------------------------------------------------------------------===//
17// Type Constraints.
18//===----------------------------------------------------------------------===//
19class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
20class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
21
22//===----------------------------------------------------------------------===//
23// Type Profiles.
24//===----------------------------------------------------------------------===//
25
26//===----------------------------------------------------------------------===//
27// MSP430 Specific Node Definitions.
28//===----------------------------------------------------------------------===//
29def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
30                     [SDNPHasChain, SDNPOptInFlag]>;
31
32def MSP430rra     : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
33
34//===----------------------------------------------------------------------===//
35// Pseudo Instructions
36//===----------------------------------------------------------------------===//
37
38let neverHasSideEffects = 1 in
39def NOP : Pseudo<(outs), (ins), "nop", []>;
40
41//===----------------------------------------------------------------------===//
42// Real Instructions
43//===----------------------------------------------------------------------===//
44
45// FIXME: Provide proper encoding!
46let isReturn = 1, isTerminator = 1 in {
47  def RETI : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
48}
49
50//===----------------------------------------------------------------------===//
51// Move Instructions
52
53// FIXME: Provide proper encoding!
54let neverHasSideEffects = 1 in {
55def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
56                     "mov.w\t{$src, $dst|$dst, $src}",
57                     []>;
58def MOV8rr  : Pseudo<(outs GR8:$dst), (ins GR8:$src),
59                     "mov.b\t{$src, $dst|$dst, $src}",
60                     []>;
61}
62
63// FIXME: Provide proper encoding!
64let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
65def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
66                     "mov.w\t{$src, $dst|$dst, $src}",
67                     [(set GR16:$dst, imm:$src)]>;
68def MOV8ri  : Pseudo<(outs GR8:$dst), (ins i8imm:$src),
69                     "mov.b\t{$src, $dst|$dst, $src}",
70                     [(set GR8:$dst, imm:$src)]>;
71
72}
73
74//===----------------------------------------------------------------------===//
75// Arithmetic Instructions
76
77let isTwoAddress = 1 in {
78
79let Defs = [SRW] in {
80
81let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
82// FIXME: Provide proper encoding!
83def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
84                     "add.w\t{$src2, $dst|$dst, $src2}",
85                     [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
86                      (implicit SRW)]>;
87
88def ADD8rr  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
89                     "add.b\t{$src2, $dst|$dst, $src2}",
90                     [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
91                      (implicit SRW)]>;
92}
93
94def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
95                     "add.w\t{$src2, $dst|$dst, $src2}",
96                     [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
97                      (implicit SRW)]>;
98def ADD8ri  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
99                     "add.b\t{$src2, $dst|$dst, $src2}",
100                     [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
101                      (implicit SRW)]>;
102
103let Uses = [SRW] in {
104
105let isCommutable = 1 in { // X = ADDC Y, Z  == X = ADDC Z, Y
106def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
107                     "addc.w\t{$src2, $dst|$dst, $src2}",
108                     [(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
109                      (implicit SRW)]>;
110def ADC8rr  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
111                     "addc.b\t{$src2, $dst|$dst, $src2}",
112                     [(set GR8:$dst, (adde GR8:$src1, GR8:$src2)),
113                      (implicit SRW)]>;
114} // isCommutable
115
116def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
117                     "addc.w\t{$src2, $dst|$dst, $src2}",
118                     [(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
119                      (implicit SRW)]>;
120def ADC8ri  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
121                     "addc.b\t{$src2, $dst|$dst, $src2}",
122                     [(set GR8:$dst, (adde GR8:$src1, imm:$src2)),
123                      (implicit SRW)]>;
124}
125
126let isCommutable = 1 in { // X = AND Y, Z  == X = AND Z, Y
127def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
128                     "and.w\t{$src2, $dst|$dst, $src2}",
129                     [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
130                      (implicit SRW)]>;
131def AND8rr  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
132                     "and.b\t{$src2, $dst|$dst, $src2}",
133                     [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
134                      (implicit SRW)]>;
135}
136
137def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
138                     "and.w\t{$src2, $dst|$dst, $src2}",
139                     [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
140                      (implicit SRW)]>;
141def AND8ri  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
142                     "and.b\t{$src2, $dst|$dst, $src2}",
143                     [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
144                      (implicit SRW)]>;
145
146let isCommutable = 1 in { // X = XOR Y, Z  == X = XOR Z, Y
147def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
148                     "xor.w\t{$src2, $dst|$dst, $src2}",
149                     [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
150                      (implicit SRW)]>;
151def XOR8rr  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
152                     "xor.b\t{$src2, $dst|$dst, $src2}",
153                     [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
154                      (implicit SRW)]>;
155}
156
157def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
158                     "xor.w\t{$src2, $dst|$dst, $src2}",
159                     [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
160                      (implicit SRW)]>;
161def XOR8ri  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
162                     "xor.b\t{$src2, $dst|$dst, $src2}",
163                     [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
164                      (implicit SRW)]>;
165
166
167def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
168                     "sub.w\t{$src2, $dst|$dst, $src2}",
169                     [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
170                      (implicit SRW)]>;
171def SUB8rr  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
172                     "sub.b\t{$src2, $dst|$dst, $src2}",
173                     [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
174                      (implicit SRW)]>;
175
176def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
177                     "sub.w\t{$src2, $dst|$dst, $src2}",
178                     [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
179                      (implicit SRW)]>;
180def SUB8ri  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
181                     "sub.b\t{$src2, $dst|$dst, $src2}",
182                     [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
183                      (implicit SRW)]>;
184
185let Uses = [SRW] in {
186def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
187                     "subc.w\t{$src2, $dst|$dst, $src2}",
188                     [(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
189                      (implicit SRW)]>;
190def SBC8rr  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
191                     "subc.b\t{$src2, $dst|$dst, $src2}",
192                     [(set GR8:$dst, (sube GR8:$src1, GR8:$src2)),
193                      (implicit SRW)]>;
194
195def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
196                     "subc.w\t{$src2, $dst|$dst, $src2}",
197                     [(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
198                      (implicit SRW)]>;
199def SBC8ri  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
200                     "subc.b\t{$src2, $dst|$dst, $src2}",
201                     [(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
202                      (implicit SRW)]>;
203}
204
205// FIXME: Provide proper encoding!
206def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
207                     "rra.w\t$dst",
208                     [(set GR16:$dst, (MSP430rra GR16:$src)),
209                      (implicit SRW)]>;
210
211def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
212                     "sxt\t$dst",
213                     [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
214                      (implicit SRW)]>;
215
216} // Defs = [SRW]
217
218let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
219def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
220                    "bis.w\t{$src2, $dst|$dst, $src2}",
221                    [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
222def OR8rr  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
223                    "bis.b\t{$src2, $dst|$dst, $src2}",
224                    [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
225}
226
227def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
228                    "bis.w\t{$src2, $dst|$dst, $src2}",
229                    [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
230def OR8ri  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
231                    "bis.b\t{$src2, $dst|$dst, $src2}",
232                    [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
233
234} // isTwoAddress = 1
235