Mips16InstrInfo.cpp revision 29cb2591f9f7ec948e7b0e719b1db6cef99010d0 
1//===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips16 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Mips16InstrInfo.h"
15#include "InstPrinter/MipsInstPrinter.h"
16#include "MipsMachineFunction.h"
17#include "MipsTargetMachine.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/RegisterScavenging.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/Debug.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/TargetRegistry.h"
27
28using namespace llvm;
29
30static cl::opt<bool> NeverUseSaveRestore(
31  "mips16-never-use-save-restore",
32  cl::init(false),
33  cl::desc("For testing ability to adjust stack pointer "
34           "without save/restore instruction"),
35  cl::Hidden);
36
37
38Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
39  : MipsInstrInfo(tm, Mips::BimmX16),
40    RI(*tm.getSubtargetImpl(), *this) {}
41
42const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
43  return RI;
44}
45
46/// isLoadFromStackSlot - If the specified machine instruction is a direct
47/// load from a stack slot, return the virtual or physical register number of
48/// the destination along with the FrameIndex of the loaded stack slot.  If
49/// not, return 0.  This predicate must return 0 if the instruction has
50/// any side effects other than loading from the stack slot.
51unsigned Mips16InstrInfo::
52isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
53{
54  return 0;
55}
56
57/// isStoreToStackSlot - If the specified machine instruction is a direct
58/// store to a stack slot, return the virtual or physical register number of
59/// the source reg along with the FrameIndex of the loaded stack slot.  If
60/// not, return 0.  This predicate must return 0 if the instruction has
61/// any side effects other than storing to the stack slot.
62unsigned Mips16InstrInfo::
63isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
64{
65  return 0;
66}
67
68void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
69                                  MachineBasicBlock::iterator I, DebugLoc DL,
70                                  unsigned DestReg, unsigned SrcReg,
71                                  bool KillSrc) const {
72  unsigned Opc = 0;
73
74  if (Mips::CPU16RegsRegClass.contains(DestReg) &&
75      Mips::CPURegsRegClass.contains(SrcReg))
76    Opc = Mips::MoveR3216;
77  else if (Mips::CPURegsRegClass.contains(DestReg) &&
78           Mips::CPU16RegsRegClass.contains(SrcReg))
79    Opc = Mips::Move32R16;
80  else if ((SrcReg == Mips::HI) &&
81           (Mips::CPU16RegsRegClass.contains(DestReg)))
82    Opc = Mips::Mfhi16, SrcReg = 0;
83
84  else if ((SrcReg == Mips::LO) &&
85           (Mips::CPU16RegsRegClass.contains(DestReg)))
86    Opc = Mips::Mflo16, SrcReg = 0;
87
88
89  assert(Opc && "Cannot copy registers");
90
91  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
92
93  if (DestReg)
94    MIB.addReg(DestReg, RegState::Define);
95
96  if (SrcReg)
97    MIB.addReg(SrcReg, getKillRegState(KillSrc));
98}
99
100void Mips16InstrInfo::
101storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
102                    unsigned SrcReg, bool isKill, int FI,
103                    const TargetRegisterClass *RC,
104                    const TargetRegisterInfo *TRI) const {
105  DebugLoc DL;
106  if (I != MBB.end()) DL = I->getDebugLoc();
107  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
108  unsigned Opc = 0;
109  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
110    Opc = Mips::SwRxSpImmX16;
111  assert(Opc && "Register class not handled!");
112  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
113    .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
114}
115
116void Mips16InstrInfo::
117loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
118                     unsigned DestReg, int FI,
119                     const TargetRegisterClass *RC,
120                     const TargetRegisterInfo *TRI) const {
121  DebugLoc DL;
122  if (I != MBB.end()) DL = I->getDebugLoc();
123  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
124  unsigned Opc = 0;
125
126  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
127    Opc = Mips::LwRxSpImmX16;
128  assert(Opc && "Register class not handled!");
129  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
130    .addMemOperand(MMO);
131}
132
133bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
134  MachineBasicBlock &MBB = *MI->getParent();
135  switch(MI->getDesc().getOpcode()) {
136  default:
137    return false;
138  case Mips::RetRA16:
139    ExpandRetRA16(MBB, MI, Mips::JrcRa16);
140    break;
141  case Mips::SltCCRxRy16:
142    ExpandFEXT_CCRX16_ins(MBB, MI, Mips::SltRxRy16);
143    break;
144  case Mips::SltiCCRxImmX16:
145    ExpandFEXT_CCRXI16_ins(MBB, MI, Mips::SltiRxImm16, Mips::SltiRxImmX16);
146    break;
147  case Mips::SltiuCCRxImmX16:
148    ExpandFEXT_CCRXI16_ins(MBB, MI, Mips::SltiuRxImm16, Mips::SltiuRxImmX16);
149    break;
150  case Mips::SltuCCRxRy16:
151    ExpandFEXT_CCRX16_ins(MBB, MI, Mips::SltuRxRy16);
152    break;
153  }
154
155  MBB.erase(MI);
156  return true;
157}
158
159/// GetOppositeBranchOpc - Return the inverse of the specified
160/// opcode, e.g. turning BEQ to BNE.
161unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
162  switch (Opc) {
163  default:  llvm_unreachable("Illegal opcode!");
164  case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
165  case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
166  case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
167  case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
168  case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
169  case Mips::BtnezX16: return Mips::BteqzX16;
170  case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
171  case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
172  case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
173  case Mips::BteqzX16: return Mips::BtnezX16;
174  case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
175  case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
176  case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
177  case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
178  case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
179  case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
180  }
181  assert(false && "Implement this function.");
182  return 0;
183}
184
185// Adjust SP by FrameSize bytes. Save RA, S0, S1
186void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
187                    MachineBasicBlock &MBB,
188                    MachineBasicBlock::iterator I) const {
189  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
190  if (!NeverUseSaveRestore) {
191    if (isUInt<11>(FrameSize))
192      BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
193    else {
194      int Base = 2040; // should create template function like isUInt that
195                       // returns largest possible n bit unsigned integer
196      int64_t Remainder = FrameSize - Base;
197      BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
198      if (isInt<16>(-Remainder))
199        BuildAddiuSpImm(MBB, I, -Remainder);
200      else
201        adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
202    }
203
204  }
205  else {
206    //
207    // sw ra, -4[sp]
208    // sw s1, -8[sp]
209    // sw s0, -12[sp]
210
211    MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
212                                       Mips::RA);
213    MIB1.addReg(Mips::SP);
214    MIB1.addImm(-4);
215    MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
216                                       Mips::S1);
217    MIB2.addReg(Mips::SP);
218    MIB2.addImm(-8);
219    MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
220                                       Mips::S0);
221    MIB3.addReg(Mips::SP);
222    MIB3.addImm(-12);
223    adjustStackPtrBig(SP, -FrameSize, MBB, I, Mips::V0, Mips::V1);
224  }
225}
226
227// Adjust SP by FrameSize bytes. Restore RA, S0, S1
228void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
229                                   MachineBasicBlock &MBB,
230                                   MachineBasicBlock::iterator I) const {
231  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
232  if (!NeverUseSaveRestore) {
233    if (isUInt<11>(FrameSize))
234      BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
235    else {
236      int Base = 2040; // should create template function like isUInt that
237                       // returns largest possible n bit unsigned integer
238      int64_t Remainder = FrameSize - Base;
239      if (isInt<16>(Remainder))
240        BuildAddiuSpImm(MBB, I, Remainder);
241      else
242        adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
243      BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
244    }
245  }
246  else {
247    adjustStackPtrBig(SP, FrameSize, MBB, I, Mips::A0, Mips::A1);
248    // lw ra, -4[sp]
249    // lw s1, -8[sp]
250    // lw s0, -12[sp]
251    MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
252                                       Mips::A0);
253    MIB1.addReg(Mips::SP);
254    MIB1.addImm(-4);
255    MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
256                                       Mips::RA);
257     MIB0.addReg(Mips::A0);
258    MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
259                                       Mips::S1);
260    MIB2.addReg(Mips::SP);
261    MIB2.addImm(-8);
262    MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
263                                       Mips::S0);
264    MIB3.addReg(Mips::SP);
265    MIB3.addImm(-12);
266  }
267
268}
269
270// Adjust SP by Amount bytes where bytes can be up to 32bit number.
271// This can only be called at times that we know that there is at least one free
272// register.
273// This is clearly safe at prologue and epilogue.
274//
275void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
276                                        MachineBasicBlock &MBB,
277                                        MachineBasicBlock::iterator I,
278                                        unsigned Reg1, unsigned Reg2) const {
279  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
280//  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
281//  unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
282//  unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
283  //
284  // li reg1, constant
285  // move reg2, sp
286  // add reg1, reg1, reg2
287  // move sp, reg1
288  //
289  //
290  MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
291  MIB1.addImm(Amount);
292  MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
293  MIB2.addReg(Mips::SP, RegState::Kill);
294  MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
295  MIB3.addReg(Reg1);
296  MIB3.addReg(Reg2, RegState::Kill);
297  MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
298                                                     Mips::SP);
299  MIB4.addReg(Reg1, RegState::Kill);
300}
301
302void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
303                    MachineBasicBlock &MBB,
304                    MachineBasicBlock::iterator I) const {
305   assert(false && "adjust stack pointer amount exceeded");
306}
307
308/// Adjust SP by Amount bytes.
309void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
310                                     MachineBasicBlock &MBB,
311                                     MachineBasicBlock::iterator I) const {
312  if (isInt<16>(Amount))  // need to change to addiu sp, ....and isInt<16>
313    BuildAddiuSpImm(MBB, I, Amount);
314  else
315    adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
316}
317
318/// This function generates the sequence of instructions needed to get the
319/// result of adding register REG and immediate IMM.
320unsigned
321Mips16InstrInfo::loadImmediate(unsigned FrameReg,
322                               int64_t Imm, MachineBasicBlock &MBB,
323                               MachineBasicBlock::iterator II, DebugLoc DL,
324                               unsigned &NewImm) const {
325  //
326  // given original instruction is:
327  // Instr rx, T[offset] where offset is too big.
328  //
329  // lo = offset & 0xFFFF
330  // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
331  //
332  // let T = temporary register
333  // li T, hi
334  // shl T, 16
335  // add T, Rx, T
336  //
337  RegScavenger rs;
338  int32_t lo = Imm & 0xFFFF;
339  int32_t hi = ((Imm >> 16) + (lo >> 15)) & 0xFFFF;
340  NewImm = lo;
341  unsigned Reg =0;
342  unsigned SpReg = 0;
343  rs.enterBasicBlock(&MBB);
344  rs.forward(II);
345  //
346  // we use T0 for the first register, if we need to save something away.
347  // we use T1 for the second register, if we need to save something away.
348  //
349  unsigned FirstRegSaved =0, SecondRegSaved=0;
350  unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
351
352  Reg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
353  if (Reg == 0) {
354    FirstRegSaved = Reg = Mips::V0;
355    FirstRegSavedTo = Mips::T0;
356    copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
357  }
358  else
359    rs.setUsed(Reg);
360  BuildMI(MBB, II, DL, get(Mips::LiRxImmX16), Reg).addImm(hi);
361  BuildMI(MBB, II, DL, get(Mips::SllX16), Reg).addReg(Reg).
362    addImm(16);
363  if (FrameReg == Mips::SP) {
364    SpReg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
365    if (SpReg == 0) {
366      if (Reg != Mips::V1) {
367        SecondRegSaved = SpReg = Mips::V1;
368        SecondRegSavedTo = Mips::T1;
369      }
370      else {
371        SecondRegSaved = SpReg = Mips::V0;
372        SecondRegSavedTo = Mips::T0;
373      }
374      copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
375    }
376    else
377      rs.setUsed(SpReg);
378
379    copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
380    BuildMI(MBB, II, DL, get(Mips::  AdduRxRyRz16), Reg).addReg(SpReg)
381      .addReg(Reg);
382  }
383  else
384    BuildMI(MBB, II, DL, get(Mips::  AdduRxRyRz16), Reg).addReg(FrameReg)
385      .addReg(Reg, RegState::Kill);
386  if (FirstRegSaved || SecondRegSaved) {
387    II = llvm::next(II);
388    if (FirstRegSaved)
389      copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
390    if (SecondRegSaved)
391      copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
392  }
393  return Reg;
394}
395
396unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
397  return (Opc == Mips::BeqzRxImmX16   || Opc == Mips::BimmX16  ||
398          Opc == Mips::BnezRxImmX16   || Opc == Mips::BteqzX16 ||
399          Opc == Mips::BteqzT8CmpX16  || Opc == Mips::BteqzT8CmpiX16 ||
400          Opc == Mips::BteqzT8SltX16  || Opc == Mips::BteqzT8SltuX16  ||
401          Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
402          Opc == Mips::BtnezX16       || Opc == Mips::BtnezT8CmpX16 ||
403          Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
404          Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
405          Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
406}
407
408void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
409                                  MachineBasicBlock::iterator I,
410                                  unsigned Opc) const {
411  BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
412}
413
414void Mips16InstrInfo::ExpandFEXT_CCRX16_ins(
415  MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
416  unsigned SltOpc) const {
417  unsigned CC = I->getOperand(0).getReg();
418  unsigned regX = I->getOperand(1).getReg();
419  unsigned regY = I->getOperand(2).getReg();
420  BuildMI(MBB, I, I->getDebugLoc(), get(SltOpc)).addReg(regX).addReg(regY);
421  BuildMI(MBB, I, I->getDebugLoc(),
422          get(Mips::MoveR3216), CC).addReg(Mips::T8);
423
424}
425void Mips16InstrInfo::ExpandFEXT_CCRXI16_ins(
426  MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
427  unsigned SltiOpc, unsigned SltiXOpc) const {
428  unsigned CC = I->getOperand(0).getReg();
429  unsigned regX = I->getOperand(1).getReg();
430  int64_t Imm = I->getOperand(2).getImm();
431  unsigned SltOpc = whichOp8u_or_16simm(SltiOpc, SltiXOpc, Imm);
432  BuildMI(MBB, I, I->getDebugLoc(), get(SltOpc)).addReg(regX).addImm(Imm);
433  BuildMI(MBB, I, I->getDebugLoc(),
434          get(Mips::MoveR3216), CC).addReg(Mips::T8);
435
436}
437
438const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
439  if (validSpImm8(Imm))
440    return get(Mips::AddiuSpImm16);
441  else
442    return get(Mips::AddiuSpImmX16);
443}
444
445void Mips16InstrInfo::BuildAddiuSpImm
446  (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
447  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
448  BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
449}
450
451unsigned Mips16InstrInfo::whichOp8_or_16uimm
452  (unsigned shortOp, unsigned longOp, int64_t Imm) {
453  if (isUInt<8>(Imm))
454    return shortOp;
455  else if (isUInt<16>(Imm))
456    return longOp;
457  else
458    llvm_unreachable("immediate field not usable");
459}
460
461unsigned Mips16InstrInfo::whichOp8u_or_16simm
462  (unsigned shortOp, unsigned longOp, int64_t Imm) {
463  if (isUInt<8>(Imm))
464    return shortOp;
465  else if (isInt<16>(Imm))
466    return longOp;
467  else
468    llvm_unreachable("immediate field not usable");
469}
470
471const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
472  return new Mips16InstrInfo(TM);
473}
474