Mips16InstrInfo.cpp revision 41e632d9e1a55d36cb08b0551ad82a13d9137a5e
15f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)//===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===// 25f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// 35f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// The LLVM Compiler Infrastructure 45f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// 55f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// This file is distributed under the University of Illinois Open Source 65f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// License. See LICENSE.TXT for details. 75f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// 85f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)//===----------------------------------------------------------------------===// 95f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// 105f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// This file contains the Mips16 implementation of the TargetInstrInfo class. 115f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// 125f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)//===----------------------------------------------------------------------===// 135f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 145f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "Mips16InstrInfo.h" 155f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "InstPrinter/MipsInstPrinter.h" 165f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "MipsMachineFunction.h" 175f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "MipsTargetMachine.h" 185f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/ADT/STLExtras.h" 195f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/ADT/StringRef.h" 205f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/CodeGen/MachineInstrBuilder.h" 215f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/CodeGen/MachineRegisterInfo.h" 225f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/CodeGen/RegisterScavenging.h" 235f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/Support/CommandLine.h" 245f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/Support/Debug.h" 255f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/Support/ErrorHandling.h" 265f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "llvm/Support/TargetRegistry.h" 275f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 285f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)using namespace llvm; 295f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 305f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)static cl::opt<bool> NeverUseSaveRestore( 315f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) "mips16-never-use-save-restore", 325f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) cl::init(false), 335f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) cl::desc("For testing ability to adjust stack pointer " 345f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) "without save/restore instruction"), 355f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) cl::Hidden); 365f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 375f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 385f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm) 395f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) : MipsInstrInfo(tm, Mips::BimmX16), 405f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) RI(*tm.getSubtargetImpl()) {} 415f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 425f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const { 435f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) return RI; 445f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)} 455f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 465f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)/// isLoadFromStackSlot - If the specified machine instruction is a direct 475f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)/// load from a stack slot, return the virtual or physical register number of 485f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)/// the destination along with the FrameIndex of the loaded stack slot. If 495f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)/// not, return 0. This predicate must return 0 if the instruction has 505f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)/// any side effects other than loading from the stack slot. 515f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)unsigned Mips16InstrInfo:: 525f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const 535f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles){ 545f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) return 0; 555f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)} 565f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 575f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)/// isStoreToStackSlot - If the specified machine instruction is a direct 585f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)/// store to a stack slot, return the virtual or physical register number of 595f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)/// the source reg along with the FrameIndex of the loaded stack slot. If 605f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)/// not, return 0. This predicate must return 0 if the instruction has 615f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)/// any side effects other than storing to the stack slot. 625f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)unsigned Mips16InstrInfo:: 635f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const 645f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles){ 655f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) return 0; 665f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)} 675f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 685f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 695f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) MachineBasicBlock::iterator I, DebugLoc DL, 705f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) unsigned DestReg, unsigned SrcReg, 715f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) bool KillSrc) const { 725f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) unsigned Opc = 0; 735f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 745f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) if (Mips::CPU16RegsRegClass.contains(DestReg) && 755f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) Mips::CPURegsRegClass.contains(SrcReg)) 765f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) Opc = Mips::MoveR3216; 775f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) else if (Mips::CPURegsRegClass.contains(DestReg) && 785f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) Mips::CPU16RegsRegClass.contains(SrcReg)) 795f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) Opc = Mips::Move32R16; 805f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) else if ((SrcReg == Mips::HI) && 815f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) (Mips::CPU16RegsRegClass.contains(DestReg))) 825f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) Opc = Mips::Mfhi16, SrcReg = 0; 835f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 845f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) else if ((SrcReg == Mips::LO) && 855f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) (Mips::CPU16RegsRegClass.contains(DestReg))) 865f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) Opc = Mips::Mflo16, SrcReg = 0; 875f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 885f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 895f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) assert(Opc && "Cannot copy registers"); 905f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 915f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); 925f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 935f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) if (DestReg) 945f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) MIB.addReg(DestReg, RegState::Define); 955f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 965f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) if (SrcReg) 975f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) MIB.addReg(SrcReg, getKillRegState(KillSrc)); 985f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)} 995f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 1005f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)void Mips16InstrInfo:: 1015f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1025f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) unsigned SrcReg, bool isKill, int FI, 1035f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, 1045f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) int64_t Offset) const { 1055f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) DebugLoc DL; 1065f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) if (I != MBB.end()) DL = I->getDebugLoc(); 1075f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); 1085f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) unsigned Opc = 0; 1095f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) 1105f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) Opc = Mips::SwRxSpImmX16; 1115f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) assert(Opc && "Register class not handled!"); 1125f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) 1135f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); 1145f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)} 1155f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 1165f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)void Mips16InstrInfo:: 1175f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1185f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) unsigned DestReg, int FI, const TargetRegisterClass *RC, 1195f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) const TargetRegisterInfo *TRI, int64_t Offset) const { 1205f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) DebugLoc DL; 1215f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) if (I != MBB.end()) DL = I->getDebugLoc(); 1225f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); 1235f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) unsigned Opc = 0; 1245f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 1255f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) 1265f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) Opc = Mips::LwRxSpImmX16; 1275f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) assert(Opc && "Register class not handled!"); 1285f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset) 1295f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) .addMemOperand(MMO); 1305f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)} 1315f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 1325f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 1335f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) MachineBasicBlock &MBB = *MI->getParent(); 1345f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) switch(MI->getDesc().getOpcode()) { 1355f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) default: 1365f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) return false; 1375f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) case Mips::RetRA16: 1385f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) ExpandRetRA16(MBB, MI, Mips::JrcRa16); 1395f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) break; 1405f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) } 1415f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 1425f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) MBB.erase(MI); 1435f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) return true; 1445f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)} 1455f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 1465f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)/// GetOppositeBranchOpc - Return the inverse of the specified 1475f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)/// opcode, e.g. turning BEQ to BNE. 1485f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const { 1495f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) switch (Opc) { 1505f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) default: llvm_unreachable("Illegal opcode!"); 1515f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16; 1525f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16; 1535f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16; 1545f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16; 1555f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16; 1565f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) case Mips::BtnezX16: return Mips::BteqzX16; 1575f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16; 1585f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16; 1595f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16; 160 case Mips::BteqzX16: return Mips::BtnezX16; 161 case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16; 162 case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16; 163 case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16; 164 case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16; 165 case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16; 166 case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16; 167 } 168 assert(false && "Implement this function."); 169 return 0; 170} 171 172// Adjust SP by FrameSize bytes. Save RA, S0, S1 173void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize, 174 MachineBasicBlock &MBB, 175 MachineBasicBlock::iterator I) const { 176 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); 177 if (!NeverUseSaveRestore) { 178 if (isUInt<11>(FrameSize)) 179 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize); 180 else { 181 int Base = 2040; // should create template function like isUInt that 182 // returns largest possible n bit unsigned integer 183 int64_t Remainder = FrameSize - Base; 184 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base); 185 if (isInt<16>(-Remainder)) 186 BuildAddiuSpImm(MBB, I, -Remainder); 187 else 188 adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1); 189 } 190 191 } 192 else { 193 // 194 // sw ra, -4[sp] 195 // sw s1, -8[sp] 196 // sw s0, -12[sp] 197 198 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16), 199 Mips::RA); 200 MIB1.addReg(Mips::SP); 201 MIB1.addImm(-4); 202 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16), 203 Mips::S1); 204 MIB2.addReg(Mips::SP); 205 MIB2.addImm(-8); 206 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16), 207 Mips::S0); 208 MIB3.addReg(Mips::SP); 209 MIB3.addImm(-12); 210 adjustStackPtrBig(SP, -FrameSize, MBB, I, Mips::V0, Mips::V1); 211 } 212} 213 214// Adjust SP by FrameSize bytes. Restore RA, S0, S1 215void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize, 216 MachineBasicBlock &MBB, 217 MachineBasicBlock::iterator I) const { 218 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); 219 if (!NeverUseSaveRestore) { 220 if (isUInt<11>(FrameSize)) 221 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize); 222 else { 223 int Base = 2040; // should create template function like isUInt that 224 // returns largest possible n bit unsigned integer 225 int64_t Remainder = FrameSize - Base; 226 if (isInt<16>(Remainder)) 227 BuildAddiuSpImm(MBB, I, Remainder); 228 else 229 adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1); 230 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base); 231 } 232 } 233 else { 234 adjustStackPtrBig(SP, FrameSize, MBB, I, Mips::A0, Mips::A1); 235 // lw ra, -4[sp] 236 // lw s1, -8[sp] 237 // lw s0, -12[sp] 238 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16), 239 Mips::A0); 240 MIB1.addReg(Mips::SP); 241 MIB1.addImm(-4); 242 MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16), 243 Mips::RA); 244 MIB0.addReg(Mips::A0); 245 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16), 246 Mips::S1); 247 MIB2.addReg(Mips::SP); 248 MIB2.addImm(-8); 249 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16), 250 Mips::S0); 251 MIB3.addReg(Mips::SP); 252 MIB3.addImm(-12); 253 } 254 255} 256 257// Adjust SP by Amount bytes where bytes can be up to 32bit number. 258// This can only be called at times that we know that there is at least one free 259// register. 260// This is clearly safe at prologue and epilogue. 261// 262void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount, 263 MachineBasicBlock &MBB, 264 MachineBasicBlock::iterator I, 265 unsigned Reg1, unsigned Reg2) const { 266 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); 267// MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); 268// unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass); 269// unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass); 270 // 271 // li reg1, constant 272 // move reg2, sp 273 // add reg1, reg1, reg2 274 // move sp, reg1 275 // 276 // 277 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1); 278 MIB1.addImm(Amount); 279 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2); 280 MIB2.addReg(Mips::SP, RegState::Kill); 281 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1); 282 MIB3.addReg(Reg1); 283 MIB3.addReg(Reg2, RegState::Kill); 284 MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16), 285 Mips::SP); 286 MIB4.addReg(Reg1, RegState::Kill); 287} 288 289void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount, 290 MachineBasicBlock &MBB, 291 MachineBasicBlock::iterator I) const { 292 assert(false && "adjust stack pointer amount exceeded"); 293} 294 295/// Adjust SP by Amount bytes. 296void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, 297 MachineBasicBlock &MBB, 298 MachineBasicBlock::iterator I) const { 299 if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16> 300 BuildAddiuSpImm(MBB, I, Amount); 301 else 302 adjustStackPtrBigUnrestricted(SP, Amount, MBB, I); 303} 304 305/// This function generates the sequence of instructions needed to get the 306/// result of adding register REG and immediate IMM. 307unsigned 308Mips16InstrInfo::loadImmediate(unsigned FrameReg, 309 int64_t Imm, MachineBasicBlock &MBB, 310 MachineBasicBlock::iterator II, DebugLoc DL, 311 unsigned &NewImm) const { 312 // 313 // given original instruction is: 314 // Instr rx, T[offset] where offset is too big. 315 // 316 // lo = offset & 0xFFFF 317 // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF; 318 // 319 // let T = temporary register 320 // li T, hi 321 // shl T, 16 322 // add T, Rx, T 323 // 324 RegScavenger rs; 325 int32_t lo = Imm & 0xFFFF; 326 int32_t hi = ((Imm >> 16) + (lo >> 15)) & 0xFFFF; 327 NewImm = lo; 328 unsigned Reg =0; 329 unsigned SpReg = 0; 330 rs.enterBasicBlock(&MBB); 331 rs.forward(II); 332 // 333 // we use T0 for the first register, if we need to save something away. 334 // we use T1 for the second register, if we need to save something away. 335 // 336 unsigned FirstRegSaved =0, SecondRegSaved=0; 337 unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0; 338 339 Reg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass); 340 if (Reg == 0) { 341 FirstRegSaved = Reg = Mips::V0; 342 FirstRegSavedTo = Mips::T0; 343 copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true); 344 } 345 else 346 rs.setUsed(Reg); 347 BuildMI(MBB, II, DL, get(Mips::LiRxImmX16), Reg).addImm(hi); 348 BuildMI(MBB, II, DL, get(Mips::SllX16), Reg).addReg(Reg). 349 addImm(16); 350 if (FrameReg == Mips::SP) { 351 SpReg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass); 352 if (SpReg == 0) { 353 if (Reg != Mips::V1) { 354 SecondRegSaved = SpReg = Mips::V1; 355 SecondRegSavedTo = Mips::T1; 356 } 357 else { 358 SecondRegSaved = SpReg = Mips::V0; 359 SecondRegSavedTo = Mips::T0; 360 } 361 copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true); 362 } 363 else 364 rs.setUsed(SpReg); 365 366 copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false); 367 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg) 368 .addReg(Reg); 369 } 370 else 371 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg) 372 .addReg(Reg, RegState::Kill); 373 if (FirstRegSaved || SecondRegSaved) { 374 II = llvm::next(II); 375 if (FirstRegSaved) 376 copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true); 377 if (SecondRegSaved) 378 copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true); 379 } 380 return Reg; 381} 382 383unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const { 384 return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 || 385 Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 || 386 Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 || 387 Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 || 388 Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 || 389 Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 || 390 Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 || 391 Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 || 392 Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0; 393} 394 395void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB, 396 MachineBasicBlock::iterator I, 397 unsigned Opc) const { 398 BuildMI(MBB, I, I->getDebugLoc(), get(Opc)); 399} 400 401 402const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const { 403 if (validSpImm8(Imm)) 404 return get(Mips::AddiuSpImm16); 405 else 406 return get(Mips::AddiuSpImmX16); 407} 408 409void Mips16InstrInfo::BuildAddiuSpImm 410 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const { 411 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); 412 BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm); 413} 414 415const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) { 416 return new Mips16InstrInfo(TM); 417} 418