Mips16InstrInfo.cpp revision 459d35cb7975804048684261f2358eedbd2209c1 
1//===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips16 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Mips16InstrInfo.h"
15#include "InstPrinter/MipsInstPrinter.h"
16#include "MipsMachineFunction.h"
17#include "MipsTargetMachine.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/RegisterScavenging.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/Debug.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/TargetRegistry.h"
27
28using namespace llvm;
29
30static cl::opt<bool> NeverUseSaveRestore(
31  "mips16-never-use-save-restore",
32  cl::init(false),
33  cl::desc("For testing ability to adjust stack pointer "
34           "without save/restore instruction"),
35  cl::Hidden);
36
37
38Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
39  : MipsInstrInfo(tm, Mips::BimmX16),
40    RI(*tm.getSubtargetImpl(), *this) {}
41
42const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
43  return RI;
44}
45
46/// isLoadFromStackSlot - If the specified machine instruction is a direct
47/// load from a stack slot, return the virtual or physical register number of
48/// the destination along with the FrameIndex of the loaded stack slot.  If
49/// not, return 0.  This predicate must return 0 if the instruction has
50/// any side effects other than loading from the stack slot.
51unsigned Mips16InstrInfo::
52isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
53{
54  return 0;
55}
56
57/// isStoreToStackSlot - If the specified machine instruction is a direct
58/// store to a stack slot, return the virtual or physical register number of
59/// the source reg along with the FrameIndex of the loaded stack slot.  If
60/// not, return 0.  This predicate must return 0 if the instruction has
61/// any side effects other than storing to the stack slot.
62unsigned Mips16InstrInfo::
63isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
64{
65  return 0;
66}
67
68void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
69                                  MachineBasicBlock::iterator I, DebugLoc DL,
70                                  unsigned DestReg, unsigned SrcReg,
71                                  bool KillSrc) const {
72  unsigned Opc = 0;
73
74  if (Mips::CPU16RegsRegClass.contains(DestReg) &&
75      Mips::CPURegsRegClass.contains(SrcReg))
76    Opc = Mips::MoveR3216;
77  else if (Mips::CPURegsRegClass.contains(DestReg) &&
78           Mips::CPU16RegsRegClass.contains(SrcReg))
79    Opc = Mips::Move32R16;
80  else if ((SrcReg == Mips::HI) &&
81           (Mips::CPU16RegsRegClass.contains(DestReg)))
82    Opc = Mips::Mfhi16, SrcReg = 0;
83
84  else if ((SrcReg == Mips::LO) &&
85           (Mips::CPU16RegsRegClass.contains(DestReg)))
86    Opc = Mips::Mflo16, SrcReg = 0;
87
88
89  assert(Opc && "Cannot copy registers");
90
91  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
92
93  if (DestReg)
94    MIB.addReg(DestReg, RegState::Define);
95
96  if (SrcReg)
97    MIB.addReg(SrcReg, getKillRegState(KillSrc));
98}
99
100void Mips16InstrInfo::
101storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
102                    unsigned SrcReg, bool isKill, int FI,
103                    const TargetRegisterClass *RC,
104                    const TargetRegisterInfo *TRI) const {
105  DebugLoc DL;
106  if (I != MBB.end()) DL = I->getDebugLoc();
107  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
108  unsigned Opc = 0;
109  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
110    Opc = Mips::SwRxSpImmX16;
111  assert(Opc && "Register class not handled!");
112  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
113    .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
114}
115
116void Mips16InstrInfo::
117loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
118                     unsigned DestReg, int FI,
119                     const TargetRegisterClass *RC,
120                     const TargetRegisterInfo *TRI) const {
121  DebugLoc DL;
122  if (I != MBB.end()) DL = I->getDebugLoc();
123  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
124  unsigned Opc = 0;
125
126  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
127    Opc = Mips::LwRxSpImmX16;
128  assert(Opc && "Register class not handled!");
129  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
130    .addMemOperand(MMO);
131}
132
133bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
134  MachineBasicBlock &MBB = *MI->getParent();
135  switch(MI->getDesc().getOpcode()) {
136  default:
137    return false;
138  case Mips::BteqzT8CmpiX16:
139    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
140                           Mips::CmpiRxImm16, Mips::CmpiRxImmX16);
141    break;
142  case Mips::BteqzT8SltiX16:
143    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
144                           Mips::SltiRxImm16, Mips::SltiRxImmX16);
145    break;
146  case Mips::BteqzT8SltiuX16:
147    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
148                           Mips::SltiuRxImm16, Mips::SltiuRxImmX16);
149    break;
150  case Mips::BtnezT8CmpiX16:
151    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
152                           Mips::CmpiRxImm16, Mips::CmpiRxImmX16);
153    break;
154  case Mips::BtnezT8SltiX16:
155    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
156                           Mips::SltiRxImm16, Mips::SltiRxImmX16);
157    break;
158  case Mips::BtnezT8SltiuX16:
159    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
160                           Mips::SltiuRxImm16, Mips::SltiuRxImmX16);
161    break;
162  case Mips::RetRA16:
163    ExpandRetRA16(MBB, MI, Mips::JrcRa16);
164    break;
165  case Mips::SltCCRxRy16:
166    ExpandFEXT_CCRX16_ins(MBB, MI, Mips::SltRxRy16);
167    break;
168  case Mips::SltiCCRxImmX16:
169    ExpandFEXT_CCRXI16_ins(MBB, MI, Mips::SltiRxImm16, Mips::SltiRxImmX16);
170    break;
171  case Mips::SltiuCCRxImmX16:
172    ExpandFEXT_CCRXI16_ins(MBB, MI, Mips::SltiuRxImm16, Mips::SltiuRxImmX16);
173    break;
174  case Mips::SltuCCRxRy16:
175    ExpandFEXT_CCRX16_ins(MBB, MI, Mips::SltuRxRy16);
176    break;
177  }
178
179  MBB.erase(MI);
180  return true;
181}
182
183/// GetOppositeBranchOpc - Return the inverse of the specified
184/// opcode, e.g. turning BEQ to BNE.
185unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
186  switch (Opc) {
187  default:  llvm_unreachable("Illegal opcode!");
188  case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
189  case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
190  case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
191  case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
192  case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
193  case Mips::BtnezX16: return Mips::BteqzX16;
194  case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
195  case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
196  case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
197  case Mips::BteqzX16: return Mips::BtnezX16;
198  case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
199  case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
200  case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
201  case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
202  case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
203  case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
204  }
205  assert(false && "Implement this function.");
206  return 0;
207}
208
209// Adjust SP by FrameSize bytes. Save RA, S0, S1
210void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
211                    MachineBasicBlock &MBB,
212                    MachineBasicBlock::iterator I) const {
213  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
214  if (!NeverUseSaveRestore) {
215    if (isUInt<11>(FrameSize))
216      BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
217    else {
218      int Base = 2040; // should create template function like isUInt that
219                       // returns largest possible n bit unsigned integer
220      int64_t Remainder = FrameSize - Base;
221      BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
222      if (isInt<16>(-Remainder))
223        BuildAddiuSpImm(MBB, I, -Remainder);
224      else
225        adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
226    }
227
228  }
229  else {
230    //
231    // sw ra, -4[sp]
232    // sw s1, -8[sp]
233    // sw s0, -12[sp]
234
235    MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
236                                       Mips::RA);
237    MIB1.addReg(Mips::SP);
238    MIB1.addImm(-4);
239    MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
240                                       Mips::S1);
241    MIB2.addReg(Mips::SP);
242    MIB2.addImm(-8);
243    MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
244                                       Mips::S0);
245    MIB3.addReg(Mips::SP);
246    MIB3.addImm(-12);
247    adjustStackPtrBig(SP, -FrameSize, MBB, I, Mips::V0, Mips::V1);
248  }
249}
250
251// Adjust SP by FrameSize bytes. Restore RA, S0, S1
252void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
253                                   MachineBasicBlock &MBB,
254                                   MachineBasicBlock::iterator I) const {
255  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
256  if (!NeverUseSaveRestore) {
257    if (isUInt<11>(FrameSize))
258      BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
259    else {
260      int Base = 2040; // should create template function like isUInt that
261                       // returns largest possible n bit unsigned integer
262      int64_t Remainder = FrameSize - Base;
263      if (isInt<16>(Remainder))
264        BuildAddiuSpImm(MBB, I, Remainder);
265      else
266        adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
267      BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
268    }
269  }
270  else {
271    adjustStackPtrBig(SP, FrameSize, MBB, I, Mips::A0, Mips::A1);
272    // lw ra, -4[sp]
273    // lw s1, -8[sp]
274    // lw s0, -12[sp]
275    MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
276                                       Mips::A0);
277    MIB1.addReg(Mips::SP);
278    MIB1.addImm(-4);
279    MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
280                                       Mips::RA);
281     MIB0.addReg(Mips::A0);
282    MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
283                                       Mips::S1);
284    MIB2.addReg(Mips::SP);
285    MIB2.addImm(-8);
286    MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
287                                       Mips::S0);
288    MIB3.addReg(Mips::SP);
289    MIB3.addImm(-12);
290  }
291
292}
293
294// Adjust SP by Amount bytes where bytes can be up to 32bit number.
295// This can only be called at times that we know that there is at least one free
296// register.
297// This is clearly safe at prologue and epilogue.
298//
299void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
300                                        MachineBasicBlock &MBB,
301                                        MachineBasicBlock::iterator I,
302                                        unsigned Reg1, unsigned Reg2) const {
303  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
304//  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
305//  unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
306//  unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
307  //
308  // li reg1, constant
309  // move reg2, sp
310  // add reg1, reg1, reg2
311  // move sp, reg1
312  //
313  //
314  MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
315  MIB1.addImm(Amount);
316  MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
317  MIB2.addReg(Mips::SP, RegState::Kill);
318  MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
319  MIB3.addReg(Reg1);
320  MIB3.addReg(Reg2, RegState::Kill);
321  MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
322                                                     Mips::SP);
323  MIB4.addReg(Reg1, RegState::Kill);
324}
325
326void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
327                    MachineBasicBlock &MBB,
328                    MachineBasicBlock::iterator I) const {
329   assert(false && "adjust stack pointer amount exceeded");
330}
331
332/// Adjust SP by Amount bytes.
333void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
334                                     MachineBasicBlock &MBB,
335                                     MachineBasicBlock::iterator I) const {
336  if (isInt<16>(Amount))  // need to change to addiu sp, ....and isInt<16>
337    BuildAddiuSpImm(MBB, I, Amount);
338  else
339    adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
340}
341
342/// This function generates the sequence of instructions needed to get the
343/// result of adding register REG and immediate IMM.
344unsigned
345Mips16InstrInfo::loadImmediate(unsigned FrameReg,
346                               int64_t Imm, MachineBasicBlock &MBB,
347                               MachineBasicBlock::iterator II, DebugLoc DL,
348                               unsigned &NewImm) const {
349  //
350  // given original instruction is:
351  // Instr rx, T[offset] where offset is too big.
352  //
353  // lo = offset & 0xFFFF
354  // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
355  //
356  // let T = temporary register
357  // li T, hi
358  // shl T, 16
359  // add T, Rx, T
360  //
361  RegScavenger rs;
362  int32_t lo = Imm & 0xFFFF;
363  int32_t hi = ((Imm >> 16) + (lo >> 15)) & 0xFFFF;
364  NewImm = lo;
365  unsigned Reg =0;
366  unsigned SpReg = 0;
367  rs.enterBasicBlock(&MBB);
368  rs.forward(II);
369  //
370  // we use T0 for the first register, if we need to save something away.
371  // we use T1 for the second register, if we need to save something away.
372  //
373  unsigned FirstRegSaved =0, SecondRegSaved=0;
374  unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
375
376  Reg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
377  if (Reg == 0) {
378    FirstRegSaved = Reg = Mips::V0;
379    FirstRegSavedTo = Mips::T0;
380    copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
381  }
382  else
383    rs.setUsed(Reg);
384  BuildMI(MBB, II, DL, get(Mips::LiRxImmX16), Reg).addImm(hi);
385  BuildMI(MBB, II, DL, get(Mips::SllX16), Reg).addReg(Reg).
386    addImm(16);
387  if (FrameReg == Mips::SP) {
388    SpReg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
389    if (SpReg == 0) {
390      if (Reg != Mips::V1) {
391        SecondRegSaved = SpReg = Mips::V1;
392        SecondRegSavedTo = Mips::T1;
393      }
394      else {
395        SecondRegSaved = SpReg = Mips::V0;
396        SecondRegSavedTo = Mips::T0;
397      }
398      copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
399    }
400    else
401      rs.setUsed(SpReg);
402
403    copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
404    BuildMI(MBB, II, DL, get(Mips::  AdduRxRyRz16), Reg).addReg(SpReg)
405      .addReg(Reg);
406  }
407  else
408    BuildMI(MBB, II, DL, get(Mips::  AdduRxRyRz16), Reg).addReg(FrameReg)
409      .addReg(Reg, RegState::Kill);
410  if (FirstRegSaved || SecondRegSaved) {
411    II = llvm::next(II);
412    if (FirstRegSaved)
413      copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
414    if (SecondRegSaved)
415      copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
416  }
417  return Reg;
418}
419
420unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
421  return (Opc == Mips::BeqzRxImmX16   || Opc == Mips::BimmX16  ||
422          Opc == Mips::BnezRxImmX16   || Opc == Mips::BteqzX16 ||
423          Opc == Mips::BteqzT8CmpX16  || Opc == Mips::BteqzT8CmpiX16 ||
424          Opc == Mips::BteqzT8SltX16  || Opc == Mips::BteqzT8SltuX16  ||
425          Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
426          Opc == Mips::BtnezX16       || Opc == Mips::BtnezT8CmpX16 ||
427          Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
428          Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
429          Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
430}
431
432void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
433                                  MachineBasicBlock::iterator I,
434                                  unsigned Opc) const {
435  BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
436}
437
438
439void Mips16InstrInfo::ExpandFEXT_T8I816_ins(
440  MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
441  unsigned BtOpc, unsigned CmpOpc) const {
442  unsigned regX = I->getOperand(0).getReg();
443  unsigned regY = I->getOperand(1).getReg();
444  MachineBasicBlock *target = I->getOperand(2).getMBB();
445  BuildMI(MBB, I, I->getDebugLoc(), get(CmpOpc)).addReg(regX).addReg(regY);
446  BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target);
447
448}
449
450void Mips16InstrInfo::ExpandFEXT_T8I8I16_ins(
451  MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
452  unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc) const {
453  unsigned regX = I->getOperand(0).getReg();
454  int64_t imm = I->getOperand(1).getImm();
455  MachineBasicBlock *target = I->getOperand(2).getMBB();
456  unsigned CmpOpc;
457  if (isUInt<8>(imm))
458    CmpOpc = CmpiOpc;
459  else if (isUInt<16>(imm))
460    CmpOpc = CmpiXOpc;
461  else
462    llvm_unreachable("immediate field not usable");
463  BuildMI(MBB, I, I->getDebugLoc(), get(CmpOpc)).addReg(regX).addImm(imm);
464  BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target);
465}
466
467void Mips16InstrInfo::ExpandFEXT_CCRX16_ins(
468  MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
469  unsigned SltOpc) const {
470  unsigned CC = I->getOperand(0).getReg();
471  unsigned regX = I->getOperand(1).getReg();
472  unsigned regY = I->getOperand(2).getReg();
473  BuildMI(MBB, I, I->getDebugLoc(), get(SltOpc)).addReg(regX).addReg(regY);
474  BuildMI(MBB, I, I->getDebugLoc(),
475          get(Mips::MoveR3216), CC).addReg(Mips::T8);
476
477}
478void Mips16InstrInfo::ExpandFEXT_CCRXI16_ins(
479  MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
480  unsigned SltiOpc, unsigned SltiXOpc) const {
481  unsigned CC = I->getOperand(0).getReg();
482  unsigned regX = I->getOperand(1).getReg();
483  int64_t Imm = I->getOperand(2).getImm();
484  unsigned SltOpc = whichOp8u_or_16simm(SltiOpc, SltiXOpc, Imm);
485  BuildMI(MBB, I, I->getDebugLoc(), get(SltOpc)).addReg(regX).addImm(Imm);
486  BuildMI(MBB, I, I->getDebugLoc(),
487          get(Mips::MoveR3216), CC).addReg(Mips::T8);
488
489}
490
491const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
492  if (validSpImm8(Imm))
493    return get(Mips::AddiuSpImm16);
494  else
495    return get(Mips::AddiuSpImmX16);
496}
497
498void Mips16InstrInfo::BuildAddiuSpImm
499  (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
500  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
501  BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
502}
503
504unsigned Mips16InstrInfo::whichOp8_or_16uimm
505  (unsigned shortOp, unsigned longOp, int64_t Imm) {
506  if (isUInt<8>(Imm))
507    return shortOp;
508  else if (isUInt<16>(Imm))
509    return longOp;
510  else
511    llvm_unreachable("immediate field not usable");
512}
513
514unsigned Mips16InstrInfo::whichOp8u_or_16simm
515  (unsigned shortOp, unsigned longOp, int64_t Imm) {
516  if (isUInt<8>(Imm))
517    return shortOp;
518  else if (isInt<16>(Imm))
519    return longOp;
520  else
521    llvm_unreachable("immediate field not usable");
522}
523
524const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
525  return new Mips16InstrInfo(TM);
526}
527