Mips16InstrInfo.cpp revision 8a20844e277d1f51600134589aeb9ca88d9ca25d 
1//===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips16 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Mips16InstrInfo.h"
15#include "InstPrinter/MipsInstPrinter.h"
16#include "MipsMachineFunction.h"
17#include "MipsTargetMachine.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/RegisterScavenging.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/Debug.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/TargetRegistry.h"
27
28using namespace llvm;
29
30static cl::opt<bool> NeverUseSaveRestore(
31  "mips16-never-use-save-restore",
32  cl::init(false),
33  cl::desc("For testing ability to adjust stack pointer "
34           "without save/restore instruction"),
35  cl::Hidden);
36
37
38Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
39  : MipsInstrInfo(tm, Mips::BimmX16),
40    RI(*tm.getSubtargetImpl(), *this) {}
41
42const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
43  return RI;
44}
45
46/// isLoadFromStackSlot - If the specified machine instruction is a direct
47/// load from a stack slot, return the virtual or physical register number of
48/// the destination along with the FrameIndex of the loaded stack slot.  If
49/// not, return 0.  This predicate must return 0 if the instruction has
50/// any side effects other than loading from the stack slot.
51unsigned Mips16InstrInfo::
52isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
53{
54  return 0;
55}
56
57/// isStoreToStackSlot - If the specified machine instruction is a direct
58/// store to a stack slot, return the virtual or physical register number of
59/// the source reg along with the FrameIndex of the loaded stack slot.  If
60/// not, return 0.  This predicate must return 0 if the instruction has
61/// any side effects other than storing to the stack slot.
62unsigned Mips16InstrInfo::
63isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
64{
65  return 0;
66}
67
68void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
69                                  MachineBasicBlock::iterator I, DebugLoc DL,
70                                  unsigned DestReg, unsigned SrcReg,
71                                  bool KillSrc) const {
72  unsigned Opc = 0;
73
74  if (Mips::CPU16RegsRegClass.contains(DestReg) &&
75      Mips::CPURegsRegClass.contains(SrcReg))
76    Opc = Mips::MoveR3216;
77  else if (Mips::CPURegsRegClass.contains(DestReg) &&
78           Mips::CPU16RegsRegClass.contains(SrcReg))
79    Opc = Mips::Move32R16;
80  else if ((SrcReg == Mips::HI) &&
81           (Mips::CPU16RegsRegClass.contains(DestReg)))
82    Opc = Mips::Mfhi16, SrcReg = 0;
83
84  else if ((SrcReg == Mips::LO) &&
85           (Mips::CPU16RegsRegClass.contains(DestReg)))
86    Opc = Mips::Mflo16, SrcReg = 0;
87
88
89  assert(Opc && "Cannot copy registers");
90
91  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
92
93  if (DestReg)
94    MIB.addReg(DestReg, RegState::Define);
95
96  if (SrcReg)
97    MIB.addReg(SrcReg, getKillRegState(KillSrc));
98}
99
100void Mips16InstrInfo::
101storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
102                    unsigned SrcReg, bool isKill, int FI,
103                    const TargetRegisterClass *RC,
104                    const TargetRegisterInfo *TRI) const {
105  DebugLoc DL;
106  if (I != MBB.end()) DL = I->getDebugLoc();
107  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
108  unsigned Opc = 0;
109  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
110    Opc = Mips::SwRxSpImmX16;
111  assert(Opc && "Register class not handled!");
112  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
113    .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
114}
115
116void Mips16InstrInfo::
117loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
118                     unsigned DestReg, int FI,
119                     const TargetRegisterClass *RC,
120                     const TargetRegisterInfo *TRI) const {
121  DebugLoc DL;
122  if (I != MBB.end()) DL = I->getDebugLoc();
123  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
124  unsigned Opc = 0;
125
126  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
127    Opc = Mips::LwRxSpImmX16;
128  assert(Opc && "Register class not handled!");
129  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
130    .addMemOperand(MMO);
131}
132
133bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
134  MachineBasicBlock &MBB = *MI->getParent();
135  switch(MI->getDesc().getOpcode()) {
136  default:
137    return false;
138  case Mips::BteqzT8CmpX16:
139    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::CmpRxRy16);
140    break;
141  case Mips::BteqzT8CmpiX16:
142    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
143                           Mips::CmpiRxImm16, Mips::CmpiRxImmX16);
144    break;
145  case Mips::BteqzT8SltX16:
146    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltRxRy16);
147    break;
148  case Mips::BteqzT8SltiX16:
149    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
150                           Mips::SltiRxImm16, Mips::SltiRxImmX16);
151    break;
152  case Mips::BteqzT8SltuX16:
153    // TBD: figure out a way to get this or remove the instruction
154    // altogether.
155    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltuRxRy16);
156    break;
157  case Mips::BteqzT8SltiuX16:
158    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
159                           Mips::SltiuRxImm16, Mips::SltiuRxImmX16);
160    break;
161  case Mips::BtnezT8CmpX16:
162    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16);
163    break;
164  case Mips::BtnezT8CmpiX16:
165    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
166                           Mips::CmpiRxImm16, Mips::CmpiRxImmX16);
167    break;
168  case Mips::BtnezT8SltX16:
169    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltRxRy16);
170    break;
171  case Mips::BtnezT8SltiX16:
172    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
173                           Mips::SltiRxImm16, Mips::SltiRxImmX16);
174    break;
175  case Mips::BtnezT8SltuX16:
176    // TBD: figure out a way to get this or remove the instruction
177    // altogether.
178    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltuRxRy16);
179    break;
180  case Mips::BtnezT8SltiuX16:
181    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
182                           Mips::SltiuRxImm16, Mips::SltiuRxImmX16);
183    break;
184  case Mips::RetRA16:
185    ExpandRetRA16(MBB, MI, Mips::JrcRa16);
186    break;
187  }
188
189  MBB.erase(MI);
190  return true;
191}
192
193/// GetOppositeBranchOpc - Return the inverse of the specified
194/// opcode, e.g. turning BEQ to BNE.
195unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
196  switch (Opc) {
197  default:  llvm_unreachable("Illegal opcode!");
198  case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
199  case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
200  case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
201  case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
202  case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
203  case Mips::BtnezX16: return Mips::BteqzX16;
204  case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
205  case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
206  case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
207  case Mips::BteqzX16: return Mips::BtnezX16;
208  case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
209  case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
210  case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
211  case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
212  case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
213  case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
214  }
215  assert(false && "Implement this function.");
216  return 0;
217}
218
219// Adjust SP by FrameSize bytes. Save RA, S0, S1
220void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
221                    MachineBasicBlock &MBB,
222                    MachineBasicBlock::iterator I) const {
223  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
224  if (!NeverUseSaveRestore) {
225    if (isUInt<11>(FrameSize))
226      BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
227    else {
228      int Base = 2040; // should create template function like isUInt that
229                       // returns largest possible n bit unsigned integer
230      int64_t Remainder = FrameSize - Base;
231      BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
232      if (isInt<16>(-Remainder))
233        BuildAddiuSpImm(MBB, I, -Remainder);
234      else
235        adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
236    }
237
238  }
239  else {
240    //
241    // sw ra, -4[sp]
242    // sw s1, -8[sp]
243    // sw s0, -12[sp]
244
245    MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
246                                       Mips::RA);
247    MIB1.addReg(Mips::SP);
248    MIB1.addImm(-4);
249    MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
250                                       Mips::S1);
251    MIB2.addReg(Mips::SP);
252    MIB2.addImm(-8);
253    MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
254                                       Mips::S0);
255    MIB3.addReg(Mips::SP);
256    MIB3.addImm(-12);
257    adjustStackPtrBig(SP, -FrameSize, MBB, I, Mips::V0, Mips::V1);
258  }
259}
260
261// Adjust SP by FrameSize bytes. Restore RA, S0, S1
262void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
263                                   MachineBasicBlock &MBB,
264                                   MachineBasicBlock::iterator I) const {
265  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
266  if (!NeverUseSaveRestore) {
267    if (isUInt<11>(FrameSize))
268      BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
269    else {
270      int Base = 2040; // should create template function like isUInt that
271                       // returns largest possible n bit unsigned integer
272      int64_t Remainder = FrameSize - Base;
273      if (isInt<16>(Remainder))
274        BuildAddiuSpImm(MBB, I, Remainder);
275      else
276        adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
277      BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
278    }
279  }
280  else {
281    adjustStackPtrBig(SP, FrameSize, MBB, I, Mips::A0, Mips::A1);
282    // lw ra, -4[sp]
283    // lw s1, -8[sp]
284    // lw s0, -12[sp]
285    MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
286                                       Mips::A0);
287    MIB1.addReg(Mips::SP);
288    MIB1.addImm(-4);
289    MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
290                                       Mips::RA);
291     MIB0.addReg(Mips::A0);
292    MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
293                                       Mips::S1);
294    MIB2.addReg(Mips::SP);
295    MIB2.addImm(-8);
296    MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
297                                       Mips::S0);
298    MIB3.addReg(Mips::SP);
299    MIB3.addImm(-12);
300  }
301
302}
303
304// Adjust SP by Amount bytes where bytes can be up to 32bit number.
305// This can only be called at times that we know that there is at least one free
306// register.
307// This is clearly safe at prologue and epilogue.
308//
309void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
310                                        MachineBasicBlock &MBB,
311                                        MachineBasicBlock::iterator I,
312                                        unsigned Reg1, unsigned Reg2) const {
313  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
314//  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
315//  unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
316//  unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
317  //
318  // li reg1, constant
319  // move reg2, sp
320  // add reg1, reg1, reg2
321  // move sp, reg1
322  //
323  //
324  MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
325  MIB1.addImm(Amount);
326  MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
327  MIB2.addReg(Mips::SP, RegState::Kill);
328  MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
329  MIB3.addReg(Reg1);
330  MIB3.addReg(Reg2, RegState::Kill);
331  MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
332                                                     Mips::SP);
333  MIB4.addReg(Reg1, RegState::Kill);
334}
335
336void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
337                    MachineBasicBlock &MBB,
338                    MachineBasicBlock::iterator I) const {
339   assert(false && "adjust stack pointer amount exceeded");
340}
341
342/// Adjust SP by Amount bytes.
343void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
344                                     MachineBasicBlock &MBB,
345                                     MachineBasicBlock::iterator I) const {
346  if (isInt<16>(Amount))  // need to change to addiu sp, ....and isInt<16>
347    BuildAddiuSpImm(MBB, I, Amount);
348  else
349    adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
350}
351
352/// This function generates the sequence of instructions needed to get the
353/// result of adding register REG and immediate IMM.
354unsigned
355Mips16InstrInfo::loadImmediate(unsigned FrameReg,
356                               int64_t Imm, MachineBasicBlock &MBB,
357                               MachineBasicBlock::iterator II, DebugLoc DL,
358                               unsigned &NewImm) const {
359  //
360  // given original instruction is:
361  // Instr rx, T[offset] where offset is too big.
362  //
363  // lo = offset & 0xFFFF
364  // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
365  //
366  // let T = temporary register
367  // li T, hi
368  // shl T, 16
369  // add T, Rx, T
370  //
371  RegScavenger rs;
372  int32_t lo = Imm & 0xFFFF;
373  int32_t hi = ((Imm >> 16) + (lo >> 15)) & 0xFFFF;
374  NewImm = lo;
375  unsigned Reg =0;
376  unsigned SpReg = 0;
377  rs.enterBasicBlock(&MBB);
378  rs.forward(II);
379  //
380  // we use T0 for the first register, if we need to save something away.
381  // we use T1 for the second register, if we need to save something away.
382  //
383  unsigned FirstRegSaved =0, SecondRegSaved=0;
384  unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
385
386  Reg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
387  if (Reg == 0) {
388    FirstRegSaved = Reg = Mips::V0;
389    FirstRegSavedTo = Mips::T0;
390    copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
391  }
392  else
393    rs.setUsed(Reg);
394  BuildMI(MBB, II, DL, get(Mips::LiRxImmX16), Reg).addImm(hi);
395  BuildMI(MBB, II, DL, get(Mips::SllX16), Reg).addReg(Reg).
396    addImm(16);
397  if (FrameReg == Mips::SP) {
398    SpReg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
399    if (SpReg == 0) {
400      if (Reg != Mips::V1) {
401        SecondRegSaved = SpReg = Mips::V1;
402        SecondRegSavedTo = Mips::T1;
403      }
404      else {
405        SecondRegSaved = SpReg = Mips::V0;
406        SecondRegSavedTo = Mips::T0;
407      }
408      copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
409    }
410    else
411      rs.setUsed(SpReg);
412
413    copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
414    BuildMI(MBB, II, DL, get(Mips::  AdduRxRyRz16), Reg).addReg(SpReg)
415      .addReg(Reg);
416  }
417  else
418    BuildMI(MBB, II, DL, get(Mips::  AdduRxRyRz16), Reg).addReg(FrameReg)
419      .addReg(Reg, RegState::Kill);
420  if (FirstRegSaved || SecondRegSaved) {
421    II = llvm::next(II);
422    if (FirstRegSaved)
423      copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
424    if (SecondRegSaved)
425      copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
426  }
427  return Reg;
428}
429
430unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
431  return (Opc == Mips::BeqzRxImmX16   || Opc == Mips::BimmX16  ||
432          Opc == Mips::BnezRxImmX16   || Opc == Mips::BteqzX16 ||
433          Opc == Mips::BteqzT8CmpX16  || Opc == Mips::BteqzT8CmpiX16 ||
434          Opc == Mips::BteqzT8SltX16  || Opc == Mips::BteqzT8SltuX16  ||
435          Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
436          Opc == Mips::BtnezX16       || Opc == Mips::BtnezT8CmpX16 ||
437          Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
438          Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
439          Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
440}
441
442void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
443                                  MachineBasicBlock::iterator I,
444                                  unsigned Opc) const {
445  BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
446}
447
448
449void Mips16InstrInfo::ExpandFEXT_T8I816_ins(
450  MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
451  unsigned BtOpc, unsigned CmpOpc) const {
452  unsigned regX = I->getOperand(0).getReg();
453  unsigned regY = I->getOperand(1).getReg();
454  MachineBasicBlock *target = I->getOperand(2).getMBB();
455  BuildMI(MBB, I, I->getDebugLoc(), get(CmpOpc)).addReg(regX).addReg(regY);
456  BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target);
457
458}
459
460void Mips16InstrInfo::ExpandFEXT_T8I8I16_ins(
461  MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
462  unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc) const {
463  unsigned regX = I->getOperand(0).getReg();
464  int64_t imm = I->getOperand(1).getImm();
465  MachineBasicBlock *target = I->getOperand(2).getMBB();
466  unsigned CmpOpc;
467  if (isUInt<8>(imm))
468    CmpOpc = CmpiOpc;
469  else if (isUInt<16>(imm))
470    CmpOpc = CmpiXOpc;
471  else
472    llvm_unreachable("immediate field not usable");
473  BuildMI(MBB, I, I->getDebugLoc(), get(CmpOpc)).addReg(regX).addImm(imm);
474  BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target);
475}
476
477const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
478  if (validSpImm8(Imm))
479    return get(Mips::AddiuSpImm16);
480  else
481    return get(Mips::AddiuSpImmX16);
482}
483
484void Mips16InstrInfo::BuildAddiuSpImm
485  (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
486  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
487  BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
488}
489
490const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
491  return new Mips16InstrInfo(TM);
492}
493