Mips64InstrInfo.td revision 68698cc20d7e1fa1b45a30e7c25313796f40d5c6 
1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes Mips64 instructions.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Mips Operand, Complex Patterns and Transformations Definitions.
16//===----------------------------------------------------------------------===//
17
18// Instruction operand types
19def shamt_64       : Operand<i64>;
20
21// Unsigned Operand
22def uimm16_64      : Operand<i64> {
23  let PrintMethod = "printUnsignedImm";
24}
25
26// Transformation Function - get Imm - 32.
27def Subtract32 : SDNodeXForm<imm, [{
28  return getI32Imm((unsigned)N->getZExtValue() - 32);
29}]>;
30
31// shamt field must fit in 5 bits.
32def immZExt5_64 : ImmLeaf<i64, [{return Imm == (Imm & 0x1f);}]>;
33
34// imm32_63 predicate - True if imm is in range [32, 63].
35def imm32_63 : ImmLeaf<i32,
36                       [{return (int32_t)Imm >= 32 && (int32_t)Imm < 64;}],
37                       Subtract32>;
38
39//===----------------------------------------------------------------------===//
40// Instructions specific format
41//===----------------------------------------------------------------------===//
42// Shifts
43// 64-bit shift instructions.
44class shift_rotate_imm64<bits<6> func, bits<5> isRotate, string instr_asm,
45                         SDNode OpNode>:
46  shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt,
47                   CPU64Regs>;
48
49class shift_rotate_imm64_32<bits<6> func, bits<5> isRotate, string instr_asm,
50                            SDNode OpNode>:
51  shift_rotate_imm<func, isRotate, instr_asm, OpNode, imm32_63, shamt,
52                   CPU64Regs>;
53
54// Mul, Div
55class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>:
56  Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
57class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
58  Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
59
60//===----------------------------------------------------------------------===//
61// Instruction definition
62//===----------------------------------------------------------------------===//
63
64/// Arithmetic Instructions (ALU Immediate)
65def DADDiu   : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16,
66                           CPU64Regs>;
67def DANDi    : ArithLogicI<0x0c, "andi", and, uimm16_64, immZExt16, CPU64Regs>;
68def SLTi64   : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
69def SLTiu64  : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
70def ORi64    : ArithLogicI<0x0d, "ori", or, uimm16_64, immZExt16, CPU64Regs>;
71def XORi64   : ArithLogicI<0x0e, "xori", xor, uimm16_64, immZExt16, CPU64Regs>;
72
73/// Arithmetic Instructions (3-Operand, R-Type)
74def DADDu    : ArithLogicR<0x00, 0x2d, "daddu", add, IIAlu, CPU64Regs, 1>;
75def DSUBu    : ArithLogicR<0x00, 0x2f, "dsubu", sub, IIAlu, CPU64Regs>;
76def SLT64    : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>;
77def SLTu64   : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>;
78def AND64    : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPU64Regs, 1>;
79def OR64     : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPU64Regs, 1>;
80def XOR64    : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>;
81def NOR64    : LogicNOR<0x00, 0x27, "nor", CPU64Regs>;
82
83/// Shift Instructions
84def DSLL     : shift_rotate_imm64<0x38, 0x00, "dsll", shl>;
85def DSRL     : shift_rotate_imm64<0x3a, 0x00, "dsrl", srl>;
86def DSRA     : shift_rotate_imm64<0x3b, 0x00, "dsra", sra>;
87def DSLL32   : shift_rotate_imm64_32<0x3c, 0x00, "dsll32", shl>;
88def DSRL32   : shift_rotate_imm64_32<0x3e, 0x00, "dsrl32", srl>;
89def DSRA32   : shift_rotate_imm64_32<0x3f, 0x00, "dsra32", sra>;
90def DSLLV    : shift_rotate_reg<0x24, 0x00, "dsllv", shl, CPU64Regs>;
91def DSRLV    : shift_rotate_reg<0x26, 0x00, "dsrlv", srl, CPU64Regs>;
92def DSRAV    : shift_rotate_reg<0x27, 0x00, "dsrav", sra, CPU64Regs>;
93
94// Rotate Instructions
95let Predicates = [HasMips64r2] in {
96  def DROTR    : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>;
97  def DROTR32  : shift_rotate_imm64_32<0x3e, 0x01, "drotr32", rotr>;
98  def DROTRV   : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>;
99}
100
101/// Load and Store Instructions
102///  aligned 
103defm LB64    : LoadM64<0x20, "lb",  sextloadi8>;
104defm LBu64   : LoadM64<0x24, "lbu", zextloadi8>;
105defm LH64    : LoadM64<0x21, "lh",  sextloadi16_a>;
106defm LHu64   : LoadM64<0x25, "lhu", zextloadi16_a>;
107defm LW64    : LoadM64<0x23, "lw",  sextloadi32_a>;
108defm LWu64   : LoadM64<0x27, "lwu", zextloadi32_a>;
109defm SB64    : StoreM64<0x28, "sb", truncstorei8>;
110defm SH64    : StoreM64<0x29, "sh", truncstorei16_a>;
111defm SW64    : StoreM64<0x2b, "sw", truncstorei32_a>;
112defm LD      : LoadM64<0x37, "ld",  load_a>;
113defm SD      : StoreM64<0x3f, "sd", store_a>;
114
115///  unaligned
116defm ULH64     : LoadM64<0x21, "ulh",  sextloadi16_u, 1>;
117defm ULHu64    : LoadM64<0x25, "ulhu", zextloadi16_u, 1>;
118defm ULW64     : LoadM64<0x23, "ulw",  sextloadi32_u, 1>;
119defm USH64     : StoreM64<0x29, "ush", truncstorei16_u, 1>;
120defm USW64     : StoreM64<0x2b, "usw", truncstorei32_u, 1>;
121defm ULD       : LoadM64<0x37, "uld",  load_u, 1>;
122defm USD       : StoreM64<0x3f, "usd", store_u, 1>;
123
124/// Jump and Branch Instructions
125def BEQ64  : CBranch<0x04, "beq", seteq, CPU64Regs>;
126def BNE64  : CBranch<0x05, "bne", setne, CPU64Regs>;
127def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>;
128def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>;
129def BLEZ64 : CBranchZero<0x07, 0, "blez", setle, CPU64Regs>;
130def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>;
131
132/// Multiply and Divide Instructions.
133def DMULT    : Mult64<0x1c, "dmult", IIImul>;
134def DMULTu   : Mult64<0x1d, "dmultu", IIImul>;
135def DSDIV    : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
136def DUDIV    : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>;
137
138def MTHI64 : MoveToLOHI<0x11, "mthi", CPU64Regs, [HI64]>;
139def MTLO64 : MoveToLOHI<0x13, "mtlo", CPU64Regs, [LO64]>;
140def MFHI64 : MoveFromLOHI<0x10, "mfhi", CPU64Regs, [HI64]>;
141def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>;
142
143/// Count Leading
144def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>;
145def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>;
146
147//===----------------------------------------------------------------------===//
148//  Arbitrary patterns that map to one or more instructions
149//===----------------------------------------------------------------------===//
150
151// Small immediates
152def : Pat<(i64 immSExt16:$in),
153          (DADDiu ZERO_64, imm:$in)>;
154def : Pat<(i64 immZExt16:$in),
155          (ORi64 ZERO_64, imm:$in)>;
156
157// zextloadi32_u
158def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>,
159      Requires<[IsN64]>;
160def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>,
161      Requires<[NotN64]>;
162
163// hi/lo relocs
164def : Pat<(i64 (MipsLo tglobaladdr:$in)), (DADDiu ZERO_64, tglobaladdr:$in)>;
165
166defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
167                  ZERO_64>;
168
169// setcc patterns
170defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
171defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
172defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
173defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
174defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;
175
176// truncate
177def : Pat<(i32 (trunc CPU64Regs:$src)),
178          (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, Requires<[IsN64]>;
179 
180