Mips64InstrInfo.td revision 71ab7a79a74ebb3dad1aac02c5a5c7c2c20b547f
12a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 22a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// 32a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// The LLVM Compiler Infrastructure 42a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// 52a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// This file is distributed under the University of Illinois Open Source 62a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// License. See LICENSE.TXT for details. 72a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// 82a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)//===----------------------------------------------------------------------===// 97d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles)// 103551c9c881056c480085172ff9840cab31610854Torne (Richard Coles)// This file describes Mips64 instructions. 112a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// 122a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)//===----------------------------------------------------------------------===// 132a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 142a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)//===----------------------------------------------------------------------===// 152a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// Mips Operand, Complex Patterns and Transformations Definitions. 1690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)//===----------------------------------------------------------------------===// 17ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch 182a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// Instruction operand types 1990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)def shamt_64 : Operand<i64>; 202a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 215d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)// Unsigned Operand 2290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)def uimm16_64 : Operand<i64> { 23b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) let PrintMethod = "printUnsignedImm"; 242a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)} 25f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) 261e9bf3e0803691d0a228da41fc608347b6db4340Torne (Richard Coles)// Transformation Function - get Imm - 32. 27a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)def Subtract32 : SDNodeXForm<imm, [{ 285d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return getImm(N, (unsigned)N->getZExtValue() - 32); 292a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)}]>; 302a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 312a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// shamt must fit in 6 bits. 322a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 332a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 342a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)//===----------------------------------------------------------------------===// 352a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// Instructions specific format 362a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)//===----------------------------------------------------------------------===// 372a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)let DecoderNamespace = "Mips64" in { 382a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 392a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)multiclass Atomic2Ops64<PatFrag Op> { 402a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>, 412a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) Requires<[NotN64, HasStdEnc]>; 422a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>, 432a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) Requires<[IsN64, HasStdEnc]> { 442a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) let isCodeGenOnly = 1; 452385ea399aae016c0806a4f9ef3c9cfe3d2a39dfBen Murdoch } 462a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)} 475f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 485f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)multiclass AtomicCmpSwap64<PatFrag Op> { 495f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) def NAME : AtomicCmpSwap<Op, CPU64Regs, CPURegs>, 502a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) Requires<[NotN64, HasStdEnc]>; 512a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>, 522a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) Requires<[IsN64, HasStdEnc]> { 532a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) let isCodeGenOnly = 1; 542a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 55f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles)} 56f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles)} 575d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)let usesCustomInserter = 1, Predicates = [HasStdEnc], 585d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) DecoderNamespace = "Mips64" in { 595d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>; 60a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>; 61a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>; 622a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>; 63868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>; 6490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>; 652a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>; 662a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>; 672a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)} 682a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 69f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles)//===----------------------------------------------------------------------===// 70f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles)// Instruction definition 712a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)//===----------------------------------------------------------------------===// 722a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)let DecoderNamespace = "Mips64" in { 732a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)/// Arithmetic Instructions (ALU Immediate) 742a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)def DADDi : ArithLogicI<"daddi", simm16_64, CPU64Regs>, ADDI_FM<0x18>; 752a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64Regs, immSExt16, add>, 7603b57e008b61dfcb1fbad3aea950ae0e001748b0Torne (Richard Coles) ADDI_FM<0x19>, IsAsCheapAsAMove; 7703b57e008b61dfcb1fbad3aea950ae0e001748b0Torne (Richard Coles)def DANDi : ArithLogicI<"andi", uimm16_64, CPU64Regs, immZExt16, and>, 7803b57e008b61dfcb1fbad3aea950ae0e001748b0Torne (Richard Coles) ADDI_FM<0xc>; 792a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>, 802a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) SLTI_FM<0xa>; 812a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>, 822a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) SLTI_FM<0xb>; 832a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64Regs, immZExt16, or>, 842a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) ADDI_FM<0xd>; 852a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64Regs, immZExt16, xor>, 862a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) ADDI_FM<0xe>; 872a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM; 887d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) 897d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles)/// Arithmetic Instructions (3-Operand, R-Type) 907d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles)def DADD : ArithLogicR<"dadd", CPU64Regs>, ADD_FM<0, 0x2c>; 9158537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles)def DADDu : ArithLogicR<"daddu", CPU64Regs, 1, IIAlu, add>, ADD_FM<0, 0x2d>; 9258537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles)def DSUBu : ArithLogicR<"dsubu", CPU64Regs, 0, IIAlu, sub>, ADD_FM<0, 0x2f>; 9358537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles)def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>; 94b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles)def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>; 95b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles)def AND64 : ArithLogicR<"and", CPU64Regs, 1, IIAlu, and>, ADD_FM<0, 0x24>; 9690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)def OR64 : ArithLogicR<"or", CPU64Regs, 1, IIAlu, or>, ADD_FM<0, 0x25>; 9790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)def XOR64 : ArithLogicR<"xor", CPU64Regs, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 98ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdochdef NOR64 : LogicNOR<"nor", CPU64Regs>, ADD_FM<0, 0x27>; 99ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch 10090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)/// Shift Instructions 10190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)def DSLL : shift_rotate_imm<"dsll", shamt, CPU64Regs, shl, immZExt6>, 10290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) SRA_FM<0x38, 0>; 103ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdochdef DSRL : shift_rotate_imm<"dsrl", shamt, CPU64Regs, srl, immZExt6>, 1040529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch SRA_FM<0x3a, 0>; 1050529e5d033099cbfc42635f6f6183833b09dff6eBen Murdochdef DSRA : shift_rotate_imm<"dsra", shamt, CPU64Regs, sra, immZExt6>, 106ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch SRA_FM<0x3b, 0>; 107ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdochdef DSLLV : shift_rotate_reg<"dsllv", CPU64Regs, shl>, SRLV_FM<0x14, 0>; 108ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdochdef DSRLV : shift_rotate_reg<"dsrlv", CPU64Regs, srl>, SRLV_FM<0x16, 0>; 109ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdochdef DSRAV : shift_rotate_reg<"dsrav", CPU64Regs, sra>, SRLV_FM<0x17, 0>; 1101e9bf3e0803691d0a228da41fc608347b6db4340Torne (Richard Coles)def DSLL32 : shift_rotate_imm<"dsll32", shamt, CPU64Regs>, SRA_FM<0x3c, 0>; 1115f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)def DSRL32 : shift_rotate_imm<"dsrl32", shamt, CPU64Regs>, SRA_FM<0x3e, 0>; 1125f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)def DSRA32 : shift_rotate_imm<"dsra32", shamt, CPU64Regs>, SRA_FM<0x3f, 0>; 1135f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)} 1145f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// Rotate Instructions 1155d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)let Predicates = [HasMips64r2, HasStdEnc], 1165d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) DecoderNamespace = "Mips64" in { 1175d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) def DROTR : shift_rotate_imm<"drotr", shamt, CPU64Regs, rotr, immZExt6>, 1181e9bf3e0803691d0a228da41fc608347b6db4340Torne (Richard Coles) SRA_FM<0x3a, 1>; 11946d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) def DROTRV : shift_rotate_reg<"drotrv", CPU64Regs, rotr>, SRLV_FM<0x16, 1>; 12046d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles)} 12146d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) 1222a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)let DecoderNamespace = "Mips64" in { 1232a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)/// Load and Store Instructions 1242a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)/// aligned 1252a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)defm LB64 : LoadM<"lb", CPU64Regs, sextloadi8>, LW_FM<0x20>; 1262a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8>, LW_FM<0x24>; 1275d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)defm LH64 : LoadM<"lh", CPU64Regs, sextloadi16>, LW_FM<0x21>; 1282a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16>, LW_FM<0x25>; 1292a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)defm LW64 : LoadM<"lw", CPU64Regs, sextloadi32>, LW_FM<0x23>; 1305d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32>, LW_FM<0x27>; 131defm SB64 : StoreM<"sb", CPU64Regs, truncstorei8>, LW_FM<0x28>; 132defm SH64 : StoreM<"sh", CPU64Regs, truncstorei16>, LW_FM<0x29>; 133defm SW64 : StoreM<"sw", CPU64Regs, truncstorei32>, LW_FM<0x2b>; 134defm LD : LoadM<"ld", CPU64Regs, load>, LW_FM<0x37>; 135defm SD : StoreM<"sd", CPU64Regs, store>, LW_FM<0x3f>; 136 137/// load/store left/right 138let isCodeGenOnly = 1 in { 139 defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>; 140 defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>; 141 defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>; 142 defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>; 143} 144defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>; 145defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>; 146defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>; 147defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>; 148 149/// Load-linked, Store-conditional 150let Predicates = [NotN64, HasStdEnc] in { 151 def LLD : LLBase<"lld", CPU64Regs, mem>, LW_FM<0x34>; 152 def SCD : SCBase<"scd", CPU64Regs, mem>, LW_FM<0x3c>; 153} 154 155let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in { 156 def LLD_P8 : LLBase<"lld", CPU64Regs, mem64>, LW_FM<0x34>; 157 def SCD_P8 : SCBase<"scd", CPU64Regs, mem64>, LW_FM<0x3c>; 158} 159 160/// Jump and Branch Instructions 161def JR64 : IndirectBranch<CPU64Regs>, MTLO_FM<8>; 162def BEQ64 : CBranch<"beq", seteq, CPU64Regs>, BEQ_FM<4>; 163def BNE64 : CBranch<"bne", setne, CPU64Regs>, BEQ_FM<5>; 164def BGEZ64 : CBranchZero<"bgez", setge, CPU64Regs>, BGEZ_FM<1, 1>; 165def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64Regs>, BGEZ_FM<7, 0>; 166def BLEZ64 : CBranchZero<"blez", setle, CPU64Regs>, BGEZ_FM<6, 0>; 167def BLTZ64 : CBranchZero<"bltz", setlt, CPU64Regs>, BGEZ_FM<1, 0>; 168} 169let DecoderNamespace = "Mips64" in 170def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM; 171def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 172 173let DecoderNamespace = "Mips64" in { 174/// Multiply and Divide Instructions. 175def DMULT : Mult<"dmult", IIImul, CPU64Regs, [HI64, LO64]>, MULT_FM<0, 0x1c>; 176def DMULTu : Mult<"dmultu", IIImul, CPU64Regs, [HI64, LO64]>, MULT_FM<0, 0x1d>; 177def DSDIV : Div<MipsDivRem, "ddiv", IIIdiv, CPU64Regs, [HI64, LO64]>, 178 MULT_FM<0, 0x1e>; 179def DUDIV : Div<MipsDivRemU, "ddivu", IIIdiv, CPU64Regs, [HI64, LO64]>, 180 MULT_FM<0, 0x1f>; 181 182def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>; 183def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>; 184def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>; 185def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>; 186 187/// Sign Ext In Register Instructions. 188def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10, 0x20>; 189def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18, 0x20>; 190 191/// Count Leading 192def DCLZ : CountLeading0<"dclz", CPU64Regs>, CLO_FM<0x24>; 193def DCLO : CountLeading1<"dclo", CPU64Regs>, CLO_FM<0x25>; 194 195/// Double Word Swap Bytes/HalfWords 196def DSBH : SubwordSwap<"dsbh", CPU64Regs>, SEB_FM<2, 0x24>; 197def DSHD : SubwordSwap<"dshd", CPU64Regs>, SEB_FM<5, 0x24>; 198 199def LEA_ADDiu64 : EffectiveAddress<"daddiu", CPU64Regs, mem_ea_64>, LW_FM<0x19>; 200 201} 202let DecoderNamespace = "Mips64" in { 203def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>, RDHWR_FM; 204 205def DEXT : ExtBase<"dext", CPU64Regs>, EXT_FM<3>; 206let Pattern = []<dag> in { 207 def DEXTU : ExtBase<"dextu", CPU64Regs>, EXT_FM<2>; 208 def DEXTM : ExtBase<"dextm", CPU64Regs>, EXT_FM<1>; 209} 210def DINS : InsBase<"dins", CPU64Regs>, EXT_FM<7>; 211let Pattern = []<dag> in { 212 def DINSU : InsBase<"dinsu", CPU64Regs>, EXT_FM<6>; 213 def DINSM : InsBase<"dinsm", CPU64Regs>, EXT_FM<5>; 214} 215 216let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 217 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 218 "dsll\t$rd, $rt, 32", [], IIAlu>; 219 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 220 "sll\t$rd, $rt, 0", [], IIAlu>; 221 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), 222 "sll\t$rd, $rt, 0", [], IIAlu>; 223} 224} 225//===----------------------------------------------------------------------===// 226// Arbitrary patterns that map to one or more instructions 227//===----------------------------------------------------------------------===// 228 229// extended loads 230let Predicates = [NotN64, HasStdEnc] in { 231 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 232 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 233 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 234 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; 235} 236let Predicates = [IsN64, HasStdEnc] in { 237 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>; 238 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>; 239 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>; 240 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>; 241} 242 243// hi/lo relocs 244def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 245def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 246def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 247def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 248def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 249def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>; 250 251def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 252def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>; 253def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 254def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 255def : MipsPat<(MipsLo tglobaltlsaddr:$in), 256 (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 257def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>; 258 259def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)), 260 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>; 261def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)), 262 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>; 263def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)), 264 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>; 265def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)), 266 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>; 267def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)), 268 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>; 269 270def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>; 271def : WrapperPat<tconstpool, DADDiu, CPU64Regs>; 272def : WrapperPat<texternalsym, DADDiu, CPU64Regs>; 273def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>; 274def : WrapperPat<tjumptable, DADDiu, CPU64Regs>; 275def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>; 276 277defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 278 ZERO_64>; 279 280// setcc patterns 281defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>; 282defm : SetlePats<CPU64Regs, SLT64, SLTu64>; 283defm : SetgtPats<CPU64Regs, SLT64, SLTu64>; 284defm : SetgePats<CPU64Regs, SLT64, SLTu64>; 285defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>; 286 287// truncate 288def : MipsPat<(i32 (trunc CPU64Regs:$src)), 289 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, 290 Requires<[IsN64, HasStdEnc]>; 291 292// 32-to-64-bit extension 293def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 294def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; 295def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 296 297// Sign extend in register 298def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)), 299 (SLL64_64 CPU64Regs:$src)>; 300 301// bswap MipsPattern 302def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>; 303 304//===----------------------------------------------------------------------===// 305// Instruction aliases 306//===----------------------------------------------------------------------===// 307def : InstAlias<"move $dst,$src", (DADD CPU64Regs:$dst,CPU64Regs:$src,ZERO_64)>; 308 309/// Move between CPU and coprocessor registers 310let DecoderNamespace = "Mips64" in { 311def MFC0_3OP64 : MFC3OP<(outs CPU64Regs:$rt), (ins CPU64Regs:$rd, uimm16:$sel), 312 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>; 313def MTC0_3OP64 : MFC3OP<(outs CPU64Regs:$rd, uimm16:$sel), (ins CPU64Regs:$rt), 314 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>; 315def MFC2_3OP64 : MFC3OP<(outs CPU64Regs:$rt), (ins CPU64Regs:$rd, uimm16:$sel), 316 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>; 317def MTC2_3OP64 : MFC3OP<(outs CPU64Regs:$rd, uimm16:$sel), (ins CPU64Regs:$rt), 318 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>; 319def DMFC0_3OP64 : MFC3OP<(outs CPU64Regs:$rt), (ins CPU64Regs:$rd, uimm16:$sel), 320 "dmfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 1>; 321def DMTC0_3OP64 : MFC3OP<(outs CPU64Regs:$rd, uimm16:$sel), (ins CPU64Regs:$rt), 322 "dmtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 5>; 323def DMFC2_3OP64 : MFC3OP<(outs CPU64Regs:$rt), (ins CPU64Regs:$rd, uimm16:$sel), 324 "dmfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 1>; 325def DMTC2_3OP64 : MFC3OP<(outs CPU64Regs:$rd, uimm16:$sel), (ins CPU64Regs:$rt), 326 "dmtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 5>; 327} 328// Two operand (implicit 0 selector) versions: 329def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 330def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 331def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 332def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 333def : InstAlias<"dmfc0 $rt, $rd", 334 (DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 335def : InstAlias<"dmtc0 $rt, $rd", 336 (DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 337def : InstAlias<"dmfc2 $rt, $rd", 338 (DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 339def : InstAlias<"dmtc2 $rt, $rd", 340 (DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 341 342