Mips64InstrInfo.td revision aa5b393c69cf24d47a5727d15584f3daeba1aead
1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips64 instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Mips Operand, Complex Patterns and Transformations Definitions. 16//===----------------------------------------------------------------------===// 17 18// Instruction operand types 19def shamt_64 : Operand<i64>; 20 21// Unsigned Operand 22def uimm16_64 : Operand<i64> { 23 let PrintMethod = "printUnsignedImm"; 24} 25 26// Transformation Function - get Imm - 32. 27def Subtract32 : SDNodeXForm<imm, [{ 28 return getImm(N, (unsigned)N->getZExtValue() - 32); 29}]>; 30 31// shamt must fit in 6 bits. 32def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 33 34//===----------------------------------------------------------------------===// 35// Instructions specific format 36//===----------------------------------------------------------------------===// 37// Shifts 38// 64-bit shift instructions. 39let DecoderNamespace = "Mips64" in { 40class shift_rotate_imm64<bits<6> func, bits<5> isRotate, string instr_asm, 41 SDNode OpNode>: 42 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt6, shamt, 43 CPU64Regs>; 44 45// Mul, Div 46class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>: 47 Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; 48class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 49 Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; 50 51multiclass Atomic2Ops64<PatFrag Op, string Opstr> { 52 def #NAME# : Atomic2Ops<Op, Opstr, CPU64Regs, CPURegs>, 53 Requires<[NotN64, HasStandardEncoding]>; 54 def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>, 55 Requires<[IsN64, HasStandardEncoding]> { 56 let isCodeGenOnly = 1; 57 } 58} 59 60multiclass AtomicCmpSwap64<PatFrag Op, string Width> { 61 def #NAME# : AtomicCmpSwap<Op, Width, CPU64Regs, CPURegs>, 62 Requires<[NotN64, HasStandardEncoding]>; 63 def _P8 : AtomicCmpSwap<Op, Width, CPU64Regs, CPU64Regs>, 64 Requires<[IsN64, HasStandardEncoding]> { 65 let isCodeGenOnly = 1; 66 } 67} 68} 69let usesCustomInserter = 1, Predicates = [HasMips64, HasStandardEncoding], 70 DecoderNamespace = "Mips64" in { 71 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">; 72 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">; 73 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64, "load_and_64">; 74 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64, "load_or_64">; 75 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64, "load_xor_64">; 76 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64, "load_nand_64">; 77 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64, "swap_64">; 78 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64, "64">; 79} 80 81//===----------------------------------------------------------------------===// 82// Instruction definition 83//===----------------------------------------------------------------------===// 84let DecoderNamespace = "Mips64" in { 85/// Arithmetic Instructions (ALU Immediate) 86def DADDi : ArithOverflowI<0x18, "daddi", add, simm16_64, immSExt16, 87 CPU64Regs>; 88def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16, 89 CPU64Regs>; 90def DANDi : ArithLogicI<0x0c, "andi", and, uimm16_64, immZExt16, CPU64Regs>; 91def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>; 92def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>; 93def ORi64 : ArithLogicI<0x0d, "ori", or, uimm16_64, immZExt16, CPU64Regs>; 94def XORi64 : ArithLogicI<0x0e, "xori", xor, uimm16_64, immZExt16, CPU64Regs>; 95def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>; 96 97/// Arithmetic Instructions (3-Operand, R-Type) 98def DADD : ArithOverflowR<0x00, 0x2C, "dadd", IIAlu, CPU64Regs, 1>; 99def DADDu : ArithLogicR<0x00, 0x2d, "daddu", add, IIAlu, CPU64Regs, 1>; 100def DSUBu : ArithLogicR<0x00, 0x2f, "dsubu", sub, IIAlu, CPU64Regs>; 101def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>; 102def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>; 103def AND64 : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPU64Regs, 1>; 104def OR64 : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPU64Regs, 1>; 105def XOR64 : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>; 106def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>; 107 108/// Shift Instructions 109def DSLL : shift_rotate_imm64<0x38, 0x00, "dsll", shl>; 110def DSRL : shift_rotate_imm64<0x3a, 0x00, "dsrl", srl>; 111def DSRA : shift_rotate_imm64<0x3b, 0x00, "dsra", sra>; 112def DSLLV : shift_rotate_reg<0x14, 0x00, "dsllv", shl, CPU64Regs>; 113def DSRLV : shift_rotate_reg<0x16, 0x00, "dsrlv", srl, CPU64Regs>; 114def DSRAV : shift_rotate_reg<0x17, 0x00, "dsrav", sra, CPU64Regs>; 115let Pattern = []<dag> in { 116 def DSLL32 : shift_rotate_imm64<0x3c, 0x00, "dsll32", shl>; 117 def DSRL32 : shift_rotate_imm64<0x3e, 0x00, "dsrl32", srl>; 118 def DSRA32 : shift_rotate_imm64<0x3f, 0x00, "dsra32", sra>; 119} 120} 121// Rotate Instructions 122let Predicates = [HasMips64r2, HasStandardEncoding], 123 DecoderNamespace = "Mips64" in { 124 def DROTR : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>; 125 def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>; 126} 127 128let DecoderNamespace = "Mips64" in { 129/// Load and Store Instructions 130/// aligned 131defm LB64 : LoadM64<0x20, "lb", sextloadi8>; 132defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>; 133defm LH64 : LoadM64<0x21, "lh", sextloadi16>; 134defm LHu64 : LoadM64<0x25, "lhu", zextloadi16>; 135defm LW64 : LoadM64<0x23, "lw", sextloadi32>; 136defm LWu64 : LoadM64<0x27, "lwu", zextloadi32>; 137defm SB64 : StoreM64<0x28, "sb", truncstorei8>; 138defm SH64 : StoreM64<0x29, "sh", truncstorei16>; 139defm SW64 : StoreM64<0x2b, "sw", truncstorei32>; 140defm LD : LoadM64<0x37, "ld", load>; 141defm SD : StoreM64<0x3f, "sd", store>; 142 143/// load/store left/right 144let isCodeGenOnly = 1 in { 145 defm LWL64 : LoadLeftRightM64<0x22, "lwl", MipsLWL>; 146 defm LWR64 : LoadLeftRightM64<0x26, "lwr", MipsLWR>; 147 defm SWL64 : StoreLeftRightM64<0x2a, "swl", MipsSWL>; 148 defm SWR64 : StoreLeftRightM64<0x2e, "swr", MipsSWR>; 149} 150defm LDL : LoadLeftRightM64<0x1a, "ldl", MipsLDL>; 151defm LDR : LoadLeftRightM64<0x1b, "ldr", MipsLDR>; 152defm SDL : StoreLeftRightM64<0x2c, "sdl", MipsSDL>; 153defm SDR : StoreLeftRightM64<0x2d, "sdr", MipsSDR>; 154 155/// Load-linked, Store-conditional 156def LLD : LLBase<0x34, "lld", CPU64Regs, mem>, 157 Requires<[NotN64, HasStandardEncoding]>; 158def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>, 159 Requires<[IsN64, HasStandardEncoding]> { 160 let isCodeGenOnly = 1; 161} 162def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>, 163 Requires<[NotN64, HasStandardEncoding]>; 164def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, 165 Requires<[IsN64, HasStandardEncoding]> { 166 let isCodeGenOnly = 1; 167} 168 169/// Jump and Branch Instructions 170def JR64 : IndirectBranch<CPU64Regs>; 171def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>; 172def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>; 173def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>; 174def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>; 175def BLEZ64 : CBranchZero<0x06, 0, "blez", setle, CPU64Regs>; 176def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>; 177} 178let DecoderNamespace = "Mips64" in 179def JALR64 : JumpLinkReg<0x00, 0x09, "jalr", CPU64Regs>; 180 181let DecoderNamespace = "Mips64" in { 182/// Multiply and Divide Instructions. 183def DMULT : Mult64<0x1c, "dmult", IIImul>; 184def DMULTu : Mult64<0x1d, "dmultu", IIImul>; 185def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>; 186def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>; 187 188def MTHI64 : MoveToLOHI<0x11, "mthi", CPU64Regs, [HI64]>; 189def MTLO64 : MoveToLOHI<0x13, "mtlo", CPU64Regs, [LO64]>; 190def MFHI64 : MoveFromLOHI<0x10, "mfhi", CPU64Regs, [HI64]>; 191def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>; 192 193/// Sign Ext In Register Instructions. 194def SEB64 : SignExtInReg<0x10, "seb", i8, CPU64Regs>; 195def SEH64 : SignExtInReg<0x18, "seh", i16, CPU64Regs>; 196 197/// Count Leading 198def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>; 199def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>; 200 201/// Double Word Swap Bytes/HalfWords 202def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>; 203def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>; 204 205def LEA_ADDiu64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>; 206} 207let Uses = [SP_64], DecoderNamespace = "Mips64" in 208def DynAlloc64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>, 209 Requires<[IsN64, HasStandardEncoding]>; 210let DecoderNamespace = "Mips64" in { 211def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>; 212 213def DEXT : ExtBase<3, "dext", CPU64Regs>; 214let Pattern = []<dag> in { 215 def DEXTU : ExtBase<2, "dextu", CPU64Regs>; 216 def DEXTM : ExtBase<1, "dextm", CPU64Regs>; 217} 218def DINS : InsBase<7, "dins", CPU64Regs>; 219let Pattern = []<dag> in { 220 def DINSU : InsBase<6, "dinsu", CPU64Regs>; 221 def DINSM : InsBase<5, "dinsm", CPU64Regs>; 222} 223 224let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 225 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 226 "dsll\t$rd, $rt, 32", [], IIAlu>; 227 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 228 "sll\t$rd, $rt, 0", [], IIAlu>; 229 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), 230 "sll\t$rd, $rt, 0", [], IIAlu>; 231} 232} 233//===----------------------------------------------------------------------===// 234// Arbitrary patterns that map to one or more instructions 235//===----------------------------------------------------------------------===// 236 237// extended loads 238let Predicates = [NotN64, HasStandardEncoding] in { 239 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 240 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 241 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 242 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; 243} 244let Predicates = [IsN64, HasStandardEncoding] in { 245 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>; 246 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>; 247 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>; 248 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>; 249} 250 251// hi/lo relocs 252def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 253def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 254def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 255def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 256def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 257 258def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 259def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>; 260def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 261def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 262def : MipsPat<(MipsLo tglobaltlsaddr:$in), 263 (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 264 265def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)), 266 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>; 267def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)), 268 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>; 269def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)), 270 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>; 271def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)), 272 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>; 273def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)), 274 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>; 275 276def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>; 277def : WrapperPat<tconstpool, DADDiu, CPU64Regs>; 278def : WrapperPat<texternalsym, DADDiu, CPU64Regs>; 279def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>; 280def : WrapperPat<tjumptable, DADDiu, CPU64Regs>; 281def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>; 282 283defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 284 ZERO_64>; 285 286// setcc patterns 287defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>; 288defm : SetlePats<CPU64Regs, SLT64, SLTu64>; 289defm : SetgtPats<CPU64Regs, SLT64, SLTu64>; 290defm : SetgePats<CPU64Regs, SLT64, SLTu64>; 291defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>; 292 293// select MipsDynAlloc 294def : MipsPat<(MipsDynAlloc addr:$f), (DynAlloc64 addr:$f)>, 295 Requires<[IsN64, HasStandardEncoding]>; 296 297// truncate 298def : MipsPat<(i32 (trunc CPU64Regs:$src)), 299 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, 300 Requires<[IsN64, HasStandardEncoding]>; 301 302// 32-to-64-bit extension 303def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 304def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; 305def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 306 307// Sign extend in register 308def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)), 309 (SLL64_64 CPU64Regs:$src)>; 310 311// bswap MipsPattern 312def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>; 313 314//===----------------------------------------------------------------------===// 315// Instruction aliases 316//===----------------------------------------------------------------------===// 317def : InstAlias<"move $dst,$src", (DADD CPU64Regs:$dst,CPU64Regs:$src,ZERO_64)>; 318 319/// Move between CPU and coprocessor registers 320let DecoderNamespace = "Mips64" in { 321def MFC0_3OP64 : MFC3OP<0x10, 0, (outs CPU64Regs:$rt), 322 (ins CPU64Regs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">; 323def MTC0_3OP64 : MFC3OP<0x10, 4, (outs CPU64Regs:$rd, uimm16:$sel), 324 (ins CPU64Regs:$rt),"mtc0\t$rt, $rd, $sel">; 325def MFC2_3OP64 : MFC3OP<0x12, 0, (outs CPU64Regs:$rt), 326 (ins CPU64Regs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">; 327def MTC2_3OP64 : MFC3OP<0x12, 4, (outs CPU64Regs:$rd, uimm16:$sel), 328 (ins CPU64Regs:$rt),"mtc2\t$rt, $rd, $sel">; 329def DMFC0_3OP64 : MFC3OP<0x10, 1, (outs CPU64Regs:$rt), 330 (ins CPU64Regs:$rd, uimm16:$sel),"dmfc0\t$rt, $rd, $sel">; 331def DMTC0_3OP64 : MFC3OP<0x10, 5, (outs CPU64Regs:$rd, uimm16:$sel), 332 (ins CPU64Regs:$rt),"dmtc0\t$rt, $rd, $sel">; 333def DMFC2_3OP64 : MFC3OP<0x12, 1, (outs CPU64Regs:$rt), 334 (ins CPU64Regs:$rd, uimm16:$sel),"dmfc2\t$rt, $rd, $sel">; 335def DMTC2_3OP64 : MFC3OP<0x12, 5, (outs CPU64Regs:$rd, uimm16:$sel), 336 (ins CPU64Regs:$rt),"dmtc2\t$rt, $rd, $sel">; 337} 338// Two operand (implicit 0 selector) versions: 339def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 340def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 341def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 342def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 343def : InstAlias<"dmfc0 $rt, $rd", (DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 344def : InstAlias<"dmtc0 $rt, $rd", (DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 345def : InstAlias<"dmfc2 $rt, $rd", (DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 346def : InstAlias<"dmtc2 $rt, $rd", (DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 347 348