Mips64InstrInfo.td revision ee973147ac0aad6471f5506c3278654baec4d1c0
1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips64 instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Mips Operand, Complex Patterns and Transformations Definitions. 16//===----------------------------------------------------------------------===// 17 18// Instruction operand types 19def shamt_64 : Operand<i64>; 20 21// Unsigned Operand 22def uimm16_64 : Operand<i64> { 23 let PrintMethod = "printUnsignedImm"; 24} 25 26// Transformation Function - get Imm - 32. 27def Subtract32 : SDNodeXForm<imm, [{ 28 return getImm(N, (unsigned)N->getZExtValue() - 32); 29}]>; 30 31// shamt must fit in 6 bits. 32def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 33 34// Is a 32-bit int. 35def immSExt32 : ImmLeaf<i64, [{return isInt<32>(Imm);}]>; 36 37// Transformation Function - get the higher 16 bits. 38def HIGHER : SDNodeXForm<imm, [{ 39 return getImm(N, (N->getZExtValue() >> 32) & 0xFFFF); 40}]>; 41 42// Transformation Function - get the highest 16 bits. 43def HIGHEST : SDNodeXForm<imm, [{ 44 return getImm(N, (N->getZExtValue() >> 48) & 0xFFFF); 45}]>; 46 47//===----------------------------------------------------------------------===// 48// Instructions specific format 49//===----------------------------------------------------------------------===// 50// Shifts 51// 64-bit shift instructions. 52class shift_rotate_imm64<bits<6> func, bits<5> isRotate, string instr_asm, 53 SDNode OpNode>: 54 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt6, shamt, 55 CPU64Regs>; 56 57// Jump and Link (Call) 58let isCall=1, hasDelaySlot=1, 59 // All calls clobber the non-callee saved registers... 60 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, 61 K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in { 62 class JumpLink64<bits<6> op, string instr_asm>: 63 FJ<op, (outs), (ins calltarget64:$target, variable_ops), 64 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)], 65 IIBranch>; 66 67 class JumpLinkReg64<bits<6> op, bits<6> func, string instr_asm>: 68 FR<op, func, (outs), (ins CPU64Regs:$rs, variable_ops), 69 !strconcat(instr_asm, "\t$rs"), 70 [(MipsJmpLink CPU64Regs:$rs)], IIBranch> { 71 let rt = 0; 72 let rd = 31; 73 let shamt = 0; 74 } 75 76 class BranchLink64<string instr_asm>: 77 FI<0x1, (outs), (ins CPU64Regs:$rs, brtarget:$imm16, variable_ops), 78 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch>; 79} 80 81// Mul, Div 82class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>: 83 Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; 84class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 85 Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; 86 87multiclass Atomic2Ops64<PatFrag Op, string Opstr> { 88 def #NAME# : Atomic2Ops<Op, Opstr, CPU64Regs, CPURegs>, Requires<[NotN64]>; 89 def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>, Requires<[IsN64]>; 90} 91 92multiclass AtomicCmpSwap64<PatFrag Op, string Width> { 93 def #NAME# : AtomicCmpSwap<Op, Width, CPU64Regs, CPURegs>, Requires<[NotN64]>; 94 def _P8 : AtomicCmpSwap<Op, Width, CPU64Regs, CPU64Regs>, 95 Requires<[IsN64]>; 96} 97 98let usesCustomInserter = 1, Predicates = [HasMips64] in { 99 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">; 100 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">; 101 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64, "load_and_64">; 102 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64, "load_or_64">; 103 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64, "load_xor_64">; 104 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64, "load_nand_64">; 105 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64, "swap_64">; 106 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64, "64">; 107} 108 109//===----------------------------------------------------------------------===// 110// Instruction definition 111//===----------------------------------------------------------------------===// 112 113/// Arithmetic Instructions (ALU Immediate) 114def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16, 115 CPU64Regs>; 116def DANDi : ArithLogicI<0x0c, "andi", and, uimm16_64, immZExt16, CPU64Regs>; 117def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>; 118def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>; 119def ORi64 : ArithLogicI<0x0d, "ori", or, uimm16_64, immZExt16, CPU64Regs>; 120def XORi64 : ArithLogicI<0x0e, "xori", xor, uimm16_64, immZExt16, CPU64Regs>; 121def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>; 122 123/// Arithmetic Instructions (3-Operand, R-Type) 124def DADDu : ArithLogicR<0x00, 0x2d, "daddu", add, IIAlu, CPU64Regs, 1>; 125def DSUBu : ArithLogicR<0x00, 0x2f, "dsubu", sub, IIAlu, CPU64Regs>; 126def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>; 127def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>; 128def AND64 : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPU64Regs, 1>; 129def OR64 : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPU64Regs, 1>; 130def XOR64 : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>; 131def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>; 132 133/// Shift Instructions 134def DSLL : shift_rotate_imm64<0x38, 0x00, "dsll", shl>; 135def DSRL : shift_rotate_imm64<0x3a, 0x00, "dsrl", srl>; 136def DSRA : shift_rotate_imm64<0x3b, 0x00, "dsra", sra>; 137def DSLLV : shift_rotate_reg<0x24, 0x00, "dsllv", shl, CPU64Regs>; 138def DSRLV : shift_rotate_reg<0x26, 0x00, "dsrlv", srl, CPU64Regs>; 139def DSRAV : shift_rotate_reg<0x27, 0x00, "dsrav", sra, CPU64Regs>; 140 141// Rotate Instructions 142let Predicates = [HasMips64r2] in { 143 def DROTR : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>; 144 def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>; 145} 146 147/// Load and Store Instructions 148/// aligned 149defm LB64 : LoadM64<0x20, "lb", sextloadi8>; 150defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>; 151defm LH64 : LoadM64<0x21, "lh", sextloadi16_a>; 152defm LHu64 : LoadM64<0x25, "lhu", zextloadi16_a>; 153defm LW64 : LoadM64<0x23, "lw", sextloadi32_a>; 154defm LWu64 : LoadM64<0x27, "lwu", zextloadi32_a>; 155defm SB64 : StoreM64<0x28, "sb", truncstorei8>; 156defm SH64 : StoreM64<0x29, "sh", truncstorei16_a>; 157defm SW64 : StoreM64<0x2b, "sw", truncstorei32_a>; 158defm LD : LoadM64<0x37, "ld", load_a>; 159defm SD : StoreM64<0x3f, "sd", store_a>; 160 161/// unaligned 162defm ULH64 : LoadM64<0x21, "ulh", sextloadi16_u, 1>; 163defm ULHu64 : LoadM64<0x25, "ulhu", zextloadi16_u, 1>; 164defm ULW64 : LoadM64<0x23, "ulw", sextloadi32_u, 1>; 165defm USH64 : StoreM64<0x29, "ush", truncstorei16_u, 1>; 166defm USW64 : StoreM64<0x2b, "usw", truncstorei32_u, 1>; 167defm ULD : LoadM64<0x37, "uld", load_u, 1>; 168defm USD : StoreM64<0x3f, "usd", store_u, 1>; 169 170/// Load-linked, Store-conditional 171def LLD : LLBase<0x34, "lld", CPU64Regs, mem>, Requires<[NotN64]>; 172def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>, Requires<[IsN64]>; 173def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>, Requires<[NotN64]>; 174def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, Requires<[IsN64]>; 175 176/// Jump and Branch Instructions 177def JR64 : JumpFR<0x00, 0x08, "jr", CPU64Regs>; 178def JAL64 : JumpLink64<0x03, "jal">; 179def JALR64 : JumpLinkReg64<0x00, 0x09, "jalr">; 180def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>; 181def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>; 182def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>; 183def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>; 184def BLEZ64 : CBranchZero<0x07, 0, "blez", setle, CPU64Regs>; 185def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>; 186 187/// Multiply and Divide Instructions. 188def DMULT : Mult64<0x1c, "dmult", IIImul>; 189def DMULTu : Mult64<0x1d, "dmultu", IIImul>; 190def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>; 191def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>; 192 193def MTHI64 : MoveToLOHI<0x11, "mthi", CPU64Regs, [HI64]>; 194def MTLO64 : MoveToLOHI<0x13, "mtlo", CPU64Regs, [LO64]>; 195def MFHI64 : MoveFromLOHI<0x10, "mfhi", CPU64Regs, [HI64]>; 196def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>; 197 198/// Count Leading 199def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>; 200def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>; 201 202def LEA_ADDiu64 : EffectiveAddress<"addiu\t$rt, $addr", CPU64Regs, mem_ea_64>; 203 204let Uses = [SP_64] in 205def DynAlloc64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>, 206 Requires<[IsN64]>; 207 208def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>; 209 210def DEXT : ExtBase<3, "dext", CPU64Regs>; 211def DINS : InsBase<7, "dins", CPU64Regs>; 212 213def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 214 "dsll\t$rd, $rt, 32", [], IIAlu>; 215 216def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 217 "sll\t$rd, $rt, 0", [], IIAlu>; 218 219//===----------------------------------------------------------------------===// 220// Arbitrary patterns that map to one or more instructions 221//===----------------------------------------------------------------------===// 222 223// Small immediates 224def : Pat<(i64 immSExt16:$in), 225 (DADDiu ZERO_64, imm:$in)>; 226def : Pat<(i64 immZExt16:$in), 227 (ORi64 ZERO_64, imm:$in)>; 228 229// 32-bit immediates 230def : Pat<(i64 immSExt32:$imm), 231 (ORi64 (LUi64 (HI16 imm:$imm)), (LO16 imm:$imm))>; 232 233// Arbitrary immediates 234def : Pat<(i64 imm:$imm), 235 (ORi64 (DSLL (ORi64 (DSLL (ORi64 (LUi64 (HIGHEST imm:$imm)), 236 (HIGHER imm:$imm)), 16), (HI16 imm:$imm)), 16), 237 (LO16 imm:$imm))>; 238 239// extended loads 240let Predicates = [NotN64] in { 241 def : Pat<(extloadi32_a addr:$a), (DSRL (DSLL (LW64 addr:$a), 32), 32)>; 242 def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>; 243} 244let Predicates = [IsN64] in { 245 def : Pat<(extloadi32_a addr:$a), (DSRL (DSLL (LW64_P8 addr:$a), 32), 32)>; 246 def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>; 247} 248 249// hi/lo relocs 250def : Pat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 251def : Pat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 252def : Pat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 253def : Pat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 254def : Pat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 255 256def : Pat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 257def : Pat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>; 258def : Pat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 259def : Pat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 260def : Pat<(MipsLo tglobaltlsaddr:$in), (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 261 262def : Pat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)), 263 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>; 264def : Pat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)), 265 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>; 266def : Pat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)), 267 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>; 268def : Pat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)), 269 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>; 270def : Pat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)), 271 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>; 272 273def : WrapperPat<tglobaladdr, DADDiu, GP_64>; 274def : WrapperPat<tconstpool, DADDiu, GP_64>; 275def : WrapperPat<texternalsym, DADDiu, GP_64>; 276def : WrapperPat<tblockaddress, DADDiu, GP_64>; 277def : WrapperPat<tjumptable, DADDiu, GP_64>; 278def : WrapperPat<tglobaltlsaddr, DADDiu, GP_64>; 279 280defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 281 ZERO_64>; 282 283// setcc patterns 284defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>; 285defm : SetlePats<CPU64Regs, SLT64, SLTu64>; 286defm : SetgtPats<CPU64Regs, SLT64, SLTu64>; 287defm : SetgePats<CPU64Regs, SLT64, SLTu64>; 288defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>; 289 290// select MipsDynAlloc 291def : Pat<(MipsDynAlloc addr:$f), (DynAlloc64 addr:$f)>, Requires<[IsN64]>; 292 293// truncate 294def : Pat<(i32 (trunc CPU64Regs:$src)), 295 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, Requires<[IsN64]>; 296 297// 32-to-64-bit extension 298def : Pat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 299def : Pat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; 300