MipsAsmPrinter.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a printer that converts from our internal representation
11// of machine-dependent LLVM code to GAS-format MIPS assembly language.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "mips-asm-printer"
16#include "InstPrinter/MipsInstPrinter.h"
17#include "MCTargetDesc/MipsBaseInfo.h"
18#include "MCTargetDesc/MipsMCNaCl.h"
19#include "Mips.h"
20#include "MipsAsmPrinter.h"
21#include "MipsInstrInfo.h"
22#include "MipsMCInstLower.h"
23#include "MipsTargetStreamer.h"
24#include "llvm/ADT/SmallString.h"
25#include "llvm/ADT/StringExtras.h"
26#include "llvm/ADT/Twine.h"
27#include "llvm/CodeGen/MachineConstantPool.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/IR/BasicBlock.h"
34#include "llvm/IR/DataLayout.h"
35#include "llvm/IR/InlineAsm.h"
36#include "llvm/IR/Instructions.h"
37#include "llvm/IR/Mangler.h"
38#include "llvm/MC/MCAsmInfo.h"
39#include "llvm/MC/MCContext.h"
40#include "llvm/MC/MCELFStreamer.h"
41#include "llvm/MC/MCExpr.h"
42#include "llvm/MC/MCInst.h"
43#include "llvm/MC/MCSection.h"
44#include "llvm/MC/MCSectionELF.h"
45#include "llvm/MC/MCSymbol.h"
46#include "llvm/Support/ELF.h"
47#include "llvm/Support/TargetRegistry.h"
48#include "llvm/Support/raw_ostream.h"
49#include "llvm/Target/TargetLoweringObjectFile.h"
50#include "llvm/Target/TargetOptions.h"
51#include <string>
52
53using namespace llvm;
54
55MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() {
56  return static_cast<MipsTargetStreamer &>(*OutStreamer.getTargetStreamer());
57}
58
59bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
60  // Initialize TargetLoweringObjectFile.
61  if (Subtarget->allowMixed16_32())
62    const_cast<TargetLoweringObjectFile&>(getObjFileLowering())
63      .Initialize(OutContext, TM);
64  MipsFI = MF.getInfo<MipsFunctionInfo>();
65  if (Subtarget->inMips16Mode())
66    for (std::map<
67             const char *,
68             const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
69             it = MipsFI->StubsNeeded.begin();
70         it != MipsFI->StubsNeeded.end(); ++it) {
71      const char *Symbol = it->first;
72      const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
73      if (StubsNeeded.find(Symbol) == StubsNeeded.end())
74        StubsNeeded[Symbol] = Signature;
75    }
76  MCP = MF.getConstantPool();
77
78  // In NaCl, all indirect jump targets must be aligned to bundle size.
79  if (Subtarget->isTargetNaCl())
80    NaClAlignIndirectJumpTargets(MF);
81
82  AsmPrinter::runOnMachineFunction(MF);
83  return true;
84}
85
86bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
87  MCOp = MCInstLowering.LowerOperand(MO);
88  return MCOp.isValid();
89}
90
91#include "MipsGenMCPseudoLowering.inc"
92
93void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
94  if (MI->isDebugValue()) {
95    SmallString<128> Str;
96    raw_svector_ostream OS(Str);
97
98    PrintDebugValueComment(MI, OS);
99    return;
100  }
101
102  // If we just ended a constant pool, mark it as such.
103  if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
104    OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
105    InConstantPool = false;
106  }
107  if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
108    // CONSTPOOL_ENTRY - This instruction represents a floating
109    //constant pool in the function.  The first operand is the ID#
110    // for this instruction, the second is the index into the
111    // MachineConstantPool that this is, the third is the size in
112    // bytes of this constant pool entry.
113    // The required alignment is specified on the basic block holding this MI.
114    //
115    unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
116    unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
117
118    // If this is the first entry of the pool, mark it.
119    if (!InConstantPool) {
120      OutStreamer.EmitDataRegion(MCDR_DataRegion);
121      InConstantPool = true;
122    }
123
124    OutStreamer.EmitLabel(GetCPISymbol(LabelId));
125
126    const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
127    if (MCPE.isMachineConstantPoolEntry())
128      EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
129    else
130      EmitGlobalConstant(MCPE.Val.ConstVal);
131    return;
132  }
133
134
135  MachineBasicBlock::const_instr_iterator I = MI;
136  MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
137
138  do {
139    // Do any auto-generated pseudo lowerings.
140    if (emitPseudoExpansionLowering(OutStreamer, &*I))
141      continue;
142
143    // The inMips16Mode() test is not permanent.
144    // Some instructions are marked as pseudo right now which
145    // would make the test fail for the wrong reason but
146    // that will be fixed soon. We need this here because we are
147    // removing another test for this situation downstream in the
148    // callchain.
149    //
150    if (I->isPseudo() && !Subtarget->inMips16Mode())
151      llvm_unreachable("Pseudo opcode found in EmitInstruction()");
152
153    MCInst TmpInst0;
154    MCInstLowering.Lower(I, TmpInst0);
155    EmitToStreamer(OutStreamer, TmpInst0);
156  } while ((++I != E) && I->isInsideBundle()); // Delay slot check
157}
158
159//===----------------------------------------------------------------------===//
160//
161//  Mips Asm Directives
162//
163//  -- Frame directive "frame Stackpointer, Stacksize, RARegister"
164//  Describe the stack frame.
165//
166//  -- Mask directives "(f)mask  bitmask, offset"
167//  Tells the assembler which registers are saved and where.
168//  bitmask - contain a little endian bitset indicating which registers are
169//            saved on function prologue (e.g. with a 0x80000000 mask, the
170//            assembler knows the register 31 (RA) is saved at prologue.
171//  offset  - the position before stack pointer subtraction indicating where
172//            the first saved register on prologue is located. (e.g. with a
173//
174//  Consider the following function prologue:
175//
176//    .frame  $fp,48,$ra
177//    .mask   0xc0000000,-8
178//       addiu $sp, $sp, -48
179//       sw $ra, 40($sp)
180//       sw $fp, 36($sp)
181//
182//    With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
183//    30 (FP) are saved at prologue. As the save order on prologue is from
184//    left to right, RA is saved first. A -8 offset means that after the
185//    stack pointer subtration, the first register in the mask (RA) will be
186//    saved at address 48-8=40.
187//
188//===----------------------------------------------------------------------===//
189
190//===----------------------------------------------------------------------===//
191// Mask directives
192//===----------------------------------------------------------------------===//
193
194// Create a bitmask with all callee saved registers for CPU or Floating Point
195// registers. For CPU registers consider RA, GP and FP for saving if necessary.
196void MipsAsmPrinter::printSavedRegsBitmask() {
197  // CPU and FPU Saved Registers Bitmasks
198  unsigned CPUBitmask = 0, FPUBitmask = 0;
199  int CPUTopSavedRegOff, FPUTopSavedRegOff;
200
201  // Set the CPU and FPU Bitmasks
202  const MachineFrameInfo *MFI = MF->getFrameInfo();
203  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
204  // size of stack area to which FP callee-saved regs are saved.
205  unsigned CPURegSize = Mips::GPR32RegClass.getSize();
206  unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
207  unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
208  bool HasAFGR64Reg = false;
209  unsigned CSFPRegsSize = 0;
210  unsigned i, e = CSI.size();
211
212  // Set FPU Bitmask.
213  for (i = 0; i != e; ++i) {
214    unsigned Reg = CSI[i].getReg();
215    if (Mips::GPR32RegClass.contains(Reg))
216      break;
217
218    unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
219    if (Mips::AFGR64RegClass.contains(Reg)) {
220      FPUBitmask |= (3 << RegNum);
221      CSFPRegsSize += AFGR64RegSize;
222      HasAFGR64Reg = true;
223      continue;
224    }
225
226    FPUBitmask |= (1 << RegNum);
227    CSFPRegsSize += FGR32RegSize;
228  }
229
230  // Set CPU Bitmask.
231  for (; i != e; ++i) {
232    unsigned Reg = CSI[i].getReg();
233    unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
234    CPUBitmask |= (1 << RegNum);
235  }
236
237  // FP Regs are saved right below where the virtual frame pointer points to.
238  FPUTopSavedRegOff = FPUBitmask ?
239    (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
240
241  // CPU Regs are saved below FP Regs.
242  CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
243
244  MipsTargetStreamer &TS = getTargetStreamer();
245  // Print CPUBitmask
246  TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
247
248  // Print FPUBitmask
249  TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
250}
251
252//===----------------------------------------------------------------------===//
253// Frame and Set directives
254//===----------------------------------------------------------------------===//
255
256/// Frame Directive
257void MipsAsmPrinter::emitFrameDirective() {
258  const TargetRegisterInfo &RI = *TM.getRegisterInfo();
259
260  unsigned stackReg  = RI.getFrameRegister(*MF);
261  unsigned returnReg = RI.getRARegister();
262  unsigned stackSize = MF->getFrameInfo()->getStackSize();
263
264  getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
265}
266
267/// Emit Set directives.
268const char *MipsAsmPrinter::getCurrentABIString() const {
269  switch (Subtarget->getTargetABI()) {
270  case MipsSubtarget::O32:  return "abi32";
271  case MipsSubtarget::N32:  return "abiN32";
272  case MipsSubtarget::N64:  return "abi64";
273  case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
274  default: llvm_unreachable("Unknown Mips ABI");
275  }
276}
277
278void MipsAsmPrinter::EmitFunctionEntryLabel() {
279  MipsTargetStreamer &TS = getTargetStreamer();
280
281  // NaCl sandboxing requires that indirect call instructions are masked.
282  // This means that function entry points should be bundle-aligned.
283  if (Subtarget->isTargetNaCl())
284    EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN));
285
286  if (Subtarget->inMicroMipsMode())
287    TS.emitDirectiveSetMicroMips();
288  // leave out until FSF available gas has micromips changes
289  //  else
290  //    TS.emitDirectiveSetNoMicroMips();
291
292  if (Subtarget->inMips16Mode())
293    TS.emitDirectiveSetMips16();
294  else
295    TS.emitDirectiveSetNoMips16();
296
297  TS.emitDirectiveEnt(*CurrentFnSym);
298  OutStreamer.EmitLabel(CurrentFnSym);
299}
300
301/// EmitFunctionBodyStart - Targets can override this to emit stuff before
302/// the first basic block in the function.
303void MipsAsmPrinter::EmitFunctionBodyStart() {
304  MipsTargetStreamer &TS = getTargetStreamer();
305
306  MCInstLowering.Initialize(&MF->getContext());
307
308  bool IsNakedFunction =
309    MF->getFunction()->
310      getAttributes().hasAttribute(AttributeSet::FunctionIndex,
311                                   Attribute::Naked);
312  if (!IsNakedFunction)
313    emitFrameDirective();
314
315  if (!IsNakedFunction)
316    printSavedRegsBitmask();
317
318  if (!Subtarget->inMips16Mode()) {
319    TS.emitDirectiveSetNoReorder();
320    TS.emitDirectiveSetNoMacro();
321    TS.emitDirectiveSetNoAt();
322  }
323}
324
325/// EmitFunctionBodyEnd - Targets can override this to emit stuff after
326/// the last basic block in the function.
327void MipsAsmPrinter::EmitFunctionBodyEnd() {
328  MipsTargetStreamer &TS = getTargetStreamer();
329
330  // There are instruction for this macros, but they must
331  // always be at the function end, and we can't emit and
332  // break with BB logic.
333  if (!Subtarget->inMips16Mode()) {
334    TS.emitDirectiveSetAt();
335    TS.emitDirectiveSetMacro();
336    TS.emitDirectiveSetReorder();
337  }
338  TS.emitDirectiveEnd(CurrentFnSym->getName());
339  // Make sure to terminate any constant pools that were at the end
340  // of the function.
341  if (!InConstantPool)
342    return;
343  InConstantPool = false;
344  OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
345}
346
347/// isBlockOnlyReachableByFallthough - Return true if the basic block has
348/// exactly one predecessor and the control transfer mechanism between
349/// the predecessor and this block is a fall-through.
350bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
351                                                       MBB) const {
352  // The predecessor has to be immediately before this block.
353  const MachineBasicBlock *Pred = *MBB->pred_begin();
354
355  // If the predecessor is a switch statement, assume a jump table
356  // implementation, so it is not a fall through.
357  if (const BasicBlock *bb = Pred->getBasicBlock())
358    if (isa<SwitchInst>(bb->getTerminator()))
359      return false;
360
361  // If this is a landing pad, it isn't a fall through.  If it has no preds,
362  // then nothing falls through to it.
363  if (MBB->isLandingPad() || MBB->pred_empty())
364    return false;
365
366  // If there isn't exactly one predecessor, it can't be a fall through.
367  MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
368  ++PI2;
369
370  if (PI2 != MBB->pred_end())
371    return false;
372
373  // The predecessor has to be immediately before this block.
374  if (!Pred->isLayoutSuccessor(MBB))
375    return false;
376
377  // If the block is completely empty, then it definitely does fall through.
378  if (Pred->empty())
379    return true;
380
381  // Otherwise, check the last instruction.
382  // Check if the last terminator is an unconditional branch.
383  MachineBasicBlock::const_iterator I = Pred->end();
384  while (I != Pred->begin() && !(--I)->isTerminator()) ;
385
386  return !I->isBarrier();
387}
388
389// Print out an operand for an inline asm expression.
390bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
391                                     unsigned AsmVariant,const char *ExtraCode,
392                                     raw_ostream &O) {
393  // Does this asm operand have a single letter operand modifier?
394  if (ExtraCode && ExtraCode[0]) {
395    if (ExtraCode[1] != 0) return true; // Unknown modifier.
396
397    const MachineOperand &MO = MI->getOperand(OpNum);
398    switch (ExtraCode[0]) {
399    default:
400      // See if this is a generic print operand
401      return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
402    case 'X': // hex const int
403      if ((MO.getType()) != MachineOperand::MO_Immediate)
404        return true;
405      O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
406      return false;
407    case 'x': // hex const int (low 16 bits)
408      if ((MO.getType()) != MachineOperand::MO_Immediate)
409        return true;
410      O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
411      return false;
412    case 'd': // decimal const int
413      if ((MO.getType()) != MachineOperand::MO_Immediate)
414        return true;
415      O << MO.getImm();
416      return false;
417    case 'm': // decimal const int minus 1
418      if ((MO.getType()) != MachineOperand::MO_Immediate)
419        return true;
420      O << MO.getImm() - 1;
421      return false;
422    case 'z': {
423      // $0 if zero, regular printing otherwise
424      if (MO.getType() != MachineOperand::MO_Immediate)
425        return true;
426      int64_t Val = MO.getImm();
427      if (Val)
428        O << Val;
429      else
430        O << "$0";
431      return false;
432    }
433    case 'D': // Second part of a double word register operand
434    case 'L': // Low order register of a double word register operand
435    case 'M': // High order register of a double word register operand
436    {
437      if (OpNum == 0)
438        return true;
439      const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
440      if (!FlagsOP.isImm())
441        return true;
442      unsigned Flags = FlagsOP.getImm();
443      unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
444      // Number of registers represented by this operand. We are looking
445      // for 2 for 32 bit mode and 1 for 64 bit mode.
446      if (NumVals != 2) {
447        if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
448          unsigned Reg = MO.getReg();
449          O << '$' << MipsInstPrinter::getRegisterName(Reg);
450          return false;
451        }
452        return true;
453      }
454
455      unsigned RegOp = OpNum;
456      if (!Subtarget->isGP64bit()){
457        // Endianess reverses which register holds the high or low value
458        // between M and L.
459        switch(ExtraCode[0]) {
460        case 'M':
461          RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
462          break;
463        case 'L':
464          RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
465          break;
466        case 'D': // Always the second part
467          RegOp = OpNum + 1;
468        }
469        if (RegOp >= MI->getNumOperands())
470          return true;
471        const MachineOperand &MO = MI->getOperand(RegOp);
472        if (!MO.isReg())
473          return true;
474        unsigned Reg = MO.getReg();
475        O << '$' << MipsInstPrinter::getRegisterName(Reg);
476        return false;
477      }
478    }
479    case 'w':
480      // Print MSA registers for the 'f' constraint
481      // In LLVM, the 'w' modifier doesn't need to do anything.
482      // We can just call printOperand as normal.
483      break;
484    }
485  }
486
487  printOperand(MI, OpNum, O);
488  return false;
489}
490
491bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
492                                           unsigned OpNum, unsigned AsmVariant,
493                                           const char *ExtraCode,
494                                           raw_ostream &O) {
495  int Offset = 0;
496  // Currently we are expecting either no ExtraCode or 'D'
497  if (ExtraCode) {
498    if (ExtraCode[0] == 'D')
499      Offset = 4;
500    else
501      return true; // Unknown modifier.
502  }
503
504  const MachineOperand &MO = MI->getOperand(OpNum);
505  assert(MO.isReg() && "unexpected inline asm memory operand");
506  O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
507
508  return false;
509}
510
511void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
512                                  raw_ostream &O) {
513  const DataLayout *DL = TM.getDataLayout();
514  const MachineOperand &MO = MI->getOperand(opNum);
515  bool closeP = false;
516
517  if (MO.getTargetFlags())
518    closeP = true;
519
520  switch(MO.getTargetFlags()) {
521  case MipsII::MO_GPREL:    O << "%gp_rel("; break;
522  case MipsII::MO_GOT_CALL: O << "%call16("; break;
523  case MipsII::MO_GOT:      O << "%got(";    break;
524  case MipsII::MO_ABS_HI:   O << "%hi(";     break;
525  case MipsII::MO_ABS_LO:   O << "%lo(";     break;
526  case MipsII::MO_TLSGD:    O << "%tlsgd(";  break;
527  case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
528  case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
529  case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
530  case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
531  case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
532  case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
533  case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
534  case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
535  }
536
537  switch (MO.getType()) {
538    case MachineOperand::MO_Register:
539      O << '$'
540        << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
541      break;
542
543    case MachineOperand::MO_Immediate:
544      O << MO.getImm();
545      break;
546
547    case MachineOperand::MO_MachineBasicBlock:
548      O << *MO.getMBB()->getSymbol();
549      return;
550
551    case MachineOperand::MO_GlobalAddress:
552      O << *getSymbol(MO.getGlobal());
553      break;
554
555    case MachineOperand::MO_BlockAddress: {
556      MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
557      O << BA->getName();
558      break;
559    }
560
561    case MachineOperand::MO_ConstantPoolIndex:
562      O << DL->getPrivateGlobalPrefix() << "CPI"
563        << getFunctionNumber() << "_" << MO.getIndex();
564      if (MO.getOffset())
565        O << "+" << MO.getOffset();
566      break;
567
568    default:
569      llvm_unreachable("<unknown operand type>");
570  }
571
572  if (closeP) O << ")";
573}
574
575void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
576                                      raw_ostream &O) {
577  const MachineOperand &MO = MI->getOperand(opNum);
578  if (MO.isImm())
579    O << (unsigned short int)MO.getImm();
580  else
581    printOperand(MI, opNum, O);
582}
583
584void MipsAsmPrinter::printUnsignedImm8(const MachineInstr *MI, int opNum,
585                                       raw_ostream &O) {
586  const MachineOperand &MO = MI->getOperand(opNum);
587  if (MO.isImm())
588    O << (unsigned short int)(unsigned char)MO.getImm();
589  else
590    printOperand(MI, opNum, O);
591}
592
593void MipsAsmPrinter::
594printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
595  // Load/Store memory operands -- imm($reg)
596  // If PIC target the target is loaded as the
597  // pattern lw $25,%call16($28)
598  printOperand(MI, opNum+1, O);
599  O << "(";
600  printOperand(MI, opNum, O);
601  O << ")";
602}
603
604void MipsAsmPrinter::
605printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
606  // when using stack locations for not load/store instructions
607  // print the same way as all normal 3 operand instructions.
608  printOperand(MI, opNum, O);
609  O << ", ";
610  printOperand(MI, opNum+1, O);
611  return;
612}
613
614void MipsAsmPrinter::
615printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
616                const char *Modifier) {
617  const MachineOperand &MO = MI->getOperand(opNum);
618  O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
619}
620
621void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
622  // TODO: Need to add -mabicalls and -mno-abicalls flags.
623  // Currently we assume that -mabicalls is the default.
624  getTargetStreamer().emitDirectiveAbiCalls();
625  Reloc::Model RM = Subtarget->getRelocationModel();
626  if (RM == Reloc::Static && !Subtarget->hasMips64())
627    getTargetStreamer().emitDirectiveOptionPic0();
628
629  // Tell the assembler which ABI we are using
630  std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
631  OutStreamer.SwitchSection(OutContext.getELFSection(
632      SectionName, ELF::SHT_PROGBITS, 0, SectionKind::getDataRel()));
633
634  // TODO: handle O64 ABI
635
636  if (Subtarget->isABI_EABI()) {
637    if (Subtarget->isGP32bit())
638      OutStreamer.SwitchSection(
639          OutContext.getELFSection(".gcc_compiled_long32", ELF::SHT_PROGBITS, 0,
640                                   SectionKind::getDataRel()));
641    else
642      OutStreamer.SwitchSection(
643          OutContext.getELFSection(".gcc_compiled_long64", ELF::SHT_PROGBITS, 0,
644                                   SectionKind::getDataRel()));
645  }
646}
647
648void MipsAsmPrinter::EmitJal(MCSymbol *Symbol) {
649  MCInst I;
650  I.setOpcode(Mips::JAL);
651  I.addOperand(
652      MCOperand::CreateExpr(MCSymbolRefExpr::Create(Symbol, OutContext)));
653  OutStreamer.EmitInstruction(I, getSubtargetInfo());
654}
655
656void MipsAsmPrinter::EmitInstrReg(unsigned Opcode, unsigned Reg) {
657  MCInst I;
658  I.setOpcode(Opcode);
659  I.addOperand(MCOperand::CreateReg(Reg));
660  OutStreamer.EmitInstruction(I, getSubtargetInfo());
661}
662
663void MipsAsmPrinter::EmitInstrRegReg(unsigned Opcode, unsigned Reg1,
664                                     unsigned Reg2) {
665  MCInst I;
666  //
667  // Because of the current td files for Mips32, the operands for MTC1
668  // appear backwards from their normal assembly order. It's not a trivial
669  // change to fix this in the td file so we adjust for it here.
670  //
671  if (Opcode == Mips::MTC1) {
672    unsigned Temp = Reg1;
673    Reg1 = Reg2;
674    Reg2 = Temp;
675  }
676  I.setOpcode(Opcode);
677  I.addOperand(MCOperand::CreateReg(Reg1));
678  I.addOperand(MCOperand::CreateReg(Reg2));
679  OutStreamer.EmitInstruction(I, getSubtargetInfo());
680}
681
682void MipsAsmPrinter::EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1,
683                                        unsigned Reg2, unsigned Reg3) {
684  MCInst I;
685  I.setOpcode(Opcode);
686  I.addOperand(MCOperand::CreateReg(Reg1));
687  I.addOperand(MCOperand::CreateReg(Reg2));
688  I.addOperand(MCOperand::CreateReg(Reg3));
689  OutStreamer.EmitInstruction(I, getSubtargetInfo());
690}
691
692void MipsAsmPrinter::EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1,
693                                      unsigned Reg2, unsigned FPReg1,
694                                      unsigned FPReg2, bool LE) {
695  if (!LE) {
696    unsigned temp = Reg1;
697    Reg1 = Reg2;
698    Reg2 = temp;
699  }
700  EmitInstrRegReg(MovOpc, Reg1, FPReg1);
701  EmitInstrRegReg(MovOpc, Reg2, FPReg2);
702}
703
704void MipsAsmPrinter::EmitSwapFPIntParams(Mips16HardFloatInfo::FPParamVariant PV,
705                                         bool LE, bool ToFP) {
706  using namespace Mips16HardFloatInfo;
707  unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
708  switch (PV) {
709  case FSig:
710    EmitInstrRegReg(MovOpc, Mips::A0, Mips::F12);
711    break;
712  case FFSig:
713    EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
714    break;
715  case FDSig:
716    EmitInstrRegReg(MovOpc, Mips::A0, Mips::F12);
717    EmitMovFPIntPair(MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
718    break;
719  case DSig:
720    EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
721    break;
722  case DDSig:
723    EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
724    EmitMovFPIntPair(MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
725    break;
726  case DFSig:
727    EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
728    EmitInstrRegReg(MovOpc, Mips::A2, Mips::F14);
729    break;
730  case NoSig:
731    return;
732  }
733}
734
735void
736MipsAsmPrinter::EmitSwapFPIntRetval(Mips16HardFloatInfo::FPReturnVariant RV,
737                                    bool LE) {
738  using namespace Mips16HardFloatInfo;
739  unsigned MovOpc = Mips::MFC1;
740  switch (RV) {
741  case FRet:
742    EmitInstrRegReg(MovOpc, Mips::V0, Mips::F0);
743    break;
744  case DRet:
745    EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
746    break;
747  case CFRet:
748    EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
749    break;
750  case CDRet:
751    EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
752    EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
753    break;
754  case NoFPRet:
755    break;
756  }
757}
758
759void MipsAsmPrinter::EmitFPCallStub(
760    const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
761  MCSymbol *MSymbol = OutContext.GetOrCreateSymbol(StringRef(Symbol));
762  using namespace Mips16HardFloatInfo;
763  bool LE = Subtarget->isLittle();
764  //
765  // .global xxxx
766  //
767  OutStreamer.EmitSymbolAttribute(MSymbol, MCSA_Global);
768  const char *RetType;
769  //
770  // make the comment field identifying the return and parameter
771  // types of the floating point stub
772  // # Stub function to call rettype xxxx (params)
773  //
774  switch (Signature->RetSig) {
775  case FRet:
776    RetType = "float";
777    break;
778  case DRet:
779    RetType = "double";
780    break;
781  case CFRet:
782    RetType = "complex";
783    break;
784  case CDRet:
785    RetType = "double complex";
786    break;
787  case NoFPRet:
788    RetType = "";
789    break;
790  }
791  const char *Parms;
792  switch (Signature->ParamSig) {
793  case FSig:
794    Parms = "float";
795    break;
796  case FFSig:
797    Parms = "float, float";
798    break;
799  case FDSig:
800    Parms = "float, double";
801    break;
802  case DSig:
803    Parms = "double";
804    break;
805  case DDSig:
806    Parms = "double, double";
807    break;
808  case DFSig:
809    Parms = "double, float";
810    break;
811  case NoSig:
812    Parms = "";
813    break;
814  }
815  OutStreamer.AddComment("\t# Stub function to call " + Twine(RetType) + " " +
816                         Twine(Symbol) + " (" + Twine(Parms) + ")");
817  //
818  // probably not necessary but we save and restore the current section state
819  //
820  OutStreamer.PushSection();
821  //
822  // .section mips16.call.fpxxxx,"ax",@progbits
823  //
824  const MCSectionELF *M = OutContext.getELFSection(
825      ".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
826      ELF::SHF_ALLOC | ELF::SHF_EXECINSTR, SectionKind::getText());
827  OutStreamer.SwitchSection(M, 0);
828  //
829  // .align 2
830  //
831  OutStreamer.EmitValueToAlignment(4);
832  MipsTargetStreamer &TS = getTargetStreamer();
833  //
834  // .set nomips16
835  // .set nomicromips
836  //
837  TS.emitDirectiveSetNoMips16();
838  TS.emitDirectiveSetNoMicroMips();
839  //
840  // .ent __call_stub_fp_xxxx
841  // .type	__call_stub_fp_xxxx,@function
842  //  __call_stub_fp_xxxx:
843  //
844  std::string x = "__call_stub_fp_" + std::string(Symbol);
845  MCSymbol *Stub = OutContext.GetOrCreateSymbol(StringRef(x));
846  TS.emitDirectiveEnt(*Stub);
847  MCSymbol *MType =
848      OutContext.GetOrCreateSymbol("__call_stub_fp_" + Twine(Symbol));
849  OutStreamer.EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction);
850  OutStreamer.EmitLabel(Stub);
851  //
852  // we just handle non pic for now. these function will not be
853  // called otherwise. when the full stub generation is moved here
854  // we need to deal with pic.
855  //
856  if (Subtarget->getRelocationModel() == Reloc::PIC_)
857    llvm_unreachable("should not be here if we are compiling pic");
858  TS.emitDirectiveSetReorder();
859  //
860  // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
861  // stubs without raw text but this current patch is for compiler generated
862  // functions and they all return some value.
863  // The calling sequence for non pic is different in that case and we need
864  // to implement %lo and %hi in order to handle the case of no return value
865  // See the corresponding method in Mips16HardFloat for details.
866  //
867  // mov the return address to S2.
868  // we have no stack space to store it and we are about to make another call.
869  // We need to make sure that the enclosing function knows to save S2
870  // This should have already been handled.
871  //
872  // Mov $18, $31
873
874  EmitInstrRegRegReg(Mips::ADDu, Mips::S2, Mips::RA, Mips::ZERO);
875
876  EmitSwapFPIntParams(Signature->ParamSig, LE, true);
877
878  // Jal xxxx
879  //
880  EmitJal(MSymbol);
881
882  // fix return values
883  EmitSwapFPIntRetval(Signature->RetSig, LE);
884  //
885  // do the return
886  // if (Signature->RetSig == NoFPRet)
887  //  llvm_unreachable("should not be any stubs here with no return value");
888  // else
889  EmitInstrReg(Mips::JR, Mips::S2);
890
891  MCSymbol *Tmp = OutContext.CreateTempSymbol();
892  OutStreamer.EmitLabel(Tmp);
893  const MCSymbolRefExpr *E = MCSymbolRefExpr::Create(Stub, OutContext);
894  const MCSymbolRefExpr *T = MCSymbolRefExpr::Create(Tmp, OutContext);
895  const MCExpr *T_min_E = MCBinaryExpr::CreateSub(T, E, OutContext);
896  OutStreamer.EmitELFSize(Stub, T_min_E);
897  TS.emitDirectiveEnd(x);
898  OutStreamer.PopSection();
899}
900
901void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
902  // Emit needed stubs
903  //
904  for (std::map<
905           const char *,
906           const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
907           it = StubsNeeded.begin();
908       it != StubsNeeded.end(); ++it) {
909    const char *Symbol = it->first;
910    const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
911    EmitFPCallStub(Symbol, Signature);
912  }
913  // return to the text section
914  OutStreamer.SwitchSection(OutContext.getObjectFileInfo()->getTextSection());
915}
916
917void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
918                                           raw_ostream &OS) {
919  // TODO: implement
920}
921
922// Align all targets of indirect branches on bundle size.  Used only if target
923// is NaCl.
924void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
925  // Align all blocks that are jumped to through jump table.
926  if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
927    const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
928    for (unsigned I = 0; I < JT.size(); ++I) {
929      const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
930
931      for (unsigned J = 0; J < MBBs.size(); ++J)
932        MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
933    }
934  }
935
936  // If basic block address is taken, block can be target of indirect branch.
937  for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
938                                 MBB != E; ++MBB) {
939    if (MBB->hasAddressTaken())
940      MBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
941  }
942}
943
944// Force static initialization.
945extern "C" void LLVMInitializeMipsAsmPrinter() {
946  RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
947  RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
948  RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
949  RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);
950}
951