MipsAsmPrinter.cpp revision a0f14afee16ca976fef79c64df9a678e7f26cf43
1//===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains a printer that converts from our internal representation 11// of machine-dependent LLVM code to GAS-format MIPS assembly language. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-asm-printer" 16#include "Mips.h" 17#include "MipsAsmPrinter.h" 18#include "MipsInstrInfo.h" 19#include "MipsMCInstLower.h" 20#include "InstPrinter/MipsInstPrinter.h" 21#include "MCTargetDesc/MipsBaseInfo.h" 22#include "llvm/ADT/SmallString.h" 23#include "llvm/ADT/StringExtras.h" 24#include "llvm/ADT/Twine.h" 25#include "llvm/BasicBlock.h" 26#include "llvm/CodeGen/MachineConstantPool.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunctionPass.h" 29#include "llvm/CodeGen/MachineInstr.h" 30#include "llvm/CodeGen/MachineMemOperand.h" 31#include "llvm/InlineAsm.h" 32#include "llvm/Instructions.h" 33#include "llvm/MC/MCAsmInfo.h" 34#include "llvm/MC/MCInst.h" 35#include "llvm/MC/MCStreamer.h" 36#include "llvm/MC/MCSymbol.h" 37#include "llvm/Support/raw_ostream.h" 38#include "llvm/Support/TargetRegistry.h" 39#include "llvm/Target/Mangler.h" 40#include "llvm/Target/TargetData.h" 41#include "llvm/Target/TargetLoweringObjectFile.h" 42#include "llvm/Target/TargetOptions.h" 43 44using namespace llvm; 45 46bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) { 47 MipsFI = MF.getInfo<MipsFunctionInfo>(); 48 AsmPrinter::runOnMachineFunction(MF); 49 return true; 50} 51 52void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { 53 if (MI->isDebugValue()) { 54 SmallString<128> Str; 55 raw_svector_ostream OS(Str); 56 57 PrintDebugValueComment(MI, OS); 58 return; 59 } 60 61 // Direct object specific instruction lowering 62 if (!OutStreamer.hasRawTextSupport()) 63 switch (MI->getOpcode()) { 64 case Mips::DSLL: 65 case Mips::DSRL: 66 case Mips::DSRA: 67 assert(MI->getNumOperands() == 3 && 68 "Invalid no. of machine operands for shift!"); 69 assert(MI->getOperand(2).isImm()); 70 int64_t Shift = MI->getOperand(2).getImm(); 71 if (Shift > 31) { 72 MCInst TmpInst0; 73 MCInstLowering.LowerLargeShift(MI, TmpInst0, Shift - 32); 74 OutStreamer.EmitInstruction(TmpInst0); 75 return; 76 } 77 break; 78 } 79 80 MachineBasicBlock::const_instr_iterator I = MI; 81 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 82 83 do { 84 MCInst TmpInst0; 85 MCInstLowering.Lower(I++, TmpInst0); 86 OutStreamer.EmitInstruction(TmpInst0); 87 } while ((I != E) && I->isInsideBundle()); 88} 89 90//===----------------------------------------------------------------------===// 91// 92// Mips Asm Directives 93// 94// -- Frame directive "frame Stackpointer, Stacksize, RARegister" 95// Describe the stack frame. 96// 97// -- Mask directives "(f)mask bitmask, offset" 98// Tells the assembler which registers are saved and where. 99// bitmask - contain a little endian bitset indicating which registers are 100// saved on function prologue (e.g. with a 0x80000000 mask, the 101// assembler knows the register 31 (RA) is saved at prologue. 102// offset - the position before stack pointer subtraction indicating where 103// the first saved register on prologue is located. (e.g. with a 104// 105// Consider the following function prologue: 106// 107// .frame $fp,48,$ra 108// .mask 0xc0000000,-8 109// addiu $sp, $sp, -48 110// sw $ra, 40($sp) 111// sw $fp, 36($sp) 112// 113// With a 0xc0000000 mask, the assembler knows the register 31 (RA) and 114// 30 (FP) are saved at prologue. As the save order on prologue is from 115// left to right, RA is saved first. A -8 offset means that after the 116// stack pointer subtration, the first register in the mask (RA) will be 117// saved at address 48-8=40. 118// 119//===----------------------------------------------------------------------===// 120 121//===----------------------------------------------------------------------===// 122// Mask directives 123//===----------------------------------------------------------------------===// 124 125// Create a bitmask with all callee saved registers for CPU or Floating Point 126// registers. For CPU registers consider RA, GP and FP for saving if necessary. 127void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) { 128 // CPU and FPU Saved Registers Bitmasks 129 unsigned CPUBitmask = 0, FPUBitmask = 0; 130 int CPUTopSavedRegOff, FPUTopSavedRegOff; 131 132 // Set the CPU and FPU Bitmasks 133 const MachineFrameInfo *MFI = MF->getFrameInfo(); 134 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 135 // size of stack area to which FP callee-saved regs are saved. 136 unsigned CPURegSize = Mips::CPURegsRegClass.getSize(); 137 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize(); 138 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize(); 139 bool HasAFGR64Reg = false; 140 unsigned CSFPRegsSize = 0; 141 unsigned i, e = CSI.size(); 142 143 // Set FPU Bitmask. 144 for (i = 0; i != e; ++i) { 145 unsigned Reg = CSI[i].getReg(); 146 if (Mips::CPURegsRegClass.contains(Reg)) 147 break; 148 149 unsigned RegNum = getMipsRegisterNumbering(Reg); 150 if (Mips::AFGR64RegClass.contains(Reg)) { 151 FPUBitmask |= (3 << RegNum); 152 CSFPRegsSize += AFGR64RegSize; 153 HasAFGR64Reg = true; 154 continue; 155 } 156 157 FPUBitmask |= (1 << RegNum); 158 CSFPRegsSize += FGR32RegSize; 159 } 160 161 // Set CPU Bitmask. 162 for (; i != e; ++i) { 163 unsigned Reg = CSI[i].getReg(); 164 unsigned RegNum = getMipsRegisterNumbering(Reg); 165 CPUBitmask |= (1 << RegNum); 166 } 167 168 // FP Regs are saved right below where the virtual frame pointer points to. 169 FPUTopSavedRegOff = FPUBitmask ? 170 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0; 171 172 // CPU Regs are saved below FP Regs. 173 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0; 174 175 // Print CPUBitmask 176 O << "\t.mask \t"; printHex32(CPUBitmask, O); 177 O << ',' << CPUTopSavedRegOff << '\n'; 178 179 // Print FPUBitmask 180 O << "\t.fmask\t"; printHex32(FPUBitmask, O); 181 O << "," << FPUTopSavedRegOff << '\n'; 182} 183 184// Print a 32 bit hex number with all numbers. 185void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) { 186 O << "0x"; 187 for (int i = 7; i >= 0; i--) 188 O.write_hex((Value & (0xF << (i*4))) >> (i*4)); 189} 190 191//===----------------------------------------------------------------------===// 192// Frame and Set directives 193//===----------------------------------------------------------------------===// 194 195/// Frame Directive 196void MipsAsmPrinter::emitFrameDirective() { 197 const TargetRegisterInfo &RI = *TM.getRegisterInfo(); 198 199 unsigned stackReg = RI.getFrameRegister(*MF); 200 unsigned returnReg = RI.getRARegister(); 201 unsigned stackSize = MF->getFrameInfo()->getStackSize(); 202 203 if (OutStreamer.hasRawTextSupport()) 204 OutStreamer.EmitRawText("\t.frame\t$" + 205 StringRef(MipsInstPrinter::getRegisterName(stackReg)).lower() + 206 "," + Twine(stackSize) + ",$" + 207 StringRef(MipsInstPrinter::getRegisterName(returnReg)).lower()); 208} 209 210/// Emit Set directives. 211const char *MipsAsmPrinter::getCurrentABIString() const { 212 switch (Subtarget->getTargetABI()) { 213 case MipsSubtarget::O32: return "abi32"; 214 case MipsSubtarget::N32: return "abiN32"; 215 case MipsSubtarget::N64: return "abi64"; 216 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64 217 default: llvm_unreachable("Unknown Mips ABI");; 218 } 219} 220 221void MipsAsmPrinter::EmitFunctionEntryLabel() { 222 if (OutStreamer.hasRawTextSupport()) { 223 if (Subtarget->inMips16Mode()) 224 OutStreamer.EmitRawText(StringRef("\t.set\tmips16")); 225 else 226 OutStreamer.EmitRawText(StringRef("\t.set\tnomips16")); 227 // leave out until FSF available gas has micromips changes 228 // OutStreamer.EmitRawText(StringRef("\t.set\tnomicromips")); 229 OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName())); 230 } 231 OutStreamer.EmitLabel(CurrentFnSym); 232} 233 234/// EmitFunctionBodyStart - Targets can override this to emit stuff before 235/// the first basic block in the function. 236void MipsAsmPrinter::EmitFunctionBodyStart() { 237 MCInstLowering.Initialize(Mang, &MF->getContext()); 238 239 emitFrameDirective(); 240 241 if (OutStreamer.hasRawTextSupport()) { 242 SmallString<128> Str; 243 raw_svector_ostream OS(Str); 244 printSavedRegsBitmask(OS); 245 OutStreamer.EmitRawText(OS.str()); 246 247 OutStreamer.EmitRawText(StringRef("\t.set\tnoreorder")); 248 OutStreamer.EmitRawText(StringRef("\t.set\tnomacro")); 249 if (MipsFI->getEmitNOAT()) 250 OutStreamer.EmitRawText(StringRef("\t.set\tnoat")); 251 } 252} 253 254/// EmitFunctionBodyEnd - Targets can override this to emit stuff after 255/// the last basic block in the function. 256void MipsAsmPrinter::EmitFunctionBodyEnd() { 257 // There are instruction for this macros, but they must 258 // always be at the function end, and we can't emit and 259 // break with BB logic. 260 if (OutStreamer.hasRawTextSupport()) { 261 if (MipsFI->getEmitNOAT()) 262 OutStreamer.EmitRawText(StringRef("\t.set\tat")); 263 264 OutStreamer.EmitRawText(StringRef("\t.set\tmacro")); 265 OutStreamer.EmitRawText(StringRef("\t.set\treorder")); 266 OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName())); 267 } 268} 269 270/// isBlockOnlyReachableByFallthough - Return true if the basic block has 271/// exactly one predecessor and the control transfer mechanism between 272/// the predecessor and this block is a fall-through. 273bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock* 274 MBB) const { 275 // The predecessor has to be immediately before this block. 276 const MachineBasicBlock *Pred = *MBB->pred_begin(); 277 278 // If the predecessor is a switch statement, assume a jump table 279 // implementation, so it is not a fall through. 280 if (const BasicBlock *bb = Pred->getBasicBlock()) 281 if (isa<SwitchInst>(bb->getTerminator())) 282 return false; 283 284 // If this is a landing pad, it isn't a fall through. If it has no preds, 285 // then nothing falls through to it. 286 if (MBB->isLandingPad() || MBB->pred_empty()) 287 return false; 288 289 // If there isn't exactly one predecessor, it can't be a fall through. 290 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI; 291 ++PI2; 292 293 if (PI2 != MBB->pred_end()) 294 return false; 295 296 // The predecessor has to be immediately before this block. 297 if (!Pred->isLayoutSuccessor(MBB)) 298 return false; 299 300 // If the block is completely empty, then it definitely does fall through. 301 if (Pred->empty()) 302 return true; 303 304 // Otherwise, check the last instruction. 305 // Check if the last terminator is an unconditional branch. 306 MachineBasicBlock::const_iterator I = Pred->end(); 307 while (I != Pred->begin() && !(--I)->isTerminator()) ; 308 309 return !I->isBarrier(); 310} 311 312// Print out an operand for an inline asm expression. 313bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, 314 unsigned AsmVariant,const char *ExtraCode, 315 raw_ostream &O) { 316 // Does this asm operand have a single letter operand modifier? 317 if (ExtraCode && ExtraCode[0]) { 318 if (ExtraCode[1] != 0) return true; // Unknown modifier. 319 320 const MachineOperand &MO = MI->getOperand(OpNum); 321 switch (ExtraCode[0]) { 322 default: 323 // See if this is a generic print operand 324 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O); 325 case 'X': // hex const int 326 if ((MO.getType()) != MachineOperand::MO_Immediate) 327 return true; 328 O << "0x" << StringRef(utohexstr(MO.getImm())).lower(); 329 return false; 330 case 'x': // hex const int (low 16 bits) 331 if ((MO.getType()) != MachineOperand::MO_Immediate) 332 return true; 333 O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower(); 334 return false; 335 case 'd': // decimal const int 336 if ((MO.getType()) != MachineOperand::MO_Immediate) 337 return true; 338 O << MO.getImm(); 339 return false; 340 case 'm': // decimal const int minus 1 341 if ((MO.getType()) != MachineOperand::MO_Immediate) 342 return true; 343 O << MO.getImm() - 1; 344 return false; 345 case 'z': { 346 // $0 if zero, regular printing otherwise 347 if (MO.getType() != MachineOperand::MO_Immediate) 348 return true; 349 int64_t Val = MO.getImm(); 350 if (Val) 351 O << Val; 352 else 353 O << "$0"; 354 return false; 355 } 356 case 'D': // Second part of a double word register operand 357 case 'L': // Low order register of a double word register operand 358 case 'M': // High order register of a double word register operand 359 { 360 if (OpNum == 0) 361 return true; 362 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1); 363 if (!FlagsOP.isImm()) 364 return true; 365 unsigned Flags = FlagsOP.getImm(); 366 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 367 // Number of registers represented by this operand. We are looking 368 // for 2 for 32 bit mode and 1 for 64 bit mode. 369 if (NumVals != 2) { 370 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) { 371 unsigned Reg = MO.getReg(); 372 O << '$' << MipsInstPrinter::getRegisterName(Reg); 373 return false; 374 } 375 return true; 376 } 377 378 unsigned RegOp = OpNum; 379 if (!Subtarget->isGP64bit()){ 380 // Endianess reverses which register holds the high or low value 381 // between M and L. 382 switch(ExtraCode[0]) { 383 case 'M': 384 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; 385 break; 386 case 'L': 387 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1; 388 break; 389 case 'D': // Always the second part 390 RegOp = OpNum + 1; 391 } 392 if (RegOp >= MI->getNumOperands()) 393 return true; 394 const MachineOperand &MO = MI->getOperand(RegOp); 395 if (!MO.isReg()) 396 return true; 397 unsigned Reg = MO.getReg(); 398 O << '$' << MipsInstPrinter::getRegisterName(Reg); 399 return false; 400 } 401 } 402 } 403 } 404 405 printOperand(MI, OpNum, O); 406 return false; 407} 408 409bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, 410 unsigned OpNum, unsigned AsmVariant, 411 const char *ExtraCode, 412 raw_ostream &O) { 413 if (ExtraCode && ExtraCode[0]) 414 return true; // Unknown modifier. 415 416 const MachineOperand &MO = MI->getOperand(OpNum); 417 assert(MO.isReg() && "unexpected inline asm memory operand"); 418 O << "0($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")"; 419 420 return false; 421} 422 423void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum, 424 raw_ostream &O) { 425 const MachineOperand &MO = MI->getOperand(opNum); 426 bool closeP = false; 427 428 if (MO.getTargetFlags()) 429 closeP = true; 430 431 switch(MO.getTargetFlags()) { 432 case MipsII::MO_GPREL: O << "%gp_rel("; break; 433 case MipsII::MO_GOT_CALL: O << "%call16("; break; 434 case MipsII::MO_GOT: O << "%got("; break; 435 case MipsII::MO_ABS_HI: O << "%hi("; break; 436 case MipsII::MO_ABS_LO: O << "%lo("; break; 437 case MipsII::MO_TLSGD: O << "%tlsgd("; break; 438 case MipsII::MO_GOTTPREL: O << "%gottprel("; break; 439 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break; 440 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break; 441 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break; 442 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break; 443 case MipsII::MO_GOT_DISP: O << "%got_disp("; break; 444 case MipsII::MO_GOT_PAGE: O << "%got_page("; break; 445 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break; 446 } 447 448 switch (MO.getType()) { 449 case MachineOperand::MO_Register: 450 O << '$' 451 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower(); 452 break; 453 454 case MachineOperand::MO_Immediate: 455 O << MO.getImm(); 456 break; 457 458 case MachineOperand::MO_MachineBasicBlock: 459 O << *MO.getMBB()->getSymbol(); 460 return; 461 462 case MachineOperand::MO_GlobalAddress: 463 O << *Mang->getSymbol(MO.getGlobal()); 464 break; 465 466 case MachineOperand::MO_BlockAddress: { 467 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress()); 468 O << BA->getName(); 469 break; 470 } 471 472 case MachineOperand::MO_ExternalSymbol: 473 O << *GetExternalSymbolSymbol(MO.getSymbolName()); 474 break; 475 476 case MachineOperand::MO_JumpTableIndex: 477 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() 478 << '_' << MO.getIndex(); 479 break; 480 481 case MachineOperand::MO_ConstantPoolIndex: 482 O << MAI->getPrivateGlobalPrefix() << "CPI" 483 << getFunctionNumber() << "_" << MO.getIndex(); 484 if (MO.getOffset()) 485 O << "+" << MO.getOffset(); 486 break; 487 488 default: 489 llvm_unreachable("<unknown operand type>"); 490 } 491 492 if (closeP) O << ")"; 493} 494 495void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum, 496 raw_ostream &O) { 497 const MachineOperand &MO = MI->getOperand(opNum); 498 if (MO.isImm()) 499 O << (unsigned short int)MO.getImm(); 500 else 501 printOperand(MI, opNum, O); 502} 503 504void MipsAsmPrinter:: 505printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) { 506 // Load/Store memory operands -- imm($reg) 507 // If PIC target the target is loaded as the 508 // pattern lw $25,%call16($28) 509 printOperand(MI, opNum+1, O); 510 O << "("; 511 printOperand(MI, opNum, O); 512 O << ")"; 513} 514 515void MipsAsmPrinter:: 516printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) { 517 // when using stack locations for not load/store instructions 518 // print the same way as all normal 3 operand instructions. 519 printOperand(MI, opNum, O); 520 O << ", "; 521 printOperand(MI, opNum+1, O); 522 return; 523} 524 525void MipsAsmPrinter:: 526printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, 527 const char *Modifier) { 528 const MachineOperand &MO = MI->getOperand(opNum); 529 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm()); 530} 531 532void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) { 533 // FIXME: Use SwitchSection. 534 535 // Tell the assembler which ABI we are using 536 if (OutStreamer.hasRawTextSupport()) 537 OutStreamer.EmitRawText("\t.section .mdebug." + 538 Twine(getCurrentABIString())); 539 540 // TODO: handle O64 ABI 541 if (OutStreamer.hasRawTextSupport()) { 542 if (Subtarget->isABI_EABI()) { 543 if (Subtarget->isGP32bit()) 544 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32")); 545 else 546 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64")); 547 } 548 } 549 550 // return to previous section 551 if (OutStreamer.hasRawTextSupport()) 552 OutStreamer.EmitRawText(StringRef("\t.previous")); 553} 554 555MachineLocation 556MipsAsmPrinter::getDebugValueLocation(const MachineInstr *MI) const { 557 // Handles frame addresses emitted in MipsInstrInfo::emitFrameIndexDebugValue. 558 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!"); 559 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() && 560 "Unexpected MachineOperand types"); 561 return MachineLocation(MI->getOperand(0).getReg(), 562 MI->getOperand(1).getImm()); 563} 564 565void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI, 566 raw_ostream &OS) { 567 // TODO: implement 568} 569 570// Force static initialization. 571extern "C" void LLVMInitializeMipsAsmPrinter() { 572 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget); 573 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget); 574 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target); 575 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget); 576} 577