MipsDSPInstrFormats.td revision 01f7089bca51744226306e09db4954e3df02b3be
1e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng//===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===// 2e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng// 3e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng// The LLVM Compiler Infrastructure 4e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng// 5e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng// This file is distributed under the University of Illinois Open Source 6e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng// License. See LICENSE.TXT for details. 7e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng// 8e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng//===----------------------------------------------------------------------===// 9e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng 10e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Chengdef HasDSP : Predicate<"Subtarget.hasDSP()">, 11e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng AssemblerPredicate<"FeatureDSP">; 12e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Chengdef HasDSPR2 : Predicate<"Subtarget.hasDSPR2()">, 13e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng AssemblerPredicate<"FeatureDSPR2">; 14e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng 15e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng// Fields. 16e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Chengclass Field6<bits<6> val> { 17e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng bits<6> V = val; 18e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng} 19e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng 20e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Chengdef SPECIAL3_OPCODE : Field6<0b011111>; 21e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Chengdef REGIMM_OPCODE : Field6<0b000001>; 22e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng 23e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Chengclass DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> { 24e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng let Predicates = [HasDSP]; 25e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng} 26e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng 27e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Chengclass PseudoDSP<dag outs, dag ins, list<dag> pattern>: 28e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng MipsPseudo<outs, ins, "", pattern> { 29e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng let Predicates = [HasDSP]; 30e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng} 31e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng 32e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng// DPA.W.PH sub-class format. 33e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Chengclass DPA_W_PH_FMT<bits<5> op> : DSPInst { 34e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng bits<2> ac; 35e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng bits<5> rs; 36e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng bits<5> rt; 37e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng 38e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng let Opcode = SPECIAL3_OPCODE.V; 39e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng 40e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng let Inst{25-21} = rs; 41e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng let Inst{20-16} = rt; 42e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng let Inst{15-13} = 0; 43 let Inst{12-11} = ac; 44 let Inst{10-6} = op; 45 let Inst{5-0} = 0b110000; 46} 47 48// MULT sub-class format. 49class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst { 50 bits<2> ac; 51 bits<5> rs; 52 bits<5> rt; 53 54 let Opcode = opcode; 55 56 let Inst{25-21} = rs; 57 let Inst{20-16} = rt; 58 let Inst{15-13} = 0; 59 let Inst{12-11} = ac; 60 let Inst{10-6} = 0; 61 let Inst{5-0} = funct; 62} 63 64// EXTR.W sub-class format (type 1). 65class EXTR_W_TY1_FMT<bits<5> op> : DSPInst { 66 bits<5> rt; 67 bits<2> ac; 68 bits<5> shift_rs; 69 70 let Opcode = SPECIAL3_OPCODE.V; 71 72 let Inst{25-21} = shift_rs; 73 let Inst{20-16} = rt; 74 let Inst{15-13} = 0; 75 let Inst{12-11} = ac; 76 let Inst{10-6} = op; 77 let Inst{5-0} = 0b111000; 78} 79 80// SHILO sub-class format. 81class SHILO_R1_FMT<bits<5> op> : DSPInst { 82 bits<2> ac; 83 bits<6> shift; 84 85 let Opcode = SPECIAL3_OPCODE.V; 86 87 let Inst{25-20} = shift; 88 let Inst{19-13} = 0; 89 let Inst{12-11} = ac; 90 let Inst{10-6} = op; 91 let Inst{5-0} = 0b111000; 92} 93 94class SHILO_R2_FMT<bits<5> op> : DSPInst { 95 bits<2> ac; 96 bits<5> rs; 97 98 let Opcode = SPECIAL3_OPCODE.V; 99 100 let Inst{25-21} = rs; 101 let Inst{20-13} = 0; 102 let Inst{12-11} = ac; 103 let Inst{10-6} = op; 104 let Inst{5-0} = 0b111000; 105} 106 107class BPOSGE32_FMT<bits<5> op> : DSPInst { 108 bits<16> offset; 109 110 let Opcode = REGIMM_OPCODE.V; 111 112 let Inst{25-21} = 0; 113 let Inst{20-16} = op; 114 let Inst{15-0} = offset; 115} 116