MipsDSPInstrFormats.td revision 2df483efb3a3d99dd82eb88e13490ae464bf0e43 
1//===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10def HasDSP : Predicate<"Subtarget.hasDSP()">,
11             AssemblerPredicate<"FeatureDSP">;
12def HasDSPR2 : Predicate<"Subtarget.hasDSPR2()">,
13               AssemblerPredicate<"FeatureDSPR2">;
14
15// Fields.
16class Field6<bits<6> val> {
17  bits<6> V = val;
18}
19
20def SPECIAL3_OPCODE : Field6<0b011111>;
21def REGIMM_OPCODE : Field6<0b000001>;
22
23class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
24  let Predicates = [HasDSP];
25}
26
27class PseudoDSP<dag outs, dag ins, list<dag> pattern>:
28  MipsPseudo<outs, ins, "", pattern> {
29  let Predicates = [HasDSP];
30}
31
32// DPA.W.PH sub-class format.
33class DPA_W_PH_FMT<bits<5> op> : DSPInst {
34  bits<2> ac;
35  bits<5> rs;
36  bits<5> rt;
37
38  let Opcode = SPECIAL3_OPCODE.V;
39
40  let Inst{25-21} = rs;
41  let Inst{20-16} = rt;
42  let Inst{15-13} = 0;
43  let Inst{12-11} = ac;
44  let Inst{10-6}  = op;
45  let Inst{5-0} = 0b110000;
46}
47
48// MULT sub-class format.
49class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst {
50  bits<2> ac;
51  bits<5> rs;
52  bits<5> rt;
53
54  let Opcode = opcode;
55
56  let Inst{25-21} = rs;
57  let Inst{20-16} = rt;
58  let Inst{15-13} = 0;
59  let Inst{12-11} = ac;
60  let Inst{10-6}  = 0;
61  let Inst{5-0} = funct;
62}
63
64// EXTR.W sub-class format (type 1).
65class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
66  bits<5> rt;
67  bits<2> ac;
68  bits<5> shift_rs;
69
70  let Opcode = SPECIAL3_OPCODE.V;
71
72  let Inst{25-21} = shift_rs;
73  let Inst{20-16} = rt;
74  let Inst{15-13} = 0;
75  let Inst{12-11} = ac;
76  let Inst{10-6} = op;
77  let Inst{5-0} = 0b111000;
78}
79
80// SHILO sub-class format.
81class SHILO_R1_FMT<bits<5> op> : DSPInst {
82  bits<2> ac;
83  bits<6> shift;
84
85  let Opcode = SPECIAL3_OPCODE.V;
86
87  let Inst{25-20} = shift;
88  let Inst{19-13} = 0;
89  let Inst{12-11} = ac;
90  let Inst{10-6} = op;
91  let Inst{5-0} = 0b111000;
92}
93
94class SHILO_R2_FMT<bits<5> op> : DSPInst {
95  bits<2> ac;
96  bits<5> rs;
97
98  let Opcode = SPECIAL3_OPCODE.V;
99
100  let Inst{25-21} = rs;
101  let Inst{20-13} = 0;
102  let Inst{12-11} = ac;
103  let Inst{10-6} = op;
104  let Inst{5-0} = 0b111000;
105}
106