MipsDSPInstrFormats.td revision cb39aa05afd52f017869ce5399652223626da7b7 
1//===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10def HasDSP : Predicate<"Subtarget.hasDSP()">,
11             AssemblerPredicate<"FeatureDSP">;
12def HasDSPR2 : Predicate<"Subtarget.hasDSPR2()">,
13               AssemblerPredicate<"FeatureDSPR2">;
14
15// Fields.
16class Field6<bits<6> val> {
17  bits<6> V = val;
18}
19
20def SPECIAL3_OPCODE : Field6<0b011111>;
21def REGIMM_OPCODE : Field6<0b000001>;
22
23class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
24  let Predicates = [HasDSP];
25}
26
27class PseudoDSP<dag outs, dag ins, list<dag> pattern>:
28  MipsPseudo<outs, ins, "", pattern> {
29  let Predicates = [HasDSP];
30}
31
32// ADDU.QB sub-class format.
33class ADDU_QB_FMT<bits<5> op> : DSPInst {
34  bits<5> rd;
35  bits<5> rs;
36  bits<5> rt;
37
38  let Opcode = SPECIAL3_OPCODE.V;
39
40  let Inst{25-21} = rs;
41  let Inst{20-16} = rt;
42  let Inst{15-11} = rd;
43  let Inst{10-6}  = op;
44  let Inst{5-0}   = 0b010000;
45}
46
47class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
48  bits<5> rd;
49  bits<5> rs;
50
51  let Opcode = SPECIAL3_OPCODE.V;
52
53  let Inst{25-21} = rs;
54  let Inst{20-16} = 0;
55  let Inst{15-11} = rd;
56  let Inst{10-6}  = op;
57  let Inst{5-0}   = 0b010000;
58}
59
60// CMPU.EQ.QB sub-class format.
61class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
62  bits<5> rs;
63  bits<5> rt;
64
65  let Opcode = SPECIAL3_OPCODE.V;
66
67  let Inst{25-21} = rs;
68  let Inst{20-16} = rt;
69  let Inst{15-11} = 0;
70  let Inst{10-6}  = op;
71  let Inst{5-0}   = 0b010001;
72}
73
74class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst {
75  bits<5> rs;
76  bits<5> rt;
77  bits<5> rd;
78
79  let Opcode = SPECIAL3_OPCODE.V;
80
81  let Inst{25-21} = rs;
82  let Inst{20-16} = rt;
83  let Inst{15-11} = rd;
84  let Inst{10-6}  = op;
85  let Inst{5-0}   = 0b010001;
86}
87
88class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
89  bits<5> rs;
90  bits<5> rt;
91  bits<5> sa;
92
93  let Opcode = SPECIAL3_OPCODE.V;
94
95  let Inst{25-21} = rs;
96  let Inst{20-16} = rt;
97  let Inst{15-11} = sa;
98  let Inst{10-6}  = op;
99  let Inst{5-0}   = 0b010001;
100}
101
102// ABSQ_S.PH sub-class format.
103class ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst {
104  bits<5> rd;
105  bits<5> rt;
106
107  let Opcode = SPECIAL3_OPCODE.V;
108
109  let Inst{25-21} = 0;
110  let Inst{20-16} = rt;
111  let Inst{15-11} = rd;
112  let Inst{10-6}  = op;
113  let Inst{5-0}   = 0b010010;
114}
115
116
117class REPL_FMT<bits<5> op> : DSPInst {
118  bits<5> rd;
119  bits<10> imm;
120
121  let Opcode = SPECIAL3_OPCODE.V;
122
123  let Inst{25-16} = imm;
124  let Inst{15-11} = rd;
125  let Inst{10-6}  = op;
126  let Inst{5-0}   = 0b010010;
127}
128
129// SHLL.QB sub-class format.
130class SHLL_QB_FMT<bits<5> op> : DSPInst {
131  bits<5> rd;
132  bits<5> rt;
133  bits<5> rs_sa;
134
135  let Opcode = SPECIAL3_OPCODE.V;
136
137  let Inst{25-21} = rs_sa;
138  let Inst{20-16} = rt;
139  let Inst{15-11} = rd;
140  let Inst{10-6}  = op;
141  let Inst{5-0}   = 0b010011;
142}
143
144// DPA.W.PH sub-class format.
145class DPA_W_PH_FMT<bits<5> op> : DSPInst {
146  bits<2> ac;
147  bits<5> rs;
148  bits<5> rt;
149
150  let Opcode = SPECIAL3_OPCODE.V;
151
152  let Inst{25-21} = rs;
153  let Inst{20-16} = rt;
154  let Inst{15-13} = 0;
155  let Inst{12-11} = ac;
156  let Inst{10-6}  = op;
157  let Inst{5-0} = 0b110000;
158}
159
160// MULT sub-class format.
161class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst {
162  bits<2> ac;
163  bits<5> rs;
164  bits<5> rt;
165
166  let Opcode = opcode;
167
168  let Inst{25-21} = rs;
169  let Inst{20-16} = rt;
170  let Inst{15-13} = 0;
171  let Inst{12-11} = ac;
172  let Inst{10-6}  = 0;
173  let Inst{5-0} = funct;
174}
175
176// EXTR.W sub-class format (type 1).
177class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
178  bits<5> rt;
179  bits<2> ac;
180  bits<5> shift_rs;
181
182  let Opcode = SPECIAL3_OPCODE.V;
183
184  let Inst{25-21} = shift_rs;
185  let Inst{20-16} = rt;
186  let Inst{15-13} = 0;
187  let Inst{12-11} = ac;
188  let Inst{10-6} = op;
189  let Inst{5-0} = 0b111000;
190}
191
192// SHILO sub-class format.
193class SHILO_R1_FMT<bits<5> op> : DSPInst {
194  bits<2> ac;
195  bits<6> shift;
196
197  let Opcode = SPECIAL3_OPCODE.V;
198
199  let Inst{25-20} = shift;
200  let Inst{19-13} = 0;
201  let Inst{12-11} = ac;
202  let Inst{10-6} = op;
203  let Inst{5-0} = 0b111000;
204}
205
206class SHILO_R2_FMT<bits<5> op> : DSPInst {
207  bits<2> ac;
208  bits<5> rs;
209
210  let Opcode = SPECIAL3_OPCODE.V;
211
212  let Inst{25-21} = rs;
213  let Inst{20-13} = 0;
214  let Inst{12-11} = ac;
215  let Inst{10-6} = op;
216  let Inst{5-0} = 0b111000;
217}
218
219class RDDSP_FMT<bits<5> op> : DSPInst {
220  bits<5> rd;
221  bits<10> mask;
222
223  let Opcode = SPECIAL3_OPCODE.V;
224
225  let Inst{25-16} = mask;
226  let Inst{15-11} = rd;
227  let Inst{10-6} = op;
228  let Inst{5-0} = 0b111000;
229}
230
231class BPOSGE32_FMT<bits<5> op> : DSPInst {
232  bits<16> offset;
233
234  let Opcode = REGIMM_OPCODE.V;
235
236  let Inst{25-21} = 0;
237  let Inst{20-16} = op;
238  let Inst{15-0} = offset;
239}
240