MipsISelDAGToDAG.cpp revision 3011a33a63b055fc3c0bba51728e13c8b0f1c20e 
1//===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the MIPS target.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mips-isel"
15#include "Mips.h"
16#include "MipsAnalyzeImmediate.h"
17#include "MipsMachineFunction.h"
18#include "MipsRegisterInfo.h"
19#include "MipsSubtarget.h"
20#include "MipsTargetMachine.h"
21#include "MCTargetDesc/MipsBaseInfo.h"
22#include "llvm/GlobalValue.h"
23#include "llvm/Instructions.h"
24#include "llvm/Intrinsics.h"
25#include "llvm/Support/CFG.h"
26#include "llvm/Type.h"
27#include "llvm/CodeGen/MachineConstantPool.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/SelectionDAGNodes.h"
34#include "llvm/Target/TargetMachine.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38using namespace llvm;
39
40//===----------------------------------------------------------------------===//
41// Instruction Selector Implementation
42//===----------------------------------------------------------------------===//
43
44//===----------------------------------------------------------------------===//
45// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
46// instructions for SelectionDAG operations.
47//===----------------------------------------------------------------------===//
48namespace {
49
50class MipsDAGToDAGISel : public SelectionDAGISel {
51
52  /// TM - Keep a reference to MipsTargetMachine.
53  MipsTargetMachine &TM;
54
55  /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
56  /// make the right decision when generating code for different targets.
57  const MipsSubtarget &Subtarget;
58
59public:
60  explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
61  SelectionDAGISel(tm),
62  TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
63
64  // Pass Name
65  virtual const char *getPassName() const {
66    return "MIPS DAG->DAG Pattern Instruction Selection";
67  }
68
69  virtual bool runOnMachineFunction(MachineFunction &MF);
70
71private:
72  // Include the pieces autogenerated from the target description.
73  #include "MipsGenDAGISel.inc"
74
75  /// getTargetMachine - Return a reference to the TargetMachine, casted
76  /// to the target-specific type.
77  const MipsTargetMachine &getTargetMachine() {
78    return static_cast<const MipsTargetMachine &>(TM);
79  }
80
81  /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
82  /// to the target-specific type.
83  const MipsInstrInfo *getInstrInfo() {
84    return getTargetMachine().getInstrInfo();
85  }
86
87  SDNode *getGlobalBaseReg();
88
89  std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl,
90                                         EVT Ty, bool HasLo, bool HasHi);
91
92  SDNode *Select(SDNode *N);
93
94  // Complex Pattern.
95  bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset);
96
97  // getImm - Return a target constant with the specified value.
98  inline SDValue getImm(const SDNode *Node, unsigned Imm) {
99    return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
100  }
101
102  void ProcessFunctionAfterISel(MachineFunction &MF);
103  bool ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);
104  void InitGlobalBaseReg(MachineFunction &MF);
105
106  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
107                                            char ConstraintCode,
108                                            std::vector<SDValue> &OutOps);
109};
110
111}
112
113// Insert instructions to initialize the global base register in the
114// first MBB of the function. When the ABI is O32 and the relocation model is
115// PIC, the necessary instructions are emitted later to prevent optimization
116// passes from moving them.
117void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
118  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
119
120  if (!MipsFI->globalBaseRegSet())
121    return;
122
123  MachineBasicBlock &MBB = MF.front();
124  MachineBasicBlock::iterator I = MBB.begin();
125  MachineRegisterInfo &RegInfo = MF.getRegInfo();
126  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
127  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
128  unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
129  bool FixGlobalBaseReg = MipsFI->globalBaseRegFixed();
130
131  if (Subtarget.isABI_O32() && FixGlobalBaseReg)
132    // $gp is the global base register.
133    V0 = V1 = GlobalBaseReg;
134  else {
135    const TargetRegisterClass *RC;
136    RC = Subtarget.isABI_N64() ?
137      (const TargetRegisterClass*)&Mips::CPU64RegsRegClass :
138      (const TargetRegisterClass*)&Mips::CPURegsRegClass;
139
140    V0 = RegInfo.createVirtualRegister(RC);
141    V1 = RegInfo.createVirtualRegister(RC);
142  }
143
144  if (Subtarget.isABI_N64()) {
145    MF.getRegInfo().addLiveIn(Mips::T9_64);
146    MBB.addLiveIn(Mips::T9_64);
147
148    // lui $v0, %hi(%neg(%gp_rel(fname)))
149    // daddu $v1, $v0, $t9
150    // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
151    const GlobalValue *FName = MF.getFunction();
152    BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
153      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
154    BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0).addReg(Mips::T9_64);
155    BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
156      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
157  } else if (MF.getTarget().getRelocationModel() == Reloc::Static) {
158    // Set global register to __gnu_local_gp.
159    //
160    // lui   $v0, %hi(__gnu_local_gp)
161    // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
162    BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
163      .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
164    BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
165      .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
166  } else {
167    MF.getRegInfo().addLiveIn(Mips::T9);
168    MBB.addLiveIn(Mips::T9);
169
170    if (Subtarget.isABI_N32()) {
171      // lui $v0, %hi(%neg(%gp_rel(fname)))
172      // addu $v1, $v0, $t9
173      // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
174      const GlobalValue *FName = MF.getFunction();
175      BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
176        .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
177      BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
178      BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
179        .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
180    } else if (!MipsFI->globalBaseRegFixed()) {
181      assert(Subtarget.isABI_O32());
182
183      BuildMI(MBB, I, DL, TII.get(Mips::SETGP2), GlobalBaseReg)
184        .addReg(Mips::T9);
185    }
186  }
187}
188
189bool MipsDAGToDAGISel::ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI,
190                                              const MachineInstr& MI) {
191  unsigned DstReg = 0, ZeroReg = 0;
192
193  // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
194  if ((MI.getOpcode() == Mips::ADDiu) &&
195      (MI.getOperand(1).getReg() == Mips::ZERO) &&
196      (MI.getOperand(2).getImm() == 0)) {
197    DstReg = MI.getOperand(0).getReg();
198    ZeroReg = Mips::ZERO;
199  } else if ((MI.getOpcode() == Mips::DADDiu) &&
200             (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
201             (MI.getOperand(2).getImm() == 0)) {
202    DstReg = MI.getOperand(0).getReg();
203    ZeroReg = Mips::ZERO_64;
204  }
205
206  if (!DstReg)
207    return false;
208
209  // Replace uses with ZeroReg.
210  for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
211       E = MRI->use_end(); U != E; ++U) {
212    MachineOperand &MO = U.getOperand();
213    MachineInstr *MI = MO.getParent();
214
215    // Do not replace if it is a phi's operand or is tied to def operand.
216    if (MI->isPHI() || MI->isRegTiedToDefOperand(U.getOperandNo()) ||
217        MI->isPseudo())
218      continue;
219
220    MO.setReg(ZeroReg);
221  }
222
223  return true;
224}
225
226void MipsDAGToDAGISel::ProcessFunctionAfterISel(MachineFunction &MF) {
227  InitGlobalBaseReg(MF);
228
229  MachineRegisterInfo *MRI = &MF.getRegInfo();
230
231  for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
232       ++MFI)
233    for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I)
234      ReplaceUsesWithZeroReg(MRI, *I);
235}
236
237bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
238  bool Ret = SelectionDAGISel::runOnMachineFunction(MF);
239
240  ProcessFunctionAfterISel(MF);
241
242  return Ret;
243}
244
245/// getGlobalBaseReg - Output the instructions required to put the
246/// GOT address into a register.
247SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
248  unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
249  return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
250}
251
252/// ComplexPattern used on MipsInstrInfo
253/// Used on Mips Load/Store instructions
254bool MipsDAGToDAGISel::
255SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
256  EVT ValTy = Addr.getValueType();
257
258  // If Parent is an unaligned f32 load or store, select a (base + index)
259  // floating point load/store instruction (luxc1 or suxc1).
260  const LSBaseSDNode* LS = 0;
261
262  if (Parent && (LS = dyn_cast<LSBaseSDNode>(Parent))) {
263    EVT VT = LS->getMemoryVT();
264
265    if (VT.getSizeInBits() / 8 > LS->getAlignment()) {
266      assert(TLI.allowsUnalignedMemoryAccesses(VT) &&
267             "Unaligned loads/stores not supported for this type.");
268      if (VT == MVT::f32)
269        return false;
270    }
271  }
272
273  // if Address is FI, get the TargetFrameIndex.
274  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
275    Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
276    Offset = CurDAG->getTargetConstant(0, ValTy);
277    return true;
278  }
279
280  // on PIC code Load GA
281  if (Addr.getOpcode() == MipsISD::Wrapper) {
282    Base   = Addr.getOperand(0);
283    Offset = Addr.getOperand(1);
284    return true;
285  }
286
287  if (TM.getRelocationModel() != Reloc::PIC_) {
288    if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
289        Addr.getOpcode() == ISD::TargetGlobalAddress))
290      return false;
291  }
292
293  // Addresses of the form FI+const or FI|const
294  if (CurDAG->isBaseWithConstantOffset(Addr)) {
295    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
296    if (isInt<16>(CN->getSExtValue())) {
297
298      // If the first operand is a FI, get the TargetFI Node
299      if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
300                                  (Addr.getOperand(0)))
301        Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
302      else
303        Base = Addr.getOperand(0);
304
305      Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
306      return true;
307    }
308  }
309
310  // Operand is a result from an ADD.
311  if (Addr.getOpcode() == ISD::ADD) {
312    // When loading from constant pools, load the lower address part in
313    // the instruction itself. Example, instead of:
314    //  lui $2, %hi($CPI1_0)
315    //  addiu $2, $2, %lo($CPI1_0)
316    //  lwc1 $f0, 0($2)
317    // Generate:
318    //  lui $2, %hi($CPI1_0)
319    //  lwc1 $f0, %lo($CPI1_0)($2)
320    if (Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
321      SDValue LoVal = Addr.getOperand(1);
322      if (isa<ConstantPoolSDNode>(LoVal.getOperand(0)) ||
323          isa<GlobalAddressSDNode>(LoVal.getOperand(0))) {
324        Base = Addr.getOperand(0);
325        Offset = LoVal.getOperand(0);
326        return true;
327      }
328    }
329
330    // If an indexed floating point load/store can be emitted, return false.
331    if (LS && (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
332        Subtarget.hasMips32r2Or64())
333      return false;
334  }
335
336  Base   = Addr;
337  Offset = CurDAG->getTargetConstant(0, ValTy);
338  return true;
339}
340
341/// Select multiply instructions.
342std::pair<SDNode*, SDNode*>
343MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty,
344                             bool HasLo, bool HasHi) {
345  SDNode *Lo = 0, *Hi = 0;
346  SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0),
347                                       N->getOperand(1));
348  SDValue InFlag = SDValue(Mul, 0);
349
350  if (HasLo) {
351    Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl,
352                                Ty, MVT::Glue, InFlag);
353    InFlag = SDValue(Lo, 1);
354  }
355  if (HasHi)
356    Hi = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64, dl,
357                                Ty, InFlag);
358
359  return std::make_pair(Lo, Hi);
360}
361
362
363/// Select instructions not customized! Used for
364/// expanded, promoted and normal instructions
365SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
366  unsigned Opcode = Node->getOpcode();
367  DebugLoc dl = Node->getDebugLoc();
368
369  // Dump information about the Node being selected
370  DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
371
372  // If we have a custom node, we already have selected!
373  if (Node->isMachineOpcode()) {
374    DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
375    return NULL;
376  }
377
378  ///
379  // Instruction Selection not handled by the auto-generated
380  // tablegen selection should be handled here.
381  ///
382  EVT NodeTy = Node->getValueType(0);
383  unsigned MultOpc;
384
385  switch(Opcode) {
386  default: break;
387
388  case ISD::SUBE:
389  case ISD::ADDE: {
390    SDValue InFlag = Node->getOperand(2), CmpLHS;
391    unsigned Opc = InFlag.getOpcode(); (void)Opc;
392    assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
393            (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
394           "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
395
396    unsigned MOp;
397    if (Opcode == ISD::ADDE) {
398      CmpLHS = InFlag.getValue(0);
399      MOp = Mips::ADDu;
400    } else {
401      CmpLHS = InFlag.getOperand(0);
402      MOp = Mips::SUBu;
403    }
404
405    SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
406
407    SDValue LHS = Node->getOperand(0);
408    SDValue RHS = Node->getOperand(1);
409
410    EVT VT = LHS.getValueType();
411    SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
412    SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
413                                              SDValue(Carry,0), RHS);
414
415    return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
416                                LHS, SDValue(AddCarry,0));
417  }
418
419  /// Mul with two results
420  case ISD::SMUL_LOHI:
421  case ISD::UMUL_LOHI: {
422    if (NodeTy == MVT::i32)
423      MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
424    else
425      MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
426
427    std::pair<SDNode*, SDNode*> LoHi = SelectMULT(Node, MultOpc, dl, NodeTy,
428                                                  true, true);
429
430    if (!SDValue(Node, 0).use_empty())
431      ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
432
433    if (!SDValue(Node, 1).use_empty())
434      ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
435
436    return NULL;
437  }
438
439  /// Special Muls
440  case ISD::MUL: {
441    // Mips32 has a 32-bit three operand mul instruction.
442    if (Subtarget.hasMips32() && NodeTy == MVT::i32)
443      break;
444    return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT,
445                      dl, NodeTy, true, false).first;
446  }
447  case ISD::MULHS:
448  case ISD::MULHU: {
449    if (NodeTy == MVT::i32)
450      MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
451    else
452      MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
453
454    return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;
455  }
456
457  // Get target GOT address.
458  case ISD::GLOBAL_OFFSET_TABLE:
459    return getGlobalBaseReg();
460
461  case ISD::ConstantFP: {
462    ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
463    if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
464      if (Subtarget.hasMips64()) {
465        SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
466                                              Mips::ZERO_64, MVT::i64);
467        return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
468      }
469
470      SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
471                                            Mips::ZERO, MVT::i32);
472      return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
473                                    Zero);
474    }
475    break;
476  }
477
478  case ISD::Constant: {
479    const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
480    unsigned Size = CN->getValueSizeInBits(0);
481
482    if (Size == 32)
483      break;
484
485    MipsAnalyzeImmediate AnalyzeImm;
486    int64_t Imm = CN->getSExtValue();
487
488    const MipsAnalyzeImmediate::InstSeq &Seq =
489      AnalyzeImm.Analyze(Imm, Size, false);
490
491    MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
492    DebugLoc DL = CN->getDebugLoc();
493    SDNode *RegOpnd;
494    SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
495                                                MVT::i64);
496
497    // The first instruction can be a LUi which is different from other
498    // instructions (ADDiu, ORI and SLL) in that it does not have a register
499    // operand.
500    if (Inst->Opc == Mips::LUi64)
501      RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
502    else
503      RegOpnd =
504        CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
505                               CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
506                               ImmOpnd);
507
508    // The remaining instructions in the sequence are handled here.
509    for (++Inst; Inst != Seq.end(); ++Inst) {
510      ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
511                                          MVT::i64);
512      RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
513                                       SDValue(RegOpnd, 0), ImmOpnd);
514    }
515
516    return RegOpnd;
517  }
518
519  case MipsISD::ThreadPointer: {
520    EVT PtrVT = TLI.getPointerTy();
521    unsigned RdhwrOpc, SrcReg, DestReg;
522
523    if (PtrVT == MVT::i32) {
524      RdhwrOpc = Mips::RDHWR;
525      SrcReg = Mips::HWR29;
526      DestReg = Mips::V1;
527    } else {
528      RdhwrOpc = Mips::RDHWR64;
529      SrcReg = Mips::HWR29_64;
530      DestReg = Mips::V1_64;
531    }
532
533    SDNode *Rdhwr =
534      CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
535                             Node->getValueType(0),
536                             CurDAG->getRegister(SrcReg, PtrVT));
537    SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
538                                         SDValue(Rdhwr, 0));
539    SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
540    ReplaceUses(SDValue(Node, 0), ResNode);
541    return ResNode.getNode();
542  }
543  }
544
545  // Select the default instruction
546  SDNode *ResNode = SelectCode(Node);
547
548  DEBUG(errs() << "=> ");
549  if (ResNode == NULL || ResNode == Node)
550    DEBUG(Node->dump(CurDAG));
551  else
552    DEBUG(ResNode->dump(CurDAG));
553  DEBUG(errs() << "\n");
554  return ResNode;
555}
556
557bool MipsDAGToDAGISel::
558SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
559                             std::vector<SDValue> &OutOps) {
560  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
561  OutOps.push_back(Op);
562  return false;
563}
564
565/// createMipsISelDag - This pass converts a legalized DAG into a
566/// MIPS-specific DAG, ready for instruction scheduling.
567FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
568  return new MipsDAGToDAGISel(TM);
569}
570