MipsISelDAGToDAG.cpp revision 3ee306cbc0a295409c464ffaad5ef694de8eb09a
190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)//===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===// 290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)// 390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)// The LLVM Compiler Infrastructure 490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)// 590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)// This file is distributed under the University of Illinois Open Source 690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)// License. See LICENSE.TXT for details. 790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)// 890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)//===----------------------------------------------------------------------===// 990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)// 1090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)// This file defines an instruction selector for the MIPS target. 1190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)// 12868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)//===----------------------------------------------------------------------===// 1390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 1490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#define DEBUG_TYPE "mips-isel" 1590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "Mips.h" 1690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "MipsAnalyzeImmediate.h" 1790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "MipsMachineFunction.h" 1890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "MipsRegisterInfo.h" 197d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles)#include "MipsSubtarget.h" 207d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles)#include "MipsTargetMachine.h" 217d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles)#include "MCTargetDesc/MipsBaseInfo.h" 227d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles)#include "llvm/GlobalValue.h" 237d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles)#include "llvm/Instructions.h" 247d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles)#include "llvm/Intrinsics.h" 2590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "llvm/Support/CFG.h" 2690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "llvm/Type.h" 2790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "llvm/CodeGen/MachineConstantPool.h" 2890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "llvm/CodeGen/MachineFunction.h" 2990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "llvm/CodeGen/MachineFrameInfo.h" 3090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "llvm/CodeGen/MachineInstrBuilder.h" 3190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "llvm/CodeGen/MachineRegisterInfo.h" 3290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "llvm/CodeGen/SelectionDAGISel.h" 3390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "llvm/CodeGen/SelectionDAGNodes.h" 3490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "llvm/Target/TargetMachine.h" 3590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "llvm/Support/Debug.h" 3690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "llvm/Support/ErrorHandling.h" 3790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "llvm/Support/raw_ostream.h" 3890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)using namespace llvm; 3990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 4090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)//===----------------------------------------------------------------------===// 4190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)// Instruction Selector Implementation 4290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)//===----------------------------------------------------------------------===// 4390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 44868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)//===----------------------------------------------------------------------===// 45868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)// MipsDAGToDAGISel - MIPS specific code to select MIPS machine 4690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)// instructions for SelectionDAG operations. 4790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)//===----------------------------------------------------------------------===// 4890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)namespace { 4990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 5090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)class MipsDAGToDAGISel : public SelectionDAGISel { 5190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 5290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// TM - Keep a reference to MipsTargetMachine. 5390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) MipsTargetMachine &TM; 5490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 5590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can 5690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// make the right decision when generating code for different targets. 5790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) const MipsSubtarget &Subtarget; 5890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 5990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)public: 6090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) explicit MipsDAGToDAGISel(MipsTargetMachine &tm) : 6190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) SelectionDAGISel(tm), 6290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {} 6390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 6490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) // Pass Name 6590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) virtual const char *getPassName() const { 6690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) return "MIPS DAG->DAG Pattern Instruction Selection"; 6790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) } 6890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 6990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) virtual bool runOnMachineFunction(MachineFunction &MF); 7090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 7190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)private: 7290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) // Include the pieces autogenerated from the target description. 7390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) #include "MipsGenDAGISel.inc" 7490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 7590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// getTargetMachine - Return a reference to the TargetMachine, casted 7690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// to the target-specific type. 7790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) const MipsTargetMachine &getTargetMachine() { 7890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) return static_cast<const MipsTargetMachine &>(TM); 7990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) } 8090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 8190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// getInstrInfo - Return a reference to the TargetInstrInfo, casted 8290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// to the target-specific type. 8390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) const MipsInstrInfo *getInstrInfo() { 8490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) return getTargetMachine().getInstrInfo(); 8590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) } 8690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 8790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) SDNode *getGlobalBaseReg(); 8890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 8990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, 9090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) EVT Ty, bool HasLo, bool HasHi); 9190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 9290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) SDNode *Select(SDNode *N); 9390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 9490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) // Complex Pattern. 9590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset); 9690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 9790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) // getImm - Return a target constant with the specified value. 9890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) inline SDValue getImm(const SDNode *Node, unsigned Imm) { 9990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) return CurDAG->getTargetConstant(Imm, Node->getValueType(0)); 10090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) } 10190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 10290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) void ProcessFunctionAfterISel(MachineFunction &MF); 10390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) bool ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&); 10490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) void InitGlobalBaseReg(MachineFunction &MF); 10590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 10690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 10790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) char ConstraintCode, 10890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) std::vector<SDValue> &OutOps); 10990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)}; 11090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 11190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)} 11290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 11390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)// Insert instructions to initialize the global base register in the 11490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)// first MBB of the function. When the ABI is O32 and the relocation model is 11590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)// PIC, the necessary instructions are emitted later to prevent optimization 11690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)// passes from moving them. 11790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) { 11890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 11990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 12090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) if (((MF.getTarget().getRelocationModel() == Reloc::Static) || 12190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) Subtarget.inMips16Mode()) && !MipsFI->globalBaseRegSet()) 12290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) return; 12390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 12490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) MachineBasicBlock &MBB = MF.front(); 12590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) MachineBasicBlock::iterator I = MBB.begin(); 12690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) MachineRegisterInfo &RegInfo = MF.getRegInfo(); 12790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) const MipsRegisterInfo *TargetRegInfo = TM.getRegisterInfo(); 12890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) const MipsInstrInfo *MII = TM.getInstrInfo(); 12990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 13090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); 13190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(); 13290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) int FI = 0; 13390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 13490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) FI= MipsFI->initGlobalRegFI(); 13590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 13690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) const TargetRegisterClass *RC = Subtarget.isABI_N64() ? 13790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) (const TargetRegisterClass*)&Mips::CPU64RegsRegClass : 13890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) (const TargetRegisterClass*)&Mips::CPURegsRegClass; 13990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 14090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) if (Subtarget.inMips16Mode()) 14190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass; 14290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 14390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) V0 = RegInfo.createVirtualRegister(RC); 14490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) V1 = RegInfo.createVirtualRegister(RC); 14590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) V2 = RegInfo.createVirtualRegister(RC); 14690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 14790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) if (Subtarget.isABI_N64()) { 14890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) MF.getRegInfo().addLiveIn(Mips::T9_64); 14990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) MBB.addLiveIn(Mips::T9_64); 1507d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) 15190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) // lui $v0, %hi(%neg(%gp_rel(fname))) 15290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) // daddu $v1, $v0, $t9 15390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname))) 15490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) const GlobalValue *FName = MF.getFunction(); 15590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) 15690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI); 15790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0) 15890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) .addReg(Mips::T9_64); 15990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1) 160 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO); 161 MII->storeRegToStackSlot(MBB, I, GlobalBaseReg, false, FI, RC, 162 TargetRegInfo); 163 return; 164 } 165 166 if (Subtarget.inMips16Mode()) { 167 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0) 168 .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI); 169 BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), 170 V1) 171 .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO); 172 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), 173 V2 ).addReg(V0).addImm(16); 174 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg) 175 .addReg(V1).addReg(V2); 176 177 178 return; 179 } 180 181 if (MF.getTarget().getRelocationModel() == Reloc::Static) { 182 // Set global register to __gnu_local_gp. 183 // 184 // lui $v0, %hi(__gnu_local_gp) 185 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp) 186 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) 187 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI); 188 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) 189 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO); 190 return; 191 } 192 193 MF.getRegInfo().addLiveIn(Mips::T9); 194 MBB.addLiveIn(Mips::T9); 195 196 if (Subtarget.isABI_N32()) { 197 // lui $v0, %hi(%neg(%gp_rel(fname))) 198 // addu $v1, $v0, $t9 199 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname))) 200 const GlobalValue *FName = MF.getFunction(); 201 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) 202 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI); 203 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); 204 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1) 205 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO); 206 MII->storeRegToStackSlot(MBB, I, GlobalBaseReg, false, FI, RC, 207 TargetRegInfo); 208 return; 209 } 210 211 assert(Subtarget.isABI_O32()); 212 213 214 //if (Subtarget.inMips16Mode()) 215 // return; // no need to load GP. It can be calculated anywhere 216 217 218 219 // For O32 ABI, the following instruction sequence is emitted to initialize 220 // the global base register: 221 // 222 // 0. lui $2, %hi(_gp_disp) 223 // 1. addiu $2, $2, %lo(_gp_disp) 224 // 2. addu $globalbasereg, $2, $t9 225 // 226 // We emit only the last instruction here. 227 // 228 // GNU linker requires that the first two instructions appear at the beginning 229 // of a function and no instructions be inserted before or between them. 230 // The two instructions are emitted during lowering to MC layer in order to 231 // avoid any reordering. 232 // 233 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure 234 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu) 235 // reads it. 236 MF.getRegInfo().addLiveIn(Mips::V0); 237 MBB.addLiveIn(Mips::V0); 238 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg) 239 .addReg(Mips::V0).addReg(Mips::T9); 240 MII->storeRegToStackSlot(MBB, I, GlobalBaseReg, false, FI, RC, TargetRegInfo); 241} 242 243bool MipsDAGToDAGISel::ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI, 244 const MachineInstr& MI) { 245 unsigned DstReg = 0, ZeroReg = 0; 246 247 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0". 248 if ((MI.getOpcode() == Mips::ADDiu) && 249 (MI.getOperand(1).getReg() == Mips::ZERO) && 250 (MI.getOperand(2).getImm() == 0)) { 251 DstReg = MI.getOperand(0).getReg(); 252 ZeroReg = Mips::ZERO; 253 } else if ((MI.getOpcode() == Mips::DADDiu) && 254 (MI.getOperand(1).getReg() == Mips::ZERO_64) && 255 (MI.getOperand(2).getImm() == 0)) { 256 DstReg = MI.getOperand(0).getReg(); 257 ZeroReg = Mips::ZERO_64; 258 } 259 260 if (!DstReg) 261 return false; 262 263 // Replace uses with ZeroReg. 264 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg), 265 E = MRI->use_end(); U != E; ++U) { 266 MachineOperand &MO = U.getOperand(); 267 MachineInstr *MI = MO.getParent(); 268 269 // Do not replace if it is a phi's operand or is tied to def operand. 270 if (MI->isPHI() || MI->isRegTiedToDefOperand(U.getOperandNo()) || 271 MI->isPseudo()) 272 continue; 273 274 MO.setReg(ZeroReg); 275 } 276 277 return true; 278} 279 280void MipsDAGToDAGISel::ProcessFunctionAfterISel(MachineFunction &MF) { 281 InitGlobalBaseReg(MF); 282 283 MachineRegisterInfo *MRI = &MF.getRegInfo(); 284 285 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE; 286 ++MFI) 287 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) 288 ReplaceUsesWithZeroReg(MRI, *I); 289} 290 291bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { 292 bool Ret = SelectionDAGISel::runOnMachineFunction(MF); 293 294 ProcessFunctionAfterISel(MF); 295 296 return Ret; 297} 298 299/// getGlobalBaseReg - Output the instructions required to put the 300/// GOT address into a register. 301SDNode *MipsDAGToDAGISel::getGlobalBaseReg() { 302 unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg(); 303 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode(); 304} 305 306/// ComplexPattern used on MipsInstrInfo 307/// Used on Mips Load/Store instructions 308bool MipsDAGToDAGISel:: 309SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) { 310 EVT ValTy = Addr.getValueType(); 311 312 // If Parent is an unaligned f32 load or store, select a (base + index) 313 // floating point load/store instruction (luxc1 or suxc1). 314 const LSBaseSDNode *LS = 0; 315 316 if (Parent && (LS = dyn_cast<LSBaseSDNode>(Parent))) { 317 EVT VT = LS->getMemoryVT(); 318 319 if (VT.getSizeInBits() / 8 > LS->getAlignment()) { 320 assert(TLI.allowsUnalignedMemoryAccesses(VT) && 321 "Unaligned loads/stores not supported for this type."); 322 if (VT == MVT::f32) 323 return false; 324 } 325 } 326 327 // if Address is FI, get the TargetFrameIndex. 328 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 329 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); 330 Offset = CurDAG->getTargetConstant(0, ValTy); 331 return true; 332 } 333 334 // on PIC code Load GA 335 if (Addr.getOpcode() == MipsISD::Wrapper) { 336 Base = Addr.getOperand(0); 337 Offset = Addr.getOperand(1); 338 return true; 339 } 340 341 if (TM.getRelocationModel() != Reloc::PIC_) { 342 if ((Addr.getOpcode() == ISD::TargetExternalSymbol || 343 Addr.getOpcode() == ISD::TargetGlobalAddress)) 344 return false; 345 } 346 347 // Addresses of the form FI+const or FI|const 348 if (CurDAG->isBaseWithConstantOffset(Addr)) { 349 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)); 350 if (isInt<16>(CN->getSExtValue())) { 351 352 // If the first operand is a FI, get the TargetFI Node 353 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode> 354 (Addr.getOperand(0))) 355 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); 356 else 357 Base = Addr.getOperand(0); 358 359 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy); 360 return true; 361 } 362 } 363 364 // Operand is a result from an ADD. 365 if (Addr.getOpcode() == ISD::ADD) { 366 // When loading from constant pools, load the lower address part in 367 // the instruction itself. Example, instead of: 368 // lui $2, %hi($CPI1_0) 369 // addiu $2, $2, %lo($CPI1_0) 370 // lwc1 $f0, 0($2) 371 // Generate: 372 // lui $2, %hi($CPI1_0) 373 // lwc1 $f0, %lo($CPI1_0)($2) 374 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo) { 375 SDValue LoVal = Addr.getOperand(1), Opnd0 = LoVal.getOperand(0); 376 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) || 377 isa<JumpTableSDNode>(Opnd0)) { 378 Base = Addr.getOperand(0); 379 Offset = Opnd0; 380 return true; 381 } 382 } 383 384 // If an indexed floating point load/store can be emitted, return false. 385 if (LS && 386 (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) && 387 Subtarget.hasMips32r2Or64()) 388 return false; 389 } 390 391 Base = Addr; 392 Offset = CurDAG->getTargetConstant(0, ValTy); 393 return true; 394} 395 396/// Select multiply instructions. 397std::pair<SDNode*, SDNode*> 398MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty, 399 bool HasLo, bool HasHi) { 400 SDNode *Lo = 0, *Hi = 0; 401 SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0), 402 N->getOperand(1)); 403 SDValue InFlag = SDValue(Mul, 0); 404 405 if (HasLo) { 406 Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl, 407 Ty, MVT::Glue, InFlag); 408 InFlag = SDValue(Lo, 1); 409 } 410 if (HasHi) 411 Hi = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64, dl, 412 Ty, InFlag); 413 414 return std::make_pair(Lo, Hi); 415} 416 417 418/// Select instructions not customized! Used for 419/// expanded, promoted and normal instructions 420SDNode* MipsDAGToDAGISel::Select(SDNode *Node) { 421 unsigned Opcode = Node->getOpcode(); 422 DebugLoc dl = Node->getDebugLoc(); 423 424 // Dump information about the Node being selected 425 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n"); 426 427 // If we have a custom node, we already have selected! 428 if (Node->isMachineOpcode()) { 429 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); 430 return NULL; 431 } 432 433 /// 434 // Instruction Selection not handled by the auto-generated 435 // tablegen selection should be handled here. 436 /// 437 EVT NodeTy = Node->getValueType(0); 438 unsigned MultOpc; 439 440 switch(Opcode) { 441 default: break; 442 443 case ISD::SUBE: 444 case ISD::ADDE: { 445 SDValue InFlag = Node->getOperand(2), CmpLHS; 446 unsigned Opc = InFlag.getOpcode(); (void)Opc; 447 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || 448 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && 449 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn"); 450 451 unsigned MOp; 452 if (Opcode == ISD::ADDE) { 453 CmpLHS = InFlag.getValue(0); 454 MOp = Mips::ADDu; 455 } else { 456 CmpLHS = InFlag.getOperand(0); 457 MOp = Mips::SUBu; 458 } 459 460 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) }; 461 462 SDValue LHS = Node->getOperand(0); 463 SDValue RHS = Node->getOperand(1); 464 465 EVT VT = LHS.getValueType(); 466 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2); 467 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT, 468 SDValue(Carry,0), RHS); 469 470 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, 471 LHS, SDValue(AddCarry,0)); 472 } 473 474 /// Mul with two results 475 case ISD::SMUL_LOHI: 476 case ISD::UMUL_LOHI: { 477 if (NodeTy == MVT::i32) 478 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT); 479 else 480 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT); 481 482 std::pair<SDNode*, SDNode*> LoHi = SelectMULT(Node, MultOpc, dl, NodeTy, 483 true, true); 484 485 if (!SDValue(Node, 0).use_empty()) 486 ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0)); 487 488 if (!SDValue(Node, 1).use_empty()) 489 ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0)); 490 491 return NULL; 492 } 493 494 /// Special Muls 495 case ISD::MUL: { 496 // Mips32 has a 32-bit three operand mul instruction. 497 if (Subtarget.hasMips32() && NodeTy == MVT::i32) 498 break; 499 return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT, 500 dl, NodeTy, true, false).first; 501 } 502 case ISD::MULHS: 503 case ISD::MULHU: { 504 if (NodeTy == MVT::i32) 505 MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT); 506 else 507 MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT); 508 509 return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second; 510 } 511 512 // Get target GOT address. 513 case ISD::GLOBAL_OFFSET_TABLE: 514 return getGlobalBaseReg(); 515 516 case ISD::ConstantFP: { 517 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node); 518 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { 519 if (Subtarget.hasMips64()) { 520 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 521 Mips::ZERO_64, MVT::i64); 522 return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero); 523 } 524 525 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 526 Mips::ZERO, MVT::i32); 527 return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero, 528 Zero); 529 } 530 break; 531 } 532 533 case ISD::Constant: { 534 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node); 535 unsigned Size = CN->getValueSizeInBits(0); 536 537 if (Size == 32) 538 break; 539 540 MipsAnalyzeImmediate AnalyzeImm; 541 int64_t Imm = CN->getSExtValue(); 542 543 const MipsAnalyzeImmediate::InstSeq &Seq = 544 AnalyzeImm.Analyze(Imm, Size, false); 545 546 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 547 DebugLoc DL = CN->getDebugLoc(); 548 SDNode *RegOpnd; 549 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), 550 MVT::i64); 551 552 // The first instruction can be a LUi which is different from other 553 // instructions (ADDiu, ORI and SLL) in that it does not have a register 554 // operand. 555 if (Inst->Opc == Mips::LUi64) 556 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd); 557 else 558 RegOpnd = 559 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, 560 CurDAG->getRegister(Mips::ZERO_64, MVT::i64), 561 ImmOpnd); 562 563 // The remaining instructions in the sequence are handled here. 564 for (++Inst; Inst != Seq.end(); ++Inst) { 565 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), 566 MVT::i64); 567 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, 568 SDValue(RegOpnd, 0), ImmOpnd); 569 } 570 571 return RegOpnd; 572 } 573 574 case MipsISD::ThreadPointer: { 575 EVT PtrVT = TLI.getPointerTy(); 576 unsigned RdhwrOpc, SrcReg, DestReg; 577 578 if (PtrVT == MVT::i32) { 579 RdhwrOpc = Mips::RDHWR; 580 SrcReg = Mips::HWR29; 581 DestReg = Mips::V1; 582 } else { 583 RdhwrOpc = Mips::RDHWR64; 584 SrcReg = Mips::HWR29_64; 585 DestReg = Mips::V1_64; 586 } 587 588 SDNode *Rdhwr = 589 CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(), 590 Node->getValueType(0), 591 CurDAG->getRegister(SrcReg, PtrVT)); 592 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg, 593 SDValue(Rdhwr, 0)); 594 SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT); 595 ReplaceUses(SDValue(Node, 0), ResNode); 596 return ResNode.getNode(); 597 } 598 } 599 600 // Select the default instruction 601 SDNode *ResNode = SelectCode(Node); 602 603 DEBUG(errs() << "=> "); 604 if (ResNode == NULL || ResNode == Node) 605 DEBUG(Node->dump(CurDAG)); 606 else 607 DEBUG(ResNode->dump(CurDAG)); 608 DEBUG(errs() << "\n"); 609 return ResNode; 610} 611 612bool MipsDAGToDAGISel:: 613SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, 614 std::vector<SDValue> &OutOps) { 615 assert(ConstraintCode == 'm' && "unexpected asm memory constraint"); 616 OutOps.push_back(Op); 617 return false; 618} 619 620/// createMipsISelDag - This pass converts a legalized DAG into a 621/// MIPS-specific DAG, ready for instruction scheduling. 622FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) { 623 return new MipsDAGToDAGISel(TM); 624} 625