MipsISelDAGToDAG.cpp revision 54c5bc87992ebeaa9e71f2bfb60ac5cf74b77db3 
1//===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the MIPS target.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mips-isel"
15#include "Mips.h"
16#include "MipsAnalyzeImmediate.h"
17#include "MipsMachineFunction.h"
18#include "MipsRegisterInfo.h"
19#include "MipsSubtarget.h"
20#include "MipsTargetMachine.h"
21#include "MCTargetDesc/MipsBaseInfo.h"
22#include "llvm/GlobalValue.h"
23#include "llvm/Instructions.h"
24#include "llvm/Intrinsics.h"
25#include "llvm/Support/CFG.h"
26#include "llvm/Type.h"
27#include "llvm/CodeGen/MachineConstantPool.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/SelectionDAGNodes.h"
34#include "llvm/Target/TargetMachine.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38using namespace llvm;
39
40//===----------------------------------------------------------------------===//
41// Instruction Selector Implementation
42//===----------------------------------------------------------------------===//
43
44//===----------------------------------------------------------------------===//
45// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
46// instructions for SelectionDAG operations.
47//===----------------------------------------------------------------------===//
48namespace {
49
50class MipsDAGToDAGISel : public SelectionDAGISel {
51
52  /// TM - Keep a reference to MipsTargetMachine.
53  MipsTargetMachine &TM;
54
55  /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
56  /// make the right decision when generating code for different targets.
57  const MipsSubtarget &Subtarget;
58
59public:
60  explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
61  SelectionDAGISel(tm),
62  TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
63
64  // Pass Name
65  virtual const char *getPassName() const {
66    return "MIPS DAG->DAG Pattern Instruction Selection";
67  }
68
69  virtual bool runOnMachineFunction(MachineFunction &MF);
70
71private:
72  // Include the pieces autogenerated from the target description.
73  #include "MipsGenDAGISel.inc"
74
75  /// getTargetMachine - Return a reference to the TargetMachine, casted
76  /// to the target-specific type.
77  const MipsTargetMachine &getTargetMachine() {
78    return static_cast<const MipsTargetMachine &>(TM);
79  }
80
81  /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
82  /// to the target-specific type.
83  const MipsInstrInfo *getInstrInfo() {
84    return getTargetMachine().getInstrInfo();
85  }
86
87  SDNode *getGlobalBaseReg();
88
89  std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl,
90                                         EVT Ty, bool HasLo, bool HasHi);
91
92  SDNode *Select(SDNode *N);
93
94  // Complex Pattern.
95  bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset);
96
97  // getImm - Return a target constant with the specified value.
98  inline SDValue getImm(const SDNode *Node, unsigned Imm) {
99    return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
100  }
101
102  void ProcessFunctionAfterISel(MachineFunction &MF);
103  bool ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);
104  void InitGlobalBaseReg(MachineFunction &MF);
105
106  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
107                                            char ConstraintCode,
108                                            std::vector<SDValue> &OutOps);
109};
110
111}
112
113// Insert instructions to initialize the global base register in the
114// first MBB of the function. When the ABI is O32 and the relocation model is
115// PIC, the necessary instructions are emitted later to prevent optimization
116// passes from moving them.
117void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
118  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
119
120  MachineBasicBlock &MBB = MF.front();
121  MachineBasicBlock::iterator I = MBB.begin();
122  MachineRegisterInfo &RegInfo = MF.getRegInfo();
123  const MipsRegisterInfo *TargetRegInfo = TM.getRegisterInfo();
124  const MipsInstrInfo *MII = TM.getInstrInfo();
125  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
126  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
127  unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
128  int FI;  // should initialize this to some kind of null
129
130  if (!Subtarget.inMips16Mode())
131    FI= MipsFI->initGlobalRegFI();
132
133  const TargetRegisterClass *RC = Subtarget.isABI_N64() ?
134    (const TargetRegisterClass*)&Mips::CPU64RegsRegClass :
135    (const TargetRegisterClass*)&Mips::CPURegsRegClass;
136
137  V0 = RegInfo.createVirtualRegister(RC);
138  V1 = RegInfo.createVirtualRegister(RC);
139
140  if (Subtarget.isABI_N64()) {
141    MF.getRegInfo().addLiveIn(Mips::T9_64);
142    MBB.addLiveIn(Mips::T9_64);
143
144    // lui $v0, %hi(%neg(%gp_rel(fname)))
145    // daddu $v1, $v0, $t9
146    // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
147    const GlobalValue *FName = MF.getFunction();
148    BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
149      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
150    BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
151      .addReg(Mips::T9_64);
152    BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
153      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
154    MII->storeRegToStackSlot(MBB, I, GlobalBaseReg, false, FI, RC,
155                             TargetRegInfo);
156    return;
157  }
158
159  if (MF.getTarget().getRelocationModel() == Reloc::Static) {
160    // Set global register to __gnu_local_gp.
161    //
162    // lui   $v0, %hi(__gnu_local_gp)
163    // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
164    BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
165      .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
166    BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
167      .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
168    MII->storeRegToStackSlot(MBB, I, GlobalBaseReg, false, FI, RC,
169                             TargetRegInfo);
170    return;
171  }
172
173  MF.getRegInfo().addLiveIn(Mips::T9);
174  MBB.addLiveIn(Mips::T9);
175
176  if (Subtarget.isABI_N32()) {
177    // lui $v0, %hi(%neg(%gp_rel(fname)))
178    // addu $v1, $v0, $t9
179    // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
180    const GlobalValue *FName = MF.getFunction();
181    BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
182      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
183    BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
184    BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
185      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
186    MII->storeRegToStackSlot(MBB, I, GlobalBaseReg, false, FI, RC,
187                             TargetRegInfo);
188    return;
189  }
190
191  assert(Subtarget.isABI_O32());
192
193  if (Subtarget.inMips16Mode())
194    return; // no need to load GP. It can be calculated anywhere
195
196
197  // For O32 ABI, the following instruction sequence is emitted to initialize
198  // the global base register:
199  //
200  //  0. lui   $2, %hi(_gp_disp)
201  //  1. addiu $2, $2, %lo(_gp_disp)
202  //  2. addu  $globalbasereg, $2, $t9
203  //
204  // We emit only the last instruction here.
205  //
206  // GNU linker requires that the first two instructions appear at the beginning
207  // of a function and no instructions be inserted before or between them.
208  // The two instructions are emitted during lowering to MC layer in order to
209  // avoid any reordering.
210  //
211  // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
212  // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
213  // reads it.
214  MF.getRegInfo().addLiveIn(Mips::V0);
215  MBB.addLiveIn(Mips::V0);
216  BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
217    .addReg(Mips::V0).addReg(Mips::T9);
218  MII->storeRegToStackSlot(MBB, I, GlobalBaseReg, false, FI, RC, TargetRegInfo);
219}
220
221bool MipsDAGToDAGISel::ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI,
222                                              const MachineInstr& MI) {
223  unsigned DstReg = 0, ZeroReg = 0;
224
225  // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
226  if ((MI.getOpcode() == Mips::ADDiu) &&
227      (MI.getOperand(1).getReg() == Mips::ZERO) &&
228      (MI.getOperand(2).getImm() == 0)) {
229    DstReg = MI.getOperand(0).getReg();
230    ZeroReg = Mips::ZERO;
231  } else if ((MI.getOpcode() == Mips::DADDiu) &&
232             (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
233             (MI.getOperand(2).getImm() == 0)) {
234    DstReg = MI.getOperand(0).getReg();
235    ZeroReg = Mips::ZERO_64;
236  }
237
238  if (!DstReg)
239    return false;
240
241  // Replace uses with ZeroReg.
242  for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
243       E = MRI->use_end(); U != E; ++U) {
244    MachineOperand &MO = U.getOperand();
245    MachineInstr *MI = MO.getParent();
246
247    // Do not replace if it is a phi's operand or is tied to def operand.
248    if (MI->isPHI() || MI->isRegTiedToDefOperand(U.getOperandNo()) ||
249        MI->isPseudo())
250      continue;
251
252    MO.setReg(ZeroReg);
253  }
254
255  return true;
256}
257
258void MipsDAGToDAGISel::ProcessFunctionAfterISel(MachineFunction &MF) {
259  InitGlobalBaseReg(MF);
260
261  MachineRegisterInfo *MRI = &MF.getRegInfo();
262
263  for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
264       ++MFI)
265    for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I)
266      ReplaceUsesWithZeroReg(MRI, *I);
267}
268
269bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
270  bool Ret = SelectionDAGISel::runOnMachineFunction(MF);
271
272  ProcessFunctionAfterISel(MF);
273
274  return Ret;
275}
276
277/// getGlobalBaseReg - Output the instructions required to put the
278/// GOT address into a register.
279SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
280  unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
281  return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
282}
283
284/// ComplexPattern used on MipsInstrInfo
285/// Used on Mips Load/Store instructions
286bool MipsDAGToDAGISel::
287SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
288  EVT ValTy = Addr.getValueType();
289
290  // If Parent is an unaligned f32 load or store, select a (base + index)
291  // floating point load/store instruction (luxc1 or suxc1).
292  const LSBaseSDNode *LS = 0;
293
294  if (Parent && (LS = dyn_cast<LSBaseSDNode>(Parent))) {
295    EVT VT = LS->getMemoryVT();
296
297    if (VT.getSizeInBits() / 8 > LS->getAlignment()) {
298      assert(TLI.allowsUnalignedMemoryAccesses(VT) &&
299             "Unaligned loads/stores not supported for this type.");
300      if (VT == MVT::f32)
301        return false;
302    }
303  }
304
305  // if Address is FI, get the TargetFrameIndex.
306  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
307    Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
308    Offset = CurDAG->getTargetConstant(0, ValTy);
309    return true;
310  }
311
312  // on PIC code Load GA
313  if (Addr.getOpcode() == MipsISD::Wrapper) {
314    Base   = Addr.getOperand(0);
315    Offset = Addr.getOperand(1);
316    return true;
317  }
318
319  if (TM.getRelocationModel() != Reloc::PIC_) {
320    if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
321        Addr.getOpcode() == ISD::TargetGlobalAddress))
322      return false;
323  }
324
325  // Addresses of the form FI+const or FI|const
326  if (CurDAG->isBaseWithConstantOffset(Addr)) {
327    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
328    if (isInt<16>(CN->getSExtValue())) {
329
330      // If the first operand is a FI, get the TargetFI Node
331      if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
332                                  (Addr.getOperand(0)))
333        Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
334      else
335        Base = Addr.getOperand(0);
336
337      Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
338      return true;
339    }
340  }
341
342  // Operand is a result from an ADD.
343  if (Addr.getOpcode() == ISD::ADD) {
344    // When loading from constant pools, load the lower address part in
345    // the instruction itself. Example, instead of:
346    //  lui $2, %hi($CPI1_0)
347    //  addiu $2, $2, %lo($CPI1_0)
348    //  lwc1 $f0, 0($2)
349    // Generate:
350    //  lui $2, %hi($CPI1_0)
351    //  lwc1 $f0, %lo($CPI1_0)($2)
352    if (Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
353      SDValue LoVal = Addr.getOperand(1), Opnd0 = LoVal.getOperand(0);
354      if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
355          isa<JumpTableSDNode>(Opnd0)) {
356        Base = Addr.getOperand(0);
357        Offset = Opnd0;
358        return true;
359      }
360    }
361
362    // If an indexed floating point load/store can be emitted, return false.
363    if (LS &&
364        (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
365        Subtarget.hasMips32r2Or64())
366      return false;
367  }
368
369  Base   = Addr;
370  Offset = CurDAG->getTargetConstant(0, ValTy);
371  return true;
372}
373
374/// Select multiply instructions.
375std::pair<SDNode*, SDNode*>
376MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty,
377                             bool HasLo, bool HasHi) {
378  SDNode *Lo = 0, *Hi = 0;
379  SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0),
380                                       N->getOperand(1));
381  SDValue InFlag = SDValue(Mul, 0);
382
383  if (HasLo) {
384    Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl,
385                                Ty, MVT::Glue, InFlag);
386    InFlag = SDValue(Lo, 1);
387  }
388  if (HasHi)
389    Hi = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64, dl,
390                                Ty, InFlag);
391
392  return std::make_pair(Lo, Hi);
393}
394
395
396/// Select instructions not customized! Used for
397/// expanded, promoted and normal instructions
398SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
399  unsigned Opcode = Node->getOpcode();
400  DebugLoc dl = Node->getDebugLoc();
401
402  // Dump information about the Node being selected
403  DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
404
405  // If we have a custom node, we already have selected!
406  if (Node->isMachineOpcode()) {
407    DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
408    return NULL;
409  }
410
411  ///
412  // Instruction Selection not handled by the auto-generated
413  // tablegen selection should be handled here.
414  ///
415  EVT NodeTy = Node->getValueType(0);
416  unsigned MultOpc;
417
418  switch(Opcode) {
419  default: break;
420
421  case ISD::SUBE:
422  case ISD::ADDE: {
423    SDValue InFlag = Node->getOperand(2), CmpLHS;
424    unsigned Opc = InFlag.getOpcode(); (void)Opc;
425    assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
426            (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
427           "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
428
429    unsigned MOp;
430    if (Opcode == ISD::ADDE) {
431      CmpLHS = InFlag.getValue(0);
432      MOp = Mips::ADDu;
433    } else {
434      CmpLHS = InFlag.getOperand(0);
435      MOp = Mips::SUBu;
436    }
437
438    SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
439
440    SDValue LHS = Node->getOperand(0);
441    SDValue RHS = Node->getOperand(1);
442
443    EVT VT = LHS.getValueType();
444    SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
445    SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
446                                              SDValue(Carry,0), RHS);
447
448    return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
449                                LHS, SDValue(AddCarry,0));
450  }
451
452  /// Mul with two results
453  case ISD::SMUL_LOHI:
454  case ISD::UMUL_LOHI: {
455    if (NodeTy == MVT::i32)
456      MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
457    else
458      MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
459
460    std::pair<SDNode*, SDNode*> LoHi = SelectMULT(Node, MultOpc, dl, NodeTy,
461                                                  true, true);
462
463    if (!SDValue(Node, 0).use_empty())
464      ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
465
466    if (!SDValue(Node, 1).use_empty())
467      ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
468
469    return NULL;
470  }
471
472  /// Special Muls
473  case ISD::MUL: {
474    // Mips32 has a 32-bit three operand mul instruction.
475    if (Subtarget.hasMips32() && NodeTy == MVT::i32)
476      break;
477    return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT,
478                      dl, NodeTy, true, false).first;
479  }
480  case ISD::MULHS:
481  case ISD::MULHU: {
482    if (NodeTy == MVT::i32)
483      MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
484    else
485      MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
486
487    return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;
488  }
489
490  // Get target GOT address.
491  case ISD::GLOBAL_OFFSET_TABLE:
492    return getGlobalBaseReg();
493
494  case ISD::ConstantFP: {
495    ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
496    if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
497      if (Subtarget.hasMips64()) {
498        SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
499                                              Mips::ZERO_64, MVT::i64);
500        return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
501      }
502
503      SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
504                                            Mips::ZERO, MVT::i32);
505      return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
506                                    Zero);
507    }
508    break;
509  }
510
511  case ISD::Constant: {
512    const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
513    unsigned Size = CN->getValueSizeInBits(0);
514
515    if (Size == 32)
516      break;
517
518    MipsAnalyzeImmediate AnalyzeImm;
519    int64_t Imm = CN->getSExtValue();
520
521    const MipsAnalyzeImmediate::InstSeq &Seq =
522      AnalyzeImm.Analyze(Imm, Size, false);
523
524    MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
525    DebugLoc DL = CN->getDebugLoc();
526    SDNode *RegOpnd;
527    SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
528                                                MVT::i64);
529
530    // The first instruction can be a LUi which is different from other
531    // instructions (ADDiu, ORI and SLL) in that it does not have a register
532    // operand.
533    if (Inst->Opc == Mips::LUi64)
534      RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
535    else
536      RegOpnd =
537        CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
538                               CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
539                               ImmOpnd);
540
541    // The remaining instructions in the sequence are handled here.
542    for (++Inst; Inst != Seq.end(); ++Inst) {
543      ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
544                                          MVT::i64);
545      RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
546                                       SDValue(RegOpnd, 0), ImmOpnd);
547    }
548
549    return RegOpnd;
550  }
551
552  case MipsISD::ThreadPointer: {
553    EVT PtrVT = TLI.getPointerTy();
554    unsigned RdhwrOpc, SrcReg, DestReg;
555
556    if (PtrVT == MVT::i32) {
557      RdhwrOpc = Mips::RDHWR;
558      SrcReg = Mips::HWR29;
559      DestReg = Mips::V1;
560    } else {
561      RdhwrOpc = Mips::RDHWR64;
562      SrcReg = Mips::HWR29_64;
563      DestReg = Mips::V1_64;
564    }
565
566    SDNode *Rdhwr =
567      CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
568                             Node->getValueType(0),
569                             CurDAG->getRegister(SrcReg, PtrVT));
570    SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
571                                         SDValue(Rdhwr, 0));
572    SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
573    ReplaceUses(SDValue(Node, 0), ResNode);
574    return ResNode.getNode();
575  }
576  }
577
578  // Select the default instruction
579  SDNode *ResNode = SelectCode(Node);
580
581  DEBUG(errs() << "=> ");
582  if (ResNode == NULL || ResNode == Node)
583    DEBUG(Node->dump(CurDAG));
584  else
585    DEBUG(ResNode->dump(CurDAG));
586  DEBUG(errs() << "\n");
587  return ResNode;
588}
589
590bool MipsDAGToDAGISel::
591SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
592                             std::vector<SDValue> &OutOps) {
593  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
594  OutOps.push_back(Op);
595  return false;
596}
597
598/// createMipsISelDag - This pass converts a legalized DAG into a
599/// MIPS-specific DAG, ready for instruction scheduling.
600FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
601  return new MipsDAGToDAGISel(TM);
602}
603