MipsISelDAGToDAG.cpp revision 8782707f5074ab3951eb6424394bc8d2a2fa584a
10ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong//===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===// 20ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong// 30ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong// The LLVM Compiler Infrastructure 40ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong// 50ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong// This file is distributed under the University of Illinois Open Source 60ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong// License. See LICENSE.TXT for details. 70ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong// 80ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong//===----------------------------------------------------------------------===// 90ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong// 100ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong// This file defines an instruction selector for the MIPS target. 110ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong// 120ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong//===----------------------------------------------------------------------===// 130ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong 140ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong#define DEBUG_TYPE "mips-isel" 150ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong#include "Mips.h" 160ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong#include "MipsAnalyzeImmediate.h" 170ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong#include "MipsMachineFunction.h" 180ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong#include "MipsRegisterInfo.h" 190ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong#include "MipsSubtarget.h" 200ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong#include "MipsTargetMachine.h" 210ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong#include "MCTargetDesc/MipsBaseInfo.h" 220ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong#include "llvm/GlobalValue.h" 230ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong#include "llvm/Instructions.h" 240ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong#include "llvm/Intrinsics.h" 250ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong#include "llvm/Support/CFG.h" 260ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong#include "llvm/Type.h" 270ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong#include "llvm/CodeGen/MachineConstantPool.h" 280ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong#include "llvm/CodeGen/MachineFunction.h" 291d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling#include "llvm/CodeGen/MachineFrameInfo.h" 301d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling#include "llvm/CodeGen/MachineInstrBuilder.h" 311d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling#include "llvm/CodeGen/MachineRegisterInfo.h" 321d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling#include "llvm/CodeGen/SelectionDAGISel.h" 331d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling#include "llvm/CodeGen/SelectionDAGNodes.h" 341d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling#include "llvm/Target/TargetMachine.h" 351d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling#include "llvm/Support/Debug.h" 361d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling#include "llvm/Support/ErrorHandling.h" 370ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong#include "llvm/Support/raw_ostream.h" 381d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberlingusing namespace llvm; 390ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong 4079397c21138f54fcff6ec067b44b847f1f7e0e98Carlos Hernandez//===----------------------------------------------------------------------===// 411d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling// Instruction Selector Implementation 421d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling//===----------------------------------------------------------------------===// 4379397c21138f54fcff6ec067b44b847f1f7e0e98Carlos Hernandez 441d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling//===----------------------------------------------------------------------===// 451d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling// MipsDAGToDAGISel - MIPS specific code to select MIPS machine 4679397c21138f54fcff6ec067b44b847f1f7e0e98Carlos Hernandez// instructions for SelectionDAG operations. 4779397c21138f54fcff6ec067b44b847f1f7e0e98Carlos Hernandez//===----------------------------------------------------------------------===// 481d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberlingnamespace { 491d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling 501d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberlingclass MipsDAGToDAGISel : public SelectionDAGISel { 511d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling 521d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling /// TM - Keep a reference to MipsTargetMachine. 531d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling MipsTargetMachine &TM; 541d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling 5579397c21138f54fcff6ec067b44b847f1f7e0e98Carlos Hernandez /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can 5679397c21138f54fcff6ec067b44b847f1f7e0e98Carlos Hernandez /// make the right decision when generating code for different targets. 571d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling const MipsSubtarget &Subtarget; 581d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling 5979397c21138f54fcff6ec067b44b847f1f7e0e98Carlos Hernandezpublic: 6079397c21138f54fcff6ec067b44b847f1f7e0e98Carlos Hernandez explicit MipsDAGToDAGISel(MipsTargetMachine &tm) : 6179397c21138f54fcff6ec067b44b847f1f7e0e98Carlos Hernandez SelectionDAGISel(tm), 621d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {} 631d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling 641d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling // Pass Name 651d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling virtual const char *getPassName() const { 661d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling return "MIPS DAG->DAG Pattern Instruction Selection"; 671d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling } 680ae28bd5885b5daa526898fcf7c323dc2c3e1963Angus Kong 691d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling virtual bool runOnMachineFunction(MachineFunction &MF); 701d2624a10e2c559f8ba9ef89eaa30832c0a83a96Sascha Haeberling 71private: 72 // Include the pieces autogenerated from the target description. 73 #include "MipsGenDAGISel.inc" 74 75 /// getTargetMachine - Return a reference to the TargetMachine, casted 76 /// to the target-specific type. 77 const MipsTargetMachine &getTargetMachine() { 78 return static_cast<const MipsTargetMachine &>(TM); 79 } 80 81 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted 82 /// to the target-specific type. 83 const MipsInstrInfo *getInstrInfo() { 84 return getTargetMachine().getInstrInfo(); 85 } 86 87 SDNode *getGlobalBaseReg(); 88 89 std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, 90 EVT Ty, bool HasLo, bool HasHi); 91 92 SDNode *Select(SDNode *N); 93 94 // Complex Pattern. 95 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Offset); 96 97 // getImm - Return a target constant with the specified value. 98 inline SDValue getImm(const SDNode *Node, unsigned Imm) { 99 return CurDAG->getTargetConstant(Imm, Node->getValueType(0)); 100 } 101 102 void ProcessFunctionAfterISel(MachineFunction &MF); 103 bool ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&); 104 void InitGlobalBaseReg(MachineFunction &MF); 105 106 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 107 char ConstraintCode, 108 std::vector<SDValue> &OutOps); 109}; 110 111} 112 113// Insert instructions to initialize the global base register in the 114// first MBB of the function. When the ABI is O32 and the relocation model is 115// PIC, the necessary instructions are emitted later to prevent optimization 116// passes from moving them. 117void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) { 118 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 119 120 if (!MipsFI->globalBaseRegSet()) 121 return; 122 123 MachineBasicBlock &MBB = MF.front(); 124 MachineBasicBlock::iterator I = MBB.begin(); 125 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 126 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 127 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); 128 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg(); 129 130 const TargetRegisterClass *RC = Subtarget.isABI_N64() ? 131 (const TargetRegisterClass*)&Mips::CPU64RegsRegClass : 132 (const TargetRegisterClass*)&Mips::CPURegsRegClass; 133 134 V0 = RegInfo.createVirtualRegister(RC); 135 V1 = RegInfo.createVirtualRegister(RC); 136 137 if (Subtarget.isABI_N64()) { 138 MF.getRegInfo().addLiveIn(Mips::T9_64); 139 MBB.addLiveIn(Mips::T9_64); 140 141 // lui $v0, %hi(%neg(%gp_rel(fname))) 142 // daddu $v1, $v0, $t9 143 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname))) 144 const GlobalValue *FName = MF.getFunction(); 145 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) 146 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI); 147 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0).addReg(Mips::T9_64); 148 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1) 149 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO); 150 return; 151 } 152 153 if (MF.getTarget().getRelocationModel() == Reloc::Static) { 154 // Set global register to __gnu_local_gp. 155 // 156 // lui $v0, %hi(__gnu_local_gp) 157 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp) 158 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) 159 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI); 160 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) 161 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO); 162 return; 163 } 164 165 MF.getRegInfo().addLiveIn(Mips::T9); 166 MBB.addLiveIn(Mips::T9); 167 168 if (Subtarget.isABI_N32()) { 169 // lui $v0, %hi(%neg(%gp_rel(fname))) 170 // addu $v1, $v0, $t9 171 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname))) 172 const GlobalValue *FName = MF.getFunction(); 173 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) 174 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI); 175 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); 176 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1) 177 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO); 178 return; 179 } 180 181 assert(Subtarget.isABI_O32()); 182 183 // For O32 ABI, the following instruction sequence is emitted to initialize 184 // the global base register: 185 // 186 // 0. lui $2, %hi(_gp_disp) 187 // 1. addiu $2, $2, %lo(_gp_disp) 188 // 2. addu $globalbasereg, $2, $t9 189 // 190 // We emit only the last instruction here. 191 // 192 // GNU linker requires that the first two instructions appear at the beginning 193 // of a function and no instructions be inserted before or between them. 194 // The two instructions are emitted during lowering to MC layer in order to 195 // avoid any reordering. 196 // 197 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure 198 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu) 199 // reads it. 200 MF.getRegInfo().addLiveIn(Mips::V0); 201 MBB.addLiveIn(Mips::V0); 202 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg) 203 .addReg(Mips::V0).addReg(Mips::T9); 204} 205 206bool MipsDAGToDAGISel::ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI, 207 const MachineInstr& MI) { 208 unsigned DstReg = 0, ZeroReg = 0; 209 210 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0". 211 if ((MI.getOpcode() == Mips::ADDiu) && 212 (MI.getOperand(1).getReg() == Mips::ZERO) && 213 (MI.getOperand(2).getImm() == 0)) { 214 DstReg = MI.getOperand(0).getReg(); 215 ZeroReg = Mips::ZERO; 216 } else if ((MI.getOpcode() == Mips::DADDiu) && 217 (MI.getOperand(1).getReg() == Mips::ZERO_64) && 218 (MI.getOperand(2).getImm() == 0)) { 219 DstReg = MI.getOperand(0).getReg(); 220 ZeroReg = Mips::ZERO_64; 221 } 222 223 if (!DstReg) 224 return false; 225 226 // Replace uses with ZeroReg. 227 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg), 228 E = MRI->use_end(); U != E; ++U) { 229 MachineOperand &MO = U.getOperand(); 230 MachineInstr *MI = MO.getParent(); 231 232 // Do not replace if it is a phi's operand or is tied to def operand. 233 if (MI->isPHI() || MI->isRegTiedToDefOperand(U.getOperandNo()) || 234 MI->isPseudo()) 235 continue; 236 237 MO.setReg(ZeroReg); 238 } 239 240 return true; 241} 242 243void MipsDAGToDAGISel::ProcessFunctionAfterISel(MachineFunction &MF) { 244 InitGlobalBaseReg(MF); 245 246 MachineRegisterInfo *MRI = &MF.getRegInfo(); 247 248 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE; 249 ++MFI) 250 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) 251 ReplaceUsesWithZeroReg(MRI, *I); 252} 253 254bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { 255 bool Ret = SelectionDAGISel::runOnMachineFunction(MF); 256 257 ProcessFunctionAfterISel(MF); 258 259 return Ret; 260} 261 262/// getGlobalBaseReg - Output the instructions required to put the 263/// GOT address into a register. 264SDNode *MipsDAGToDAGISel::getGlobalBaseReg() { 265 unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg(); 266 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode(); 267} 268 269/// ComplexPattern used on MipsInstrInfo 270/// Used on Mips Load/Store instructions 271bool MipsDAGToDAGISel:: 272SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) { 273 EVT ValTy = Addr.getValueType(); 274 275 // If Parent is an unaligned f32 load or store, select a (base + index) 276 // floating point load/store instruction (luxc1 or suxc1). 277 const LSBaseSDNode* LS = 0; 278 279 if (Parent && (LS = dyn_cast<LSBaseSDNode>(Parent))) { 280 EVT VT = LS->getMemoryVT(); 281 282 if (VT.getSizeInBits() / 8 > LS->getAlignment()) { 283 assert(TLI.allowsUnalignedMemoryAccesses(VT) && 284 "Unaligned loads/stores not supported for this type."); 285 if (VT == MVT::f32) 286 return false; 287 } 288 } 289 290 // if Address is FI, get the TargetFrameIndex. 291 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 292 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); 293 Offset = CurDAG->getTargetConstant(0, ValTy); 294 return true; 295 } 296 297 // on PIC code Load GA 298 if (Addr.getOpcode() == MipsISD::Wrapper) { 299 Base = Addr.getOperand(0); 300 Offset = Addr.getOperand(1); 301 return true; 302 } 303 304 if (TM.getRelocationModel() != Reloc::PIC_) { 305 if ((Addr.getOpcode() == ISD::TargetExternalSymbol || 306 Addr.getOpcode() == ISD::TargetGlobalAddress)) 307 return false; 308 } 309 310 // Addresses of the form FI+const or FI|const 311 if (CurDAG->isBaseWithConstantOffset(Addr)) { 312 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)); 313 if (isInt<16>(CN->getSExtValue())) { 314 315 // If the first operand is a FI, get the TargetFI Node 316 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode> 317 (Addr.getOperand(0))) 318 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); 319 else 320 Base = Addr.getOperand(0); 321 322 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy); 323 return true; 324 } 325 } 326 327 // Operand is a result from an ADD. 328 if (Addr.getOpcode() == ISD::ADD) { 329 // When loading from constant pools, load the lower address part in 330 // the instruction itself. Example, instead of: 331 // lui $2, %hi($CPI1_0) 332 // addiu $2, $2, %lo($CPI1_0) 333 // lwc1 $f0, 0($2) 334 // Generate: 335 // lui $2, %hi($CPI1_0) 336 // lwc1 $f0, %lo($CPI1_0)($2) 337 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo) { 338 SDValue LoVal = Addr.getOperand(1), Opnd0 = LoVal.getOperand(0); 339 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) || 340 isa<JumpTableSDNode>(Opnd0)) { 341 Base = Addr.getOperand(0); 342 Offset = Opnd0; 343 return true; 344 } 345 } 346 347 // If an indexed floating point load/store can be emitted, return false. 348 if (LS && (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) && 349 Subtarget.hasMips32r2Or64()) 350 return false; 351 } 352 353 Base = Addr; 354 Offset = CurDAG->getTargetConstant(0, ValTy); 355 return true; 356} 357 358/// Select multiply instructions. 359std::pair<SDNode*, SDNode*> 360MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty, 361 bool HasLo, bool HasHi) { 362 SDNode *Lo = 0, *Hi = 0; 363 SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0), 364 N->getOperand(1)); 365 SDValue InFlag = SDValue(Mul, 0); 366 367 if (HasLo) { 368 Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl, 369 Ty, MVT::Glue, InFlag); 370 InFlag = SDValue(Lo, 1); 371 } 372 if (HasHi) 373 Hi = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64, dl, 374 Ty, InFlag); 375 376 return std::make_pair(Lo, Hi); 377} 378 379 380/// Select instructions not customized! Used for 381/// expanded, promoted and normal instructions 382SDNode* MipsDAGToDAGISel::Select(SDNode *Node) { 383 unsigned Opcode = Node->getOpcode(); 384 DebugLoc dl = Node->getDebugLoc(); 385 386 // Dump information about the Node being selected 387 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n"); 388 389 // If we have a custom node, we already have selected! 390 if (Node->isMachineOpcode()) { 391 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); 392 return NULL; 393 } 394 395 /// 396 // Instruction Selection not handled by the auto-generated 397 // tablegen selection should be handled here. 398 /// 399 EVT NodeTy = Node->getValueType(0); 400 unsigned MultOpc; 401 402 switch(Opcode) { 403 default: break; 404 405 case ISD::SUBE: 406 case ISD::ADDE: { 407 SDValue InFlag = Node->getOperand(2), CmpLHS; 408 unsigned Opc = InFlag.getOpcode(); (void)Opc; 409 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || 410 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && 411 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn"); 412 413 unsigned MOp; 414 if (Opcode == ISD::ADDE) { 415 CmpLHS = InFlag.getValue(0); 416 MOp = Mips::ADDu; 417 } else { 418 CmpLHS = InFlag.getOperand(0); 419 MOp = Mips::SUBu; 420 } 421 422 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) }; 423 424 SDValue LHS = Node->getOperand(0); 425 SDValue RHS = Node->getOperand(1); 426 427 EVT VT = LHS.getValueType(); 428 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2); 429 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT, 430 SDValue(Carry,0), RHS); 431 432 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, 433 LHS, SDValue(AddCarry,0)); 434 } 435 436 /// Mul with two results 437 case ISD::SMUL_LOHI: 438 case ISD::UMUL_LOHI: { 439 if (NodeTy == MVT::i32) 440 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT); 441 else 442 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT); 443 444 std::pair<SDNode*, SDNode*> LoHi = SelectMULT(Node, MultOpc, dl, NodeTy, 445 true, true); 446 447 if (!SDValue(Node, 0).use_empty()) 448 ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0)); 449 450 if (!SDValue(Node, 1).use_empty()) 451 ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0)); 452 453 return NULL; 454 } 455 456 /// Special Muls 457 case ISD::MUL: { 458 // Mips32 has a 32-bit three operand mul instruction. 459 if (Subtarget.hasMips32() && NodeTy == MVT::i32) 460 break; 461 return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT, 462 dl, NodeTy, true, false).first; 463 } 464 case ISD::MULHS: 465 case ISD::MULHU: { 466 if (NodeTy == MVT::i32) 467 MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT); 468 else 469 MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT); 470 471 return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second; 472 } 473 474 // Get target GOT address. 475 case ISD::GLOBAL_OFFSET_TABLE: 476 return getGlobalBaseReg(); 477 478 case ISD::ConstantFP: { 479 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node); 480 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) { 481 if (Subtarget.hasMips64()) { 482 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 483 Mips::ZERO_64, MVT::i64); 484 return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero); 485 } 486 487 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 488 Mips::ZERO, MVT::i32); 489 return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero, 490 Zero); 491 } 492 break; 493 } 494 495 case ISD::Constant: { 496 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node); 497 unsigned Size = CN->getValueSizeInBits(0); 498 499 if (Size == 32) 500 break; 501 502 MipsAnalyzeImmediate AnalyzeImm; 503 int64_t Imm = CN->getSExtValue(); 504 505 const MipsAnalyzeImmediate::InstSeq &Seq = 506 AnalyzeImm.Analyze(Imm, Size, false); 507 508 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 509 DebugLoc DL = CN->getDebugLoc(); 510 SDNode *RegOpnd; 511 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), 512 MVT::i64); 513 514 // The first instruction can be a LUi which is different from other 515 // instructions (ADDiu, ORI and SLL) in that it does not have a register 516 // operand. 517 if (Inst->Opc == Mips::LUi64) 518 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd); 519 else 520 RegOpnd = 521 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, 522 CurDAG->getRegister(Mips::ZERO_64, MVT::i64), 523 ImmOpnd); 524 525 // The remaining instructions in the sequence are handled here. 526 for (++Inst; Inst != Seq.end(); ++Inst) { 527 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), 528 MVT::i64); 529 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, 530 SDValue(RegOpnd, 0), ImmOpnd); 531 } 532 533 return RegOpnd; 534 } 535 536 case MipsISD::ThreadPointer: { 537 EVT PtrVT = TLI.getPointerTy(); 538 unsigned RdhwrOpc, SrcReg, DestReg; 539 540 if (PtrVT == MVT::i32) { 541 RdhwrOpc = Mips::RDHWR; 542 SrcReg = Mips::HWR29; 543 DestReg = Mips::V1; 544 } else { 545 RdhwrOpc = Mips::RDHWR64; 546 SrcReg = Mips::HWR29_64; 547 DestReg = Mips::V1_64; 548 } 549 550 SDNode *Rdhwr = 551 CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(), 552 Node->getValueType(0), 553 CurDAG->getRegister(SrcReg, PtrVT)); 554 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg, 555 SDValue(Rdhwr, 0)); 556 SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT); 557 ReplaceUses(SDValue(Node, 0), ResNode); 558 return ResNode.getNode(); 559 } 560 } 561 562 // Select the default instruction 563 SDNode *ResNode = SelectCode(Node); 564 565 DEBUG(errs() << "=> "); 566 if (ResNode == NULL || ResNode == Node) 567 DEBUG(Node->dump(CurDAG)); 568 else 569 DEBUG(ResNode->dump(CurDAG)); 570 DEBUG(errs() << "\n"); 571 return ResNode; 572} 573 574bool MipsDAGToDAGISel:: 575SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, 576 std::vector<SDValue> &OutOps) { 577 assert(ConstraintCode == 'm' && "unexpected asm memory constraint"); 578 OutOps.push_back(Op); 579 return false; 580} 581 582/// createMipsISelDag - This pass converts a legalized DAG into a 583/// MIPS-specific DAG, ready for instruction scheduling. 584FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) { 585 return new MipsDAGToDAGISel(TM); 586} 587