MipsISelDAGToDAG.cpp revision c079ad09f535925b4431f9ed9b6ae8aa33225910 
1//===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the MIPS target.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mips-isel"
15#include "Mips.h"
16#include "MipsMachineFunction.h"
17#include "MipsRegisterInfo.h"
18#include "MipsSubtarget.h"
19#include "MipsTargetMachine.h"
20#include "llvm/GlobalValue.h"
21#include "llvm/Instructions.h"
22#include "llvm/Intrinsics.h"
23#include "llvm/Support/CFG.h"
24#include "llvm/Type.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/SelectionDAGISel.h"
31#include "llvm/Target/TargetMachine.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35using namespace llvm;
36
37//===----------------------------------------------------------------------===//
38// Instruction Selector Implementation
39//===----------------------------------------------------------------------===//
40
41//===----------------------------------------------------------------------===//
42// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
43// instructions for SelectionDAG operations.
44//===----------------------------------------------------------------------===//
45namespace {
46
47class MipsDAGToDAGISel : public SelectionDAGISel {
48
49  /// TM - Keep a reference to MipsTargetMachine.
50  MipsTargetMachine &TM;
51
52  /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
53  /// make the right decision when generating code for different targets.
54  const MipsSubtarget &Subtarget;
55
56public:
57  explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
58  SelectionDAGISel(tm),
59  TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
60
61  // Pass Name
62  virtual const char *getPassName() const {
63    return "MIPS DAG->DAG Pattern Instruction Selection";
64  }
65
66
67private:
68  // Include the pieces autogenerated from the target description.
69  #include "MipsGenDAGISel.inc"
70
71  /// getTargetMachine - Return a reference to the TargetMachine, casted
72  /// to the target-specific type.
73  const MipsTargetMachine &getTargetMachine() {
74    return static_cast<const MipsTargetMachine &>(TM);
75  }
76
77  /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
78  /// to the target-specific type.
79  const MipsInstrInfo *getInstrInfo() {
80    return getTargetMachine().getInstrInfo();
81  }
82
83  SDNode *getGlobalBaseReg();
84  SDNode *Select(SDNode *N);
85
86  // Complex Pattern.
87  bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
88
89  SDNode *SelectLoadFp64(SDNode *N);
90  SDNode *SelectStoreFp64(SDNode *N);
91
92  // getI32Imm - Return a target constant with the specified
93  // value, of type i32.
94  inline SDValue getI32Imm(unsigned Imm) {
95    return CurDAG->getTargetConstant(Imm, MVT::i32);
96  }
97};
98
99}
100
101
102/// getGlobalBaseReg - Output the instructions required to put the
103/// GOT address into a register.
104SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
105  unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
106  return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
107}
108
109/// ComplexPattern used on MipsInstrInfo
110/// Used on Mips Load/Store instructions
111bool MipsDAGToDAGISel::
112SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) {
113  // if Address is FI, get the TargetFrameIndex.
114  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
115    Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
116    Offset = CurDAG->getTargetConstant(0, MVT::i32);
117    return true;
118  }
119
120  // on PIC code Load GA
121  if (TM.getRelocationModel() == Reloc::PIC_) {
122    if (Addr.getOpcode() == MipsISD::WrapperPIC) {
123      Base   = CurDAG->getRegister(Mips::GP, MVT::i32);
124      Offset = Addr.getOperand(0);
125      return true;
126    }
127  } else {
128    if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
129        Addr.getOpcode() == ISD::TargetGlobalAddress))
130      return false;
131    else if (Addr.getOpcode() == ISD::TargetGlobalTLSAddress) {
132      Base   = CurDAG->getRegister(Mips::GP, MVT::i32);
133      Offset = Addr;
134      return true;
135    }
136  }
137
138  // Addresses of the form FI+const or FI|const
139  if (CurDAG->isBaseWithConstantOffset(Addr)) {
140    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
141    if (isInt<16>(CN->getSExtValue())) {
142
143      // If the first operand is a FI, get the TargetFI Node
144      if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
145                                  (Addr.getOperand(0)))
146        Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
147      else
148        Base = Addr.getOperand(0);
149
150      Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
151      return true;
152    }
153  }
154
155  // Operand is a result from an ADD.
156  if (Addr.getOpcode() == ISD::ADD) {
157    // When loading from constant pools, load the lower address part in
158    // the instruction itself. Example, instead of:
159    //  lui $2, %hi($CPI1_0)
160    //  addiu $2, $2, %lo($CPI1_0)
161    //  lwc1 $f0, 0($2)
162    // Generate:
163    //  lui $2, %hi($CPI1_0)
164    //  lwc1 $f0, %lo($CPI1_0)($2)
165    if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
166         Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
167        Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
168      SDValue LoVal = Addr.getOperand(1);
169      if (dyn_cast<ConstantPoolSDNode>(LoVal.getOperand(0))) {
170        Base = Addr.getOperand(0);
171        Offset = LoVal.getOperand(0);
172        return true;
173      }
174    }
175  }
176
177  Base   = Addr;
178  Offset = CurDAG->getTargetConstant(0, MVT::i32);
179  return true;
180}
181
182SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
183  MVT::SimpleValueType NVT =
184    N->getValueType(0).getSimpleVT().SimpleTy;
185
186  if (!Subtarget.isMips1() || NVT != MVT::f64)
187    return NULL;
188
189  LoadSDNode *LN = cast<LoadSDNode>(N);
190  if (LN->getExtensionType() != ISD::NON_EXTLOAD ||
191      LN->getAddressingMode() != ISD::UNINDEXED)
192    return NULL;
193
194  SDValue Chain = N->getOperand(0);
195  SDValue N1 = N->getOperand(1);
196  SDValue Offset0, Offset1, Base;
197
198  if (!SelectAddr(N1, Offset0, Base) ||
199      N1.getValueType() != MVT::i32)
200    return NULL;
201
202  MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
203  MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
204  DebugLoc dl = N->getDebugLoc();
205
206  // The second load should start after for 4 bytes.
207  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
208    Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
209  else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Offset0))
210    Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(),
211                                            MVT::i32,
212                                            CP->getAlignment(),
213                                            CP->getOffset()+4,
214                                            CP->getTargetFlags());
215  else
216    return NULL;
217
218  // Choose the offsets depending on the endianess
219  if (TM.getTargetData()->isBigEndian())
220    std::swap(Offset0, Offset1);
221
222  // Instead of:
223  //    ldc $f0, X($3)
224  // Generate:
225  //    lwc $f0, X($3)
226  //    lwc $f1, X+4($3)
227  SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
228                                    MVT::Other, Offset0, Base, Chain);
229  SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
230                                                 dl, NVT), 0);
231  SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
232                            MVT::f64, Undef, SDValue(LD0, 0));
233
234  SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
235                          MVT::Other, Offset1, Base, SDValue(LD0, 1));
236  SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
237                            MVT::f64, I0, SDValue(LD1, 0));
238
239  ReplaceUses(SDValue(N, 0), I1);
240  ReplaceUses(SDValue(N, 1), Chain);
241  cast<MachineSDNode>(LD0)->setMemRefs(MemRefs0, MemRefs0 + 1);
242  cast<MachineSDNode>(LD1)->setMemRefs(MemRefs0, MemRefs0 + 1);
243  return I1.getNode();
244}
245
246SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
247
248  if (!Subtarget.isMips1() ||
249      N->getOperand(1).getValueType() != MVT::f64)
250    return NULL;
251
252  SDValue Chain = N->getOperand(0);
253
254  StoreSDNode *SN = cast<StoreSDNode>(N);
255  if (SN->isTruncatingStore() || SN->getAddressingMode() != ISD::UNINDEXED)
256    return NULL;
257
258  SDValue N1 = N->getOperand(1);
259  SDValue N2 = N->getOperand(2);
260  SDValue Offset0, Offset1, Base;
261
262  if (!SelectAddr(N2, Offset0, Base) ||
263      N1.getValueType() != MVT::f64 ||
264      N2.getValueType() != MVT::i32)
265    return NULL;
266
267  MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
268  MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
269  DebugLoc dl = N->getDebugLoc();
270
271  // Get the even and odd part from the f64 register
272  SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::sub_fpodd,
273                                                 dl, MVT::f32, N1);
274  SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::sub_fpeven,
275                                                 dl, MVT::f32, N1);
276
277  // The second store should start after for 4 bytes.
278  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
279    Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
280  else
281    return NULL;
282
283  // Choose the offsets depending on the endianess
284  if (TM.getTargetData()->isBigEndian())
285    std::swap(Offset0, Offset1);
286
287  // Instead of:
288  //    sdc $f0, X($3)
289  // Generate:
290  //    swc $f0, X($3)
291  //    swc $f1, X+4($3)
292  SDValue Ops0[] = { FPEven, Offset0, Base, Chain };
293  Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
294                                       MVT::Other, Ops0, 4), 0);
295  cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
296
297  SDValue Ops1[] = { FPOdd, Offset1, Base, Chain };
298  Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
299                                       MVT::Other, Ops1, 4), 0);
300  cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
301
302  ReplaceUses(SDValue(N, 0), Chain);
303  return Chain.getNode();
304}
305
306/// Select instructions not customized! Used for
307/// expanded, promoted and normal instructions
308SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
309  unsigned Opcode = Node->getOpcode();
310  DebugLoc dl = Node->getDebugLoc();
311
312  // Dump information about the Node being selected
313  DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
314
315  // If we have a custom node, we already have selected!
316  if (Node->isMachineOpcode()) {
317    DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
318    return NULL;
319  }
320
321  ///
322  // Instruction Selection not handled by the auto-generated
323  // tablegen selection should be handled here.
324  ///
325  switch(Opcode) {
326    default: break;
327
328    case ISD::SUBE:
329    case ISD::ADDE: {
330      SDValue InFlag = Node->getOperand(2), CmpLHS;
331      unsigned Opc = InFlag.getOpcode(); (void)Opc;
332      assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
333              (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
334             "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
335
336      unsigned MOp;
337      if (Opcode == ISD::ADDE) {
338        CmpLHS = InFlag.getValue(0);
339        MOp = Mips::ADDu;
340      } else {
341        CmpLHS = InFlag.getOperand(0);
342        MOp = Mips::SUBu;
343      }
344
345      SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
346
347      SDValue LHS = Node->getOperand(0);
348      SDValue RHS = Node->getOperand(1);
349
350      EVT VT = LHS.getValueType();
351      SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
352      SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
353                                                SDValue(Carry,0), RHS);
354
355      return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
356                                  LHS, SDValue(AddCarry,0));
357    }
358
359    /// Mul with two results
360    case ISD::SMUL_LOHI:
361    case ISD::UMUL_LOHI: {
362      SDValue Op1 = Node->getOperand(0);
363      SDValue Op2 = Node->getOperand(1);
364
365      unsigned Op;
366      Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
367
368      SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2);
369
370      SDValue InFlag = SDValue(Mul, 0);
371      SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
372                                          MVT::Glue, InFlag);
373      InFlag = SDValue(Lo,1);
374      SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
375
376      if (!SDValue(Node, 0).use_empty())
377        ReplaceUses(SDValue(Node, 0), SDValue(Lo,0));
378
379      if (!SDValue(Node, 1).use_empty())
380        ReplaceUses(SDValue(Node, 1), SDValue(Hi,0));
381
382      return NULL;
383    }
384
385    /// Special Muls
386    case ISD::MUL:
387      if (Subtarget.isMips32())
388        break;
389    case ISD::MULHS:
390    case ISD::MULHU: {
391      SDValue MulOp1 = Node->getOperand(0);
392      SDValue MulOp2 = Node->getOperand(1);
393
394      unsigned MulOp  = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
395      SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
396                                               MVT::Glue, MulOp1, MulOp2);
397
398      SDValue InFlag = SDValue(MulNode, 0);
399
400      if (Opcode == ISD::MUL)
401        return CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, InFlag);
402      else
403        return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
404    }
405
406    // Get target GOT address.
407    case ISD::GLOBAL_OFFSET_TABLE:
408      return getGlobalBaseReg();
409
410    case ISD::ConstantFP: {
411      ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
412      if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
413        SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
414                                        Mips::ZERO, MVT::i32);
415        SDValue Undef = SDValue(
416          CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0);
417        SDNode *MTC = CurDAG->getMachineNode(Mips::MTC1, dl, MVT::f32, Zero);
418        SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
419                            MVT::f64, Undef, SDValue(MTC, 0));
420        SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
421                            MVT::f64, I0, SDValue(MTC, 0));
422        ReplaceUses(SDValue(Node, 0), I1);
423        return I1.getNode();
424      }
425      break;
426    }
427
428    case ISD::LOAD:
429      if (SDNode *ResNode = SelectLoadFp64(Node))
430        return ResNode;
431      // Other cases are autogenerated.
432      break;
433
434    case ISD::STORE:
435      if (SDNode *ResNode = SelectStoreFp64(Node))
436        return ResNode;
437      // Other cases are autogenerated.
438      break;
439
440    case MipsISD::ThreadPointer: {
441      unsigned SrcReg = Mips::HWR29;
442      unsigned DestReg = Mips::V1;
443      SDNode *Rdhwr = CurDAG->getMachineNode(Mips::RDHWR, Node->getDebugLoc(),
444          Node->getValueType(0), CurDAG->getRegister(SrcReg, MVT::i32));
445      SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
446          SDValue(Rdhwr, 0));
447      SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, MVT::i32);
448      ReplaceUses(SDValue(Node, 0), ResNode);
449      return ResNode.getNode();
450    }
451  }
452
453  // Select the default instruction
454  SDNode *ResNode = SelectCode(Node);
455
456  DEBUG(errs() << "=> ");
457  if (ResNode == NULL || ResNode == Node)
458    DEBUG(Node->dump(CurDAG));
459  else
460    DEBUG(ResNode->dump(CurDAG));
461  DEBUG(errs() << "\n");
462  return ResNode;
463}
464
465/// createMipsISelDag - This pass converts a legalized DAG into a
466/// MIPS-specific DAG, ready for instruction scheduling.
467FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
468  return new MipsDAGToDAGISel(TM);
469}
470