MipsISelLowering.cpp revision 200a7434f6abc1e469fdf1ee547bc3fe4fbfcc02
15d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 25d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)// 35d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)// The LLVM Compiler Infrastructure 45d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)// 55d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)// This file is distributed under the University of Illinois Open Source 65d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)// License. See LICENSE.TXT for details. 7cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)// 85d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)//===----------------------------------------------------------------------===// 95f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// 105d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)// This file defines the interfaces that Mips uses to lower LLVM code into a 115d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)// selection DAG. 12cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)// 13cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)//===----------------------------------------------------------------------===// 14effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch#define DEBUG_TYPE "mips-lower" 155f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#include "MipsISelLowering.h" 16e5d81f57cb97b3b6b7fccc9c5610d21eb81db09dBen Murdoch#include "InstPrinter/MipsInstPrinter.h" 17cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#include "MCTargetDesc/MipsBaseInfo.h" 18cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#include "MipsMachineFunction.h" 195d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "MipsSubtarget.h" 20cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#include "MipsTargetMachine.h" 21cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#include "MipsTargetObjectFile.h" 225d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/ADT/Statistic.h" 235d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/CodeGen/CallingConvLower.h" 245d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/CodeGen/MachineFrameInfo.h" 255d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/CodeGen/MachineFunction.h" 265d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/CodeGen/MachineInstrBuilder.h" 275d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/CodeGen/MachineRegisterInfo.h" 28cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#include "llvm/CodeGen/SelectionDAGISel.h" 29cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#include "llvm/CodeGen/ValueTypes.h" 30cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#include "llvm/IR/CallingConv.h" 31cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#include "llvm/IR/DerivedTypes.h" 325d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/IR/GlobalVariable.h" 335d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/Support/CommandLine.h" 345d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/Support/Debug.h" 355d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/Support/ErrorHandling.h" 365d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include "llvm/Support/raw_ostream.h" 375d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include <cctype> 385d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 395d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)using namespace llvm; 405d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 415d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)STATISTIC(NumTailCalls, "Number of tail calls"); 425d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 435d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)static cl::opt<bool> 445d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)LargeGOT("mxgot", cl::Hidden, 455d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 46cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 475d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)static cl::opt<bool> 485d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 495d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) cl::desc("MIPS: Don't trap on integer division by zero."), 505d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) cl::init(false)); 515d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 525d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)static const uint16_t O32IntRegs[4] = { 535d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Mips::A0, Mips::A1, Mips::A2, Mips::A3 545d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)}; 555d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 56cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)static const uint16_t Mips64IntRegs[8] = { 57cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, 58cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 595d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)}; 605d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 615d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)static const uint16_t Mips64DPRegs[8] = { 625d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 635d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 645d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)}; 655d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 665d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)// If I is a shifted mask, set the size (Size) and the first bit of the 675d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)// mask (Pos), and return true. 68cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)// For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 69cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 70cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (!isShiftedMask_64(I)) 71cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return false; 72cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 73cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) Size = CountPopulation_64(I); 74cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) Pos = countTrailingZeros(I); 75cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return true; 76cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 77cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 78cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 79cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 80cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 81cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 82cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 83cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 84cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) SelectionDAG &DAG, 85cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) unsigned Flag) const { 865f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 875f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)} 885f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 895f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 905f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) SelectionDAG &DAG, 915f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) unsigned Flag) const { 925d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 935d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)} 945d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 95SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 96 SelectionDAG &DAG, 97 unsigned Flag) const { 98 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 99} 100 101SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 102 SelectionDAG &DAG, 103 unsigned Flag) const { 104 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 105} 106 107SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 108 SelectionDAG &DAG, 109 unsigned Flag) const { 110 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 111 N->getOffset(), Flag); 112} 113 114const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 115 switch (Opcode) { 116 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 117 case MipsISD::TailCall: return "MipsISD::TailCall"; 118 case MipsISD::Hi: return "MipsISD::Hi"; 119 case MipsISD::Lo: return "MipsISD::Lo"; 120 case MipsISD::GPRel: return "MipsISD::GPRel"; 121 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 122 case MipsISD::Ret: return "MipsISD::Ret"; 123 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 124 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 125 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 126 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 127 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 128 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 129 case MipsISD::ExtractLOHI: return "MipsISD::ExtractLOHI"; 130 case MipsISD::InsertLOHI: return "MipsISD::InsertLOHI"; 131 case MipsISD::Mult: return "MipsISD::Mult"; 132 case MipsISD::Multu: return "MipsISD::Multu"; 133 case MipsISD::MAdd: return "MipsISD::MAdd"; 134 case MipsISD::MAddu: return "MipsISD::MAddu"; 135 case MipsISD::MSub: return "MipsISD::MSub"; 136 case MipsISD::MSubu: return "MipsISD::MSubu"; 137 case MipsISD::DivRem: return "MipsISD::DivRem"; 138 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 139 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 140 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 141 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 142 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 143 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 144 case MipsISD::Sync: return "MipsISD::Sync"; 145 case MipsISD::Ext: return "MipsISD::Ext"; 146 case MipsISD::Ins: return "MipsISD::Ins"; 147 case MipsISD::LWL: return "MipsISD::LWL"; 148 case MipsISD::LWR: return "MipsISD::LWR"; 149 case MipsISD::SWL: return "MipsISD::SWL"; 150 case MipsISD::SWR: return "MipsISD::SWR"; 151 case MipsISD::LDL: return "MipsISD::LDL"; 152 case MipsISD::LDR: return "MipsISD::LDR"; 153 case MipsISD::SDL: return "MipsISD::SDL"; 154 case MipsISD::SDR: return "MipsISD::SDR"; 155 case MipsISD::EXTP: return "MipsISD::EXTP"; 156 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 157 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 158 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 159 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 160 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 161 case MipsISD::SHILO: return "MipsISD::SHILO"; 162 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 163 case MipsISD::MULT: return "MipsISD::MULT"; 164 case MipsISD::MULTU: return "MipsISD::MULTU"; 165 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 166 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 167 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 168 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 169 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 170 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 171 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 172 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 173 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 174 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 175 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 176 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 177 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 178 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 179 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 180 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 181 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 182 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 183 case MipsISD::VSMAX: return "MipsISD::VSMAX"; 184 case MipsISD::VSMIN: return "MipsISD::VSMIN"; 185 case MipsISD::VUMAX: return "MipsISD::VUMAX"; 186 case MipsISD::VUMIN: return "MipsISD::VUMIN"; 187 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 188 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 189 case MipsISD::VNOR: return "MipsISD::VNOR"; 190 case MipsISD::VSHF: return "MipsISD::VSHF"; 191 case MipsISD::SHF: return "MipsISD::SHF"; 192 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 193 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 194 case MipsISD::ILVL: return "MipsISD::ILVL"; 195 case MipsISD::ILVR: return "MipsISD::ILVR"; 196 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 197 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 198 default: return NULL; 199 } 200} 201 202MipsTargetLowering:: 203MipsTargetLowering(MipsTargetMachine &TM) 204 : TargetLowering(TM, new MipsTargetObjectFile()), 205 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 206 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()), 207 IsO32(Subtarget->isABI_O32()) { 208 // Mips does not have i1 type, so use i32 for 209 // setcc operations results (slt, sgt, ...). 210 setBooleanContents(ZeroOrOneBooleanContent); 211 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 212 213 // Load extented operations for i1 types must be promoted 214 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 215 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 216 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 217 218 // MIPS doesn't have extending float->double load/store 219 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 220 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 221 222 // Used by legalize types to correctly generate the setcc result. 223 // Without this, every float setcc comes with a AND/OR with the result, 224 // we don't want this, since the fpcmp result goes to a flag register, 225 // which is used implicitly by brcond and select operations. 226 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 227 228 // Mips Custom Operations 229 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 230 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 231 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 232 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 233 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 234 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 235 setOperationAction(ISD::SELECT, MVT::f32, Custom); 236 setOperationAction(ISD::SELECT, MVT::f64, Custom); 237 setOperationAction(ISD::SELECT, MVT::i32, Custom); 238 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 239 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 240 setOperationAction(ISD::SETCC, MVT::f32, Custom); 241 setOperationAction(ISD::SETCC, MVT::f64, Custom); 242 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 243 setOperationAction(ISD::VASTART, MVT::Other, Custom); 244 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 245 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 246 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 247 248 if (!TM.Options.NoNaNsFPMath) { 249 setOperationAction(ISD::FABS, MVT::f32, Custom); 250 setOperationAction(ISD::FABS, MVT::f64, Custom); 251 } 252 253 if (HasMips64) { 254 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 255 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 256 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 257 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 258 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 259 setOperationAction(ISD::SELECT, MVT::i64, Custom); 260 setOperationAction(ISD::LOAD, MVT::i64, Custom); 261 setOperationAction(ISD::STORE, MVT::i64, Custom); 262 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 263 } 264 265 if (!HasMips64) { 266 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 267 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 268 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 269 } 270 271 setOperationAction(ISD::ADD, MVT::i32, Custom); 272 if (HasMips64) 273 setOperationAction(ISD::ADD, MVT::i64, Custom); 274 275 setOperationAction(ISD::SDIV, MVT::i32, Expand); 276 setOperationAction(ISD::SREM, MVT::i32, Expand); 277 setOperationAction(ISD::UDIV, MVT::i32, Expand); 278 setOperationAction(ISD::UREM, MVT::i32, Expand); 279 setOperationAction(ISD::SDIV, MVT::i64, Expand); 280 setOperationAction(ISD::SREM, MVT::i64, Expand); 281 setOperationAction(ISD::UDIV, MVT::i64, Expand); 282 setOperationAction(ISD::UREM, MVT::i64, Expand); 283 284 // Operations not directly supported by Mips. 285 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 286 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 287 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 288 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 289 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 290 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 291 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 292 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 293 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 294 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 295 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 296 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 297 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 298 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 299 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 300 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 301 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 302 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 303 setOperationAction(ISD::ROTL, MVT::i32, Expand); 304 setOperationAction(ISD::ROTL, MVT::i64, Expand); 305 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 306 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 307 308 if (!Subtarget->hasMips32r2()) 309 setOperationAction(ISD::ROTR, MVT::i32, Expand); 310 311 if (!Subtarget->hasMips64r2()) 312 setOperationAction(ISD::ROTR, MVT::i64, Expand); 313 314 setOperationAction(ISD::FSIN, MVT::f32, Expand); 315 setOperationAction(ISD::FSIN, MVT::f64, Expand); 316 setOperationAction(ISD::FCOS, MVT::f32, Expand); 317 setOperationAction(ISD::FCOS, MVT::f64, Expand); 318 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 319 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 320 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 321 setOperationAction(ISD::FPOW, MVT::f32, Expand); 322 setOperationAction(ISD::FPOW, MVT::f64, Expand); 323 setOperationAction(ISD::FLOG, MVT::f32, Expand); 324 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 325 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 326 setOperationAction(ISD::FEXP, MVT::f32, Expand); 327 setOperationAction(ISD::FMA, MVT::f32, Expand); 328 setOperationAction(ISD::FMA, MVT::f64, Expand); 329 setOperationAction(ISD::FREM, MVT::f32, Expand); 330 setOperationAction(ISD::FREM, MVT::f64, Expand); 331 332 if (!TM.Options.NoNaNsFPMath) { 333 setOperationAction(ISD::FNEG, MVT::f32, Expand); 334 setOperationAction(ISD::FNEG, MVT::f64, Expand); 335 } 336 337 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 338 339 setOperationAction(ISD::VAARG, MVT::Other, Expand); 340 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 341 setOperationAction(ISD::VAEND, MVT::Other, Expand); 342 343 // Use the default for now 344 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 345 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 346 347 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 348 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 349 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 350 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 351 352 setInsertFencesForAtomic(true); 353 354 if (!Subtarget->hasSEInReg()) { 355 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 356 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 357 } 358 359 if (!Subtarget->hasBitCount()) { 360 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 361 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 362 } 363 364 if (!Subtarget->hasSwap()) { 365 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 366 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 367 } 368 369 if (HasMips64) { 370 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); 371 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom); 372 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom); 373 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 374 } 375 376 setOperationAction(ISD::TRAP, MVT::Other, Legal); 377 378 setTargetDAGCombine(ISD::SDIVREM); 379 setTargetDAGCombine(ISD::UDIVREM); 380 setTargetDAGCombine(ISD::SELECT); 381 setTargetDAGCombine(ISD::AND); 382 setTargetDAGCombine(ISD::OR); 383 setTargetDAGCombine(ISD::ADD); 384 385 setMinFunctionAlignment(HasMips64 ? 3 : 2); 386 387 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP); 388 389 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0); 390 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1); 391 392 MaxStoresPerMemcpy = 16; 393} 394 395const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) { 396 if (TM.getSubtargetImpl()->inMips16Mode()) 397 return llvm::createMips16TargetLowering(TM); 398 399 return llvm::createMipsSETargetLowering(TM); 400} 401 402EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { 403 if (!VT.isVector()) 404 return MVT::i32; 405 return VT.changeVectorElementTypeToInteger(); 406} 407 408static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 409 TargetLowering::DAGCombinerInfo &DCI, 410 const MipsSubtarget *Subtarget) { 411 if (DCI.isBeforeLegalizeOps()) 412 return SDValue(); 413 414 EVT Ty = N->getValueType(0); 415 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 416 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 417 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 418 MipsISD::DivRemU16; 419 SDLoc DL(N); 420 421 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 422 N->getOperand(0), N->getOperand(1)); 423 SDValue InChain = DAG.getEntryNode(); 424 SDValue InGlue = DivRem; 425 426 // insert MFLO 427 if (N->hasAnyUseOfValue(0)) { 428 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 429 InGlue); 430 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 431 InChain = CopyFromLo.getValue(1); 432 InGlue = CopyFromLo.getValue(2); 433 } 434 435 // insert MFHI 436 if (N->hasAnyUseOfValue(1)) { 437 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 438 HI, Ty, InGlue); 439 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 440 } 441 442 return SDValue(); 443} 444 445static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 446 switch (CC) { 447 default: llvm_unreachable("Unknown fp condition code!"); 448 case ISD::SETEQ: 449 case ISD::SETOEQ: return Mips::FCOND_OEQ; 450 case ISD::SETUNE: return Mips::FCOND_UNE; 451 case ISD::SETLT: 452 case ISD::SETOLT: return Mips::FCOND_OLT; 453 case ISD::SETGT: 454 case ISD::SETOGT: return Mips::FCOND_OGT; 455 case ISD::SETLE: 456 case ISD::SETOLE: return Mips::FCOND_OLE; 457 case ISD::SETGE: 458 case ISD::SETOGE: return Mips::FCOND_OGE; 459 case ISD::SETULT: return Mips::FCOND_ULT; 460 case ISD::SETULE: return Mips::FCOND_ULE; 461 case ISD::SETUGT: return Mips::FCOND_UGT; 462 case ISD::SETUGE: return Mips::FCOND_UGE; 463 case ISD::SETUO: return Mips::FCOND_UN; 464 case ISD::SETO: return Mips::FCOND_OR; 465 case ISD::SETNE: 466 case ISD::SETONE: return Mips::FCOND_ONE; 467 case ISD::SETUEQ: return Mips::FCOND_UEQ; 468 } 469} 470 471 472/// This function returns true if the floating point conditional branches and 473/// conditional moves which use condition code CC should be inverted. 474static bool invertFPCondCodeUser(Mips::CondCode CC) { 475 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 476 return false; 477 478 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 479 "Illegal Condition Code"); 480 481 return true; 482} 483 484// Creates and returns an FPCmp node from a setcc node. 485// Returns Op if setcc is not a floating point comparison. 486static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 487 // must be a SETCC node 488 if (Op.getOpcode() != ISD::SETCC) 489 return Op; 490 491 SDValue LHS = Op.getOperand(0); 492 493 if (!LHS.getValueType().isFloatingPoint()) 494 return Op; 495 496 SDValue RHS = Op.getOperand(1); 497 SDLoc DL(Op); 498 499 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 500 // node if necessary. 501 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 502 503 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 504 DAG.getConstant(condCodeToFCC(CC), MVT::i32)); 505} 506 507// Creates and returns a CMovFPT/F node. 508static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 509 SDValue False, SDLoc DL) { 510 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 511 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 512 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 513 514 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 515 True.getValueType(), True, FCC0, False, Cond); 516} 517 518static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 519 TargetLowering::DAGCombinerInfo &DCI, 520 const MipsSubtarget *Subtarget) { 521 if (DCI.isBeforeLegalizeOps()) 522 return SDValue(); 523 524 SDValue SetCC = N->getOperand(0); 525 526 if ((SetCC.getOpcode() != ISD::SETCC) || 527 !SetCC.getOperand(0).getValueType().isInteger()) 528 return SDValue(); 529 530 SDValue False = N->getOperand(2); 531 EVT FalseTy = False.getValueType(); 532 533 if (!FalseTy.isInteger()) 534 return SDValue(); 535 536 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False); 537 538 if (!CN || CN->getZExtValue()) 539 return SDValue(); 540 541 const SDLoc DL(N); 542 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 543 SDValue True = N->getOperand(1); 544 545 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 546 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 547 548 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 549} 550 551static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 552 TargetLowering::DAGCombinerInfo &DCI, 553 const MipsSubtarget *Subtarget) { 554 // Pattern match EXT. 555 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 556 // => ext $dst, $src, size, pos 557 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 558 return SDValue(); 559 560 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 561 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 562 563 // Op's first operand must be a shift right. 564 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 565 return SDValue(); 566 567 // The second operand of the shift must be an immediate. 568 ConstantSDNode *CN; 569 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 570 return SDValue(); 571 572 uint64_t Pos = CN->getZExtValue(); 573 uint64_t SMPos, SMSize; 574 575 // Op's second operand must be a shifted mask. 576 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 577 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 578 return SDValue(); 579 580 // Return if the shifted mask does not start at bit 0 or the sum of its size 581 // and Pos exceeds the word's size. 582 EVT ValTy = N->getValueType(0); 583 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 584 return SDValue(); 585 586 return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy, 587 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), 588 DAG.getConstant(SMSize, MVT::i32)); 589} 590 591static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 592 TargetLowering::DAGCombinerInfo &DCI, 593 const MipsSubtarget *Subtarget) { 594 // Pattern match INS. 595 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 596 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 597 // => ins $dst, $src, size, pos, $src1 598 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 599 return SDValue(); 600 601 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 602 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 603 ConstantSDNode *CN; 604 605 // See if Op's first operand matches (and $src1 , mask0). 606 if (And0.getOpcode() != ISD::AND) 607 return SDValue(); 608 609 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 610 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 611 return SDValue(); 612 613 // See if Op's second operand matches (and (shl $src, pos), mask1). 614 if (And1.getOpcode() != ISD::AND) 615 return SDValue(); 616 617 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 618 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 619 return SDValue(); 620 621 // The shift masks must have the same position and size. 622 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 623 return SDValue(); 624 625 SDValue Shl = And1.getOperand(0); 626 if (Shl.getOpcode() != ISD::SHL) 627 return SDValue(); 628 629 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 630 return SDValue(); 631 632 unsigned Shamt = CN->getZExtValue(); 633 634 // Return if the shift amount and the first bit position of mask are not the 635 // same. 636 EVT ValTy = N->getValueType(0); 637 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 638 return SDValue(); 639 640 return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0), 641 DAG.getConstant(SMPos0, MVT::i32), 642 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0)); 643} 644 645static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 646 TargetLowering::DAGCombinerInfo &DCI, 647 const MipsSubtarget *Subtarget) { 648 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 649 650 if (DCI.isBeforeLegalizeOps()) 651 return SDValue(); 652 653 SDValue Add = N->getOperand(1); 654 655 if (Add.getOpcode() != ISD::ADD) 656 return SDValue(); 657 658 SDValue Lo = Add.getOperand(1); 659 660 if ((Lo.getOpcode() != MipsISD::Lo) || 661 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 662 return SDValue(); 663 664 EVT ValTy = N->getValueType(0); 665 SDLoc DL(N); 666 667 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 668 Add.getOperand(0)); 669 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 670} 671 672SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 673 const { 674 SelectionDAG &DAG = DCI.DAG; 675 unsigned Opc = N->getOpcode(); 676 677 switch (Opc) { 678 default: break; 679 case ISD::SDIVREM: 680 case ISD::UDIVREM: 681 return performDivRemCombine(N, DAG, DCI, Subtarget); 682 case ISD::SELECT: 683 return performSELECTCombine(N, DAG, DCI, Subtarget); 684 case ISD::AND: 685 return performANDCombine(N, DAG, DCI, Subtarget); 686 case ISD::OR: 687 return performORCombine(N, DAG, DCI, Subtarget); 688 case ISD::ADD: 689 return performADDCombine(N, DAG, DCI, Subtarget); 690 } 691 692 return SDValue(); 693} 694 695void 696MipsTargetLowering::LowerOperationWrapper(SDNode *N, 697 SmallVectorImpl<SDValue> &Results, 698 SelectionDAG &DAG) const { 699 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 700 701 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 702 Results.push_back(Res.getValue(I)); 703} 704 705void 706MipsTargetLowering::ReplaceNodeResults(SDNode *N, 707 SmallVectorImpl<SDValue> &Results, 708 SelectionDAG &DAG) const { 709 return LowerOperationWrapper(N, Results, DAG); 710} 711 712SDValue MipsTargetLowering:: 713LowerOperation(SDValue Op, SelectionDAG &DAG) const 714{ 715 switch (Op.getOpcode()) 716 { 717 case ISD::BR_JT: return lowerBR_JT(Op, DAG); 718 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 719 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 720 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 721 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 722 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 723 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 724 case ISD::SELECT: return lowerSELECT(Op, DAG); 725 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG); 726 case ISD::SETCC: return lowerSETCC(Op, DAG); 727 case ISD::VASTART: return lowerVASTART(Op, DAG); 728 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 729 case ISD::FABS: return lowerFABS(Op, DAG); 730 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 731 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 732 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 733 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 734 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 735 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 736 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 737 case ISD::LOAD: return lowerLOAD(Op, DAG); 738 case ISD::STORE: return lowerSTORE(Op, DAG); 739 case ISD::ADD: return lowerADD(Op, DAG); 740 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 741 } 742 return SDValue(); 743} 744 745//===----------------------------------------------------------------------===// 746// Lower helper functions 747//===----------------------------------------------------------------------===// 748 749// addLiveIn - This helper function adds the specified physical register to the 750// MachineFunction as a live in value. It also creates a corresponding 751// virtual register for it. 752static unsigned 753addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 754{ 755 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 756 MF.getRegInfo().addLiveIn(PReg, VReg); 757 return VReg; 758} 759 760static MachineBasicBlock *expandPseudoDIV(MachineInstr *MI, 761 MachineBasicBlock &MBB, 762 const TargetInstrInfo &TII, 763 bool Is64Bit) { 764 if (NoZeroDivCheck) 765 return &MBB; 766 767 // Insert instruction "teq $divisor_reg, $zero, 7". 768 MachineBasicBlock::iterator I(MI); 769 MachineInstrBuilder MIB; 770 MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ)) 771 .addOperand(MI->getOperand(2)).addReg(Mips::ZERO).addImm(7); 772 773 // Use the 32-bit sub-register if this is a 64-bit division. 774 if (Is64Bit) 775 MIB->getOperand(0).setSubReg(Mips::sub_32); 776 777 return &MBB; 778} 779 780MachineBasicBlock * 781MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 782 MachineBasicBlock *BB) const { 783 switch (MI->getOpcode()) { 784 default: 785 llvm_unreachable("Unexpected instr type to insert"); 786 case Mips::ATOMIC_LOAD_ADD_I8: 787 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 788 case Mips::ATOMIC_LOAD_ADD_I16: 789 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 790 case Mips::ATOMIC_LOAD_ADD_I32: 791 return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 792 case Mips::ATOMIC_LOAD_ADD_I64: 793 return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 794 795 case Mips::ATOMIC_LOAD_AND_I8: 796 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 797 case Mips::ATOMIC_LOAD_AND_I16: 798 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 799 case Mips::ATOMIC_LOAD_AND_I32: 800 return emitAtomicBinary(MI, BB, 4, Mips::AND); 801 case Mips::ATOMIC_LOAD_AND_I64: 802 return emitAtomicBinary(MI, BB, 8, Mips::AND64); 803 804 case Mips::ATOMIC_LOAD_OR_I8: 805 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 806 case Mips::ATOMIC_LOAD_OR_I16: 807 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 808 case Mips::ATOMIC_LOAD_OR_I32: 809 return emitAtomicBinary(MI, BB, 4, Mips::OR); 810 case Mips::ATOMIC_LOAD_OR_I64: 811 return emitAtomicBinary(MI, BB, 8, Mips::OR64); 812 813 case Mips::ATOMIC_LOAD_XOR_I8: 814 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 815 case Mips::ATOMIC_LOAD_XOR_I16: 816 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 817 case Mips::ATOMIC_LOAD_XOR_I32: 818 return emitAtomicBinary(MI, BB, 4, Mips::XOR); 819 case Mips::ATOMIC_LOAD_XOR_I64: 820 return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 821 822 case Mips::ATOMIC_LOAD_NAND_I8: 823 return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 824 case Mips::ATOMIC_LOAD_NAND_I16: 825 return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 826 case Mips::ATOMIC_LOAD_NAND_I32: 827 return emitAtomicBinary(MI, BB, 4, 0, true); 828 case Mips::ATOMIC_LOAD_NAND_I64: 829 return emitAtomicBinary(MI, BB, 8, 0, true); 830 831 case Mips::ATOMIC_LOAD_SUB_I8: 832 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 833 case Mips::ATOMIC_LOAD_SUB_I16: 834 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 835 case Mips::ATOMIC_LOAD_SUB_I32: 836 return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 837 case Mips::ATOMIC_LOAD_SUB_I64: 838 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 839 840 case Mips::ATOMIC_SWAP_I8: 841 return emitAtomicBinaryPartword(MI, BB, 1, 0); 842 case Mips::ATOMIC_SWAP_I16: 843 return emitAtomicBinaryPartword(MI, BB, 2, 0); 844 case Mips::ATOMIC_SWAP_I32: 845 return emitAtomicBinary(MI, BB, 4, 0); 846 case Mips::ATOMIC_SWAP_I64: 847 return emitAtomicBinary(MI, BB, 8, 0); 848 849 case Mips::ATOMIC_CMP_SWAP_I8: 850 return emitAtomicCmpSwapPartword(MI, BB, 1); 851 case Mips::ATOMIC_CMP_SWAP_I16: 852 return emitAtomicCmpSwapPartword(MI, BB, 2); 853 case Mips::ATOMIC_CMP_SWAP_I32: 854 return emitAtomicCmpSwap(MI, BB, 4); 855 case Mips::ATOMIC_CMP_SWAP_I64: 856 return emitAtomicCmpSwap(MI, BB, 8); 857 case Mips::PseudoSDIV: 858 case Mips::PseudoUDIV: 859 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), false); 860 case Mips::PseudoDSDIV: 861 case Mips::PseudoDUDIV: 862 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), true); 863 } 864} 865 866// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 867// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 868MachineBasicBlock * 869MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 870 unsigned Size, unsigned BinOpcode, 871 bool Nand) const { 872 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 873 874 MachineFunction *MF = BB->getParent(); 875 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 876 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 877 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 878 DebugLoc DL = MI->getDebugLoc(); 879 unsigned LL, SC, AND, NOR, ZERO, BEQ; 880 881 if (Size == 4) { 882 LL = Mips::LL; 883 SC = Mips::SC; 884 AND = Mips::AND; 885 NOR = Mips::NOR; 886 ZERO = Mips::ZERO; 887 BEQ = Mips::BEQ; 888 } 889 else { 890 LL = Mips::LLD; 891 SC = Mips::SCD; 892 AND = Mips::AND64; 893 NOR = Mips::NOR64; 894 ZERO = Mips::ZERO_64; 895 BEQ = Mips::BEQ64; 896 } 897 898 unsigned OldVal = MI->getOperand(0).getReg(); 899 unsigned Ptr = MI->getOperand(1).getReg(); 900 unsigned Incr = MI->getOperand(2).getReg(); 901 902 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 903 unsigned AndRes = RegInfo.createVirtualRegister(RC); 904 unsigned Success = RegInfo.createVirtualRegister(RC); 905 906 // insert new blocks after the current block 907 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 908 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 909 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 910 MachineFunction::iterator It = BB; 911 ++It; 912 MF->insert(It, loopMBB); 913 MF->insert(It, exitMBB); 914 915 // Transfer the remainder of BB and its successor edges to exitMBB. 916 exitMBB->splice(exitMBB->begin(), BB, 917 llvm::next(MachineBasicBlock::iterator(MI)), 918 BB->end()); 919 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 920 921 // thisMBB: 922 // ... 923 // fallthrough --> loopMBB 924 BB->addSuccessor(loopMBB); 925 loopMBB->addSuccessor(loopMBB); 926 loopMBB->addSuccessor(exitMBB); 927 928 // loopMBB: 929 // ll oldval, 0(ptr) 930 // <binop> storeval, oldval, incr 931 // sc success, storeval, 0(ptr) 932 // beq success, $0, loopMBB 933 BB = loopMBB; 934 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 935 if (Nand) { 936 // and andres, oldval, incr 937 // nor storeval, $0, andres 938 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 939 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 940 } else if (BinOpcode) { 941 // <binop> storeval, oldval, incr 942 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 943 } else { 944 StoreVal = Incr; 945 } 946 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 947 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 948 949 MI->eraseFromParent(); // The instruction is gone now. 950 951 return exitMBB; 952} 953 954MachineBasicBlock * 955MipsTargetLowering::emitAtomicBinaryPartword(MachineInstr *MI, 956 MachineBasicBlock *BB, 957 unsigned Size, unsigned BinOpcode, 958 bool Nand) const { 959 assert((Size == 1 || Size == 2) && 960 "Unsupported size for EmitAtomicBinaryPartial."); 961 962 MachineFunction *MF = BB->getParent(); 963 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 964 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 965 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 966 DebugLoc DL = MI->getDebugLoc(); 967 968 unsigned Dest = MI->getOperand(0).getReg(); 969 unsigned Ptr = MI->getOperand(1).getReg(); 970 unsigned Incr = MI->getOperand(2).getReg(); 971 972 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 973 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 974 unsigned Mask = RegInfo.createVirtualRegister(RC); 975 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 976 unsigned NewVal = RegInfo.createVirtualRegister(RC); 977 unsigned OldVal = RegInfo.createVirtualRegister(RC); 978 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 979 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 980 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 981 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 982 unsigned AndRes = RegInfo.createVirtualRegister(RC); 983 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 984 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 985 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 986 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 987 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 988 unsigned SllRes = RegInfo.createVirtualRegister(RC); 989 unsigned Success = RegInfo.createVirtualRegister(RC); 990 991 // insert new blocks after the current block 992 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 993 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 994 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 995 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 996 MachineFunction::iterator It = BB; 997 ++It; 998 MF->insert(It, loopMBB); 999 MF->insert(It, sinkMBB); 1000 MF->insert(It, exitMBB); 1001 1002 // Transfer the remainder of BB and its successor edges to exitMBB. 1003 exitMBB->splice(exitMBB->begin(), BB, 1004 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1005 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1006 1007 BB->addSuccessor(loopMBB); 1008 loopMBB->addSuccessor(loopMBB); 1009 loopMBB->addSuccessor(sinkMBB); 1010 sinkMBB->addSuccessor(exitMBB); 1011 1012 // thisMBB: 1013 // addiu masklsb2,$0,-4 # 0xfffffffc 1014 // and alignedaddr,ptr,masklsb2 1015 // andi ptrlsb2,ptr,3 1016 // sll shiftamt,ptrlsb2,3 1017 // ori maskupper,$0,255 # 0xff 1018 // sll mask,maskupper,shiftamt 1019 // nor mask2,$0,mask 1020 // sll incr2,incr,shiftamt 1021 1022 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1023 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1024 .addReg(Mips::ZERO).addImm(-4); 1025 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1026 .addReg(Ptr).addReg(MaskLSB2); 1027 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1028 if (Subtarget->isLittle()) { 1029 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1030 } else { 1031 unsigned Off = RegInfo.createVirtualRegister(RC); 1032 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1033 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1034 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1035 } 1036 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1037 .addReg(Mips::ZERO).addImm(MaskImm); 1038 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1039 .addReg(MaskUpper).addReg(ShiftAmt); 1040 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1041 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1042 1043 // atomic.load.binop 1044 // loopMBB: 1045 // ll oldval,0(alignedaddr) 1046 // binop binopres,oldval,incr2 1047 // and newval,binopres,mask 1048 // and maskedoldval0,oldval,mask2 1049 // or storeval,maskedoldval0,newval 1050 // sc success,storeval,0(alignedaddr) 1051 // beq success,$0,loopMBB 1052 1053 // atomic.swap 1054 // loopMBB: 1055 // ll oldval,0(alignedaddr) 1056 // and newval,incr2,mask 1057 // and maskedoldval0,oldval,mask2 1058 // or storeval,maskedoldval0,newval 1059 // sc success,storeval,0(alignedaddr) 1060 // beq success,$0,loopMBB 1061 1062 BB = loopMBB; 1063 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1064 if (Nand) { 1065 // and andres, oldval, incr2 1066 // nor binopres, $0, andres 1067 // and newval, binopres, mask 1068 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1069 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1070 .addReg(Mips::ZERO).addReg(AndRes); 1071 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1072 } else if (BinOpcode) { 1073 // <binop> binopres, oldval, incr2 1074 // and newval, binopres, mask 1075 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1076 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1077 } else {// atomic.swap 1078 // and newval, incr2, mask 1079 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1080 } 1081 1082 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1083 .addReg(OldVal).addReg(Mask2); 1084 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1085 .addReg(MaskedOldVal0).addReg(NewVal); 1086 BuildMI(BB, DL, TII->get(Mips::SC), Success) 1087 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1088 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1089 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1090 1091 // sinkMBB: 1092 // and maskedoldval1,oldval,mask 1093 // srl srlres,maskedoldval1,shiftamt 1094 // sll sllres,srlres,24 1095 // sra dest,sllres,24 1096 BB = sinkMBB; 1097 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1098 1099 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1100 .addReg(OldVal).addReg(Mask); 1101 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1102 .addReg(MaskedOldVal1).addReg(ShiftAmt); 1103 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes) 1104 .addReg(SrlRes).addImm(ShiftImm); 1105 BuildMI(BB, DL, TII->get(Mips::SRA), Dest) 1106 .addReg(SllRes).addImm(ShiftImm); 1107 1108 MI->eraseFromParent(); // The instruction is gone now. 1109 1110 return exitMBB; 1111} 1112 1113MachineBasicBlock * 1114MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI, 1115 MachineBasicBlock *BB, 1116 unsigned Size) const { 1117 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1118 1119 MachineFunction *MF = BB->getParent(); 1120 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1121 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1122 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1123 DebugLoc DL = MI->getDebugLoc(); 1124 unsigned LL, SC, ZERO, BNE, BEQ; 1125 1126 if (Size == 4) { 1127 LL = Mips::LL; 1128 SC = Mips::SC; 1129 ZERO = Mips::ZERO; 1130 BNE = Mips::BNE; 1131 BEQ = Mips::BEQ; 1132 } 1133 else { 1134 LL = Mips::LLD; 1135 SC = Mips::SCD; 1136 ZERO = Mips::ZERO_64; 1137 BNE = Mips::BNE64; 1138 BEQ = Mips::BEQ64; 1139 } 1140 1141 unsigned Dest = MI->getOperand(0).getReg(); 1142 unsigned Ptr = MI->getOperand(1).getReg(); 1143 unsigned OldVal = MI->getOperand(2).getReg(); 1144 unsigned NewVal = MI->getOperand(3).getReg(); 1145 1146 unsigned Success = RegInfo.createVirtualRegister(RC); 1147 1148 // insert new blocks after the current block 1149 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1150 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1151 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1152 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1153 MachineFunction::iterator It = BB; 1154 ++It; 1155 MF->insert(It, loop1MBB); 1156 MF->insert(It, loop2MBB); 1157 MF->insert(It, exitMBB); 1158 1159 // Transfer the remainder of BB and its successor edges to exitMBB. 1160 exitMBB->splice(exitMBB->begin(), BB, 1161 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1162 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1163 1164 // thisMBB: 1165 // ... 1166 // fallthrough --> loop1MBB 1167 BB->addSuccessor(loop1MBB); 1168 loop1MBB->addSuccessor(exitMBB); 1169 loop1MBB->addSuccessor(loop2MBB); 1170 loop2MBB->addSuccessor(loop1MBB); 1171 loop2MBB->addSuccessor(exitMBB); 1172 1173 // loop1MBB: 1174 // ll dest, 0(ptr) 1175 // bne dest, oldval, exitMBB 1176 BB = loop1MBB; 1177 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1178 BuildMI(BB, DL, TII->get(BNE)) 1179 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1180 1181 // loop2MBB: 1182 // sc success, newval, 0(ptr) 1183 // beq success, $0, loop1MBB 1184 BB = loop2MBB; 1185 BuildMI(BB, DL, TII->get(SC), Success) 1186 .addReg(NewVal).addReg(Ptr).addImm(0); 1187 BuildMI(BB, DL, TII->get(BEQ)) 1188 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1189 1190 MI->eraseFromParent(); // The instruction is gone now. 1191 1192 return exitMBB; 1193} 1194 1195MachineBasicBlock * 1196MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, 1197 MachineBasicBlock *BB, 1198 unsigned Size) const { 1199 assert((Size == 1 || Size == 2) && 1200 "Unsupported size for EmitAtomicCmpSwapPartial."); 1201 1202 MachineFunction *MF = BB->getParent(); 1203 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1204 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1205 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1206 DebugLoc DL = MI->getDebugLoc(); 1207 1208 unsigned Dest = MI->getOperand(0).getReg(); 1209 unsigned Ptr = MI->getOperand(1).getReg(); 1210 unsigned CmpVal = MI->getOperand(2).getReg(); 1211 unsigned NewVal = MI->getOperand(3).getReg(); 1212 1213 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1214 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1215 unsigned Mask = RegInfo.createVirtualRegister(RC); 1216 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1217 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1218 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1219 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1220 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1221 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1222 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1223 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1224 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1225 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1226 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1227 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1228 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1229 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1230 unsigned Success = RegInfo.createVirtualRegister(RC); 1231 1232 // insert new blocks after the current block 1233 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1234 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1235 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1236 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1237 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1238 MachineFunction::iterator It = BB; 1239 ++It; 1240 MF->insert(It, loop1MBB); 1241 MF->insert(It, loop2MBB); 1242 MF->insert(It, sinkMBB); 1243 MF->insert(It, exitMBB); 1244 1245 // Transfer the remainder of BB and its successor edges to exitMBB. 1246 exitMBB->splice(exitMBB->begin(), BB, 1247 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1248 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1249 1250 BB->addSuccessor(loop1MBB); 1251 loop1MBB->addSuccessor(sinkMBB); 1252 loop1MBB->addSuccessor(loop2MBB); 1253 loop2MBB->addSuccessor(loop1MBB); 1254 loop2MBB->addSuccessor(sinkMBB); 1255 sinkMBB->addSuccessor(exitMBB); 1256 1257 // FIXME: computation of newval2 can be moved to loop2MBB. 1258 // thisMBB: 1259 // addiu masklsb2,$0,-4 # 0xfffffffc 1260 // and alignedaddr,ptr,masklsb2 1261 // andi ptrlsb2,ptr,3 1262 // sll shiftamt,ptrlsb2,3 1263 // ori maskupper,$0,255 # 0xff 1264 // sll mask,maskupper,shiftamt 1265 // nor mask2,$0,mask 1266 // andi maskedcmpval,cmpval,255 1267 // sll shiftedcmpval,maskedcmpval,shiftamt 1268 // andi maskednewval,newval,255 1269 // sll shiftednewval,maskednewval,shiftamt 1270 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1271 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1272 .addReg(Mips::ZERO).addImm(-4); 1273 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1274 .addReg(Ptr).addReg(MaskLSB2); 1275 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1276 if (Subtarget->isLittle()) { 1277 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1278 } else { 1279 unsigned Off = RegInfo.createVirtualRegister(RC); 1280 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1281 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1282 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1283 } 1284 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1285 .addReg(Mips::ZERO).addImm(MaskImm); 1286 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1287 .addReg(MaskUpper).addReg(ShiftAmt); 1288 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1289 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1290 .addReg(CmpVal).addImm(MaskImm); 1291 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1292 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1293 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1294 .addReg(NewVal).addImm(MaskImm); 1295 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1296 .addReg(MaskedNewVal).addReg(ShiftAmt); 1297 1298 // loop1MBB: 1299 // ll oldval,0(alginedaddr) 1300 // and maskedoldval0,oldval,mask 1301 // bne maskedoldval0,shiftedcmpval,sinkMBB 1302 BB = loop1MBB; 1303 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1304 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1305 .addReg(OldVal).addReg(Mask); 1306 BuildMI(BB, DL, TII->get(Mips::BNE)) 1307 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1308 1309 // loop2MBB: 1310 // and maskedoldval1,oldval,mask2 1311 // or storeval,maskedoldval1,shiftednewval 1312 // sc success,storeval,0(alignedaddr) 1313 // beq success,$0,loop1MBB 1314 BB = loop2MBB; 1315 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1316 .addReg(OldVal).addReg(Mask2); 1317 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1318 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1319 BuildMI(BB, DL, TII->get(Mips::SC), Success) 1320 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1321 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1322 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1323 1324 // sinkMBB: 1325 // srl srlres,maskedoldval0,shiftamt 1326 // sll sllres,srlres,24 1327 // sra dest,sllres,24 1328 BB = sinkMBB; 1329 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1330 1331 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1332 .addReg(MaskedOldVal0).addReg(ShiftAmt); 1333 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes) 1334 .addReg(SrlRes).addImm(ShiftImm); 1335 BuildMI(BB, DL, TII->get(Mips::SRA), Dest) 1336 .addReg(SllRes).addImm(ShiftImm); 1337 1338 MI->eraseFromParent(); // The instruction is gone now. 1339 1340 return exitMBB; 1341} 1342 1343//===----------------------------------------------------------------------===// 1344// Misc Lower Operation implementation 1345//===----------------------------------------------------------------------===// 1346SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 1347 SDValue Chain = Op.getOperand(0); 1348 SDValue Table = Op.getOperand(1); 1349 SDValue Index = Op.getOperand(2); 1350 SDLoc DL(Op); 1351 EVT PTy = getPointerTy(); 1352 unsigned EntrySize = 1353 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout()); 1354 1355 Index = DAG.getNode(ISD::MUL, DL, PTy, Index, 1356 DAG.getConstant(EntrySize, PTy)); 1357 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table); 1358 1359 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 1360 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr, 1361 MachinePointerInfo::getJumpTable(), MemVT, false, false, 1362 0); 1363 Chain = Addr.getValue(1); 1364 1365 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) { 1366 // For PIC, the sequence is: 1367 // BRIND(load(Jumptable + index) + RelocBase) 1368 // RelocBase can be JumpTable, GOT or some sort of global base. 1369 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr, 1370 getPICJumpTableRelocBase(Table, DAG)); 1371 } 1372 1373 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr); 1374} 1375 1376SDValue MipsTargetLowering:: 1377lowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1378{ 1379 // The first operand is the chain, the second is the condition, the third is 1380 // the block to branch to if the condition is true. 1381 SDValue Chain = Op.getOperand(0); 1382 SDValue Dest = Op.getOperand(2); 1383 SDLoc DL(Op); 1384 1385 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1386 1387 // Return if flag is not set by a floating point comparison. 1388 if (CondRes.getOpcode() != MipsISD::FPCmp) 1389 return Op; 1390 1391 SDValue CCNode = CondRes.getOperand(2); 1392 Mips::CondCode CC = 1393 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1394 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1395 SDValue BrCode = DAG.getConstant(Opc, MVT::i32); 1396 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1397 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1398 FCC0, Dest, CondRes); 1399} 1400 1401SDValue MipsTargetLowering:: 1402lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1403{ 1404 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1405 1406 // Return if flag is not set by a floating point comparison. 1407 if (Cond.getOpcode() != MipsISD::FPCmp) 1408 return Op; 1409 1410 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1411 SDLoc(Op)); 1412} 1413 1414SDValue MipsTargetLowering:: 1415lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 1416{ 1417 SDLoc DL(Op); 1418 EVT Ty = Op.getOperand(0).getValueType(); 1419 SDValue Cond = DAG.getNode(ISD::SETCC, DL, 1420 getSetCCResultType(*DAG.getContext(), Ty), 1421 Op.getOperand(0), Op.getOperand(1), 1422 Op.getOperand(4)); 1423 1424 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2), 1425 Op.getOperand(3)); 1426} 1427 1428SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1429 SDValue Cond = createFPCmp(DAG, Op); 1430 1431 assert(Cond.getOpcode() == MipsISD::FPCmp && 1432 "Floating point operand expected."); 1433 1434 SDValue True = DAG.getConstant(1, MVT::i32); 1435 SDValue False = DAG.getConstant(0, MVT::i32); 1436 1437 return createCMovFP(DAG, Cond, True, False, SDLoc(Op)); 1438} 1439 1440SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 1441 SelectionDAG &DAG) const { 1442 // FIXME there isn't actually debug info here 1443 SDLoc DL(Op); 1444 EVT Ty = Op.getValueType(); 1445 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 1446 const GlobalValue *GV = N->getGlobal(); 1447 1448 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1449 const MipsTargetObjectFile &TLOF = 1450 (const MipsTargetObjectFile&)getObjFileLowering(); 1451 1452 // %gp_rel relocation 1453 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1454 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0, 1455 MipsII::MO_GPREL); 1456 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL, 1457 DAG.getVTList(MVT::i32), &GA, 1); 1458 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32); 1459 return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode); 1460 } 1461 1462 // %hi/%lo relocation 1463 return getAddrNonPIC(N, Ty, DAG); 1464 } 1465 1466 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV))) 1467 return getAddrLocal(N, Ty, DAG, HasMips64); 1468 1469 if (LargeGOT) 1470 return getAddrGlobalLargeGOT(N, Ty, DAG, MipsII::MO_GOT_HI16, 1471 MipsII::MO_GOT_LO16); 1472 1473 return getAddrGlobal(N, Ty, DAG, 1474 HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16); 1475} 1476 1477SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 1478 SelectionDAG &DAG) const { 1479 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 1480 EVT Ty = Op.getValueType(); 1481 1482 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1483 return getAddrNonPIC(N, Ty, DAG); 1484 1485 return getAddrLocal(N, Ty, DAG, HasMips64); 1486} 1487 1488SDValue MipsTargetLowering:: 1489lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1490{ 1491 // If the relocation model is PIC, use the General Dynamic TLS Model or 1492 // Local Dynamic TLS model, otherwise use the Initial Exec or 1493 // Local Exec TLS Model. 1494 1495 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1496 SDLoc DL(GA); 1497 const GlobalValue *GV = GA->getGlobal(); 1498 EVT PtrVT = getPointerTy(); 1499 1500 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1501 1502 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1503 // General Dynamic and Local Dynamic TLS Model. 1504 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1505 : MipsII::MO_TLSGD; 1506 1507 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 1508 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 1509 getGlobalReg(DAG, PtrVT), TGA); 1510 unsigned PtrSize = PtrVT.getSizeInBits(); 1511 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1512 1513 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1514 1515 ArgListTy Args; 1516 ArgListEntry Entry; 1517 Entry.Node = Argument; 1518 Entry.Ty = PtrTy; 1519 Args.push_back(Entry); 1520 1521 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy, 1522 false, false, false, false, 0, CallingConv::C, 1523 /*IsTailCall=*/false, /*doesNotRet=*/false, 1524 /*isReturnValueUsed=*/true, 1525 TlsGetAddr, Args, DAG, DL); 1526 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1527 1528 SDValue Ret = CallResult.first; 1529 1530 if (model != TLSModel::LocalDynamic) 1531 return Ret; 1532 1533 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1534 MipsII::MO_DTPREL_HI); 1535 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1536 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1537 MipsII::MO_DTPREL_LO); 1538 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1539 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 1540 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 1541 } 1542 1543 SDValue Offset; 1544 if (model == TLSModel::InitialExec) { 1545 // Initial Exec TLS Model 1546 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1547 MipsII::MO_GOTTPREL); 1548 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 1549 TGA); 1550 Offset = DAG.getLoad(PtrVT, DL, 1551 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1552 false, false, false, 0); 1553 } else { 1554 // Local Exec TLS Model 1555 assert(model == TLSModel::LocalExec); 1556 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1557 MipsII::MO_TPREL_HI); 1558 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1559 MipsII::MO_TPREL_LO); 1560 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1561 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1562 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1563 } 1564 1565 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 1566 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 1567} 1568 1569SDValue MipsTargetLowering:: 1570lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1571{ 1572 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 1573 EVT Ty = Op.getValueType(); 1574 1575 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1576 return getAddrNonPIC(N, Ty, DAG); 1577 1578 return getAddrLocal(N, Ty, DAG, HasMips64); 1579} 1580 1581SDValue MipsTargetLowering:: 1582lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1583{ 1584 // gp_rel relocation 1585 // FIXME: we should reference the constant pool using small data sections, 1586 // but the asm printer currently doesn't support this feature without 1587 // hacking it. This feature should come soon so we can uncomment the 1588 // stuff below. 1589 //if (IsInSmallSection(C->getType())) { 1590 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1591 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1592 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1593 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1594 EVT Ty = Op.getValueType(); 1595 1596 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1597 return getAddrNonPIC(N, Ty, DAG); 1598 1599 return getAddrLocal(N, Ty, DAG, HasMips64); 1600} 1601 1602SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1603 MachineFunction &MF = DAG.getMachineFunction(); 1604 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1605 1606 SDLoc DL(Op); 1607 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1608 getPointerTy()); 1609 1610 // vastart just stores the address of the VarArgsFrameIndex slot into the 1611 // memory location argument. 1612 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1613 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 1614 MachinePointerInfo(SV), false, false, 0); 1615} 1616 1617static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1618 EVT TyX = Op.getOperand(0).getValueType(); 1619 EVT TyY = Op.getOperand(1).getValueType(); 1620 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1621 SDValue Const31 = DAG.getConstant(31, MVT::i32); 1622 SDLoc DL(Op); 1623 SDValue Res; 1624 1625 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1626 // to i32. 1627 SDValue X = (TyX == MVT::f32) ? 1628 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1629 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1630 Const1); 1631 SDValue Y = (TyY == MVT::f32) ? 1632 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 1633 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 1634 Const1); 1635 1636 if (HasR2) { 1637 // ext E, Y, 31, 1 ; extract bit31 of Y 1638 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 1639 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 1640 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 1641 } else { 1642 // sll SllX, X, 1 1643 // srl SrlX, SllX, 1 1644 // srl SrlY, Y, 31 1645 // sll SllY, SrlX, 31 1646 // or Or, SrlX, SllY 1647 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1648 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1649 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 1650 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 1651 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 1652 } 1653 1654 if (TyX == MVT::f32) 1655 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 1656 1657 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1658 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1659 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1660} 1661 1662static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1663 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 1664 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 1665 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 1666 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1667 SDLoc DL(Op); 1668 1669 // Bitcast to integer nodes. 1670 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 1671 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 1672 1673 if (HasR2) { 1674 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 1675 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 1676 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 1677 DAG.getConstant(WidthY - 1, MVT::i32), Const1); 1678 1679 if (WidthX > WidthY) 1680 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 1681 else if (WidthY > WidthX) 1682 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 1683 1684 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 1685 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X); 1686 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 1687 } 1688 1689 // (d)sll SllX, X, 1 1690 // (d)srl SrlX, SllX, 1 1691 // (d)srl SrlY, Y, width(Y)-1 1692 // (d)sll SllY, SrlX, width(Y)-1 1693 // or Or, SrlX, SllY 1694 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 1695 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 1696 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 1697 DAG.getConstant(WidthY - 1, MVT::i32)); 1698 1699 if (WidthX > WidthY) 1700 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 1701 else if (WidthY > WidthX) 1702 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 1703 1704 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 1705 DAG.getConstant(WidthX - 1, MVT::i32)); 1706 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 1707 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 1708} 1709 1710SDValue 1711MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 1712 if (Subtarget->hasMips64()) 1713 return lowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2()); 1714 1715 return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2()); 1716} 1717 1718static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1719 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1720 SDLoc DL(Op); 1721 1722 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1723 // to i32. 1724 SDValue X = (Op.getValueType() == MVT::f32) ? 1725 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1726 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1727 Const1); 1728 1729 // Clear MSB. 1730 if (HasR2) 1731 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 1732 DAG.getRegister(Mips::ZERO, MVT::i32), 1733 DAG.getConstant(31, MVT::i32), Const1, X); 1734 else { 1735 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1736 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1737 } 1738 1739 if (Op.getValueType() == MVT::f32) 1740 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 1741 1742 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1743 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1744 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1745} 1746 1747static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1748 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1749 SDLoc DL(Op); 1750 1751 // Bitcast to integer node. 1752 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 1753 1754 // Clear MSB. 1755 if (HasR2) 1756 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 1757 DAG.getRegister(Mips::ZERO_64, MVT::i64), 1758 DAG.getConstant(63, MVT::i32), Const1, X); 1759 else { 1760 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 1761 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 1762 } 1763 1764 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 1765} 1766 1767SDValue 1768MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const { 1769 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64)) 1770 return lowerFABS64(Op, DAG, Subtarget->hasMips32r2()); 1771 1772 return lowerFABS32(Op, DAG, Subtarget->hasMips32r2()); 1773} 1774 1775SDValue MipsTargetLowering:: 1776lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1777 // check the depth 1778 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1779 "Frame address can only be determined for current frame."); 1780 1781 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1782 MFI->setFrameAddressIsTaken(true); 1783 EVT VT = Op.getValueType(); 1784 SDLoc DL(Op); 1785 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, 1786 IsN64 ? Mips::FP_64 : Mips::FP, VT); 1787 return FrameAddr; 1788} 1789 1790SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 1791 SelectionDAG &DAG) const { 1792 // check the depth 1793 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1794 "Return address can be determined only for current frame."); 1795 1796 MachineFunction &MF = DAG.getMachineFunction(); 1797 MachineFrameInfo *MFI = MF.getFrameInfo(); 1798 MVT VT = Op.getSimpleValueType(); 1799 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA; 1800 MFI->setReturnAddressIsTaken(true); 1801 1802 // Return RA, which contains the return address. Mark it an implicit live-in. 1803 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 1804 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 1805} 1806 1807// An EH_RETURN is the result of lowering llvm.eh.return which in turn is 1808// generated from __builtin_eh_return (offset, handler) 1809// The effect of this is to adjust the stack pointer by "offset" 1810// and then branch to "handler". 1811SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 1812 const { 1813 MachineFunction &MF = DAG.getMachineFunction(); 1814 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1815 1816 MipsFI->setCallsEhReturn(); 1817 SDValue Chain = Op.getOperand(0); 1818 SDValue Offset = Op.getOperand(1); 1819 SDValue Handler = Op.getOperand(2); 1820 SDLoc DL(Op); 1821 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 1822 1823 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 1824 // EH_RETURN nodes, so that instructions are emitted back-to-back. 1825 unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1; 1826 unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0; 1827 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 1828 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 1829 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 1830 DAG.getRegister(OffsetReg, Ty), 1831 DAG.getRegister(AddrReg, getPointerTy()), 1832 Chain.getValue(1)); 1833} 1834 1835SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 1836 SelectionDAG &DAG) const { 1837 // FIXME: Need pseudo-fence for 'singlethread' fences 1838 // FIXME: Set SType for weaker fences where supported/appropriate. 1839 unsigned SType = 0; 1840 SDLoc DL(Op); 1841 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 1842 DAG.getConstant(SType, MVT::i32)); 1843} 1844 1845SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 1846 SelectionDAG &DAG) const { 1847 SDLoc DL(Op); 1848 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 1849 SDValue Shamt = Op.getOperand(2); 1850 1851 // if shamt < 32: 1852 // lo = (shl lo, shamt) 1853 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 1854 // else: 1855 // lo = 0 1856 // hi = (shl lo, shamt[4:0]) 1857 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 1858 DAG.getConstant(-1, MVT::i32)); 1859 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, 1860 DAG.getConstant(1, MVT::i32)); 1861 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, 1862 Not); 1863 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); 1864 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 1865 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); 1866 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 1867 DAG.getConstant(0x20, MVT::i32)); 1868 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 1869 DAG.getConstant(0, MVT::i32), ShiftLeftLo); 1870 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or); 1871 1872 SDValue Ops[2] = {Lo, Hi}; 1873 return DAG.getMergeValues(Ops, 2, DL); 1874} 1875 1876SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 1877 bool IsSRA) const { 1878 SDLoc DL(Op); 1879 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 1880 SDValue Shamt = Op.getOperand(2); 1881 1882 // if shamt < 32: 1883 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 1884 // if isSRA: 1885 // hi = (sra hi, shamt) 1886 // else: 1887 // hi = (srl hi, shamt) 1888 // else: 1889 // if isSRA: 1890 // lo = (sra hi, shamt[4:0]) 1891 // hi = (sra hi, 31) 1892 // else: 1893 // lo = (srl hi, shamt[4:0]) 1894 // hi = 0 1895 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 1896 DAG.getConstant(-1, MVT::i32)); 1897 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, 1898 DAG.getConstant(1, MVT::i32)); 1899 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not); 1900 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); 1901 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 1902 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, 1903 Hi, Shamt); 1904 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 1905 DAG.getConstant(0x20, MVT::i32)); 1906 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi, 1907 DAG.getConstant(31, MVT::i32)); 1908 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or); 1909 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 1910 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32), 1911 ShiftRightHi); 1912 1913 SDValue Ops[2] = {Lo, Hi}; 1914 return DAG.getMergeValues(Ops, 2, DL); 1915} 1916 1917static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 1918 SDValue Chain, SDValue Src, unsigned Offset) { 1919 SDValue Ptr = LD->getBasePtr(); 1920 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 1921 EVT BasePtrVT = Ptr.getValueType(); 1922 SDLoc DL(LD); 1923 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 1924 1925 if (Offset) 1926 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 1927 DAG.getConstant(Offset, BasePtrVT)); 1928 1929 SDValue Ops[] = { Chain, Ptr, Src }; 1930 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 1931 LD->getMemOperand()); 1932} 1933 1934// Expand an unaligned 32 or 64-bit integer load node. 1935SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 1936 LoadSDNode *LD = cast<LoadSDNode>(Op); 1937 EVT MemVT = LD->getMemoryVT(); 1938 1939 // Return if load is aligned or if MemVT is neither i32 nor i64. 1940 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 1941 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 1942 return SDValue(); 1943 1944 bool IsLittle = Subtarget->isLittle(); 1945 EVT VT = Op.getValueType(); 1946 ISD::LoadExtType ExtType = LD->getExtensionType(); 1947 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 1948 1949 assert((VT == MVT::i32) || (VT == MVT::i64)); 1950 1951 // Expand 1952 // (set dst, (i64 (load baseptr))) 1953 // to 1954 // (set tmp, (ldl (add baseptr, 7), undef)) 1955 // (set dst, (ldr baseptr, tmp)) 1956 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 1957 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 1958 IsLittle ? 7 : 0); 1959 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 1960 IsLittle ? 0 : 7); 1961 } 1962 1963 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 1964 IsLittle ? 3 : 0); 1965 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 1966 IsLittle ? 0 : 3); 1967 1968 // Expand 1969 // (set dst, (i32 (load baseptr))) or 1970 // (set dst, (i64 (sextload baseptr))) or 1971 // (set dst, (i64 (extload baseptr))) 1972 // to 1973 // (set tmp, (lwl (add baseptr, 3), undef)) 1974 // (set dst, (lwr baseptr, tmp)) 1975 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 1976 (ExtType == ISD::EXTLOAD)) 1977 return LWR; 1978 1979 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 1980 1981 // Expand 1982 // (set dst, (i64 (zextload baseptr))) 1983 // to 1984 // (set tmp0, (lwl (add baseptr, 3), undef)) 1985 // (set tmp1, (lwr baseptr, tmp0)) 1986 // (set tmp2, (shl tmp1, 32)) 1987 // (set dst, (srl tmp2, 32)) 1988 SDLoc DL(LD); 1989 SDValue Const32 = DAG.getConstant(32, MVT::i32); 1990 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 1991 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 1992 SDValue Ops[] = { SRL, LWR.getValue(1) }; 1993 return DAG.getMergeValues(Ops, 2, DL); 1994} 1995 1996static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 1997 SDValue Chain, unsigned Offset) { 1998 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 1999 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2000 SDLoc DL(SD); 2001 SDVTList VTList = DAG.getVTList(MVT::Other); 2002 2003 if (Offset) 2004 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2005 DAG.getConstant(Offset, BasePtrVT)); 2006 2007 SDValue Ops[] = { Chain, Value, Ptr }; 2008 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2009 SD->getMemOperand()); 2010} 2011 2012// Expand an unaligned 32 or 64-bit integer store node. 2013static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2014 bool IsLittle) { 2015 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2016 EVT VT = Value.getValueType(); 2017 2018 // Expand 2019 // (store val, baseptr) or 2020 // (truncstore val, baseptr) 2021 // to 2022 // (swl val, (add baseptr, 3)) 2023 // (swr val, baseptr) 2024 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2025 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2026 IsLittle ? 3 : 0); 2027 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2028 } 2029 2030 assert(VT == MVT::i64); 2031 2032 // Expand 2033 // (store val, baseptr) 2034 // to 2035 // (sdl val, (add baseptr, 7)) 2036 // (sdr val, baseptr) 2037 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2038 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2039} 2040 2041// Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2042static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2043 SDValue Val = SD->getValue(); 2044 2045 if (Val.getOpcode() != ISD::FP_TO_SINT) 2046 return SDValue(); 2047 2048 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2049 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2050 Val.getOperand(0)); 2051 2052 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2053 SD->getPointerInfo(), SD->isVolatile(), 2054 SD->isNonTemporal(), SD->getAlignment()); 2055} 2056 2057SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2058 StoreSDNode *SD = cast<StoreSDNode>(Op); 2059 EVT MemVT = SD->getMemoryVT(); 2060 2061 // Lower unaligned integer stores. 2062 if ((SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2063 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2064 return lowerUnalignedIntStore(SD, DAG, Subtarget->isLittle()); 2065 2066 return lowerFP_TO_SINT_STORE(SD, DAG); 2067} 2068 2069SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const { 2070 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR 2071 || cast<ConstantSDNode> 2072 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0 2073 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET) 2074 return SDValue(); 2075 2076 // The pattern 2077 // (add (frameaddr 0), (frame_to_args_offset)) 2078 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to 2079 // (add FrameObject, 0) 2080 // where FrameObject is a fixed StackObject with offset 0 which points to 2081 // the old stack pointer. 2082 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2083 EVT ValTy = Op->getValueType(0); 2084 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2085 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy); 2086 return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr, 2087 DAG.getConstant(0, ValTy)); 2088} 2089 2090SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2091 SelectionDAG &DAG) const { 2092 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2093 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2094 Op.getOperand(0)); 2095 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2096} 2097 2098//===----------------------------------------------------------------------===// 2099// Calling Convention Implementation 2100//===----------------------------------------------------------------------===// 2101 2102//===----------------------------------------------------------------------===// 2103// TODO: Implement a generic logic using tblgen that can support this. 2104// Mips O32 ABI rules: 2105// --- 2106// i32 - Passed in A0, A1, A2, A3 and stack 2107// f32 - Only passed in f32 registers if no int reg has been used yet to hold 2108// an argument. Otherwise, passed in A1, A2, A3 and stack. 2109// f64 - Only passed in two aliased f32 registers if no int reg has been used 2110// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2111// not used, it must be shadowed. If only A3 is avaiable, shadow it and 2112// go to stack. 2113// 2114// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2115//===----------------------------------------------------------------------===// 2116 2117static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 2118 MVT LocVT, CCValAssign::LocInfo LocInfo, 2119 ISD::ArgFlagsTy ArgFlags, CCState &State, 2120 const uint16_t *F64Regs) { 2121 2122 static const unsigned IntRegsSize=4, FloatRegsSize=2; 2123 2124 static const uint16_t IntRegs[] = { 2125 Mips::A0, Mips::A1, Mips::A2, Mips::A3 2126 }; 2127 static const uint16_t F32Regs[] = { 2128 Mips::F12, Mips::F14 2129 }; 2130 2131 // Do not process byval args here. 2132 if (ArgFlags.isByVal()) 2133 return true; 2134 2135 // Promote i8 and i16 2136 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2137 LocVT = MVT::i32; 2138 if (ArgFlags.isSExt()) 2139 LocInfo = CCValAssign::SExt; 2140 else if (ArgFlags.isZExt()) 2141 LocInfo = CCValAssign::ZExt; 2142 else 2143 LocInfo = CCValAssign::AExt; 2144 } 2145 2146 unsigned Reg; 2147 2148 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2149 // is true: function is vararg, argument is 3rd or higher, there is previous 2150 // argument which is not f32 or f64. 2151 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 2152 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 2153 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2154 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2155 2156 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2157 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2158 // If this is the first part of an i64 arg, 2159 // the allocated register must be either A0 or A2. 2160 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2161 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2162 LocVT = MVT::i32; 2163 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2164 // Allocate int register and shadow next int register. If first 2165 // available register is Mips::A1 or Mips::A3, shadow it too. 2166 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2167 if (Reg == Mips::A1 || Reg == Mips::A3) 2168 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2169 State.AllocateReg(IntRegs, IntRegsSize); 2170 LocVT = MVT::i32; 2171 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2172 // we are guaranteed to find an available float register 2173 if (ValVT == MVT::f32) { 2174 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 2175 // Shadow int register 2176 State.AllocateReg(IntRegs, IntRegsSize); 2177 } else { 2178 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 2179 // Shadow int registers 2180 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 2181 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2182 State.AllocateReg(IntRegs, IntRegsSize); 2183 State.AllocateReg(IntRegs, IntRegsSize); 2184 } 2185 } else 2186 llvm_unreachable("Cannot handle this ValVT."); 2187 2188 if (!Reg) { 2189 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2190 OrigAlign); 2191 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2192 } else 2193 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2194 2195 return false; 2196} 2197 2198static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2199 MVT LocVT, CCValAssign::LocInfo LocInfo, 2200 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2201 static const uint16_t F64Regs[] = { Mips::D6, Mips::D7 }; 2202 2203 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2204} 2205 2206static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2207 MVT LocVT, CCValAssign::LocInfo LocInfo, 2208 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2209 static const uint16_t F64Regs[] = { Mips::D12_64, Mips::D12_64 }; 2210 2211 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2212} 2213 2214#include "MipsGenCallingConv.inc" 2215 2216//===----------------------------------------------------------------------===// 2217// Call Calling Convention Implementation 2218//===----------------------------------------------------------------------===// 2219 2220// Return next O32 integer argument register. 2221static unsigned getNextIntArgReg(unsigned Reg) { 2222 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2223 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2224} 2225 2226SDValue 2227MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2228 SDValue Chain, SDValue Arg, SDLoc DL, 2229 bool IsTailCall, SelectionDAG &DAG) const { 2230 if (!IsTailCall) { 2231 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, 2232 DAG.getIntPtrConstant(Offset)); 2233 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false, 2234 false, 0); 2235 } 2236 2237 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2238 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2239 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2240 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2241 /*isVolatile=*/ true, false, 0); 2242} 2243 2244void MipsTargetLowering:: 2245getOpndList(SmallVectorImpl<SDValue> &Ops, 2246 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 2247 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2248 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { 2249 // Insert node "GP copy globalreg" before call to function. 2250 // 2251 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2252 // in PIC mode) allow symbols to be resolved via lazy binding. 2253 // The lazy binding stub requires GP to point to the GOT. 2254 if (IsPICCall && !InternalLinkage) { 2255 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP; 2256 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 2257 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2258 } 2259 2260 // Build a sequence of copy-to-reg nodes chained together with token 2261 // chain and flag operands which copy the outgoing args into registers. 2262 // The InFlag in necessary since all emitted instructions must be 2263 // stuck together. 2264 SDValue InFlag; 2265 2266 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2267 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2268 RegsToPass[i].second, InFlag); 2269 InFlag = Chain.getValue(1); 2270 } 2271 2272 // Add argument registers to the end of the list so that they are 2273 // known live into the call. 2274 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2275 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2276 RegsToPass[i].second.getValueType())); 2277 2278 // Add a register mask operand representing the call-preserved registers. 2279 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2280 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv); 2281 assert(Mask && "Missing call preserved mask for calling convention"); 2282 if (Subtarget->inMips16HardFloat()) { 2283 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2284 llvm::StringRef Sym = G->getGlobal()->getName(); 2285 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2286 if (F->hasFnAttribute("__Mips16RetHelper")) { 2287 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2288 } 2289 } 2290 } 2291 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2292 2293 if (InFlag.getNode()) 2294 Ops.push_back(InFlag); 2295} 2296 2297/// LowerCall - functions arguments are copied from virtual regs to 2298/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2299SDValue 2300MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2301 SmallVectorImpl<SDValue> &InVals) const { 2302 SelectionDAG &DAG = CLI.DAG; 2303 SDLoc DL = CLI.DL; 2304 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2305 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2306 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2307 SDValue Chain = CLI.Chain; 2308 SDValue Callee = CLI.Callee; 2309 bool &IsTailCall = CLI.IsTailCall; 2310 CallingConv::ID CallConv = CLI.CallConv; 2311 bool IsVarArg = CLI.IsVarArg; 2312 2313 MachineFunction &MF = DAG.getMachineFunction(); 2314 MachineFrameInfo *MFI = MF.getFrameInfo(); 2315 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 2316 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2317 2318 // Analyze operands of the call, assigning locations to each operand. 2319 SmallVector<CCValAssign, 16> ArgLocs; 2320 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2321 getTargetMachine(), ArgLocs, *DAG.getContext()); 2322 MipsCC::SpecialCallingConvType SpecialCallingConv = 2323 getSpecialCallingConv(Callee); 2324 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo, 2325 SpecialCallingConv); 2326 2327 MipsCCInfo.analyzeCallOperands(Outs, IsVarArg, 2328 Subtarget->mipsSEUsesSoftFloat(), 2329 Callee.getNode(), CLI.Args); 2330 2331 // Get a count of how many bytes are to be pushed on the stack. 2332 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2333 2334 // Check if it's really possible to do a tail call. 2335 if (IsTailCall) 2336 IsTailCall = 2337 isEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset, 2338 *MF.getInfo<MipsFunctionInfo>()); 2339 2340 if (IsTailCall) 2341 ++NumTailCalls; 2342 2343 // Chain is the output chain of the last Load/Store or CopyToReg node. 2344 // ByValChain is the output chain of the last Memcpy node created for copying 2345 // byval arguments to the stack. 2346 unsigned StackAlignment = TFL->getStackAlignment(); 2347 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment); 2348 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 2349 2350 if (!IsTailCall) 2351 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL); 2352 2353 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, 2354 IsN64 ? Mips::SP_64 : Mips::SP, 2355 getPointerTy()); 2356 2357 // With EABI is it possible to have 16 args on registers. 2358 std::deque< std::pair<unsigned, SDValue> > RegsToPass; 2359 SmallVector<SDValue, 8> MemOpChains; 2360 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 2361 2362 // Walk the register/memloc assignments, inserting copies/loads. 2363 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2364 SDValue Arg = OutVals[i]; 2365 CCValAssign &VA = ArgLocs[i]; 2366 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2367 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2368 2369 // ByVal Arg. 2370 if (Flags.isByVal()) { 2371 assert(Flags.getByValSize() && 2372 "ByVal args of size 0 should have been ignored by front-end."); 2373 assert(ByValArg != MipsCCInfo.byval_end()); 2374 assert(!IsTailCall && 2375 "Do not tail-call optimize if there is a byval argument."); 2376 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2377 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle()); 2378 ++ByValArg; 2379 continue; 2380 } 2381 2382 // Promote the value if needed. 2383 switch (VA.getLocInfo()) { 2384 default: llvm_unreachable("Unknown loc info!"); 2385 case CCValAssign::Full: 2386 if (VA.isRegLoc()) { 2387 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2388 (ValVT == MVT::f64 && LocVT == MVT::i64) || 2389 (ValVT == MVT::i64 && LocVT == MVT::f64)) 2390 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2391 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2392 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2393 Arg, DAG.getConstant(0, MVT::i32)); 2394 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2395 Arg, DAG.getConstant(1, MVT::i32)); 2396 if (!Subtarget->isLittle()) 2397 std::swap(Lo, Hi); 2398 unsigned LocRegLo = VA.getLocReg(); 2399 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2400 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2401 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2402 continue; 2403 } 2404 } 2405 break; 2406 case CCValAssign::SExt: 2407 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 2408 break; 2409 case CCValAssign::ZExt: 2410 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 2411 break; 2412 case CCValAssign::AExt: 2413 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 2414 break; 2415 } 2416 2417 // Arguments that can be passed on register must be kept at 2418 // RegsToPass vector 2419 if (VA.isRegLoc()) { 2420 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2421 continue; 2422 } 2423 2424 // Register can't get to this point... 2425 assert(VA.isMemLoc()); 2426 2427 // emit ISD::STORE whichs stores the 2428 // parameter value to a stack Location 2429 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 2430 Chain, Arg, DL, IsTailCall, DAG)); 2431 } 2432 2433 // Transform all store nodes into one single node because all store 2434 // nodes are independent of each other. 2435 if (!MemOpChains.empty()) 2436 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 2437 &MemOpChains[0], MemOpChains.size()); 2438 2439 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2440 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2441 // node so that legalize doesn't hack it. 2442 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25 2443 bool GlobalOrExternal = false, InternalLinkage = false; 2444 SDValue CalleeLo; 2445 EVT Ty = Callee.getValueType(); 2446 2447 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2448 if (IsPICCall) { 2449 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 2450 2451 if (InternalLinkage) 2452 Callee = getAddrLocal(G, Ty, DAG, HasMips64); 2453 else if (LargeGOT) 2454 Callee = getAddrGlobalLargeGOT(G, Ty, DAG, MipsII::MO_CALL_HI16, 2455 MipsII::MO_CALL_LO16); 2456 else 2457 Callee = getAddrGlobal(G, Ty, DAG, MipsII::MO_GOT_CALL); 2458 } else 2459 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0, 2460 MipsII::MO_NO_FLAG); 2461 GlobalOrExternal = true; 2462 } 2463 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2464 if (!IsN64 && !IsPIC) // !N64 && static 2465 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2466 MipsII::MO_NO_FLAG); 2467 else if (LargeGOT) 2468 Callee = getAddrGlobalLargeGOT(S, Ty, DAG, MipsII::MO_CALL_HI16, 2469 MipsII::MO_CALL_LO16); 2470 else // N64 || PIC 2471 Callee = getAddrGlobal(S, Ty, DAG, MipsII::MO_GOT_CALL); 2472 2473 GlobalOrExternal = true; 2474 } 2475 2476 SmallVector<SDValue, 8> Ops(1, Chain); 2477 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2478 2479 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage, 2480 CLI, Callee, Chain); 2481 2482 if (IsTailCall) 2483 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, &Ops[0], Ops.size()); 2484 2485 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, &Ops[0], Ops.size()); 2486 SDValue InFlag = Chain.getValue(1); 2487 2488 // Create the CALLSEQ_END node. 2489 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2490 DAG.getIntPtrConstant(0, true), InFlag, DL); 2491 InFlag = Chain.getValue(1); 2492 2493 // Handle result values, copying them out of physregs into vregs that we 2494 // return. 2495 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, 2496 Ins, DL, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy); 2497} 2498 2499/// LowerCallResult - Lower the result values of a call into the 2500/// appropriate copies out of appropriate physical registers. 2501SDValue 2502MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2503 CallingConv::ID CallConv, bool IsVarArg, 2504 const SmallVectorImpl<ISD::InputArg> &Ins, 2505 SDLoc DL, SelectionDAG &DAG, 2506 SmallVectorImpl<SDValue> &InVals, 2507 const SDNode *CallNode, 2508 const Type *RetTy) const { 2509 // Assign locations to each value returned by this call. 2510 SmallVector<CCValAssign, 16> RVLocs; 2511 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2512 getTargetMachine(), RVLocs, *DAG.getContext()); 2513 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo); 2514 2515 MipsCCInfo.analyzeCallResult(Ins, Subtarget->mipsSEUsesSoftFloat(), 2516 CallNode, RetTy); 2517 2518 // Copy all of the result registers out of their specified physreg. 2519 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2520 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 2521 RVLocs[i].getLocVT(), InFlag); 2522 Chain = Val.getValue(1); 2523 InFlag = Val.getValue(2); 2524 2525 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) 2526 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val); 2527 2528 InVals.push_back(Val); 2529 } 2530 2531 return Chain; 2532} 2533 2534//===----------------------------------------------------------------------===// 2535// Formal Arguments Calling Convention Implementation 2536//===----------------------------------------------------------------------===// 2537/// LowerFormalArguments - transform physical registers into virtual registers 2538/// and generate load operations for arguments places on the stack. 2539SDValue 2540MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2541 CallingConv::ID CallConv, 2542 bool IsVarArg, 2543 const SmallVectorImpl<ISD::InputArg> &Ins, 2544 SDLoc DL, SelectionDAG &DAG, 2545 SmallVectorImpl<SDValue> &InVals) 2546 const { 2547 MachineFunction &MF = DAG.getMachineFunction(); 2548 MachineFrameInfo *MFI = MF.getFrameInfo(); 2549 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2550 2551 MipsFI->setVarArgsFrameIndex(0); 2552 2553 // Used with vargs to acumulate store chains. 2554 std::vector<SDValue> OutChains; 2555 2556 // Assign locations to all of the incoming arguments. 2557 SmallVector<CCValAssign, 16> ArgLocs; 2558 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2559 getTargetMachine(), ArgLocs, *DAG.getContext()); 2560 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo); 2561 Function::const_arg_iterator FuncArg = 2562 DAG.getMachineFunction().getFunction()->arg_begin(); 2563 bool UseSoftFloat = Subtarget->mipsSEUsesSoftFloat(); 2564 2565 MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg); 2566 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 2567 MipsCCInfo.hasByValArg()); 2568 2569 unsigned CurArgIdx = 0; 2570 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 2571 2572 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2573 CCValAssign &VA = ArgLocs[i]; 2574 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx); 2575 CurArgIdx = Ins[i].OrigArgIndex; 2576 EVT ValVT = VA.getValVT(); 2577 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2578 bool IsRegLoc = VA.isRegLoc(); 2579 2580 if (Flags.isByVal()) { 2581 assert(Flags.getByValSize() && 2582 "ByVal args of size 0 should have been ignored by front-end."); 2583 assert(ByValArg != MipsCCInfo.byval_end()); 2584 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 2585 MipsCCInfo, *ByValArg); 2586 ++ByValArg; 2587 continue; 2588 } 2589 2590 // Arguments stored on registers 2591 if (IsRegLoc) { 2592 EVT RegVT = VA.getLocVT(); 2593 unsigned ArgReg = VA.getLocReg(); 2594 const TargetRegisterClass *RC; 2595 2596 if (RegVT == MVT::i32) 2597 RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass : 2598 &Mips::GPR32RegClass; 2599 else if (RegVT == MVT::i64) 2600 RC = &Mips::GPR64RegClass; 2601 else if (RegVT == MVT::f32) 2602 RC = &Mips::FGR32RegClass; 2603 else if (RegVT == MVT::f64) 2604 RC = Subtarget->isFP64bit() ? &Mips::FGR64RegClass : 2605 &Mips::AFGR64RegClass; 2606 else 2607 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 2608 2609 // Transform the arguments stored on 2610 // physical registers into virtual ones 2611 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2612 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 2613 2614 // If this is an 8 or 16-bit value, it has been passed promoted 2615 // to 32 bits. Insert an assert[sz]ext to capture this, then 2616 // truncate to the right size. 2617 if (VA.getLocInfo() != CCValAssign::Full) { 2618 unsigned Opcode = 0; 2619 if (VA.getLocInfo() == CCValAssign::SExt) 2620 Opcode = ISD::AssertSext; 2621 else if (VA.getLocInfo() == CCValAssign::ZExt) 2622 Opcode = ISD::AssertZext; 2623 if (Opcode) 2624 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue, 2625 DAG.getValueType(ValVT)); 2626 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue); 2627 } 2628 2629 // Handle floating point arguments passed in integer registers and 2630 // long double arguments passed in floating point registers. 2631 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 2632 (RegVT == MVT::i64 && ValVT == MVT::f64) || 2633 (RegVT == MVT::f64 && ValVT == MVT::i64)) 2634 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 2635 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) { 2636 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 2637 getNextIntArgReg(ArgReg), RC); 2638 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 2639 if (!Subtarget->isLittle()) 2640 std::swap(ArgValue, ArgValue2); 2641 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 2642 ArgValue, ArgValue2); 2643 } 2644 2645 InVals.push_back(ArgValue); 2646 } else { // VA.isRegLoc() 2647 2648 // sanity check 2649 assert(VA.isMemLoc()); 2650 2651 // The stack pointer offset is relative to the caller stack frame. 2652 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 2653 VA.getLocMemOffset(), true); 2654 2655 // Create load nodes to retrieve arguments from the stack 2656 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2657 InVals.push_back(DAG.getLoad(ValVT, DL, Chain, FIN, 2658 MachinePointerInfo::getFixedStack(FI), 2659 false, false, false, 0)); 2660 } 2661 } 2662 2663 // The mips ABIs for returning structs by value requires that we copy 2664 // the sret argument into $v0 for the return. Save the argument into 2665 // a virtual register so that we can access it from the return points. 2666 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2667 unsigned Reg = MipsFI->getSRetReturnReg(); 2668 if (!Reg) { 2669 Reg = MF.getRegInfo(). 2670 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32)); 2671 MipsFI->setSRetReturnReg(Reg); 2672 } 2673 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]); 2674 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 2675 } 2676 2677 if (IsVarArg) 2678 writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG); 2679 2680 // All stores are grouped in one node to allow the matching between 2681 // the size of Ins and InVals. This only happens when on varg functions 2682 if (!OutChains.empty()) { 2683 OutChains.push_back(Chain); 2684 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 2685 &OutChains[0], OutChains.size()); 2686 } 2687 2688 return Chain; 2689} 2690 2691//===----------------------------------------------------------------------===// 2692// Return Value Calling Convention Implementation 2693//===----------------------------------------------------------------------===// 2694 2695bool 2696MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 2697 MachineFunction &MF, bool IsVarArg, 2698 const SmallVectorImpl<ISD::OutputArg> &Outs, 2699 LLVMContext &Context) const { 2700 SmallVector<CCValAssign, 16> RVLocs; 2701 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), 2702 RVLocs, Context); 2703 return CCInfo.CheckReturn(Outs, RetCC_Mips); 2704} 2705 2706SDValue 2707MipsTargetLowering::LowerReturn(SDValue Chain, 2708 CallingConv::ID CallConv, bool IsVarArg, 2709 const SmallVectorImpl<ISD::OutputArg> &Outs, 2710 const SmallVectorImpl<SDValue> &OutVals, 2711 SDLoc DL, SelectionDAG &DAG) const { 2712 // CCValAssign - represent the assignment of 2713 // the return value to a location 2714 SmallVector<CCValAssign, 16> RVLocs; 2715 MachineFunction &MF = DAG.getMachineFunction(); 2716 2717 // CCState - Info about the registers and stack slot. 2718 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs, 2719 *DAG.getContext()); 2720 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo); 2721 2722 // Analyze return values. 2723 MipsCCInfo.analyzeReturn(Outs, Subtarget->mipsSEUsesSoftFloat(), 2724 MF.getFunction()->getReturnType()); 2725 2726 SDValue Flag; 2727 SmallVector<SDValue, 4> RetOps(1, Chain); 2728 2729 // Copy the result values into the output registers. 2730 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2731 SDValue Val = OutVals[i]; 2732 CCValAssign &VA = RVLocs[i]; 2733 assert(VA.isRegLoc() && "Can only return in registers!"); 2734 2735 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) 2736 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val); 2737 2738 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 2739 2740 // Guarantee that all emitted copies are stuck together with flags. 2741 Flag = Chain.getValue(1); 2742 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 2743 } 2744 2745 // The mips ABIs for returning structs by value requires that we copy 2746 // the sret argument into $v0 for the return. We saved the argument into 2747 // a virtual register in the entry block, so now we copy the value out 2748 // and into $v0. 2749 if (MF.getFunction()->hasStructRetAttr()) { 2750 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2751 unsigned Reg = MipsFI->getSRetReturnReg(); 2752 2753 if (!Reg) 2754 llvm_unreachable("sret virtual register not created in the entry block"); 2755 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 2756 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0; 2757 2758 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 2759 Flag = Chain.getValue(1); 2760 RetOps.push_back(DAG.getRegister(V0, getPointerTy())); 2761 } 2762 2763 RetOps[0] = Chain; // Update chain. 2764 2765 // Add the flag if we have it. 2766 if (Flag.getNode()) 2767 RetOps.push_back(Flag); 2768 2769 // Return on Mips is always a "jr $ra" 2770 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, &RetOps[0], RetOps.size()); 2771} 2772 2773//===----------------------------------------------------------------------===// 2774// Mips Inline Assembly Support 2775//===----------------------------------------------------------------------===// 2776 2777/// getConstraintType - Given a constraint letter, return the type of 2778/// constraint it is for this target. 2779MipsTargetLowering::ConstraintType MipsTargetLowering:: 2780getConstraintType(const std::string &Constraint) const 2781{ 2782 // Mips specific constrainy 2783 // GCC config/mips/constraints.md 2784 // 2785 // 'd' : An address register. Equivalent to r 2786 // unless generating MIPS16 code. 2787 // 'y' : Equivalent to r; retained for 2788 // backwards compatibility. 2789 // 'c' : A register suitable for use in an indirect 2790 // jump. This will always be $25 for -mabicalls. 2791 // 'l' : The lo register. 1 word storage. 2792 // 'x' : The hilo register pair. Double word storage. 2793 if (Constraint.size() == 1) { 2794 switch (Constraint[0]) { 2795 default : break; 2796 case 'd': 2797 case 'y': 2798 case 'f': 2799 case 'c': 2800 case 'l': 2801 case 'x': 2802 return C_RegisterClass; 2803 case 'R': 2804 return C_Memory; 2805 } 2806 } 2807 return TargetLowering::getConstraintType(Constraint); 2808} 2809 2810/// Examine constraint type and operand type and determine a weight value. 2811/// This object must already have been set up with the operand type 2812/// and the current alternative constraint selected. 2813TargetLowering::ConstraintWeight 2814MipsTargetLowering::getSingleConstraintMatchWeight( 2815 AsmOperandInfo &info, const char *constraint) const { 2816 ConstraintWeight weight = CW_Invalid; 2817 Value *CallOperandVal = info.CallOperandVal; 2818 // If we don't have a value, we can't do a match, 2819 // but allow it at the lowest weight. 2820 if (CallOperandVal == NULL) 2821 return CW_Default; 2822 Type *type = CallOperandVal->getType(); 2823 // Look at the constraint type. 2824 switch (*constraint) { 2825 default: 2826 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 2827 break; 2828 case 'd': 2829 case 'y': 2830 if (type->isIntegerTy()) 2831 weight = CW_Register; 2832 break; 2833 case 'f': 2834 if (type->isFloatTy()) 2835 weight = CW_Register; 2836 break; 2837 case 'c': // $25 for indirect jumps 2838 case 'l': // lo register 2839 case 'x': // hilo register pair 2840 if (type->isIntegerTy()) 2841 weight = CW_SpecificReg; 2842 break; 2843 case 'I': // signed 16 bit immediate 2844 case 'J': // integer zero 2845 case 'K': // unsigned 16 bit immediate 2846 case 'L': // signed 32 bit immediate where lower 16 bits are 0 2847 case 'N': // immediate in the range of -65535 to -1 (inclusive) 2848 case 'O': // signed 15 bit immediate (+- 16383) 2849 case 'P': // immediate in the range of 65535 to 1 (inclusive) 2850 if (isa<ConstantInt>(CallOperandVal)) 2851 weight = CW_Constant; 2852 break; 2853 case 'R': 2854 weight = CW_Memory; 2855 break; 2856 } 2857 return weight; 2858} 2859 2860/// This is a helper function to parse a physical register string and split it 2861/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 2862/// that is returned indicates whether parsing was successful. The second flag 2863/// is true if the numeric part exists. 2864static std::pair<bool, bool> 2865parsePhysicalReg(const StringRef &C, std::string &Prefix, 2866 unsigned long long &Reg) { 2867 if (C.front() != '{' || C.back() != '}') 2868 return std::make_pair(false, false); 2869 2870 // Search for the first numeric character. 2871 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 2872 I = std::find_if(B, E, std::ptr_fun(isdigit)); 2873 2874 Prefix.assign(B, I - B); 2875 2876 // The second flag is set to false if no numeric characters were found. 2877 if (I == E) 2878 return std::make_pair(true, false); 2879 2880 // Parse the numeric characters. 2881 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 2882 true); 2883} 2884 2885std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 2886parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const { 2887 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2888 const TargetRegisterClass *RC; 2889 std::string Prefix; 2890 unsigned long long Reg; 2891 2892 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 2893 2894 if (!R.first) 2895 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); 2896 2897 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 2898 // No numeric characters follow "hi" or "lo". 2899 if (R.second) 2900 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); 2901 2902 RC = TRI->getRegClass(Prefix == "hi" ? 2903 Mips::HI32RegClassID : Mips::LO32RegClassID); 2904 return std::make_pair(*(RC->begin()), RC); 2905 } 2906 2907 if (!R.second) 2908 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); 2909 2910 if (Prefix == "$f") { // Parse $f0-$f31. 2911 // If the size of FP registers is 64-bit or Reg is an even number, select 2912 // the 64-bit register class. Otherwise, select the 32-bit register class. 2913 if (VT == MVT::Other) 2914 VT = (Subtarget->isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 2915 2916 RC= getRegClassFor(VT); 2917 2918 if (RC == &Mips::AFGR64RegClass) { 2919 assert(Reg % 2 == 0); 2920 Reg >>= 1; 2921 } 2922 } else if (Prefix == "$fcc") { // Parse $fcc0-$fcc7. 2923 RC = TRI->getRegClass(Mips::FCCRegClassID); 2924 } else { // Parse $0-$31. 2925 assert(Prefix == "$"); 2926 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 2927 } 2928 2929 assert(Reg < RC->getNumRegs()); 2930 return std::make_pair(*(RC->begin() + Reg), RC); 2931} 2932 2933/// Given a register class constraint, like 'r', if this corresponds directly 2934/// to an LLVM register class, return a register of 0 and the register class 2935/// pointer. 2936std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 2937getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const 2938{ 2939 if (Constraint.size() == 1) { 2940 switch (Constraint[0]) { 2941 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 2942 case 'y': // Same as 'r'. Exists for compatibility. 2943 case 'r': 2944 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 2945 if (Subtarget->inMips16Mode()) 2946 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 2947 return std::make_pair(0U, &Mips::GPR32RegClass); 2948 } 2949 if (VT == MVT::i64 && !HasMips64) 2950 return std::make_pair(0U, &Mips::GPR32RegClass); 2951 if (VT == MVT::i64 && HasMips64) 2952 return std::make_pair(0U, &Mips::GPR64RegClass); 2953 // This will generate an error message 2954 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2955 case 'f': 2956 if (VT == MVT::f32) 2957 return std::make_pair(0U, &Mips::FGR32RegClass); 2958 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { 2959 if (Subtarget->isFP64bit()) 2960 return std::make_pair(0U, &Mips::FGR64RegClass); 2961 return std::make_pair(0U, &Mips::AFGR64RegClass); 2962 } 2963 break; 2964 case 'c': // register suitable for indirect jump 2965 if (VT == MVT::i32) 2966 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 2967 assert(VT == MVT::i64 && "Unexpected type."); 2968 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 2969 case 'l': // register suitable for indirect jump 2970 if (VT == MVT::i32) 2971 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 2972 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 2973 case 'x': // register suitable for indirect jump 2974 // Fixme: Not triggering the use of both hi and low 2975 // This will generate an error message 2976 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2977 } 2978 } 2979 2980 std::pair<unsigned, const TargetRegisterClass *> R; 2981 R = parseRegForInlineAsmConstraint(Constraint, VT); 2982 2983 if (R.second) 2984 return R; 2985 2986 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 2987} 2988 2989/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2990/// vector. If it is invalid, don't add anything to Ops. 2991void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2992 std::string &Constraint, 2993 std::vector<SDValue>&Ops, 2994 SelectionDAG &DAG) const { 2995 SDValue Result(0, 0); 2996 2997 // Only support length 1 constraints for now. 2998 if (Constraint.length() > 1) return; 2999 3000 char ConstraintLetter = Constraint[0]; 3001 switch (ConstraintLetter) { 3002 default: break; // This will fall through to the generic implementation 3003 case 'I': // Signed 16 bit constant 3004 // If this fails, the parent routine will give an error 3005 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3006 EVT Type = Op.getValueType(); 3007 int64_t Val = C->getSExtValue(); 3008 if (isInt<16>(Val)) { 3009 Result = DAG.getTargetConstant(Val, Type); 3010 break; 3011 } 3012 } 3013 return; 3014 case 'J': // integer zero 3015 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3016 EVT Type = Op.getValueType(); 3017 int64_t Val = C->getZExtValue(); 3018 if (Val == 0) { 3019 Result = DAG.getTargetConstant(0, Type); 3020 break; 3021 } 3022 } 3023 return; 3024 case 'K': // unsigned 16 bit immediate 3025 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3026 EVT Type = Op.getValueType(); 3027 uint64_t Val = (uint64_t)C->getZExtValue(); 3028 if (isUInt<16>(Val)) { 3029 Result = DAG.getTargetConstant(Val, Type); 3030 break; 3031 } 3032 } 3033 return; 3034 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3035 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3036 EVT Type = Op.getValueType(); 3037 int64_t Val = C->getSExtValue(); 3038 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3039 Result = DAG.getTargetConstant(Val, Type); 3040 break; 3041 } 3042 } 3043 return; 3044 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3045 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3046 EVT Type = Op.getValueType(); 3047 int64_t Val = C->getSExtValue(); 3048 if ((Val >= -65535) && (Val <= -1)) { 3049 Result = DAG.getTargetConstant(Val, Type); 3050 break; 3051 } 3052 } 3053 return; 3054 case 'O': // signed 15 bit immediate 3055 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3056 EVT Type = Op.getValueType(); 3057 int64_t Val = C->getSExtValue(); 3058 if ((isInt<15>(Val))) { 3059 Result = DAG.getTargetConstant(Val, Type); 3060 break; 3061 } 3062 } 3063 return; 3064 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3065 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3066 EVT Type = Op.getValueType(); 3067 int64_t Val = C->getSExtValue(); 3068 if ((Val <= 65535) && (Val >= 1)) { 3069 Result = DAG.getTargetConstant(Val, Type); 3070 break; 3071 } 3072 } 3073 return; 3074 } 3075 3076 if (Result.getNode()) { 3077 Ops.push_back(Result); 3078 return; 3079 } 3080 3081 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3082} 3083 3084bool 3085MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const { 3086 // No global is ever allowed as a base. 3087 if (AM.BaseGV) 3088 return false; 3089 3090 switch (AM.Scale) { 3091 case 0: // "r+i" or just "i", depending on HasBaseReg. 3092 break; 3093 case 1: 3094 if (!AM.HasBaseReg) // allow "r+i". 3095 break; 3096 return false; // disallow "r+r" or "r+r+i". 3097 default: 3098 return false; 3099 } 3100 3101 return true; 3102} 3103 3104bool 3105MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3106 // The Mips target isn't yet aware of offsets. 3107 return false; 3108} 3109 3110EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3111 unsigned SrcAlign, 3112 bool IsMemset, bool ZeroMemset, 3113 bool MemcpyStrSrc, 3114 MachineFunction &MF) const { 3115 if (Subtarget->hasMips64()) 3116 return MVT::i64; 3117 3118 return MVT::i32; 3119} 3120 3121bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3122 if (VT != MVT::f32 && VT != MVT::f64) 3123 return false; 3124 if (Imm.isNegZero()) 3125 return false; 3126 return Imm.isZero(); 3127} 3128 3129unsigned MipsTargetLowering::getJumpTableEncoding() const { 3130 if (IsN64) 3131 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3132 3133 return TargetLowering::getJumpTableEncoding(); 3134} 3135 3136/// This function returns true if CallSym is a long double emulation routine. 3137static bool isF128SoftLibCall(const char *CallSym) { 3138 const char *const LibCalls[] = 3139 {"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2", 3140 "__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi", 3141 "__fixunstfti", "__floatditf", "__floatsitf", "__floattitf", 3142 "__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2", 3143 "__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3", 3144 "__trunctfdf2", "__trunctfsf2", "__unordtf2", 3145 "ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl", 3146 "log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl", 3147 "truncl"}; 3148 3149 const char * const *End = LibCalls + array_lengthof(LibCalls); 3150 3151 // Check that LibCalls is sorted alphabetically. 3152 MipsTargetLowering::LTStr Comp; 3153 3154#ifndef NDEBUG 3155 for (const char * const *I = LibCalls; I < End - 1; ++I) 3156 assert(Comp(*I, *(I + 1))); 3157#endif 3158 3159 return std::binary_search(LibCalls, End, CallSym, Comp); 3160} 3161 3162/// This function returns true if Ty is fp128 or i128 which was originally a 3163/// fp128. 3164static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) { 3165 if (Ty->isFP128Ty()) 3166 return true; 3167 3168 const ExternalSymbolSDNode *ES = 3169 dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode); 3170 3171 // If the Ty is i128 and the function being called is a long double emulation 3172 // routine, then the original type is f128. 3173 return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol())); 3174} 3175 3176MipsTargetLowering::MipsCC::SpecialCallingConvType 3177 MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const { 3178 MipsCC::SpecialCallingConvType SpecialCallingConv = 3179 MipsCC::NoSpecialCallingConv;; 3180 if (Subtarget->inMips16HardFloat()) { 3181 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3182 llvm::StringRef Sym = G->getGlobal()->getName(); 3183 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 3184 if (F->hasFnAttribute("__Mips16RetHelper")) { 3185 SpecialCallingConv = MipsCC::Mips16RetHelperConv; 3186 } 3187 } 3188 } 3189 return SpecialCallingConv; 3190} 3191 3192MipsTargetLowering::MipsCC::MipsCC( 3193 CallingConv::ID CC, bool IsO32_, bool IsFP64_, CCState &Info, 3194 MipsCC::SpecialCallingConvType SpecialCallingConv_) 3195 : CCInfo(Info), CallConv(CC), IsO32(IsO32_), IsFP64(IsFP64_), 3196 SpecialCallingConv(SpecialCallingConv_){ 3197 // Pre-allocate reserved argument area. 3198 CCInfo.AllocateStack(reservedArgArea(), 1); 3199} 3200 3201 3202void MipsTargetLowering::MipsCC:: 3203analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args, 3204 bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode, 3205 std::vector<ArgListEntry> &FuncArgs) { 3206 assert((CallConv != CallingConv::Fast || !IsVarArg) && 3207 "CallingConv::Fast shouldn't be used for vararg functions."); 3208 3209 unsigned NumOpnds = Args.size(); 3210 llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn(); 3211 3212 for (unsigned I = 0; I != NumOpnds; ++I) { 3213 MVT ArgVT = Args[I].VT; 3214 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3215 bool R; 3216 3217 if (ArgFlags.isByVal()) { 3218 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3219 continue; 3220 } 3221 3222 if (IsVarArg && !Args[I].IsFixed) 3223 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 3224 else { 3225 MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode, 3226 IsSoftFloat); 3227 R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo); 3228 } 3229 3230 if (R) { 3231#ifndef NDEBUG 3232 dbgs() << "Call operand #" << I << " has unhandled type " 3233 << EVT(ArgVT).getEVTString(); 3234#endif 3235 llvm_unreachable(0); 3236 } 3237 } 3238} 3239 3240void MipsTargetLowering::MipsCC:: 3241analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args, 3242 bool IsSoftFloat, Function::const_arg_iterator FuncArg) { 3243 unsigned NumArgs = Args.size(); 3244 llvm::CCAssignFn *FixedFn = fixedArgFn(); 3245 unsigned CurArgIdx = 0; 3246 3247 for (unsigned I = 0; I != NumArgs; ++I) { 3248 MVT ArgVT = Args[I].VT; 3249 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3250 std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx); 3251 CurArgIdx = Args[I].OrigArgIndex; 3252 3253 if (ArgFlags.isByVal()) { 3254 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3255 continue; 3256 } 3257 3258 MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), 0, IsSoftFloat); 3259 3260 if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo)) 3261 continue; 3262 3263#ifndef NDEBUG 3264 dbgs() << "Formal Arg #" << I << " has unhandled type " 3265 << EVT(ArgVT).getEVTString(); 3266#endif 3267 llvm_unreachable(0); 3268 } 3269} 3270 3271template<typename Ty> 3272void MipsTargetLowering::MipsCC:: 3273analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat, 3274 const SDNode *CallNode, const Type *RetTy) const { 3275 CCAssignFn *Fn; 3276 3277 if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode)) 3278 Fn = RetCC_F128Soft; 3279 else 3280 Fn = RetCC_Mips; 3281 3282 for (unsigned I = 0, E = RetVals.size(); I < E; ++I) { 3283 MVT VT = RetVals[I].VT; 3284 ISD::ArgFlagsTy Flags = RetVals[I].Flags; 3285 MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat); 3286 3287 if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) { 3288#ifndef NDEBUG 3289 dbgs() << "Call result #" << I << " has unhandled type " 3290 << EVT(VT).getEVTString() << '\n'; 3291#endif 3292 llvm_unreachable(0); 3293 } 3294 } 3295} 3296 3297void MipsTargetLowering::MipsCC:: 3298analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat, 3299 const SDNode *CallNode, const Type *RetTy) const { 3300 analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy); 3301} 3302 3303void MipsTargetLowering::MipsCC:: 3304analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat, 3305 const Type *RetTy) const { 3306 analyzeReturn(Outs, IsSoftFloat, 0, RetTy); 3307} 3308 3309void 3310MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT, 3311 MVT LocVT, 3312 CCValAssign::LocInfo LocInfo, 3313 ISD::ArgFlagsTy ArgFlags) { 3314 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0."); 3315 3316 struct ByValArgInfo ByVal; 3317 unsigned RegSize = regSize(); 3318 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize); 3319 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize), 3320 RegSize * 2); 3321 3322 if (useRegsForByval()) 3323 allocateRegs(ByVal, ByValSize, Align); 3324 3325 // Allocate space on caller's stack. 3326 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs, 3327 Align); 3328 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT, 3329 LocInfo)); 3330 ByValArgs.push_back(ByVal); 3331} 3332 3333unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const { 3334 return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs); 3335} 3336 3337unsigned MipsTargetLowering::MipsCC::reservedArgArea() const { 3338 return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0; 3339} 3340 3341const uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const { 3342 return IsO32 ? O32IntRegs : Mips64IntRegs; 3343} 3344 3345llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const { 3346 if (CallConv == CallingConv::Fast) 3347 return CC_Mips_FastCC; 3348 3349 if (SpecialCallingConv == Mips16RetHelperConv) 3350 return CC_Mips16RetHelper; 3351 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN; 3352} 3353 3354llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const { 3355 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN_VarArg; 3356} 3357 3358const uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const { 3359 return IsO32 ? O32IntRegs : Mips64DPRegs; 3360} 3361 3362void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal, 3363 unsigned ByValSize, 3364 unsigned Align) { 3365 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs(); 3366 const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs(); 3367 assert(!(ByValSize % RegSize) && !(Align % RegSize) && 3368 "Byval argument's size and alignment should be a multiple of" 3369 "RegSize."); 3370 3371 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs); 3372 3373 // If Align > RegSize, the first arg register must be even. 3374 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) { 3375 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]); 3376 ++ByVal.FirstIdx; 3377 } 3378 3379 // Mark the registers allocated. 3380 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs); 3381 ByValSize -= RegSize, ++I, ++ByVal.NumRegs) 3382 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]); 3383} 3384 3385MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy, 3386 const SDNode *CallNode, 3387 bool IsSoftFloat) const { 3388 if (IsSoftFloat || IsO32) 3389 return VT; 3390 3391 // Check if the original type was fp128. 3392 if (originalTypeIsF128(OrigTy, CallNode)) { 3393 assert(VT == MVT::i64); 3394 return MVT::f64; 3395 } 3396 3397 return VT; 3398} 3399 3400void MipsTargetLowering:: 3401copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, 3402 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 3403 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 3404 const MipsCC &CC, const ByValArgInfo &ByVal) const { 3405 MachineFunction &MF = DAG.getMachineFunction(); 3406 MachineFrameInfo *MFI = MF.getFrameInfo(); 3407 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize(); 3408 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3409 int FrameObjOffset; 3410 3411 if (RegAreaSize) 3412 FrameObjOffset = (int)CC.reservedArgArea() - 3413 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize()); 3414 else 3415 FrameObjOffset = ByVal.Address; 3416 3417 // Create frame object. 3418 EVT PtrTy = getPointerTy(); 3419 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3420 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3421 InVals.push_back(FIN); 3422 3423 if (!ByVal.NumRegs) 3424 return; 3425 3426 // Copy arg registers. 3427 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8); 3428 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3429 3430 for (unsigned I = 0; I < ByVal.NumRegs; ++I) { 3431 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I]; 3432 unsigned VReg = addLiveIn(MF, ArgReg, RC); 3433 unsigned Offset = I * CC.regSize(); 3434 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3435 DAG.getConstant(Offset, PtrTy)); 3436 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3437 StorePtr, MachinePointerInfo(FuncArg, Offset), 3438 false, false, 0); 3439 OutChains.push_back(Store); 3440 } 3441} 3442 3443// Copy byVal arg to registers and stack. 3444void MipsTargetLowering:: 3445passByValArg(SDValue Chain, SDLoc DL, 3446 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 3447 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 3448 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 3449 const MipsCC &CC, const ByValArgInfo &ByVal, 3450 const ISD::ArgFlagsTy &Flags, bool isLittle) const { 3451 unsigned ByValSize = Flags.getByValSize(); 3452 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct. 3453 unsigned RegSize = CC.regSize(); 3454 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize); 3455 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8); 3456 3457 if (ByVal.NumRegs) { 3458 const uint16_t *ArgRegs = CC.intArgRegs(); 3459 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize); 3460 unsigned I = 0; 3461 3462 // Copy words to registers. 3463 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) { 3464 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3465 DAG.getConstant(Offset, PtrTy)); 3466 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3467 MachinePointerInfo(), false, false, false, 3468 Alignment); 3469 MemOpChains.push_back(LoadVal.getValue(1)); 3470 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3471 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3472 } 3473 3474 // Return if the struct has been fully copied. 3475 if (ByValSize == Offset) 3476 return; 3477 3478 // Copy the remainder of the byval argument with sub-word loads and shifts. 3479 if (LeftoverBytes) { 3480 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) && 3481 "Size of the remainder should be smaller than RegSize."); 3482 SDValue Val; 3483 3484 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0; 3485 Offset < ByValSize; LoadSize /= 2) { 3486 unsigned RemSize = ByValSize - Offset; 3487 3488 if (RemSize < LoadSize) 3489 continue; 3490 3491 // Load subword. 3492 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3493 DAG.getConstant(Offset, PtrTy)); 3494 SDValue LoadVal = 3495 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, 3496 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8), 3497 false, false, Alignment); 3498 MemOpChains.push_back(LoadVal.getValue(1)); 3499 3500 // Shift the loaded value. 3501 unsigned Shamt; 3502 3503 if (isLittle) 3504 Shamt = TotalSizeLoaded; 3505 else 3506 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8; 3507 3508 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 3509 DAG.getConstant(Shamt, MVT::i32)); 3510 3511 if (Val.getNode()) 3512 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3513 else 3514 Val = Shift; 3515 3516 Offset += LoadSize; 3517 TotalSizeLoaded += LoadSize; 3518 Alignment = std::min(Alignment, LoadSize); 3519 } 3520 3521 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3522 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 3523 return; 3524 } 3525 } 3526 3527 // Copy remainder of byval arg to it with memcpy. 3528 unsigned MemCpySize = ByValSize - Offset; 3529 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3530 DAG.getConstant(Offset, PtrTy)); 3531 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 3532 DAG.getIntPtrConstant(ByVal.Address)); 3533 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 3534 DAG.getConstant(MemCpySize, PtrTy), Alignment, 3535 /*isVolatile=*/false, /*AlwaysInline=*/false, 3536 MachinePointerInfo(0), MachinePointerInfo(0)); 3537 MemOpChains.push_back(Chain); 3538} 3539 3540void 3541MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 3542 const MipsCC &CC, SDValue Chain, 3543 SDLoc DL, SelectionDAG &DAG) const { 3544 unsigned NumRegs = CC.numIntArgRegs(); 3545 const uint16_t *ArgRegs = CC.intArgRegs(); 3546 const CCState &CCInfo = CC.getCCInfo(); 3547 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs); 3548 unsigned RegSize = CC.regSize(); 3549 MVT RegTy = MVT::getIntegerVT(RegSize * 8); 3550 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3551 MachineFunction &MF = DAG.getMachineFunction(); 3552 MachineFrameInfo *MFI = MF.getFrameInfo(); 3553 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3554 3555 // Offset of the first variable argument from stack pointer. 3556 int VaArgOffset; 3557 3558 if (NumRegs == Idx) 3559 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize); 3560 else 3561 VaArgOffset = 3562 (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx)); 3563 3564 // Record the frame index of the first variable argument 3565 // which is a value necessary to VASTART. 3566 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3567 MipsFI->setVarArgsFrameIndex(FI); 3568 3569 // Copy the integer registers that have not been used for argument passing 3570 // to the argument register save area. For O32, the save area is allocated 3571 // in the caller's stack frame, while for N32/64, it is allocated in the 3572 // callee's stack frame. 3573 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) { 3574 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 3575 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 3576 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3577 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 3578 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, 3579 MachinePointerInfo(), false, false, 0); 3580 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0); 3581 OutChains.push_back(Store); 3582 } 3583} 3584