MipsISelLowering.cpp revision 29cb2591f9f7ec948e7b0e719b1db6cef99010d0 
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14#define DEBUG_TYPE "mips-lower"
15#include <set>
16#include "MipsISelLowering.h"
17#include "InstPrinter/MipsInstPrinter.h"
18#include "MCTargetDesc/MipsBaseInfo.h"
19#include "MipsMachineFunction.h"
20#include "MipsSubtarget.h"
21#include "MipsTargetMachine.h"
22#include "MipsTargetObjectFile.h"
23#include "llvm/ADT/Statistic.h"
24#include "llvm/CodeGen/CallingConvLower.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/SelectionDAGISel.h"
30#include "llvm/CodeGen/ValueTypes.h"
31#include "llvm/IR/CallingConv.h"
32#include "llvm/IR/DerivedTypes.h"
33#include "llvm/IR/Function.h"
34#include "llvm/IR/GlobalVariable.h"
35#include "llvm/IR/Intrinsics.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
40
41using namespace llvm;
42
43STATISTIC(NumTailCalls, "Number of tail calls");
44
45static cl::opt<bool>
46EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
47                    cl::desc("MIPS: Enable tail calls."), cl::init(false));
48
49static cl::opt<bool>
50LargeGOT("mxgot", cl::Hidden,
51         cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
52
53static cl::opt<bool>
54Mips16HardFloat("mips16-hard-float", cl::NotHidden,
55                cl::desc("MIPS: mips16 hard float enable."),
56                cl::init(false));
57
58static cl::opt<bool> DontExpandCondPseudos16(
59  "mips16-dont-expand-cond-pseudo",
60  cl::init(false),
61  cl::desc("Dont expand conditional move related "
62           "pseudos for Mips 16"),
63  cl::Hidden);
64
65
66static const uint16_t O32IntRegs[4] = {
67  Mips::A0, Mips::A1, Mips::A2, Mips::A3
68};
69
70static const uint16_t Mips64IntRegs[8] = {
71  Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
72  Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
73};
74
75static const uint16_t Mips64DPRegs[8] = {
76  Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
77  Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
78};
79
80// If I is a shifted mask, set the size (Size) and the first bit of the
81// mask (Pos), and return true.
82// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
83static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
84  if (!isShiftedMask_64(I))
85     return false;
86
87  Size = CountPopulation_64(I);
88  Pos = CountTrailingZeros_64(I);
89  return true;
90}
91
92static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) {
93  MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
94  return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
95}
96
97static SDValue getTargetNode(SDValue Op, SelectionDAG &DAG, unsigned Flag) {
98  EVT Ty = Op.getValueType();
99
100  if (GlobalAddressSDNode *N = dyn_cast<GlobalAddressSDNode>(Op))
101    return DAG.getTargetGlobalAddress(N->getGlobal(), Op.getDebugLoc(), Ty, 0,
102                                      Flag);
103  if (ExternalSymbolSDNode *N = dyn_cast<ExternalSymbolSDNode>(Op))
104    return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
105  if (BlockAddressSDNode *N = dyn_cast<BlockAddressSDNode>(Op))
106    return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
107  if (JumpTableSDNode *N = dyn_cast<JumpTableSDNode>(Op))
108    return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
109  if (ConstantPoolSDNode *N = dyn_cast<ConstantPoolSDNode>(Op))
110    return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
111                                     N->getOffset(), Flag);
112
113  llvm_unreachable("Unexpected node type.");
114  return SDValue();
115}
116
117static SDValue getAddrNonPIC(SDValue Op, SelectionDAG &DAG) {
118  DebugLoc DL = Op.getDebugLoc();
119  EVT Ty = Op.getValueType();
120  SDValue Hi = getTargetNode(Op, DAG, MipsII::MO_ABS_HI);
121  SDValue Lo = getTargetNode(Op, DAG, MipsII::MO_ABS_LO);
122  return DAG.getNode(ISD::ADD, DL, Ty,
123                     DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
124                     DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
125}
126
127static SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) {
128  DebugLoc DL = Op.getDebugLoc();
129  EVT Ty = Op.getValueType();
130  unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
131  SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, GetGlobalReg(DAG, Ty),
132                            getTargetNode(Op, DAG, GOTFlag));
133  SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
134                             MachinePointerInfo::getGOT(), false, false, false,
135                             0);
136  unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
137  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(Op, DAG, LoFlag));
138  return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
139}
140
141static SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) {
142  DebugLoc DL = Op.getDebugLoc();
143  EVT Ty = Op.getValueType();
144  SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, GetGlobalReg(DAG, Ty),
145                            getTargetNode(Op, DAG, Flag));
146  return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Tgt,
147                     MachinePointerInfo::getGOT(), false, false, false, 0);
148}
149
150static SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
151                                     unsigned HiFlag, unsigned LoFlag) {
152  DebugLoc DL = Op.getDebugLoc();
153  EVT Ty = Op.getValueType();
154  SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(Op, DAG, HiFlag));
155  Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, GetGlobalReg(DAG, Ty));
156  SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
157                                getTargetNode(Op, DAG, LoFlag));
158  return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Wrapper,
159                     MachinePointerInfo::getGOT(), false, false, false, 0);
160}
161
162const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
163  switch (Opcode) {
164  case MipsISD::JmpLink:           return "MipsISD::JmpLink";
165  case MipsISD::TailCall:          return "MipsISD::TailCall";
166  case MipsISD::Hi:                return "MipsISD::Hi";
167  case MipsISD::Lo:                return "MipsISD::Lo";
168  case MipsISD::GPRel:             return "MipsISD::GPRel";
169  case MipsISD::ThreadPointer:     return "MipsISD::ThreadPointer";
170  case MipsISD::Ret:               return "MipsISD::Ret";
171  case MipsISD::EH_RETURN:         return "MipsISD::EH_RETURN";
172  case MipsISD::FPBrcond:          return "MipsISD::FPBrcond";
173  case MipsISD::FPCmp:             return "MipsISD::FPCmp";
174  case MipsISD::CMovFP_T:          return "MipsISD::CMovFP_T";
175  case MipsISD::CMovFP_F:          return "MipsISD::CMovFP_F";
176  case MipsISD::FPRound:           return "MipsISD::FPRound";
177  case MipsISD::MAdd:              return "MipsISD::MAdd";
178  case MipsISD::MAddu:             return "MipsISD::MAddu";
179  case MipsISD::MSub:              return "MipsISD::MSub";
180  case MipsISD::MSubu:             return "MipsISD::MSubu";
181  case MipsISD::DivRem:            return "MipsISD::DivRem";
182  case MipsISD::DivRemU:           return "MipsISD::DivRemU";
183  case MipsISD::BuildPairF64:      return "MipsISD::BuildPairF64";
184  case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
185  case MipsISD::Wrapper:           return "MipsISD::Wrapper";
186  case MipsISD::Sync:              return "MipsISD::Sync";
187  case MipsISD::Ext:               return "MipsISD::Ext";
188  case MipsISD::Ins:               return "MipsISD::Ins";
189  case MipsISD::LWL:               return "MipsISD::LWL";
190  case MipsISD::LWR:               return "MipsISD::LWR";
191  case MipsISD::SWL:               return "MipsISD::SWL";
192  case MipsISD::SWR:               return "MipsISD::SWR";
193  case MipsISD::LDL:               return "MipsISD::LDL";
194  case MipsISD::LDR:               return "MipsISD::LDR";
195  case MipsISD::SDL:               return "MipsISD::SDL";
196  case MipsISD::SDR:               return "MipsISD::SDR";
197  case MipsISD::EXTP:              return "MipsISD::EXTP";
198  case MipsISD::EXTPDP:            return "MipsISD::EXTPDP";
199  case MipsISD::EXTR_S_H:          return "MipsISD::EXTR_S_H";
200  case MipsISD::EXTR_W:            return "MipsISD::EXTR_W";
201  case MipsISD::EXTR_R_W:          return "MipsISD::EXTR_R_W";
202  case MipsISD::EXTR_RS_W:         return "MipsISD::EXTR_RS_W";
203  case MipsISD::SHILO:             return "MipsISD::SHILO";
204  case MipsISD::MTHLIP:            return "MipsISD::MTHLIP";
205  case MipsISD::MULT:              return "MipsISD::MULT";
206  case MipsISD::MULTU:             return "MipsISD::MULTU";
207  case MipsISD::MADD_DSP:          return "MipsISD::MADD_DSPDSP";
208  case MipsISD::MADDU_DSP:         return "MipsISD::MADDU_DSP";
209  case MipsISD::MSUB_DSP:          return "MipsISD::MSUB_DSP";
210  case MipsISD::MSUBU_DSP:         return "MipsISD::MSUBU_DSP";
211  default:                         return NULL;
212  }
213}
214
215namespace {
216  struct ltstr {
217    bool operator()(const char *s1, const char *s2) const
218    {
219      return strcmp(s1, s2) < 0;
220    }
221  };
222
223  std::set<const char*, ltstr> noHelperNeeded;
224}
225
226void MipsTargetLowering::SetMips16LibcallName
227  (RTLIB::Libcall l, const char *Name) {
228  setLibcallName(l, Name);
229  noHelperNeeded.insert(Name);
230}
231
232void MipsTargetLowering::setMips16HardFloatLibCalls() {
233  SetMips16LibcallName(RTLIB::ADD_F32, "__mips16_addsf3");
234  SetMips16LibcallName(RTLIB::ADD_F64, "__mips16_adddf3");
235  SetMips16LibcallName(RTLIB::SUB_F32, "__mips16_subsf3");
236  SetMips16LibcallName(RTLIB::SUB_F64, "__mips16_subdf3");
237  SetMips16LibcallName(RTLIB::MUL_F32, "__mips16_mulsf3");
238  SetMips16LibcallName(RTLIB::MUL_F64, "__mips16_muldf3");
239  SetMips16LibcallName(RTLIB::DIV_F32, "__mips16_divsf3");
240  SetMips16LibcallName(RTLIB::DIV_F64, "__mips16_divdf3");
241  SetMips16LibcallName(RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2");
242  SetMips16LibcallName(RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2");
243  SetMips16LibcallName(RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi");
244  SetMips16LibcallName(RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi");
245  SetMips16LibcallName(RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf");
246  SetMips16LibcallName(RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf");
247  SetMips16LibcallName(RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf");
248  SetMips16LibcallName(RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf");
249  SetMips16LibcallName(RTLIB::OEQ_F32, "__mips16_eqsf2");
250  SetMips16LibcallName(RTLIB::OEQ_F64, "__mips16_eqdf2");
251  SetMips16LibcallName(RTLIB::UNE_F32, "__mips16_nesf2");
252  SetMips16LibcallName(RTLIB::UNE_F64, "__mips16_nedf2");
253  SetMips16LibcallName(RTLIB::OGE_F32, "__mips16_gesf2");
254  SetMips16LibcallName(RTLIB::OGE_F64, "__mips16_gedf2");
255  SetMips16LibcallName(RTLIB::OLT_F32, "__mips16_ltsf2");
256  SetMips16LibcallName(RTLIB::OLT_F64, "__mips16_ltdf2");
257  SetMips16LibcallName(RTLIB::OLE_F32, "__mips16_lesf2");
258  SetMips16LibcallName(RTLIB::OLE_F64, "__mips16_ledf2");
259  SetMips16LibcallName(RTLIB::OGT_F32, "__mips16_gtsf2");
260  SetMips16LibcallName(RTLIB::OGT_F64, "__mips16_gtdf2");
261  SetMips16LibcallName(RTLIB::UO_F32, "__mips16_unordsf2");
262  SetMips16LibcallName(RTLIB::UO_F64, "__mips16_unorddf2");
263  SetMips16LibcallName(RTLIB::O_F32, "__mips16_unordsf2");
264  SetMips16LibcallName(RTLIB::O_F64, "__mips16_unorddf2");
265}
266
267MipsTargetLowering::
268MipsTargetLowering(MipsTargetMachine &TM)
269  : TargetLowering(TM, new MipsTargetObjectFile()),
270    Subtarget(&TM.getSubtarget<MipsSubtarget>()),
271    HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
272    IsO32(Subtarget->isABI_O32()) {
273
274  // Mips does not have i1 type, so use i32 for
275  // setcc operations results (slt, sgt, ...).
276  setBooleanContents(ZeroOrOneBooleanContent);
277  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
278
279  // Set up the register classes
280  addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
281
282  if (HasMips64)
283    addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
284
285  if (Subtarget->inMips16Mode()) {
286    addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
287    if (Mips16HardFloat)
288      setMips16HardFloatLibCalls();
289  }
290
291  if (Subtarget->hasDSP()) {
292    MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
293
294    for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
295      addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass);
296
297      // Expand all builtin opcodes.
298      for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
299        setOperationAction(Opc, VecTys[i], Expand);
300
301      setOperationAction(ISD::LOAD, VecTys[i], Legal);
302      setOperationAction(ISD::STORE, VecTys[i], Legal);
303      setOperationAction(ISD::BITCAST, VecTys[i], Legal);
304    }
305  }
306
307  if (!TM.Options.UseSoftFloat) {
308    addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
309
310    // When dealing with single precision only, use libcalls
311    if (!Subtarget->isSingleFloat()) {
312      if (HasMips64)
313        addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
314      else
315        addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
316    }
317  }
318
319  // Load extented operations for i1 types must be promoted
320  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
321  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
322  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
323
324  // MIPS doesn't have extending float->double load/store
325  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
326  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
327
328  // Used by legalize types to correctly generate the setcc result.
329  // Without this, every float setcc comes with a AND/OR with the result,
330  // we don't want this, since the fpcmp result goes to a flag register,
331  // which is used implicitly by brcond and select operations.
332  AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
333
334  // Mips Custom Operations
335  setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);
336  setOperationAction(ISD::BlockAddress,       MVT::i32,   Custom);
337  setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);
338  setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);
339  setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);
340  setOperationAction(ISD::SELECT,             MVT::f32,   Custom);
341  setOperationAction(ISD::SELECT,             MVT::f64,   Custom);
342  setOperationAction(ISD::SELECT,             MVT::i32,   Custom);
343  setOperationAction(ISD::SELECT_CC,          MVT::f32,   Custom);
344  setOperationAction(ISD::SELECT_CC,          MVT::f64,   Custom);
345  setOperationAction(ISD::SETCC,              MVT::f32,   Custom);
346  setOperationAction(ISD::SETCC,              MVT::f64,   Custom);
347  setOperationAction(ISD::BRCOND,             MVT::Other, Custom);
348  setOperationAction(ISD::VASTART,            MVT::Other, Custom);
349  setOperationAction(ISD::FCOPYSIGN,          MVT::f32,   Custom);
350  setOperationAction(ISD::FCOPYSIGN,          MVT::f64,   Custom);
351  if (Subtarget->inMips16Mode()) {
352    setOperationAction(ISD::MEMBARRIER,         MVT::Other, Expand);
353    setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Expand);
354  }
355  else {
356    setOperationAction(ISD::MEMBARRIER,         MVT::Other, Custom);
357    setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Custom);
358  }
359  if (!Subtarget->inMips16Mode()) {
360    setOperationAction(ISD::LOAD,               MVT::i32, Custom);
361    setOperationAction(ISD::STORE,              MVT::i32, Custom);
362  }
363
364  if (!TM.Options.NoNaNsFPMath) {
365    setOperationAction(ISD::FABS,             MVT::f32,   Custom);
366    setOperationAction(ISD::FABS,             MVT::f64,   Custom);
367  }
368
369  if (HasMips64) {
370    setOperationAction(ISD::GlobalAddress,      MVT::i64,   Custom);
371    setOperationAction(ISD::BlockAddress,       MVT::i64,   Custom);
372    setOperationAction(ISD::GlobalTLSAddress,   MVT::i64,   Custom);
373    setOperationAction(ISD::JumpTable,          MVT::i64,   Custom);
374    setOperationAction(ISD::ConstantPool,       MVT::i64,   Custom);
375    setOperationAction(ISD::SELECT,             MVT::i64,   Custom);
376    setOperationAction(ISD::LOAD,               MVT::i64,   Custom);
377    setOperationAction(ISD::STORE,              MVT::i64,   Custom);
378  }
379
380  if (!HasMips64) {
381    setOperationAction(ISD::SHL_PARTS,          MVT::i32,   Custom);
382    setOperationAction(ISD::SRA_PARTS,          MVT::i32,   Custom);
383    setOperationAction(ISD::SRL_PARTS,          MVT::i32,   Custom);
384  }
385
386  setOperationAction(ISD::ADD,                MVT::i32,   Custom);
387  if (HasMips64)
388    setOperationAction(ISD::ADD,                MVT::i64,   Custom);
389
390  setOperationAction(ISD::SDIV, MVT::i32, Expand);
391  setOperationAction(ISD::SREM, MVT::i32, Expand);
392  setOperationAction(ISD::UDIV, MVT::i32, Expand);
393  setOperationAction(ISD::UREM, MVT::i32, Expand);
394  setOperationAction(ISD::SDIV, MVT::i64, Expand);
395  setOperationAction(ISD::SREM, MVT::i64, Expand);
396  setOperationAction(ISD::UDIV, MVT::i64, Expand);
397  setOperationAction(ISD::UREM, MVT::i64, Expand);
398
399  // Operations not directly supported by Mips.
400  setOperationAction(ISD::BR_JT,             MVT::Other, Expand);
401  setOperationAction(ISD::BR_CC,             MVT::Other, Expand);
402  setOperationAction(ISD::SELECT_CC,         MVT::Other, Expand);
403  setOperationAction(ISD::UINT_TO_FP,        MVT::i32,   Expand);
404  setOperationAction(ISD::UINT_TO_FP,        MVT::i64,   Expand);
405  setOperationAction(ISD::FP_TO_UINT,        MVT::i32,   Expand);
406  setOperationAction(ISD::FP_TO_UINT,        MVT::i64,   Expand);
407  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,    Expand);
408  setOperationAction(ISD::CTPOP,             MVT::i32,   Expand);
409  setOperationAction(ISD::CTPOP,             MVT::i64,   Expand);
410  setOperationAction(ISD::CTTZ,              MVT::i32,   Expand);
411  setOperationAction(ISD::CTTZ,              MVT::i64,   Expand);
412  setOperationAction(ISD::CTTZ_ZERO_UNDEF,   MVT::i32,   Expand);
413  setOperationAction(ISD::CTTZ_ZERO_UNDEF,   MVT::i64,   Expand);
414  setOperationAction(ISD::CTLZ_ZERO_UNDEF,   MVT::i32,   Expand);
415  setOperationAction(ISD::CTLZ_ZERO_UNDEF,   MVT::i64,   Expand);
416  setOperationAction(ISD::ROTL,              MVT::i32,   Expand);
417  setOperationAction(ISD::ROTL,              MVT::i64,   Expand);
418  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,  Expand);
419  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64,  Expand);
420
421  if (!Subtarget->hasMips32r2())
422    setOperationAction(ISD::ROTR, MVT::i32,   Expand);
423
424  if (!Subtarget->hasMips64r2())
425    setOperationAction(ISD::ROTR, MVT::i64,   Expand);
426
427  setOperationAction(ISD::FSIN,              MVT::f32,   Expand);
428  setOperationAction(ISD::FSIN,              MVT::f64,   Expand);
429  setOperationAction(ISD::FCOS,              MVT::f32,   Expand);
430  setOperationAction(ISD::FCOS,              MVT::f64,   Expand);
431  setOperationAction(ISD::FSINCOS,           MVT::f32,   Expand);
432  setOperationAction(ISD::FSINCOS,           MVT::f64,   Expand);
433  setOperationAction(ISD::FPOWI,             MVT::f32,   Expand);
434  setOperationAction(ISD::FPOW,              MVT::f32,   Expand);
435  setOperationAction(ISD::FPOW,              MVT::f64,   Expand);
436  setOperationAction(ISD::FLOG,              MVT::f32,   Expand);
437  setOperationAction(ISD::FLOG2,             MVT::f32,   Expand);
438  setOperationAction(ISD::FLOG10,            MVT::f32,   Expand);
439  setOperationAction(ISD::FEXP,              MVT::f32,   Expand);
440  setOperationAction(ISD::FMA,               MVT::f32,   Expand);
441  setOperationAction(ISD::FMA,               MVT::f64,   Expand);
442  setOperationAction(ISD::FREM,              MVT::f32,   Expand);
443  setOperationAction(ISD::FREM,              MVT::f64,   Expand);
444
445  if (!TM.Options.NoNaNsFPMath) {
446    setOperationAction(ISD::FNEG,             MVT::f32,   Expand);
447    setOperationAction(ISD::FNEG,             MVT::f64,   Expand);
448  }
449
450  setOperationAction(ISD::EXCEPTIONADDR,     MVT::i32, Expand);
451  setOperationAction(ISD::EXCEPTIONADDR,     MVT::i64, Expand);
452  setOperationAction(ISD::EHSELECTION,       MVT::i32, Expand);
453  setOperationAction(ISD::EHSELECTION,       MVT::i64, Expand);
454
455  setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
456
457  setOperationAction(ISD::VAARG,             MVT::Other, Expand);
458  setOperationAction(ISD::VACOPY,            MVT::Other, Expand);
459  setOperationAction(ISD::VAEND,             MVT::Other, Expand);
460
461  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
462  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
463
464  // Use the default for now
465  setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);
466  setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);
467
468  setOperationAction(ISD::ATOMIC_LOAD,       MVT::i32,    Expand);
469  setOperationAction(ISD::ATOMIC_LOAD,       MVT::i64,    Expand);
470  setOperationAction(ISD::ATOMIC_STORE,      MVT::i32,    Expand);
471  setOperationAction(ISD::ATOMIC_STORE,      MVT::i64,    Expand);
472
473  if (Subtarget->inMips16Mode()) {
474    setOperationAction(ISD::ATOMIC_CMP_SWAP,       MVT::i32,    Expand);
475    setOperationAction(ISD::ATOMIC_SWAP,           MVT::i32,    Expand);
476    setOperationAction(ISD::ATOMIC_LOAD_ADD,       MVT::i32,    Expand);
477    setOperationAction(ISD::ATOMIC_LOAD_SUB,       MVT::i32,    Expand);
478    setOperationAction(ISD::ATOMIC_LOAD_AND,       MVT::i32,    Expand);
479    setOperationAction(ISD::ATOMIC_LOAD_OR,        MVT::i32,    Expand);
480    setOperationAction(ISD::ATOMIC_LOAD_XOR,       MVT::i32,    Expand);
481    setOperationAction(ISD::ATOMIC_LOAD_NAND,      MVT::i32,    Expand);
482    setOperationAction(ISD::ATOMIC_LOAD_MIN,       MVT::i32,    Expand);
483    setOperationAction(ISD::ATOMIC_LOAD_MAX,       MVT::i32,    Expand);
484    setOperationAction(ISD::ATOMIC_LOAD_UMIN,      MVT::i32,    Expand);
485    setOperationAction(ISD::ATOMIC_LOAD_UMAX,      MVT::i32,    Expand);
486  }
487
488  setInsertFencesForAtomic(true);
489
490  if (!Subtarget->hasSEInReg()) {
491    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
492    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
493  }
494
495  if (!Subtarget->hasBitCount()) {
496    setOperationAction(ISD::CTLZ, MVT::i32, Expand);
497    setOperationAction(ISD::CTLZ, MVT::i64, Expand);
498  }
499
500  if (!Subtarget->hasSwap()) {
501    setOperationAction(ISD::BSWAP, MVT::i32, Expand);
502    setOperationAction(ISD::BSWAP, MVT::i64, Expand);
503  }
504
505  if (HasMips64) {
506    setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
507    setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
508    setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
509    setTruncStoreAction(MVT::i64, MVT::i32, Custom);
510  }
511
512  setTargetDAGCombine(ISD::ADDE);
513  setTargetDAGCombine(ISD::SUBE);
514  setTargetDAGCombine(ISD::SDIVREM);
515  setTargetDAGCombine(ISD::UDIVREM);
516  setTargetDAGCombine(ISD::SELECT);
517  setTargetDAGCombine(ISD::AND);
518  setTargetDAGCombine(ISD::OR);
519  setTargetDAGCombine(ISD::ADD);
520
521  setMinFunctionAlignment(HasMips64 ? 3 : 2);
522
523  setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
524  computeRegisterProperties();
525
526  setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
527  setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
528
529  MaxStoresPerMemcpy = 16;
530}
531
532bool
533MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
534  MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
535
536  if (Subtarget->inMips16Mode())
537    return false;
538
539  switch (SVT) {
540  case MVT::i64:
541  case MVT::i32:
542    if (Fast)
543      *Fast = true;
544    return true;
545  default:
546    return false;
547  }
548}
549
550EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
551  if (!VT.isVector())
552    return MVT::i32;
553  return VT.changeVectorElementTypeToInteger();
554}
555
556// SelectMadd -
557// Transforms a subgraph in CurDAG if the following pattern is found:
558//  (addc multLo, Lo0), (adde multHi, Hi0),
559// where,
560//  multHi/Lo: product of multiplication
561//  Lo0: initial value of Lo register
562//  Hi0: initial value of Hi register
563// Return true if pattern matching was successful.
564static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) {
565  // ADDENode's second operand must be a flag output of an ADDC node in order
566  // for the matching to be successful.
567  SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
568
569  if (ADDCNode->getOpcode() != ISD::ADDC)
570    return false;
571
572  SDValue MultHi = ADDENode->getOperand(0);
573  SDValue MultLo = ADDCNode->getOperand(0);
574  SDNode *MultNode = MultHi.getNode();
575  unsigned MultOpc = MultHi.getOpcode();
576
577  // MultHi and MultLo must be generated by the same node,
578  if (MultLo.getNode() != MultNode)
579    return false;
580
581  // and it must be a multiplication.
582  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
583    return false;
584
585  // MultLo amd MultHi must be the first and second output of MultNode
586  // respectively.
587  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
588    return false;
589
590  // Transform this to a MADD only if ADDENode and ADDCNode are the only users
591  // of the values of MultNode, in which case MultNode will be removed in later
592  // phases.
593  // If there exist users other than ADDENode or ADDCNode, this function returns
594  // here, which will result in MultNode being mapped to a single MULT
595  // instruction node rather than a pair of MULT and MADD instructions being
596  // produced.
597  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
598    return false;
599
600  SDValue Chain = CurDAG->getEntryNode();
601  DebugLoc dl = ADDENode->getDebugLoc();
602
603  // create MipsMAdd(u) node
604  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
605
606  SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue,
607                                 MultNode->getOperand(0),// Factor 0
608                                 MultNode->getOperand(1),// Factor 1
609                                 ADDCNode->getOperand(1),// Lo0
610                                 ADDENode->getOperand(1));// Hi0
611
612  // create CopyFromReg nodes
613  SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
614                                              MAdd);
615  SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
616                                              Mips::HI, MVT::i32,
617                                              CopyFromLo.getValue(2));
618
619  // replace uses of adde and addc here
620  if (!SDValue(ADDCNode, 0).use_empty())
621    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
622
623  if (!SDValue(ADDENode, 0).use_empty())
624    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
625
626  return true;
627}
628
629// SelectMsub -
630// Transforms a subgraph in CurDAG if the following pattern is found:
631//  (addc Lo0, multLo), (sube Hi0, multHi),
632// where,
633//  multHi/Lo: product of multiplication
634//  Lo0: initial value of Lo register
635//  Hi0: initial value of Hi register
636// Return true if pattern matching was successful.
637static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) {
638  // SUBENode's second operand must be a flag output of an SUBC node in order
639  // for the matching to be successful.
640  SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
641
642  if (SUBCNode->getOpcode() != ISD::SUBC)
643    return false;
644
645  SDValue MultHi = SUBENode->getOperand(1);
646  SDValue MultLo = SUBCNode->getOperand(1);
647  SDNode *MultNode = MultHi.getNode();
648  unsigned MultOpc = MultHi.getOpcode();
649
650  // MultHi and MultLo must be generated by the same node,
651  if (MultLo.getNode() != MultNode)
652    return false;
653
654  // and it must be a multiplication.
655  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
656    return false;
657
658  // MultLo amd MultHi must be the first and second output of MultNode
659  // respectively.
660  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
661    return false;
662
663  // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
664  // of the values of MultNode, in which case MultNode will be removed in later
665  // phases.
666  // If there exist users other than SUBENode or SUBCNode, this function returns
667  // here, which will result in MultNode being mapped to a single MULT
668  // instruction node rather than a pair of MULT and MSUB instructions being
669  // produced.
670  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
671    return false;
672
673  SDValue Chain = CurDAG->getEntryNode();
674  DebugLoc dl = SUBENode->getDebugLoc();
675
676  // create MipsSub(u) node
677  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
678
679  SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue,
680                                 MultNode->getOperand(0),// Factor 0
681                                 MultNode->getOperand(1),// Factor 1
682                                 SUBCNode->getOperand(0),// Lo0
683                                 SUBENode->getOperand(0));// Hi0
684
685  // create CopyFromReg nodes
686  SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
687                                              MSub);
688  SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
689                                              Mips::HI, MVT::i32,
690                                              CopyFromLo.getValue(2));
691
692  // replace uses of sube and subc here
693  if (!SDValue(SUBCNode, 0).use_empty())
694    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
695
696  if (!SDValue(SUBENode, 0).use_empty())
697    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
698
699  return true;
700}
701
702static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG,
703                                  TargetLowering::DAGCombinerInfo &DCI,
704                                  const MipsSubtarget *Subtarget) {
705  if (DCI.isBeforeLegalize())
706    return SDValue();
707
708  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
709      SelectMadd(N, &DAG))
710    return SDValue(N, 0);
711
712  return SDValue();
713}
714
715static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG,
716                                  TargetLowering::DAGCombinerInfo &DCI,
717                                  const MipsSubtarget *Subtarget) {
718  if (DCI.isBeforeLegalize())
719    return SDValue();
720
721  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
722      SelectMsub(N, &DAG))
723    return SDValue(N, 0);
724
725  return SDValue();
726}
727
728static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG,
729                                    TargetLowering::DAGCombinerInfo &DCI,
730                                    const MipsSubtarget *Subtarget) {
731  if (DCI.isBeforeLegalizeOps())
732    return SDValue();
733
734  EVT Ty = N->getValueType(0);
735  unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
736  unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
737  unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
738                                                  MipsISD::DivRemU;
739  DebugLoc dl = N->getDebugLoc();
740
741  SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
742                               N->getOperand(0), N->getOperand(1));
743  SDValue InChain = DAG.getEntryNode();
744  SDValue InGlue = DivRem;
745
746  // insert MFLO
747  if (N->hasAnyUseOfValue(0)) {
748    SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty,
749                                            InGlue);
750    DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
751    InChain = CopyFromLo.getValue(1);
752    InGlue = CopyFromLo.getValue(2);
753  }
754
755  // insert MFHI
756  if (N->hasAnyUseOfValue(1)) {
757    SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
758                                            HI, Ty, InGlue);
759    DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
760  }
761
762  return SDValue();
763}
764
765static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
766  switch (CC) {
767  default: llvm_unreachable("Unknown fp condition code!");
768  case ISD::SETEQ:
769  case ISD::SETOEQ: return Mips::FCOND_OEQ;
770  case ISD::SETUNE: return Mips::FCOND_UNE;
771  case ISD::SETLT:
772  case ISD::SETOLT: return Mips::FCOND_OLT;
773  case ISD::SETGT:
774  case ISD::SETOGT: return Mips::FCOND_OGT;
775  case ISD::SETLE:
776  case ISD::SETOLE: return Mips::FCOND_OLE;
777  case ISD::SETGE:
778  case ISD::SETOGE: return Mips::FCOND_OGE;
779  case ISD::SETULT: return Mips::FCOND_ULT;
780  case ISD::SETULE: return Mips::FCOND_ULE;
781  case ISD::SETUGT: return Mips::FCOND_UGT;
782  case ISD::SETUGE: return Mips::FCOND_UGE;
783  case ISD::SETUO:  return Mips::FCOND_UN;
784  case ISD::SETO:   return Mips::FCOND_OR;
785  case ISD::SETNE:
786  case ISD::SETONE: return Mips::FCOND_ONE;
787  case ISD::SETUEQ: return Mips::FCOND_UEQ;
788  }
789}
790
791
792// Returns true if condition code has to be inverted.
793static bool InvertFPCondCode(Mips::CondCode CC) {
794  if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
795    return false;
796
797  assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
798         "Illegal Condition Code");
799
800  return true;
801}
802
803// Creates and returns an FPCmp node from a setcc node.
804// Returns Op if setcc is not a floating point comparison.
805static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) {
806  // must be a SETCC node
807  if (Op.getOpcode() != ISD::SETCC)
808    return Op;
809
810  SDValue LHS = Op.getOperand(0);
811
812  if (!LHS.getValueType().isFloatingPoint())
813    return Op;
814
815  SDValue RHS = Op.getOperand(1);
816  DebugLoc dl = Op.getDebugLoc();
817
818  // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
819  // node if necessary.
820  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
821
822  return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
823                     DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
824}
825
826// Creates and returns a CMovFPT/F node.
827static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
828                            SDValue False, DebugLoc DL) {
829  bool invert = InvertFPCondCode((Mips::CondCode)
830                                 cast<ConstantSDNode>(Cond.getOperand(2))
831                                 ->getSExtValue());
832
833  return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
834                     True.getValueType(), True, False, Cond);
835}
836
837static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
838                                    TargetLowering::DAGCombinerInfo &DCI,
839                                    const MipsSubtarget *Subtarget) {
840  if (DCI.isBeforeLegalizeOps())
841    return SDValue();
842
843  SDValue SetCC = N->getOperand(0);
844
845  if ((SetCC.getOpcode() != ISD::SETCC) ||
846      !SetCC.getOperand(0).getValueType().isInteger())
847    return SDValue();
848
849  SDValue False = N->getOperand(2);
850  EVT FalseTy = False.getValueType();
851
852  if (!FalseTy.isInteger())
853    return SDValue();
854
855  ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
856
857  if (!CN || CN->getZExtValue())
858    return SDValue();
859
860  const DebugLoc DL = N->getDebugLoc();
861  ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
862  SDValue True = N->getOperand(1);
863
864  SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
865                       SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
866
867  return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
868}
869
870static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG,
871                                 TargetLowering::DAGCombinerInfo &DCI,
872                                 const MipsSubtarget *Subtarget) {
873  // Pattern match EXT.
874  //  $dst = and ((sra or srl) $src , pos), (2**size - 1)
875  //  => ext $dst, $src, size, pos
876  if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
877    return SDValue();
878
879  SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
880  unsigned ShiftRightOpc = ShiftRight.getOpcode();
881
882  // Op's first operand must be a shift right.
883  if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
884    return SDValue();
885
886  // The second operand of the shift must be an immediate.
887  ConstantSDNode *CN;
888  if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
889    return SDValue();
890
891  uint64_t Pos = CN->getZExtValue();
892  uint64_t SMPos, SMSize;
893
894  // Op's second operand must be a shifted mask.
895  if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
896      !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
897    return SDValue();
898
899  // Return if the shifted mask does not start at bit 0 or the sum of its size
900  // and Pos exceeds the word's size.
901  EVT ValTy = N->getValueType(0);
902  if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
903    return SDValue();
904
905  return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy,
906                     ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
907                     DAG.getConstant(SMSize, MVT::i32));
908}
909
910static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG,
911                                TargetLowering::DAGCombinerInfo &DCI,
912                                const MipsSubtarget *Subtarget) {
913  // Pattern match INS.
914  //  $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
915  //  where mask1 = (2**size - 1) << pos, mask0 = ~mask1
916  //  => ins $dst, $src, size, pos, $src1
917  if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
918    return SDValue();
919
920  SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
921  uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
922  ConstantSDNode *CN;
923
924  // See if Op's first operand matches (and $src1 , mask0).
925  if (And0.getOpcode() != ISD::AND)
926    return SDValue();
927
928  if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
929      !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
930    return SDValue();
931
932  // See if Op's second operand matches (and (shl $src, pos), mask1).
933  if (And1.getOpcode() != ISD::AND)
934    return SDValue();
935
936  if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
937      !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
938    return SDValue();
939
940  // The shift masks must have the same position and size.
941  if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
942    return SDValue();
943
944  SDValue Shl = And1.getOperand(0);
945  if (Shl.getOpcode() != ISD::SHL)
946    return SDValue();
947
948  if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
949    return SDValue();
950
951  unsigned Shamt = CN->getZExtValue();
952
953  // Return if the shift amount and the first bit position of mask are not the
954  // same.
955  EVT ValTy = N->getValueType(0);
956  if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
957    return SDValue();
958
959  return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0),
960                     DAG.getConstant(SMPos0, MVT::i32),
961                     DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
962}
963
964static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG,
965                                 TargetLowering::DAGCombinerInfo &DCI,
966                                 const MipsSubtarget *Subtarget) {
967  // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
968
969  if (DCI.isBeforeLegalizeOps())
970    return SDValue();
971
972  SDValue Add = N->getOperand(1);
973
974  if (Add.getOpcode() != ISD::ADD)
975    return SDValue();
976
977  SDValue Lo = Add.getOperand(1);
978
979  if ((Lo.getOpcode() != MipsISD::Lo) ||
980      (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
981    return SDValue();
982
983  EVT ValTy = N->getValueType(0);
984  DebugLoc DL = N->getDebugLoc();
985
986  SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
987                             Add.getOperand(0));
988  return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
989}
990
991SDValue  MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
992  const {
993  SelectionDAG &DAG = DCI.DAG;
994  unsigned opc = N->getOpcode();
995
996  switch (opc) {
997  default: break;
998  case ISD::ADDE:
999    return PerformADDECombine(N, DAG, DCI, Subtarget);
1000  case ISD::SUBE:
1001    return PerformSUBECombine(N, DAG, DCI, Subtarget);
1002  case ISD::SDIVREM:
1003  case ISD::UDIVREM:
1004    return PerformDivRemCombine(N, DAG, DCI, Subtarget);
1005  case ISD::SELECT:
1006    return PerformSELECTCombine(N, DAG, DCI, Subtarget);
1007  case ISD::AND:
1008    return PerformANDCombine(N, DAG, DCI, Subtarget);
1009  case ISD::OR:
1010    return PerformORCombine(N, DAG, DCI, Subtarget);
1011  case ISD::ADD:
1012    return PerformADDCombine(N, DAG, DCI, Subtarget);
1013  }
1014
1015  return SDValue();
1016}
1017
1018void
1019MipsTargetLowering::LowerOperationWrapper(SDNode *N,
1020                                          SmallVectorImpl<SDValue> &Results,
1021                                          SelectionDAG &DAG) const {
1022  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1023
1024  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1025    Results.push_back(Res.getValue(I));
1026}
1027
1028void
1029MipsTargetLowering::ReplaceNodeResults(SDNode *N,
1030                                       SmallVectorImpl<SDValue> &Results,
1031                                       SelectionDAG &DAG) const {
1032  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1033
1034  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1035    Results.push_back(Res.getValue(I));
1036}
1037
1038SDValue MipsTargetLowering::
1039LowerOperation(SDValue Op, SelectionDAG &DAG) const
1040{
1041  switch (Op.getOpcode())
1042  {
1043    case ISD::BRCOND:             return LowerBRCOND(Op, DAG);
1044    case ISD::ConstantPool:       return LowerConstantPool(Op, DAG);
1045    case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
1046    case ISD::BlockAddress:       return LowerBlockAddress(Op, DAG);
1047    case ISD::GlobalTLSAddress:   return LowerGlobalTLSAddress(Op, DAG);
1048    case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
1049    case ISD::SELECT:             return LowerSELECT(Op, DAG);
1050    case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
1051    case ISD::SETCC:              return LowerSETCC(Op, DAG);
1052    case ISD::VASTART:            return LowerVASTART(Op, DAG);
1053    case ISD::FCOPYSIGN:          return LowerFCOPYSIGN(Op, DAG);
1054    case ISD::FABS:               return LowerFABS(Op, DAG);
1055    case ISD::FRAMEADDR:          return LowerFRAMEADDR(Op, DAG);
1056    case ISD::RETURNADDR:         return LowerRETURNADDR(Op, DAG);
1057    case ISD::EH_RETURN:          return LowerEH_RETURN(Op, DAG);
1058    case ISD::MEMBARRIER:         return LowerMEMBARRIER(Op, DAG);
1059    case ISD::ATOMIC_FENCE:       return LowerATOMIC_FENCE(Op, DAG);
1060    case ISD::SHL_PARTS:          return LowerShiftLeftParts(Op, DAG);
1061    case ISD::SRA_PARTS:          return LowerShiftRightParts(Op, DAG, true);
1062    case ISD::SRL_PARTS:          return LowerShiftRightParts(Op, DAG, false);
1063    case ISD::LOAD:               return LowerLOAD(Op, DAG);
1064    case ISD::STORE:              return LowerSTORE(Op, DAG);
1065    case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1066    case ISD::INTRINSIC_W_CHAIN:  return LowerINTRINSIC_W_CHAIN(Op, DAG);
1067    case ISD::ADD:                return LowerADD(Op, DAG);
1068  }
1069  return SDValue();
1070}
1071
1072//===----------------------------------------------------------------------===//
1073//  Lower helper functions
1074//===----------------------------------------------------------------------===//
1075
1076// AddLiveIn - This helper function adds the specified physical register to the
1077// MachineFunction as a live in value.  It also creates a corresponding
1078// virtual register for it.
1079static unsigned
1080AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1081{
1082  unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1083  MF.getRegInfo().addLiveIn(PReg, VReg);
1084  return VReg;
1085}
1086
1087// Get fp branch code (not opcode) from condition code.
1088static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
1089  if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
1090    return Mips::BRANCH_T;
1091
1092  assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
1093         "Invalid CondCode.");
1094
1095  return Mips::BRANCH_F;
1096}
1097
1098/*
1099static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
1100                                        DebugLoc dl,
1101                                        const MipsSubtarget *Subtarget,
1102                                        const TargetInstrInfo *TII,
1103                                        bool isFPCmp, unsigned Opc) {
1104  // There is no need to expand CMov instructions if target has
1105  // conditional moves.
1106  if (Subtarget->hasCondMov())
1107    return BB;
1108
1109  // To "insert" a SELECT_CC instruction, we actually have to insert the
1110  // diamond control-flow pattern.  The incoming instruction knows the
1111  // destination vreg to set, the condition code register to branch on, the
1112  // true/false values to select between, and a branch opcode to use.
1113  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1114  MachineFunction::iterator It = BB;
1115  ++It;
1116
1117  //  thisMBB:
1118  //  ...
1119  //   TrueVal = ...
1120  //   setcc r1, r2, r3
1121  //   bNE   r1, r0, copy1MBB
1122  //   fallthrough --> copy0MBB
1123  MachineBasicBlock *thisMBB  = BB;
1124  MachineFunction *F = BB->getParent();
1125  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1126  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
1127  F->insert(It, copy0MBB);
1128  F->insert(It, sinkMBB);
1129
1130  // Transfer the remainder of BB and its successor edges to sinkMBB.
1131  sinkMBB->splice(sinkMBB->begin(), BB,
1132                  llvm::next(MachineBasicBlock::iterator(MI)),
1133                  BB->end());
1134  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1135
1136  // Next, add the true and fallthrough blocks as its successors.
1137  BB->addSuccessor(copy0MBB);
1138  BB->addSuccessor(sinkMBB);
1139
1140  // Emit the right instruction according to the type of the operands compared
1141  if (isFPCmp)
1142    BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
1143  else
1144    BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
1145      .addReg(Mips::ZERO).addMBB(sinkMBB);
1146
1147  //  copy0MBB:
1148  //   %FalseValue = ...
1149  //   # fallthrough to sinkMBB
1150  BB = copy0MBB;
1151
1152  // Update machine-CFG edges
1153  BB->addSuccessor(sinkMBB);
1154
1155  //  sinkMBB:
1156  //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
1157  //  ...
1158  BB = sinkMBB;
1159
1160  if (isFPCmp)
1161    BuildMI(*BB, BB->begin(), dl,
1162            TII->get(Mips::PHI), MI->getOperand(0).getReg())
1163      .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
1164      .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
1165  else
1166    BuildMI(*BB, BB->begin(), dl,
1167            TII->get(Mips::PHI), MI->getOperand(0).getReg())
1168      .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
1169      .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
1170
1171  MI->eraseFromParent();   // The pseudo instruction is gone now.
1172  return BB;
1173}
1174*/
1175
1176MachineBasicBlock *
1177MipsTargetLowering::EmitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
1178  // $bb:
1179  //  bposge32_pseudo $vr0
1180  //  =>
1181  // $bb:
1182  //  bposge32 $tbb
1183  // $fbb:
1184  //  li $vr2, 0
1185  //  b $sink
1186  // $tbb:
1187  //  li $vr1, 1
1188  // $sink:
1189  //  $vr0 = phi($vr2, $fbb, $vr1, $tbb)
1190
1191  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1192  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1193  const TargetRegisterClass *RC = &Mips::CPURegsRegClass;
1194  DebugLoc DL = MI->getDebugLoc();
1195  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1196  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1197  MachineFunction *F = BB->getParent();
1198  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1199  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1200  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
1201  F->insert(It, FBB);
1202  F->insert(It, TBB);
1203  F->insert(It, Sink);
1204
1205  // Transfer the remainder of BB and its successor edges to Sink.
1206  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1207               BB->end());
1208  Sink->transferSuccessorsAndUpdatePHIs(BB);
1209
1210  // Add successors.
1211  BB->addSuccessor(FBB);
1212  BB->addSuccessor(TBB);
1213  FBB->addSuccessor(Sink);
1214  TBB->addSuccessor(Sink);
1215
1216  // Insert the real bposge32 instruction to $BB.
1217  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
1218
1219  // Fill $FBB.
1220  unsigned VR2 = RegInfo.createVirtualRegister(RC);
1221  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
1222    .addReg(Mips::ZERO).addImm(0);
1223  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1224
1225  // Fill $TBB.
1226  unsigned VR1 = RegInfo.createVirtualRegister(RC);
1227  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
1228    .addReg(Mips::ZERO).addImm(1);
1229
1230  // Insert phi function to $Sink.
1231  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1232          MI->getOperand(0).getReg())
1233    .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
1234
1235  MI->eraseFromParent();   // The pseudo instruction is gone now.
1236  return Sink;
1237}
1238
1239MachineBasicBlock *MipsTargetLowering::EmitSel16(unsigned Opc, MachineInstr *MI,
1240                             MachineBasicBlock *BB) const {
1241  if (DontExpandCondPseudos16)
1242    return BB;
1243  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1244  DebugLoc dl = MI->getDebugLoc();
1245  // To "insert" a SELECT_CC instruction, we actually have to insert the
1246  // diamond control-flow pattern.  The incoming instruction knows the
1247  // destination vreg to set, the condition code register to branch on, the
1248  // true/false values to select between, and a branch opcode to use.
1249  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1250  MachineFunction::iterator It = BB;
1251  ++It;
1252
1253  //  thisMBB:
1254  //  ...
1255  //   TrueVal = ...
1256  //   setcc r1, r2, r3
1257  //   bNE   r1, r0, copy1MBB
1258  //   fallthrough --> copy0MBB
1259  MachineBasicBlock *thisMBB  = BB;
1260  MachineFunction *F = BB->getParent();
1261  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1262  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
1263  F->insert(It, copy0MBB);
1264  F->insert(It, sinkMBB);
1265
1266  // Transfer the remainder of BB and its successor edges to sinkMBB.
1267  sinkMBB->splice(sinkMBB->begin(), BB,
1268                  llvm::next(MachineBasicBlock::iterator(MI)),
1269                  BB->end());
1270  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1271
1272  // Next, add the true and fallthrough blocks as its successors.
1273  BB->addSuccessor(copy0MBB);
1274  BB->addSuccessor(sinkMBB);
1275
1276  BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
1277    .addMBB(sinkMBB);
1278
1279  //  copy0MBB:
1280  //   %FalseValue = ...
1281  //   # fallthrough to sinkMBB
1282  BB = copy0MBB;
1283
1284  // Update machine-CFG edges
1285  BB->addSuccessor(sinkMBB);
1286
1287  //  sinkMBB:
1288  //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
1289  //  ...
1290  BB = sinkMBB;
1291
1292  BuildMI(*BB, BB->begin(), dl,
1293          TII->get(Mips::PHI), MI->getOperand(0).getReg())
1294    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
1295    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
1296
1297  MI->eraseFromParent();   // The pseudo instruction is gone now.
1298  return BB;
1299}
1300
1301MachineBasicBlock *MipsTargetLowering::EmitSelT16
1302  (unsigned Opc1, unsigned Opc2,
1303   MachineInstr *MI, MachineBasicBlock *BB) const {
1304  if (DontExpandCondPseudos16)
1305    return BB;
1306  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1307  DebugLoc dl = MI->getDebugLoc();
1308  // To "insert" a SELECT_CC instruction, we actually have to insert the
1309  // diamond control-flow pattern.  The incoming instruction knows the
1310  // destination vreg to set, the condition code register to branch on, the
1311  // true/false values to select between, and a branch opcode to use.
1312  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1313  MachineFunction::iterator It = BB;
1314  ++It;
1315
1316  //  thisMBB:
1317  //  ...
1318  //   TrueVal = ...
1319  //   setcc r1, r2, r3
1320  //   bNE   r1, r0, copy1MBB
1321  //   fallthrough --> copy0MBB
1322  MachineBasicBlock *thisMBB  = BB;
1323  MachineFunction *F = BB->getParent();
1324  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1325  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
1326  F->insert(It, copy0MBB);
1327  F->insert(It, sinkMBB);
1328
1329  // Transfer the remainder of BB and its successor edges to sinkMBB.
1330  sinkMBB->splice(sinkMBB->begin(), BB,
1331                  llvm::next(MachineBasicBlock::iterator(MI)),
1332                  BB->end());
1333  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1334
1335  // Next, add the true and fallthrough blocks as its successors.
1336  BB->addSuccessor(copy0MBB);
1337  BB->addSuccessor(sinkMBB);
1338
1339  BuildMI(BB, dl, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
1340    .addReg(MI->getOperand(4).getReg());
1341  BuildMI(BB, dl, TII->get(Opc1)).addMBB(sinkMBB);
1342
1343  //  copy0MBB:
1344  //   %FalseValue = ...
1345  //   # fallthrough to sinkMBB
1346  BB = copy0MBB;
1347
1348  // Update machine-CFG edges
1349  BB->addSuccessor(sinkMBB);
1350
1351  //  sinkMBB:
1352  //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
1353  //  ...
1354  BB = sinkMBB;
1355
1356  BuildMI(*BB, BB->begin(), dl,
1357          TII->get(Mips::PHI), MI->getOperand(0).getReg())
1358    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
1359    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
1360
1361  MI->eraseFromParent();   // The pseudo instruction is gone now.
1362  return BB;
1363
1364}
1365
1366
1367MachineBasicBlock *MipsTargetLowering::EmitSeliT16
1368  (unsigned Opc1, unsigned Opc2,
1369   MachineInstr *MI, MachineBasicBlock *BB) const {
1370  if (DontExpandCondPseudos16)
1371    return BB;
1372  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1373  DebugLoc dl = MI->getDebugLoc();
1374  // To "insert" a SELECT_CC instruction, we actually have to insert the
1375  // diamond control-flow pattern.  The incoming instruction knows the
1376  // destination vreg to set, the condition code register to branch on, the
1377  // true/false values to select between, and a branch opcode to use.
1378  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1379  MachineFunction::iterator It = BB;
1380  ++It;
1381
1382  //  thisMBB:
1383  //  ...
1384  //   TrueVal = ...
1385  //   setcc r1, r2, r3
1386  //   bNE   r1, r0, copy1MBB
1387  //   fallthrough --> copy0MBB
1388  MachineBasicBlock *thisMBB  = BB;
1389  MachineFunction *F = BB->getParent();
1390  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1391  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
1392  F->insert(It, copy0MBB);
1393  F->insert(It, sinkMBB);
1394
1395  // Transfer the remainder of BB and its successor edges to sinkMBB.
1396  sinkMBB->splice(sinkMBB->begin(), BB,
1397                  llvm::next(MachineBasicBlock::iterator(MI)),
1398                  BB->end());
1399  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1400
1401  // Next, add the true and fallthrough blocks as its successors.
1402  BB->addSuccessor(copy0MBB);
1403  BB->addSuccessor(sinkMBB);
1404
1405  BuildMI(BB, dl, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
1406    .addImm(MI->getOperand(4).getImm());
1407  BuildMI(BB, dl, TII->get(Opc1)).addMBB(sinkMBB);
1408
1409  //  copy0MBB:
1410  //   %FalseValue = ...
1411  //   # fallthrough to sinkMBB
1412  BB = copy0MBB;
1413
1414  // Update machine-CFG edges
1415  BB->addSuccessor(sinkMBB);
1416
1417  //  sinkMBB:
1418  //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
1419  //  ...
1420  BB = sinkMBB;
1421
1422  BuildMI(*BB, BB->begin(), dl,
1423          TII->get(Mips::PHI), MI->getOperand(0).getReg())
1424    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
1425    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
1426
1427  MI->eraseFromParent();   // The pseudo instruction is gone now.
1428  return BB;
1429
1430}
1431
1432
1433MachineBasicBlock
1434  *MipsTargetLowering::EmitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
1435                           MachineInstr *MI,
1436                           MachineBasicBlock *BB) const {
1437  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1438  unsigned regX = MI->getOperand(0).getReg();
1439  unsigned regY = MI->getOperand(1).getReg();
1440  MachineBasicBlock *target = MI->getOperand(2).getMBB();
1441  BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addReg(regY);
1442  BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
1443  MI->eraseFromParent();   // The pseudo instruction is gone now.
1444  return BB;
1445}
1446
1447
1448MachineBasicBlock *MipsTargetLowering::EmitFEXT_T8I8I16_ins(
1449  unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc,
1450  MachineInstr *MI,  MachineBasicBlock *BB) const {
1451  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1452  unsigned regX = MI->getOperand(0).getReg();
1453  int64_t imm = MI->getOperand(1).getImm();
1454  MachineBasicBlock *target = MI->getOperand(2).getMBB();
1455  unsigned CmpOpc;
1456  if (isUInt<8>(imm))
1457    CmpOpc = CmpiOpc;
1458  else if (isUInt<16>(imm))
1459    CmpOpc = CmpiXOpc;
1460  else
1461    llvm_unreachable("immediate field not usable");
1462  BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
1463  BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
1464  MI->eraseFromParent();   // The pseudo instruction is gone now.
1465  return BB;
1466}
1467
1468MachineBasicBlock *
1469MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1470                                                MachineBasicBlock *BB) const {
1471  switch (MI->getOpcode()) {
1472  default:
1473    llvm_unreachable("Unexpected instr type to insert");
1474  case Mips::ATOMIC_LOAD_ADD_I8:
1475  case Mips::ATOMIC_LOAD_ADD_I8_P8:
1476    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
1477  case Mips::ATOMIC_LOAD_ADD_I16:
1478  case Mips::ATOMIC_LOAD_ADD_I16_P8:
1479    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
1480  case Mips::ATOMIC_LOAD_ADD_I32:
1481  case Mips::ATOMIC_LOAD_ADD_I32_P8:
1482    return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
1483  case Mips::ATOMIC_LOAD_ADD_I64:
1484  case Mips::ATOMIC_LOAD_ADD_I64_P8:
1485    return EmitAtomicBinary(MI, BB, 8, Mips::DADDu);
1486
1487  case Mips::ATOMIC_LOAD_AND_I8:
1488  case Mips::ATOMIC_LOAD_AND_I8_P8:
1489    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
1490  case Mips::ATOMIC_LOAD_AND_I16:
1491  case Mips::ATOMIC_LOAD_AND_I16_P8:
1492    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
1493  case Mips::ATOMIC_LOAD_AND_I32:
1494  case Mips::ATOMIC_LOAD_AND_I32_P8:
1495    return EmitAtomicBinary(MI, BB, 4, Mips::AND);
1496  case Mips::ATOMIC_LOAD_AND_I64:
1497  case Mips::ATOMIC_LOAD_AND_I64_P8:
1498    return EmitAtomicBinary(MI, BB, 8, Mips::AND64);
1499
1500  case Mips::ATOMIC_LOAD_OR_I8:
1501  case Mips::ATOMIC_LOAD_OR_I8_P8:
1502    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
1503  case Mips::ATOMIC_LOAD_OR_I16:
1504  case Mips::ATOMIC_LOAD_OR_I16_P8:
1505    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
1506  case Mips::ATOMIC_LOAD_OR_I32:
1507  case Mips::ATOMIC_LOAD_OR_I32_P8:
1508    return EmitAtomicBinary(MI, BB, 4, Mips::OR);
1509  case Mips::ATOMIC_LOAD_OR_I64:
1510  case Mips::ATOMIC_LOAD_OR_I64_P8:
1511    return EmitAtomicBinary(MI, BB, 8, Mips::OR64);
1512
1513  case Mips::ATOMIC_LOAD_XOR_I8:
1514  case Mips::ATOMIC_LOAD_XOR_I8_P8:
1515    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
1516  case Mips::ATOMIC_LOAD_XOR_I16:
1517  case Mips::ATOMIC_LOAD_XOR_I16_P8:
1518    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
1519  case Mips::ATOMIC_LOAD_XOR_I32:
1520  case Mips::ATOMIC_LOAD_XOR_I32_P8:
1521    return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
1522  case Mips::ATOMIC_LOAD_XOR_I64:
1523  case Mips::ATOMIC_LOAD_XOR_I64_P8:
1524    return EmitAtomicBinary(MI, BB, 8, Mips::XOR64);
1525
1526  case Mips::ATOMIC_LOAD_NAND_I8:
1527  case Mips::ATOMIC_LOAD_NAND_I8_P8:
1528    return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
1529  case Mips::ATOMIC_LOAD_NAND_I16:
1530  case Mips::ATOMIC_LOAD_NAND_I16_P8:
1531    return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
1532  case Mips::ATOMIC_LOAD_NAND_I32:
1533  case Mips::ATOMIC_LOAD_NAND_I32_P8:
1534    return EmitAtomicBinary(MI, BB, 4, 0, true);
1535  case Mips::ATOMIC_LOAD_NAND_I64:
1536  case Mips::ATOMIC_LOAD_NAND_I64_P8:
1537    return EmitAtomicBinary(MI, BB, 8, 0, true);
1538
1539  case Mips::ATOMIC_LOAD_SUB_I8:
1540  case Mips::ATOMIC_LOAD_SUB_I8_P8:
1541    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
1542  case Mips::ATOMIC_LOAD_SUB_I16:
1543  case Mips::ATOMIC_LOAD_SUB_I16_P8:
1544    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
1545  case Mips::ATOMIC_LOAD_SUB_I32:
1546  case Mips::ATOMIC_LOAD_SUB_I32_P8:
1547    return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
1548  case Mips::ATOMIC_LOAD_SUB_I64:
1549  case Mips::ATOMIC_LOAD_SUB_I64_P8:
1550    return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu);
1551
1552  case Mips::ATOMIC_SWAP_I8:
1553  case Mips::ATOMIC_SWAP_I8_P8:
1554    return EmitAtomicBinaryPartword(MI, BB, 1, 0);
1555  case Mips::ATOMIC_SWAP_I16:
1556  case Mips::ATOMIC_SWAP_I16_P8:
1557    return EmitAtomicBinaryPartword(MI, BB, 2, 0);
1558  case Mips::ATOMIC_SWAP_I32:
1559  case Mips::ATOMIC_SWAP_I32_P8:
1560    return EmitAtomicBinary(MI, BB, 4, 0);
1561  case Mips::ATOMIC_SWAP_I64:
1562  case Mips::ATOMIC_SWAP_I64_P8:
1563    return EmitAtomicBinary(MI, BB, 8, 0);
1564
1565  case Mips::ATOMIC_CMP_SWAP_I8:
1566  case Mips::ATOMIC_CMP_SWAP_I8_P8:
1567    return EmitAtomicCmpSwapPartword(MI, BB, 1);
1568  case Mips::ATOMIC_CMP_SWAP_I16:
1569  case Mips::ATOMIC_CMP_SWAP_I16_P8:
1570    return EmitAtomicCmpSwapPartword(MI, BB, 2);
1571  case Mips::ATOMIC_CMP_SWAP_I32:
1572  case Mips::ATOMIC_CMP_SWAP_I32_P8:
1573    return EmitAtomicCmpSwap(MI, BB, 4);
1574  case Mips::ATOMIC_CMP_SWAP_I64:
1575  case Mips::ATOMIC_CMP_SWAP_I64_P8:
1576    return EmitAtomicCmpSwap(MI, BB, 8);
1577  case Mips::BPOSGE32_PSEUDO:
1578    return EmitBPOSGE32(MI, BB);
1579  case Mips::SelBeqZ:
1580    return EmitSel16(Mips::BeqzRxImm16, MI, BB);
1581  case Mips::SelBneZ:
1582    return EmitSel16(Mips::BnezRxImm16, MI, BB);
1583  case Mips::SelTBteqZCmpi:
1584    return EmitSeliT16(Mips::BteqzX16, Mips::CmpiRxImmX16, MI, BB);
1585  case Mips::SelTBteqZSlti:
1586    return EmitSeliT16(Mips::BteqzX16, Mips::SltiRxImmX16, MI, BB);
1587  case Mips::SelTBteqZSltiu:
1588    return EmitSeliT16(Mips::BteqzX16, Mips::SltiuRxImmX16, MI, BB);
1589  case Mips::SelTBtneZCmpi:
1590    return EmitSeliT16(Mips::BtnezX16, Mips::CmpiRxImmX16, MI, BB);
1591  case Mips::SelTBtneZSlti:
1592    return EmitSeliT16(Mips::BtnezX16, Mips::SltiRxImmX16, MI, BB);
1593  case Mips::SelTBtneZSltiu:
1594    return EmitSeliT16(Mips::BtnezX16, Mips::SltiuRxImmX16, MI, BB);
1595  case Mips::SelTBteqZCmp:
1596    return EmitSelT16(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
1597  case Mips::SelTBteqZSlt:
1598    return EmitSelT16(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
1599  case Mips::SelTBteqZSltu:
1600    return EmitSelT16(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
1601  case Mips::SelTBtneZCmp:
1602    return EmitSelT16(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
1603  case Mips::SelTBtneZSlt:
1604    return EmitSelT16(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
1605  case Mips::SelTBtneZSltu:
1606    return EmitSelT16(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
1607  case Mips::BteqzT8CmpX16:
1608    return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
1609  case Mips::BteqzT8SltX16:
1610    return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
1611  case Mips::BteqzT8SltuX16:
1612    // TBD: figure out a way to get this or remove the instruction
1613    // altogether.
1614    return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
1615  case Mips::BtnezT8CmpX16:
1616    return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
1617  case Mips::BtnezT8SltX16:
1618    return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
1619  case Mips::BtnezT8SltuX16:
1620    // TBD: figure out a way to get this or remove the instruction
1621    // altogether.
1622    return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
1623  case Mips::BteqzT8CmpiX16: return EmitFEXT_T8I8I16_ins(
1624    Mips::BteqzX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, MI, BB);
1625  case Mips::BteqzT8SltiX16: return EmitFEXT_T8I8I16_ins(
1626    Mips::BteqzX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
1627  case Mips::BteqzT8SltiuX16: return EmitFEXT_T8I8I16_ins(
1628    Mips::BteqzX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
1629  case Mips::BtnezT8CmpiX16: return EmitFEXT_T8I8I16_ins(
1630    Mips::BtnezX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, MI, BB);
1631  case Mips::BtnezT8SltiX16: return EmitFEXT_T8I8I16_ins(
1632    Mips::BtnezX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
1633  case Mips::BtnezT8SltiuX16: return EmitFEXT_T8I8I16_ins(
1634    Mips::BtnezX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
1635    break;
1636  }
1637}
1638
1639// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1640// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1641MachineBasicBlock *
1642MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
1643                                     unsigned Size, unsigned BinOpcode,
1644                                     bool Nand) const {
1645  assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
1646
1647  MachineFunction *MF = BB->getParent();
1648  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1649  const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1650  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1651  DebugLoc dl = MI->getDebugLoc();
1652  unsigned LL, SC, AND, NOR, ZERO, BEQ;
1653
1654  if (Size == 4) {
1655    LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1656    SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1657    AND = Mips::AND;
1658    NOR = Mips::NOR;
1659    ZERO = Mips::ZERO;
1660    BEQ = Mips::BEQ;
1661  }
1662  else {
1663    LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1664    SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1665    AND = Mips::AND64;
1666    NOR = Mips::NOR64;
1667    ZERO = Mips::ZERO_64;
1668    BEQ = Mips::BEQ64;
1669  }
1670
1671  unsigned OldVal = MI->getOperand(0).getReg();
1672  unsigned Ptr = MI->getOperand(1).getReg();
1673  unsigned Incr = MI->getOperand(2).getReg();
1674
1675  unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1676  unsigned AndRes = RegInfo.createVirtualRegister(RC);
1677  unsigned Success = RegInfo.createVirtualRegister(RC);
1678
1679  // insert new blocks after the current block
1680  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1681  MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1682  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1683  MachineFunction::iterator It = BB;
1684  ++It;
1685  MF->insert(It, loopMBB);
1686  MF->insert(It, exitMBB);
1687
1688  // Transfer the remainder of BB and its successor edges to exitMBB.
1689  exitMBB->splice(exitMBB->begin(), BB,
1690                  llvm::next(MachineBasicBlock::iterator(MI)),
1691                  BB->end());
1692  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1693
1694  //  thisMBB:
1695  //    ...
1696  //    fallthrough --> loopMBB
1697  BB->addSuccessor(loopMBB);
1698  loopMBB->addSuccessor(loopMBB);
1699  loopMBB->addSuccessor(exitMBB);
1700
1701  //  loopMBB:
1702  //    ll oldval, 0(ptr)
1703  //    <binop> storeval, oldval, incr
1704  //    sc success, storeval, 0(ptr)
1705  //    beq success, $0, loopMBB
1706  BB = loopMBB;
1707  BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1708  if (Nand) {
1709    //  and andres, oldval, incr
1710    //  nor storeval, $0, andres
1711    BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1712    BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1713  } else if (BinOpcode) {
1714    //  <binop> storeval, oldval, incr
1715    BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1716  } else {
1717    StoreVal = Incr;
1718  }
1719  BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1720  BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1721
1722  MI->eraseFromParent();   // The instruction is gone now.
1723
1724  return exitMBB;
1725}
1726
1727MachineBasicBlock *
1728MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
1729                                             MachineBasicBlock *BB,
1730                                             unsigned Size, unsigned BinOpcode,
1731                                             bool Nand) const {
1732  assert((Size == 1 || Size == 2) &&
1733      "Unsupported size for EmitAtomicBinaryPartial.");
1734
1735  MachineFunction *MF = BB->getParent();
1736  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1737  const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1738  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1739  DebugLoc dl = MI->getDebugLoc();
1740  unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1741  unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1742
1743  unsigned Dest = MI->getOperand(0).getReg();
1744  unsigned Ptr = MI->getOperand(1).getReg();
1745  unsigned Incr = MI->getOperand(2).getReg();
1746
1747  unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1748  unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1749  unsigned Mask = RegInfo.createVirtualRegister(RC);
1750  unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1751  unsigned NewVal = RegInfo.createVirtualRegister(RC);
1752  unsigned OldVal = RegInfo.createVirtualRegister(RC);
1753  unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1754  unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1755  unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1756  unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1757  unsigned AndRes = RegInfo.createVirtualRegister(RC);
1758  unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1759  unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1760  unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1761  unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1762  unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1763  unsigned SllRes = RegInfo.createVirtualRegister(RC);
1764  unsigned Success = RegInfo.createVirtualRegister(RC);
1765
1766  // insert new blocks after the current block
1767  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1768  MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1769  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1770  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1771  MachineFunction::iterator It = BB;
1772  ++It;
1773  MF->insert(It, loopMBB);
1774  MF->insert(It, sinkMBB);
1775  MF->insert(It, exitMBB);
1776
1777  // Transfer the remainder of BB and its successor edges to exitMBB.
1778  exitMBB->splice(exitMBB->begin(), BB,
1779                  llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1780  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1781
1782  BB->addSuccessor(loopMBB);
1783  loopMBB->addSuccessor(loopMBB);
1784  loopMBB->addSuccessor(sinkMBB);
1785  sinkMBB->addSuccessor(exitMBB);
1786
1787  //  thisMBB:
1788  //    addiu   masklsb2,$0,-4                # 0xfffffffc
1789  //    and     alignedaddr,ptr,masklsb2
1790  //    andi    ptrlsb2,ptr,3
1791  //    sll     shiftamt,ptrlsb2,3
1792  //    ori     maskupper,$0,255               # 0xff
1793  //    sll     mask,maskupper,shiftamt
1794  //    nor     mask2,$0,mask
1795  //    sll     incr2,incr,shiftamt
1796
1797  int64_t MaskImm = (Size == 1) ? 255 : 65535;
1798  BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1799    .addReg(Mips::ZERO).addImm(-4);
1800  BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1801    .addReg(Ptr).addReg(MaskLSB2);
1802  BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1803  BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1804  BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1805    .addReg(Mips::ZERO).addImm(MaskImm);
1806  BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1807    .addReg(ShiftAmt).addReg(MaskUpper);
1808  BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1809  BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
1810
1811  // atomic.load.binop
1812  // loopMBB:
1813  //   ll      oldval,0(alignedaddr)
1814  //   binop   binopres,oldval,incr2
1815  //   and     newval,binopres,mask
1816  //   and     maskedoldval0,oldval,mask2
1817  //   or      storeval,maskedoldval0,newval
1818  //   sc      success,storeval,0(alignedaddr)
1819  //   beq     success,$0,loopMBB
1820
1821  // atomic.swap
1822  // loopMBB:
1823  //   ll      oldval,0(alignedaddr)
1824  //   and     newval,incr2,mask
1825  //   and     maskedoldval0,oldval,mask2
1826  //   or      storeval,maskedoldval0,newval
1827  //   sc      success,storeval,0(alignedaddr)
1828  //   beq     success,$0,loopMBB
1829
1830  BB = loopMBB;
1831  BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1832  if (Nand) {
1833    //  and andres, oldval, incr2
1834    //  nor binopres, $0, andres
1835    //  and newval, binopres, mask
1836    BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1837    BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
1838      .addReg(Mips::ZERO).addReg(AndRes);
1839    BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1840  } else if (BinOpcode) {
1841    //  <binop> binopres, oldval, incr2
1842    //  and newval, binopres, mask
1843    BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1844    BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1845  } else {// atomic.swap
1846    //  and newval, incr2, mask
1847    BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1848  }
1849
1850  BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1851    .addReg(OldVal).addReg(Mask2);
1852  BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1853    .addReg(MaskedOldVal0).addReg(NewVal);
1854  BuildMI(BB, dl, TII->get(SC), Success)
1855    .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1856  BuildMI(BB, dl, TII->get(Mips::BEQ))
1857    .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1858
1859  //  sinkMBB:
1860  //    and     maskedoldval1,oldval,mask
1861  //    srl     srlres,maskedoldval1,shiftamt
1862  //    sll     sllres,srlres,24
1863  //    sra     dest,sllres,24
1864  BB = sinkMBB;
1865  int64_t ShiftImm = (Size == 1) ? 24 : 16;
1866
1867  BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1868    .addReg(OldVal).addReg(Mask);
1869  BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1870      .addReg(ShiftAmt).addReg(MaskedOldVal1);
1871  BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1872      .addReg(SrlRes).addImm(ShiftImm);
1873  BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
1874      .addReg(SllRes).addImm(ShiftImm);
1875
1876  MI->eraseFromParent();   // The instruction is gone now.
1877
1878  return exitMBB;
1879}
1880
1881MachineBasicBlock *
1882MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
1883                                      MachineBasicBlock *BB,
1884                                      unsigned Size) const {
1885  assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1886
1887  MachineFunction *MF = BB->getParent();
1888  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1889  const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1890  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1891  DebugLoc dl = MI->getDebugLoc();
1892  unsigned LL, SC, ZERO, BNE, BEQ;
1893
1894  if (Size == 4) {
1895    LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1896    SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1897    ZERO = Mips::ZERO;
1898    BNE = Mips::BNE;
1899    BEQ = Mips::BEQ;
1900  }
1901  else {
1902    LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1903    SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1904    ZERO = Mips::ZERO_64;
1905    BNE = Mips::BNE64;
1906    BEQ = Mips::BEQ64;
1907  }
1908
1909  unsigned Dest    = MI->getOperand(0).getReg();
1910  unsigned Ptr     = MI->getOperand(1).getReg();
1911  unsigned OldVal  = MI->getOperand(2).getReg();
1912  unsigned NewVal  = MI->getOperand(3).getReg();
1913
1914  unsigned Success = RegInfo.createVirtualRegister(RC);
1915
1916  // insert new blocks after the current block
1917  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1918  MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1919  MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1920  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1921  MachineFunction::iterator It = BB;
1922  ++It;
1923  MF->insert(It, loop1MBB);
1924  MF->insert(It, loop2MBB);
1925  MF->insert(It, exitMBB);
1926
1927  // Transfer the remainder of BB and its successor edges to exitMBB.
1928  exitMBB->splice(exitMBB->begin(), BB,
1929                  llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1930  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1931
1932  //  thisMBB:
1933  //    ...
1934  //    fallthrough --> loop1MBB
1935  BB->addSuccessor(loop1MBB);
1936  loop1MBB->addSuccessor(exitMBB);
1937  loop1MBB->addSuccessor(loop2MBB);
1938  loop2MBB->addSuccessor(loop1MBB);
1939  loop2MBB->addSuccessor(exitMBB);
1940
1941  // loop1MBB:
1942  //   ll dest, 0(ptr)
1943  //   bne dest, oldval, exitMBB
1944  BB = loop1MBB;
1945  BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1946  BuildMI(BB, dl, TII->get(BNE))
1947    .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1948
1949  // loop2MBB:
1950  //   sc success, newval, 0(ptr)
1951  //   beq success, $0, loop1MBB
1952  BB = loop2MBB;
1953  BuildMI(BB, dl, TII->get(SC), Success)
1954    .addReg(NewVal).addReg(Ptr).addImm(0);
1955  BuildMI(BB, dl, TII->get(BEQ))
1956    .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1957
1958  MI->eraseFromParent();   // The instruction is gone now.
1959
1960  return exitMBB;
1961}
1962
1963MachineBasicBlock *
1964MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
1965                                              MachineBasicBlock *BB,
1966                                              unsigned Size) const {
1967  assert((Size == 1 || Size == 2) &&
1968      "Unsupported size for EmitAtomicCmpSwapPartial.");
1969
1970  MachineFunction *MF = BB->getParent();
1971  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1972  const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1973  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1974  DebugLoc dl = MI->getDebugLoc();
1975  unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1976  unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1977
1978  unsigned Dest    = MI->getOperand(0).getReg();
1979  unsigned Ptr     = MI->getOperand(1).getReg();
1980  unsigned CmpVal  = MI->getOperand(2).getReg();
1981  unsigned NewVal  = MI->getOperand(3).getReg();
1982
1983  unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1984  unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1985  unsigned Mask = RegInfo.createVirtualRegister(RC);
1986  unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1987  unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1988  unsigned OldVal = RegInfo.createVirtualRegister(RC);
1989  unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1990  unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1991  unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1992  unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1993  unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1994  unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1995  unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1996  unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1997  unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1998  unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1999  unsigned SllRes = RegInfo.createVirtualRegister(RC);
2000  unsigned Success = RegInfo.createVirtualRegister(RC);
2001
2002  // insert new blocks after the current block
2003  const BasicBlock *LLVM_BB = BB->getBasicBlock();
2004  MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
2005  MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
2006  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
2007  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
2008  MachineFunction::iterator It = BB;
2009  ++It;
2010  MF->insert(It, loop1MBB);
2011  MF->insert(It, loop2MBB);
2012  MF->insert(It, sinkMBB);
2013  MF->insert(It, exitMBB);
2014
2015  // Transfer the remainder of BB and its successor edges to exitMBB.
2016  exitMBB->splice(exitMBB->begin(), BB,
2017                  llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
2018  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
2019
2020  BB->addSuccessor(loop1MBB);
2021  loop1MBB->addSuccessor(sinkMBB);
2022  loop1MBB->addSuccessor(loop2MBB);
2023  loop2MBB->addSuccessor(loop1MBB);
2024  loop2MBB->addSuccessor(sinkMBB);
2025  sinkMBB->addSuccessor(exitMBB);
2026
2027  // FIXME: computation of newval2 can be moved to loop2MBB.
2028  //  thisMBB:
2029  //    addiu   masklsb2,$0,-4                # 0xfffffffc
2030  //    and     alignedaddr,ptr,masklsb2
2031  //    andi    ptrlsb2,ptr,3
2032  //    sll     shiftamt,ptrlsb2,3
2033  //    ori     maskupper,$0,255               # 0xff
2034  //    sll     mask,maskupper,shiftamt
2035  //    nor     mask2,$0,mask
2036  //    andi    maskedcmpval,cmpval,255
2037  //    sll     shiftedcmpval,maskedcmpval,shiftamt
2038  //    andi    maskednewval,newval,255
2039  //    sll     shiftednewval,maskednewval,shiftamt
2040  int64_t MaskImm = (Size == 1) ? 255 : 65535;
2041  BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
2042    .addReg(Mips::ZERO).addImm(-4);
2043  BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
2044    .addReg(Ptr).addReg(MaskLSB2);
2045  BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
2046  BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
2047  BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
2048    .addReg(Mips::ZERO).addImm(MaskImm);
2049  BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
2050    .addReg(ShiftAmt).addReg(MaskUpper);
2051  BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
2052  BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
2053    .addReg(CmpVal).addImm(MaskImm);
2054  BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
2055    .addReg(ShiftAmt).addReg(MaskedCmpVal);
2056  BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
2057    .addReg(NewVal).addImm(MaskImm);
2058  BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
2059    .addReg(ShiftAmt).addReg(MaskedNewVal);
2060
2061  //  loop1MBB:
2062  //    ll      oldval,0(alginedaddr)
2063  //    and     maskedoldval0,oldval,mask
2064  //    bne     maskedoldval0,shiftedcmpval,sinkMBB
2065  BB = loop1MBB;
2066  BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
2067  BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
2068    .addReg(OldVal).addReg(Mask);
2069  BuildMI(BB, dl, TII->get(Mips::BNE))
2070    .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
2071
2072  //  loop2MBB:
2073  //    and     maskedoldval1,oldval,mask2
2074  //    or      storeval,maskedoldval1,shiftednewval
2075  //    sc      success,storeval,0(alignedaddr)
2076  //    beq     success,$0,loop1MBB
2077  BB = loop2MBB;
2078  BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
2079    .addReg(OldVal).addReg(Mask2);
2080  BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
2081    .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
2082  BuildMI(BB, dl, TII->get(SC), Success)
2083      .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
2084  BuildMI(BB, dl, TII->get(Mips::BEQ))
2085      .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
2086
2087  //  sinkMBB:
2088  //    srl     srlres,maskedoldval0,shiftamt
2089  //    sll     sllres,srlres,24
2090  //    sra     dest,sllres,24
2091  BB = sinkMBB;
2092  int64_t ShiftImm = (Size == 1) ? 24 : 16;
2093
2094  BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
2095      .addReg(ShiftAmt).addReg(MaskedOldVal0);
2096  BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
2097      .addReg(SrlRes).addImm(ShiftImm);
2098  BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
2099      .addReg(SllRes).addImm(ShiftImm);
2100
2101  MI->eraseFromParent();   // The instruction is gone now.
2102
2103  return exitMBB;
2104}
2105
2106//===----------------------------------------------------------------------===//
2107//  Misc Lower Operation implementation
2108//===----------------------------------------------------------------------===//
2109SDValue MipsTargetLowering::
2110LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
2111{
2112  // The first operand is the chain, the second is the condition, the third is
2113  // the block to branch to if the condition is true.
2114  SDValue Chain = Op.getOperand(0);
2115  SDValue Dest = Op.getOperand(2);
2116  DebugLoc dl = Op.getDebugLoc();
2117
2118  SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
2119
2120  // Return if flag is not set by a floating point comparison.
2121  if (CondRes.getOpcode() != MipsISD::FPCmp)
2122    return Op;
2123
2124  SDValue CCNode  = CondRes.getOperand(2);
2125  Mips::CondCode CC =
2126    (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
2127  SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
2128
2129  return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
2130                     Dest, CondRes);
2131}
2132
2133SDValue MipsTargetLowering::
2134LowerSELECT(SDValue Op, SelectionDAG &DAG) const
2135{
2136  SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
2137
2138  // Return if flag is not set by a floating point comparison.
2139  if (Cond.getOpcode() != MipsISD::FPCmp)
2140    return Op;
2141
2142  return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
2143                      Op.getDebugLoc());
2144}
2145
2146SDValue MipsTargetLowering::
2147LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
2148{
2149  DebugLoc DL = Op.getDebugLoc();
2150  EVT Ty = Op.getOperand(0).getValueType();
2151  SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty),
2152                             Op.getOperand(0), Op.getOperand(1),
2153                             Op.getOperand(4));
2154
2155  return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
2156                     Op.getOperand(3));
2157}
2158
2159SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2160  SDValue Cond = CreateFPCmp(DAG, Op);
2161
2162  assert(Cond.getOpcode() == MipsISD::FPCmp &&
2163         "Floating point operand expected.");
2164
2165  SDValue True  = DAG.getConstant(1, MVT::i32);
2166  SDValue False = DAG.getConstant(0, MVT::i32);
2167
2168  return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc());
2169}
2170
2171SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
2172                                               SelectionDAG &DAG) const {
2173  // FIXME there isn't actually debug info here
2174  DebugLoc dl = Op.getDebugLoc();
2175  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2176
2177  if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
2178    const MipsTargetObjectFile &TLOF =
2179      (const MipsTargetObjectFile&)getObjFileLowering();
2180
2181    // %gp_rel relocation
2182    if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
2183      SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
2184                                              MipsII::MO_GPREL);
2185      SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl,
2186                                      DAG.getVTList(MVT::i32), &GA, 1);
2187      SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
2188      return DAG.getNode(ISD::ADD, dl, MVT::i32, GPReg, GPRelNode);
2189    }
2190
2191    // %hi/%lo relocation
2192    return getAddrNonPIC(Op, DAG);
2193  }
2194
2195  if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
2196    return getAddrLocal(Op, DAG, HasMips64);
2197
2198  if (LargeGOT)
2199    return getAddrGlobalLargeGOT(Op, DAG, MipsII::MO_GOT_HI16,
2200                                 MipsII::MO_GOT_LO16);
2201
2202  return getAddrGlobal(Op, DAG,
2203                       HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16);
2204}
2205
2206SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
2207                                              SelectionDAG &DAG) const {
2208  if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
2209    return getAddrNonPIC(Op, DAG);
2210
2211  return getAddrLocal(Op, DAG, HasMips64);
2212}
2213
2214SDValue MipsTargetLowering::
2215LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
2216{
2217  // If the relocation model is PIC, use the General Dynamic TLS Model or
2218  // Local Dynamic TLS model, otherwise use the Initial Exec or
2219  // Local Exec TLS Model.
2220
2221  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2222  DebugLoc dl = GA->getDebugLoc();
2223  const GlobalValue *GV = GA->getGlobal();
2224  EVT PtrVT = getPointerTy();
2225
2226  TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2227
2228  if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2229    // General Dynamic and Local Dynamic TLS Model.
2230    unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
2231                                                      : MipsII::MO_TLSGD;
2232
2233    SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag);
2234    SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT,
2235                                   GetGlobalReg(DAG, PtrVT), TGA);
2236    unsigned PtrSize = PtrVT.getSizeInBits();
2237    IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
2238
2239    SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
2240
2241    ArgListTy Args;
2242    ArgListEntry Entry;
2243    Entry.Node = Argument;
2244    Entry.Ty = PtrTy;
2245    Args.push_back(Entry);
2246
2247    TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
2248                  false, false, false, false, 0, CallingConv::C,
2249                  /*isTailCall=*/false, /*doesNotRet=*/false,
2250                  /*isReturnValueUsed=*/true,
2251                  TlsGetAddr, Args, DAG, dl);
2252    std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2253
2254    SDValue Ret = CallResult.first;
2255
2256    if (model != TLSModel::LocalDynamic)
2257      return Ret;
2258
2259    SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2260                                               MipsII::MO_DTPREL_HI);
2261    SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
2262    SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2263                                               MipsII::MO_DTPREL_LO);
2264    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
2265    SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret);
2266    return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo);
2267  }
2268
2269  SDValue Offset;
2270  if (model == TLSModel::InitialExec) {
2271    // Initial Exec TLS Model
2272    SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2273                                             MipsII::MO_GOTTPREL);
2274    TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
2275                      TGA);
2276    Offset = DAG.getLoad(PtrVT, dl,
2277                         DAG.getEntryNode(), TGA, MachinePointerInfo(),
2278                         false, false, false, 0);
2279  } else {
2280    // Local Exec TLS Model
2281    assert(model == TLSModel::LocalExec);
2282    SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2283                                               MipsII::MO_TPREL_HI);
2284    SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2285                                               MipsII::MO_TPREL_LO);
2286    SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
2287    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
2288    Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
2289  }
2290
2291  SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
2292  return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2293}
2294
2295SDValue MipsTargetLowering::
2296LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
2297{
2298  if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
2299    return getAddrNonPIC(Op, DAG);
2300
2301  return getAddrLocal(Op, DAG, HasMips64);
2302}
2303
2304SDValue MipsTargetLowering::
2305LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
2306{
2307  // gp_rel relocation
2308  // FIXME: we should reference the constant pool using small data sections,
2309  // but the asm printer currently doesn't support this feature without
2310  // hacking it. This feature should come soon so we can uncomment the
2311  // stuff below.
2312  //if (IsInSmallSection(C->getType())) {
2313  //  SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
2314  //  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
2315  //  ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
2316
2317  if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
2318    return getAddrNonPIC(Op, DAG);
2319
2320  return getAddrLocal(Op, DAG, HasMips64);
2321}
2322
2323SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2324  MachineFunction &MF = DAG.getMachineFunction();
2325  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2326
2327  DebugLoc dl = Op.getDebugLoc();
2328  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2329                                 getPointerTy());
2330
2331  // vastart just stores the address of the VarArgsFrameIndex slot into the
2332  // memory location argument.
2333  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2334  return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
2335                      MachinePointerInfo(SV), false, false, 0);
2336}
2337
2338static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2339  EVT TyX = Op.getOperand(0).getValueType();
2340  EVT TyY = Op.getOperand(1).getValueType();
2341  SDValue Const1 = DAG.getConstant(1, MVT::i32);
2342  SDValue Const31 = DAG.getConstant(31, MVT::i32);
2343  DebugLoc DL = Op.getDebugLoc();
2344  SDValue Res;
2345
2346  // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2347  // to i32.
2348  SDValue X = (TyX == MVT::f32) ?
2349    DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2350    DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2351                Const1);
2352  SDValue Y = (TyY == MVT::f32) ?
2353    DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2354    DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2355                Const1);
2356
2357  if (HasR2) {
2358    // ext  E, Y, 31, 1  ; extract bit31 of Y
2359    // ins  X, E, 31, 1  ; insert extracted bit at bit31 of X
2360    SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2361    Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2362  } else {
2363    // sll SllX, X, 1
2364    // srl SrlX, SllX, 1
2365    // srl SrlY, Y, 31
2366    // sll SllY, SrlX, 31
2367    // or  Or, SrlX, SllY
2368    SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2369    SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2370    SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2371    SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2372    Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2373  }
2374
2375  if (TyX == MVT::f32)
2376    return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2377
2378  SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2379                             Op.getOperand(0), DAG.getConstant(0, MVT::i32));
2380  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2381}
2382
2383static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2384  unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2385  unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2386  EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2387  SDValue Const1 = DAG.getConstant(1, MVT::i32);
2388  DebugLoc DL = Op.getDebugLoc();
2389
2390  // Bitcast to integer nodes.
2391  SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2392  SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2393
2394  if (HasR2) {
2395    // ext  E, Y, width(Y) - 1, 1  ; extract bit width(Y)-1 of Y
2396    // ins  X, E, width(X) - 1, 1  ; insert extracted bit at bit width(X)-1 of X
2397    SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2398                            DAG.getConstant(WidthY - 1, MVT::i32), Const1);
2399
2400    if (WidthX > WidthY)
2401      E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2402    else if (WidthY > WidthX)
2403      E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2404
2405    SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2406                            DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
2407    return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2408  }
2409
2410  // (d)sll SllX, X, 1
2411  // (d)srl SrlX, SllX, 1
2412  // (d)srl SrlY, Y, width(Y)-1
2413  // (d)sll SllY, SrlX, width(Y)-1
2414  // or     Or, SrlX, SllY
2415  SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2416  SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2417  SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2418                             DAG.getConstant(WidthY - 1, MVT::i32));
2419
2420  if (WidthX > WidthY)
2421    SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2422  else if (WidthY > WidthX)
2423    SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2424
2425  SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2426                             DAG.getConstant(WidthX - 1, MVT::i32));
2427  SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2428  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2429}
2430
2431SDValue
2432MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2433  if (Subtarget->hasMips64())
2434    return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
2435
2436  return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
2437}
2438
2439static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2440  SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
2441  DebugLoc DL = Op.getDebugLoc();
2442
2443  // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2444  // to i32.
2445  SDValue X = (Op.getValueType() == MVT::f32) ?
2446    DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2447    DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2448                Const1);
2449
2450  // Clear MSB.
2451  if (HasR2)
2452    Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
2453                      DAG.getRegister(Mips::ZERO, MVT::i32),
2454                      DAG.getConstant(31, MVT::i32), Const1, X);
2455  else {
2456    SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2457    Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2458  }
2459
2460  if (Op.getValueType() == MVT::f32)
2461    return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
2462
2463  SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2464                             Op.getOperand(0), DAG.getConstant(0, MVT::i32));
2465  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2466}
2467
2468static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2469  SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
2470  DebugLoc DL = Op.getDebugLoc();
2471
2472  // Bitcast to integer node.
2473  SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
2474
2475  // Clear MSB.
2476  if (HasR2)
2477    Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
2478                      DAG.getRegister(Mips::ZERO_64, MVT::i64),
2479                      DAG.getConstant(63, MVT::i32), Const1, X);
2480  else {
2481    SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
2482    Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2483  }
2484
2485  return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
2486}
2487
2488SDValue
2489MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
2490  if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
2491    return LowerFABS64(Op, DAG, Subtarget->hasMips32r2());
2492
2493  return LowerFABS32(Op, DAG, Subtarget->hasMips32r2());
2494}
2495
2496SDValue MipsTargetLowering::
2497LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2498  // check the depth
2499  assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2500         "Frame address can only be determined for current frame.");
2501
2502  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2503  MFI->setFrameAddressIsTaken(true);
2504  EVT VT = Op.getValueType();
2505  DebugLoc dl = Op.getDebugLoc();
2506  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2507                                         IsN64 ? Mips::FP_64 : Mips::FP, VT);
2508  return FrameAddr;
2509}
2510
2511SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op,
2512                                            SelectionDAG &DAG) const {
2513  // check the depth
2514  assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2515         "Return address can be determined only for current frame.");
2516
2517  MachineFunction &MF = DAG.getMachineFunction();
2518  MachineFrameInfo *MFI = MF.getFrameInfo();
2519  MVT VT = Op.getSimpleValueType();
2520  unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
2521  MFI->setReturnAddressIsTaken(true);
2522
2523  // Return RA, which contains the return address. Mark it an implicit live-in.
2524  unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2525  return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT);
2526}
2527
2528// An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2529// generated from __builtin_eh_return (offset, handler)
2530// The effect of this is to adjust the stack pointer by "offset"
2531// and then branch to "handler".
2532SDValue MipsTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2533                                                                     const {
2534  MachineFunction &MF = DAG.getMachineFunction();
2535  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2536
2537  MipsFI->setCallsEhReturn();
2538  SDValue Chain     = Op.getOperand(0);
2539  SDValue Offset    = Op.getOperand(1);
2540  SDValue Handler   = Op.getOperand(2);
2541  DebugLoc DL       = Op.getDebugLoc();
2542  EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
2543
2544  // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2545  // EH_RETURN nodes, so that instructions are emitted back-to-back.
2546  unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1;
2547  unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0;
2548  Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2549  Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2550  return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2551                     DAG.getRegister(OffsetReg, Ty),
2552                     DAG.getRegister(AddrReg, getPointerTy()),
2553                     Chain.getValue(1));
2554}
2555
2556// TODO: set SType according to the desired memory barrier behavior.
2557SDValue
2558MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const {
2559  unsigned SType = 0;
2560  DebugLoc dl = Op.getDebugLoc();
2561  return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2562                     DAG.getConstant(SType, MVT::i32));
2563}
2564
2565SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
2566                                              SelectionDAG &DAG) const {
2567  // FIXME: Need pseudo-fence for 'singlethread' fences
2568  // FIXME: Set SType for weaker fences where supported/appropriate.
2569  unsigned SType = 0;
2570  DebugLoc dl = Op.getDebugLoc();
2571  return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2572                     DAG.getConstant(SType, MVT::i32));
2573}
2574
2575SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op,
2576                                                SelectionDAG &DAG) const {
2577  DebugLoc DL = Op.getDebugLoc();
2578  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2579  SDValue Shamt = Op.getOperand(2);
2580
2581  // if shamt < 32:
2582  //  lo = (shl lo, shamt)
2583  //  hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2584  // else:
2585  //  lo = 0
2586  //  hi = (shl lo, shamt[4:0])
2587  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2588                            DAG.getConstant(-1, MVT::i32));
2589  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
2590                                      DAG.getConstant(1, MVT::i32));
2591  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
2592                                     Not);
2593  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
2594  SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2595  SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
2596  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2597                             DAG.getConstant(0x20, MVT::i32));
2598  Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2599                   DAG.getConstant(0, MVT::i32), ShiftLeftLo);
2600  Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
2601
2602  SDValue Ops[2] = {Lo, Hi};
2603  return DAG.getMergeValues(Ops, 2, DL);
2604}
2605
2606SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2607                                                 bool IsSRA) const {
2608  DebugLoc DL = Op.getDebugLoc();
2609  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2610  SDValue Shamt = Op.getOperand(2);
2611
2612  // if shamt < 32:
2613  //  lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2614  //  if isSRA:
2615  //    hi = (sra hi, shamt)
2616  //  else:
2617  //    hi = (srl hi, shamt)
2618  // else:
2619  //  if isSRA:
2620  //   lo = (sra hi, shamt[4:0])
2621  //   hi = (sra hi, 31)
2622  //  else:
2623  //   lo = (srl hi, shamt[4:0])
2624  //   hi = 0
2625  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2626                            DAG.getConstant(-1, MVT::i32));
2627  SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
2628                                     DAG.getConstant(1, MVT::i32));
2629  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
2630  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
2631  SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2632  SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2633                                     Hi, Shamt);
2634  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2635                             DAG.getConstant(0x20, MVT::i32));
2636  SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
2637                                DAG.getConstant(31, MVT::i32));
2638  Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
2639  Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2640                   IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
2641                   ShiftRightHi);
2642
2643  SDValue Ops[2] = {Lo, Hi};
2644  return DAG.getMergeValues(Ops, 2, DL);
2645}
2646
2647static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2648                            SDValue Chain, SDValue Src, unsigned Offset) {
2649  SDValue Ptr = LD->getBasePtr();
2650  EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2651  EVT BasePtrVT = Ptr.getValueType();
2652  DebugLoc DL = LD->getDebugLoc();
2653  SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2654
2655  if (Offset)
2656    Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2657                      DAG.getConstant(Offset, BasePtrVT));
2658
2659  SDValue Ops[] = { Chain, Ptr, Src };
2660  return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2661                                 LD->getMemOperand());
2662}
2663
2664// Expand an unaligned 32 or 64-bit integer load node.
2665SDValue MipsTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2666  LoadSDNode *LD = cast<LoadSDNode>(Op);
2667  EVT MemVT = LD->getMemoryVT();
2668
2669  // Return if load is aligned or if MemVT is neither i32 nor i64.
2670  if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2671      ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2672    return SDValue();
2673
2674  bool IsLittle = Subtarget->isLittle();
2675  EVT VT = Op.getValueType();
2676  ISD::LoadExtType ExtType = LD->getExtensionType();
2677  SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2678
2679  assert((VT == MVT::i32) || (VT == MVT::i64));
2680
2681  // Expand
2682  //  (set dst, (i64 (load baseptr)))
2683  // to
2684  //  (set tmp, (ldl (add baseptr, 7), undef))
2685  //  (set dst, (ldr baseptr, tmp))
2686  if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2687    SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2688                               IsLittle ? 7 : 0);
2689    return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2690                        IsLittle ? 0 : 7);
2691  }
2692
2693  SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2694                             IsLittle ? 3 : 0);
2695  SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2696                             IsLittle ? 0 : 3);
2697
2698  // Expand
2699  //  (set dst, (i32 (load baseptr))) or
2700  //  (set dst, (i64 (sextload baseptr))) or
2701  //  (set dst, (i64 (extload baseptr)))
2702  // to
2703  //  (set tmp, (lwl (add baseptr, 3), undef))
2704  //  (set dst, (lwr baseptr, tmp))
2705  if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2706      (ExtType == ISD::EXTLOAD))
2707    return LWR;
2708
2709  assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2710
2711  // Expand
2712  //  (set dst, (i64 (zextload baseptr)))
2713  // to
2714  //  (set tmp0, (lwl (add baseptr, 3), undef))
2715  //  (set tmp1, (lwr baseptr, tmp0))
2716  //  (set tmp2, (shl tmp1, 32))
2717  //  (set dst, (srl tmp2, 32))
2718  DebugLoc DL = LD->getDebugLoc();
2719  SDValue Const32 = DAG.getConstant(32, MVT::i32);
2720  SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2721  SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2722  SDValue Ops[] = { SRL, LWR.getValue(1) };
2723  return DAG.getMergeValues(Ops, 2, DL);
2724}
2725
2726static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2727                             SDValue Chain, unsigned Offset) {
2728  SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2729  EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2730  DebugLoc DL = SD->getDebugLoc();
2731  SDVTList VTList = DAG.getVTList(MVT::Other);
2732
2733  if (Offset)
2734    Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2735                      DAG.getConstant(Offset, BasePtrVT));
2736
2737  SDValue Ops[] = { Chain, Value, Ptr };
2738  return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2739                                 SD->getMemOperand());
2740}
2741
2742// Expand an unaligned 32 or 64-bit integer store node.
2743SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2744  StoreSDNode *SD = cast<StoreSDNode>(Op);
2745  EVT MemVT = SD->getMemoryVT();
2746
2747  // Return if store is aligned or if MemVT is neither i32 nor i64.
2748  if ((SD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2749      ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2750    return SDValue();
2751
2752  bool IsLittle = Subtarget->isLittle();
2753  SDValue Value = SD->getValue(), Chain = SD->getChain();
2754  EVT VT = Value.getValueType();
2755
2756  // Expand
2757  //  (store val, baseptr) or
2758  //  (truncstore val, baseptr)
2759  // to
2760  //  (swl val, (add baseptr, 3))
2761  //  (swr val, baseptr)
2762  if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2763    SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain,
2764                                IsLittle ? 3 : 0);
2765    return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2766  }
2767
2768  assert(VT == MVT::i64);
2769
2770  // Expand
2771  //  (store val, baseptr)
2772  // to
2773  //  (sdl val, (add baseptr, 7))
2774  //  (sdr val, baseptr)
2775  SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2776  return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2777}
2778
2779// This function expands mips intrinsic nodes which have 64-bit input operands
2780// or output values.
2781//
2782// out64 = intrinsic-node in64
2783// =>
2784// lo = copy (extract-element (in64, 0))
2785// hi = copy (extract-element (in64, 1))
2786// mips-specific-node
2787// v0 = copy lo
2788// v1 = copy hi
2789// out64 = merge-values (v0, v1)
2790//
2791static SDValue LowerDSPIntr(SDValue Op, SelectionDAG &DAG,
2792                            unsigned Opc, bool HasI64In, bool HasI64Out) {
2793  DebugLoc DL = Op.getDebugLoc();
2794  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
2795  SDValue Chain = HasChainIn ? Op->getOperand(0) : DAG.getEntryNode();
2796  SmallVector<SDValue, 3> Ops;
2797
2798  if (HasI64In) {
2799    SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
2800                               Op->getOperand(1 + HasChainIn),
2801                               DAG.getConstant(0, MVT::i32));
2802    SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
2803                               Op->getOperand(1 + HasChainIn),
2804                               DAG.getConstant(1, MVT::i32));
2805
2806    Chain = DAG.getCopyToReg(Chain, DL, Mips::LO, InLo, SDValue());
2807    Chain = DAG.getCopyToReg(Chain, DL, Mips::HI, InHi, Chain.getValue(1));
2808
2809    Ops.push_back(Chain);
2810    Ops.append(Op->op_begin() + HasChainIn + 2, Op->op_end());
2811    Ops.push_back(Chain.getValue(1));
2812  } else {
2813    Ops.push_back(Chain);
2814    Ops.append(Op->op_begin() + HasChainIn + 1, Op->op_end());
2815  }
2816
2817  if (!HasI64Out)
2818    return DAG.getNode(Opc, DL, Op->value_begin(), Op->getNumValues(),
2819                       Ops.begin(), Ops.size());
2820
2821  SDValue Intr = DAG.getNode(Opc, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2822                             Ops.begin(), Ops.size());
2823  SDValue OutLo = DAG.getCopyFromReg(Intr.getValue(0), DL, Mips::LO, MVT::i32,
2824                                     Intr.getValue(1));
2825  SDValue OutHi = DAG.getCopyFromReg(OutLo.getValue(1), DL, Mips::HI, MVT::i32,
2826                                     OutLo.getValue(2));
2827  SDValue Out = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, OutLo, OutHi);
2828
2829  if (!HasChainIn)
2830    return Out;
2831
2832  SDValue Vals[] = { Out, OutHi.getValue(1) };
2833  return DAG.getMergeValues(Vals, 2, DL);
2834}
2835
2836SDValue MipsTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2837                                                    SelectionDAG &DAG) const {
2838  switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
2839  default:
2840    return SDValue();
2841  case Intrinsic::mips_shilo:
2842    return LowerDSPIntr(Op, DAG, MipsISD::SHILO, true, true);
2843  case Intrinsic::mips_dpau_h_qbl:
2844    return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL, true, true);
2845  case Intrinsic::mips_dpau_h_qbr:
2846    return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR, true, true);
2847  case Intrinsic::mips_dpsu_h_qbl:
2848    return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL, true, true);
2849  case Intrinsic::mips_dpsu_h_qbr:
2850    return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR, true, true);
2851  case Intrinsic::mips_dpa_w_ph:
2852    return LowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH, true, true);
2853  case Intrinsic::mips_dps_w_ph:
2854    return LowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH, true, true);
2855  case Intrinsic::mips_dpax_w_ph:
2856    return LowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH, true, true);
2857  case Intrinsic::mips_dpsx_w_ph:
2858    return LowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH, true, true);
2859  case Intrinsic::mips_mulsa_w_ph:
2860    return LowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH, true, true);
2861  case Intrinsic::mips_mult:
2862    return LowerDSPIntr(Op, DAG, MipsISD::MULT, false, true);
2863  case Intrinsic::mips_multu:
2864    return LowerDSPIntr(Op, DAG, MipsISD::MULTU, false, true);
2865  case Intrinsic::mips_madd:
2866    return LowerDSPIntr(Op, DAG, MipsISD::MADD_DSP, true, true);
2867  case Intrinsic::mips_maddu:
2868    return LowerDSPIntr(Op, DAG, MipsISD::MADDU_DSP, true, true);
2869  case Intrinsic::mips_msub:
2870    return LowerDSPIntr(Op, DAG, MipsISD::MSUB_DSP, true, true);
2871  case Intrinsic::mips_msubu:
2872    return LowerDSPIntr(Op, DAG, MipsISD::MSUBU_DSP, true, true);
2873  }
2874}
2875
2876SDValue MipsTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
2877                                                   SelectionDAG &DAG) const {
2878  switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) {
2879  default:
2880    return SDValue();
2881  case Intrinsic::mips_extp:
2882    return LowerDSPIntr(Op, DAG, MipsISD::EXTP, true, false);
2883  case Intrinsic::mips_extpdp:
2884    return LowerDSPIntr(Op, DAG, MipsISD::EXTPDP, true, false);
2885  case Intrinsic::mips_extr_w:
2886    return LowerDSPIntr(Op, DAG, MipsISD::EXTR_W, true, false);
2887  case Intrinsic::mips_extr_r_w:
2888    return LowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W, true, false);
2889  case Intrinsic::mips_extr_rs_w:
2890    return LowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W, true, false);
2891  case Intrinsic::mips_extr_s_h:
2892    return LowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H, true, false);
2893  case Intrinsic::mips_mthlip:
2894    return LowerDSPIntr(Op, DAG, MipsISD::MTHLIP, true, true);
2895  case Intrinsic::mips_mulsaq_s_w_ph:
2896    return LowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH, true, true);
2897  case Intrinsic::mips_maq_s_w_phl:
2898    return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL, true, true);
2899  case Intrinsic::mips_maq_s_w_phr:
2900    return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR, true, true);
2901  case Intrinsic::mips_maq_sa_w_phl:
2902    return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL, true, true);
2903  case Intrinsic::mips_maq_sa_w_phr:
2904    return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR, true, true);
2905  case Intrinsic::mips_dpaq_s_w_ph:
2906    return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH, true, true);
2907  case Intrinsic::mips_dpsq_s_w_ph:
2908    return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH, true, true);
2909  case Intrinsic::mips_dpaq_sa_l_w:
2910    return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W, true, true);
2911  case Intrinsic::mips_dpsq_sa_l_w:
2912    return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W, true, true);
2913  case Intrinsic::mips_dpaqx_s_w_ph:
2914    return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH, true, true);
2915  case Intrinsic::mips_dpaqx_sa_w_ph:
2916    return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH, true, true);
2917  case Intrinsic::mips_dpsqx_s_w_ph:
2918    return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH, true, true);
2919  case Intrinsic::mips_dpsqx_sa_w_ph:
2920    return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH, true, true);
2921  }
2922}
2923
2924SDValue MipsTargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
2925  if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2926      || cast<ConstantSDNode>
2927        (Op->getOperand(0).getOperand(0))->getZExtValue() != 0
2928      || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2929    return SDValue();
2930
2931  // The pattern
2932  //   (add (frameaddr 0), (frame_to_args_offset))
2933  // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
2934  //   (add FrameObject, 0)
2935  // where FrameObject is a fixed StackObject with offset 0 which points to
2936  // the old stack pointer.
2937  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2938  EVT ValTy = Op->getValueType(0);
2939  int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2940  SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
2941  return DAG.getNode(ISD::ADD, Op->getDebugLoc(), ValTy, InArgsAddr,
2942                     DAG.getConstant(0, ValTy));
2943}
2944
2945//===----------------------------------------------------------------------===//
2946//                      Calling Convention Implementation
2947//===----------------------------------------------------------------------===//
2948
2949//===----------------------------------------------------------------------===//
2950// TODO: Implement a generic logic using tblgen that can support this.
2951// Mips O32 ABI rules:
2952// ---
2953// i32 - Passed in A0, A1, A2, A3 and stack
2954// f32 - Only passed in f32 registers if no int reg has been used yet to hold
2955//       an argument. Otherwise, passed in A1, A2, A3 and stack.
2956// f64 - Only passed in two aliased f32 registers if no int reg has been used
2957//       yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2958//       not used, it must be shadowed. If only A3 is avaiable, shadow it and
2959//       go to stack.
2960//
2961//  For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2962//===----------------------------------------------------------------------===//
2963
2964static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
2965                       MVT LocVT, CCValAssign::LocInfo LocInfo,
2966                       ISD::ArgFlagsTy ArgFlags, CCState &State) {
2967
2968  static const unsigned IntRegsSize=4, FloatRegsSize=2;
2969
2970  static const uint16_t IntRegs[] = {
2971      Mips::A0, Mips::A1, Mips::A2, Mips::A3
2972  };
2973  static const uint16_t F32Regs[] = {
2974      Mips::F12, Mips::F14
2975  };
2976  static const uint16_t F64Regs[] = {
2977      Mips::D6, Mips::D7
2978  };
2979
2980  // Do not process byval args here.
2981  if (ArgFlags.isByVal())
2982    return true;
2983
2984  // Promote i8 and i16
2985  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2986    LocVT = MVT::i32;
2987    if (ArgFlags.isSExt())
2988      LocInfo = CCValAssign::SExt;
2989    else if (ArgFlags.isZExt())
2990      LocInfo = CCValAssign::ZExt;
2991    else
2992      LocInfo = CCValAssign::AExt;
2993  }
2994
2995  unsigned Reg;
2996
2997  // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2998  // is true: function is vararg, argument is 3rd or higher, there is previous
2999  // argument which is not f32 or f64.
3000  bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
3001      || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
3002  unsigned OrigAlign = ArgFlags.getOrigAlign();
3003  bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
3004
3005  if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
3006    Reg = State.AllocateReg(IntRegs, IntRegsSize);
3007    // If this is the first part of an i64 arg,
3008    // the allocated register must be either A0 or A2.
3009    if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
3010      Reg = State.AllocateReg(IntRegs, IntRegsSize);
3011    LocVT = MVT::i32;
3012  } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
3013    // Allocate int register and shadow next int register. If first
3014    // available register is Mips::A1 or Mips::A3, shadow it too.
3015    Reg = State.AllocateReg(IntRegs, IntRegsSize);
3016    if (Reg == Mips::A1 || Reg == Mips::A3)
3017      Reg = State.AllocateReg(IntRegs, IntRegsSize);
3018    State.AllocateReg(IntRegs, IntRegsSize);
3019    LocVT = MVT::i32;
3020  } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
3021    // we are guaranteed to find an available float register
3022    if (ValVT == MVT::f32) {
3023      Reg = State.AllocateReg(F32Regs, FloatRegsSize);
3024      // Shadow int register
3025      State.AllocateReg(IntRegs, IntRegsSize);
3026    } else {
3027      Reg = State.AllocateReg(F64Regs, FloatRegsSize);
3028      // Shadow int registers
3029      unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
3030      if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
3031        State.AllocateReg(IntRegs, IntRegsSize);
3032      State.AllocateReg(IntRegs, IntRegsSize);
3033    }
3034  } else
3035    llvm_unreachable("Cannot handle this ValVT.");
3036
3037  if (!Reg) {
3038    unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
3039                                          OrigAlign);
3040    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
3041  } else
3042    State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3043
3044  return false;
3045}
3046
3047#include "MipsGenCallingConv.inc"
3048
3049//===----------------------------------------------------------------------===//
3050//                  Call Calling Convention Implementation
3051//===----------------------------------------------------------------------===//
3052
3053static const unsigned O32IntRegsSize = 4;
3054
3055// Return next O32 integer argument register.
3056static unsigned getNextIntArgReg(unsigned Reg) {
3057  assert((Reg == Mips::A0) || (Reg == Mips::A2));
3058  return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
3059}
3060
3061/// IsEligibleForTailCallOptimization - Check whether the call is eligible
3062/// for tail call optimization.
3063bool MipsTargetLowering::
3064IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
3065                                  unsigned NextStackOffset,
3066                                  const MipsFunctionInfo& FI) const {
3067  if (!EnableMipsTailCalls)
3068    return false;
3069
3070  // No tail call optimization for mips16.
3071  if (Subtarget->inMips16Mode())
3072    return false;
3073
3074  // Return false if either the callee or caller has a byval argument.
3075  if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
3076    return false;
3077
3078  // Return true if the callee's argument area is no larger than the
3079  // caller's.
3080  return NextStackOffset <= FI.getIncomingArgSize();
3081}
3082
3083SDValue
3084MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
3085                                   SDValue Chain, SDValue Arg, DebugLoc DL,
3086                                   bool IsTailCall, SelectionDAG &DAG) const {
3087  if (!IsTailCall) {
3088    SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
3089                                 DAG.getIntPtrConstant(Offset));
3090    return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
3091                        false, 0);
3092  }
3093
3094  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3095  int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
3096  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3097  return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
3098                      /*isVolatile=*/ true, false, 0);
3099}
3100
3101//
3102// The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
3103// cleaner way to do all of this but it will have to wait until the traditional
3104// gcc mechanism is completed.
3105//
3106// For Pic, in order for Mips16 code to call Mips32 code which according the abi
3107// have either arguments or returned values placed in floating point registers,
3108// we use a set of helper functions. (This includes functions which return type
3109//  complex which on Mips are returned in a pair of floating point registers).
3110//
3111// This is an encoding that we inherited from gcc.
3112// In Mips traditional O32, N32 ABI, floating point numbers are passed in
3113// floating point argument registers 1,2 only when the first and optionally
3114// the second arguments are float (sf) or double (df).
3115// For Mips16 we are only concerned with the situations where floating point
3116// arguments are being passed in floating point registers by the ABI, because
3117// Mips16 mode code cannot execute floating point instructions to load those
3118// values and hence helper functions are needed.
3119// The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
3120// the helper function suffixs for these are:
3121//                        0,  1,    5,        9,         2,   6,        10
3122// this suffix can then be calculated as follows:
3123// for a given argument Arg:
3124//     Arg1x, Arg2x = 1 :  Arg is sf
3125//                    2 :  Arg is df
3126//                    0:   Arg is neither sf or df
3127// So this stub is the string for number Arg1x + Arg2x*4.
3128// However not all numbers between 0 and 10 are possible, we check anyway and
3129// assert if the impossible exists.
3130//
3131
3132unsigned int MipsTargetLowering::getMips16HelperFunctionStubNumber
3133  (ArgListTy &Args) const {
3134  unsigned int resultNum = 0;
3135  if (Args.size() >= 1) {
3136    Type *t = Args[0].Ty;
3137    if (t->isFloatTy()) {
3138      resultNum = 1;
3139    }
3140    else if (t->isDoubleTy()) {
3141      resultNum = 2;
3142    }
3143  }
3144  if (resultNum) {
3145    if (Args.size() >=2) {
3146      Type *t = Args[1].Ty;
3147      if (t->isFloatTy()) {
3148        resultNum += 4;
3149      }
3150      else if (t->isDoubleTy()) {
3151        resultNum += 8;
3152      }
3153    }
3154  }
3155  return resultNum;
3156}
3157
3158//
3159// prefixs are attached to stub numbers depending on the return type .
3160// return type: float  sf_
3161//              double df_
3162//              single complex sc_
3163//              double complext dc_
3164//              others  NO PREFIX
3165//
3166//
3167// The full name of a helper function is__mips16_call_stub +
3168//    return type dependent prefix + stub number
3169//
3170//
3171// This is something that probably should be in a different source file and
3172// perhaps done differently but my main purpose is to not waste runtime
3173// on something that we can enumerate in the source. Another possibility is
3174// to have a python script to generate these mapping tables. This will do
3175// for now. There are a whole series of helper function mapping arrays, one
3176// for each return type class as outlined above. There there are 11 possible
3177//  entries. Ones with 0 are ones which should never be selected
3178//
3179// All the arrays are similar except for ones which return neither
3180// sf, df, sc, dc, in which only care about ones which have sf or df as a
3181// first parameter.
3182//
3183#define P_ "__mips16_call_stub_"
3184#define MAX_STUB_NUMBER 10
3185#define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
3186#define T P "0" , T1
3187#define P P_
3188static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
3189  {0, T1 };
3190#undef P
3191#define P P_ "sf_"
3192static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
3193  { T };
3194#undef P
3195#define P P_ "df_"
3196static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
3197  { T };
3198#undef P
3199#define P P_ "sc_"
3200static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
3201  { T };
3202#undef P
3203#define P P_ "dc_"
3204static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
3205  { T };
3206#undef P
3207#undef P_
3208
3209
3210const char* MipsTargetLowering::
3211  getMips16HelperFunction
3212    (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
3213  const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
3214#ifndef NDEBUG
3215  const unsigned int maxStubNum = 10;
3216  assert(stubNum <= maxStubNum);
3217  const bool validStubNum[maxStubNum+1] =
3218    {true, true, true, false, false, true, true, false, false, true, true};
3219  assert(validStubNum[stubNum]);
3220#endif
3221  const char *result;
3222  if (RetTy->isFloatTy()) {
3223    result = sfMips16Helper[stubNum];
3224  }
3225  else if (RetTy ->isDoubleTy()) {
3226    result = dfMips16Helper[stubNum];
3227  }
3228  else if (RetTy->isStructTy()) {
3229    // check if it's complex
3230    if (RetTy->getNumContainedTypes() == 2) {
3231      if ((RetTy->getContainedType(0)->isFloatTy()) &&
3232          (RetTy->getContainedType(1)->isFloatTy())) {
3233        result = scMips16Helper[stubNum];
3234      }
3235      else if ((RetTy->getContainedType(0)->isDoubleTy()) &&
3236               (RetTy->getContainedType(1)->isDoubleTy())) {
3237        result = dcMips16Helper[stubNum];
3238      }
3239      else {
3240        llvm_unreachable("Uncovered condition");
3241      }
3242    }
3243    else {
3244      llvm_unreachable("Uncovered condition");
3245    }
3246  }
3247  else {
3248    if (stubNum == 0) {
3249      needHelper = false;
3250      return "";
3251    }
3252    result = vMips16Helper[stubNum];
3253  }
3254  needHelper = true;
3255  return result;
3256}
3257
3258/// LowerCall - functions arguments are copied from virtual regs to
3259/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
3260SDValue
3261MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3262                              SmallVectorImpl<SDValue> &InVals) const {
3263  SelectionDAG &DAG                     = CLI.DAG;
3264  DebugLoc &dl                          = CLI.DL;
3265  SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
3266  SmallVector<SDValue, 32> &OutVals     = CLI.OutVals;
3267  SmallVector<ISD::InputArg, 32> &Ins   = CLI.Ins;
3268  SDValue Chain                         = CLI.Chain;
3269  SDValue Callee                        = CLI.Callee;
3270  bool &isTailCall                      = CLI.IsTailCall;
3271  CallingConv::ID CallConv              = CLI.CallConv;
3272  bool isVarArg                         = CLI.IsVarArg;
3273
3274  const char* mips16HelperFunction = 0;
3275  bool needMips16Helper = false;
3276
3277  if (Subtarget->inMips16Mode() && getTargetMachine().Options.UseSoftFloat &&
3278      Mips16HardFloat) {
3279    //
3280    // currently we don't have symbols tagged with the mips16 or mips32
3281    // qualifier so we will assume that we don't know what kind it is.
3282    // and generate the helper
3283    //
3284    bool lookupHelper = true;
3285    if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3286      if (noHelperNeeded.find(S->getSymbol()) != noHelperNeeded.end()) {
3287        lookupHelper = false;
3288      }
3289    }
3290    if (lookupHelper) mips16HelperFunction =
3291      getMips16HelperFunction(CLI.RetTy, CLI.Args, needMips16Helper);
3292
3293  }
3294  MachineFunction &MF = DAG.getMachineFunction();
3295  MachineFrameInfo *MFI = MF.getFrameInfo();
3296  const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
3297  bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
3298
3299  // Analyze operands of the call, assigning locations to each operand.
3300  SmallVector<CCValAssign, 16> ArgLocs;
3301  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3302                 getTargetMachine(), ArgLocs, *DAG.getContext());
3303  MipsCC MipsCCInfo(CallConv, IsO32, CCInfo);
3304
3305  MipsCCInfo.analyzeCallOperands(Outs, isVarArg);
3306
3307  // Get a count of how many bytes are to be pushed on the stack.
3308  unsigned NextStackOffset = CCInfo.getNextStackOffset();
3309
3310  // Check if it's really possible to do a tail call.
3311  if (isTailCall)
3312    isTailCall =
3313      IsEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset,
3314                                        *MF.getInfo<MipsFunctionInfo>());
3315
3316  if (isTailCall)
3317    ++NumTailCalls;
3318
3319  // Chain is the output chain of the last Load/Store or CopyToReg node.
3320  // ByValChain is the output chain of the last Memcpy node created for copying
3321  // byval arguments to the stack.
3322  unsigned StackAlignment = TFL->getStackAlignment();
3323  NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
3324  SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
3325
3326  if (!isTailCall)
3327    Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal);
3328
3329  SDValue StackPtr = DAG.getCopyFromReg(Chain, dl,
3330                                        IsN64 ? Mips::SP_64 : Mips::SP,
3331                                        getPointerTy());
3332
3333  // With EABI is it possible to have 16 args on registers.
3334  std::deque< std::pair<unsigned, SDValue> > RegsToPass;
3335  SmallVector<SDValue, 8> MemOpChains;
3336  MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
3337
3338  // Walk the register/memloc assignments, inserting copies/loads.
3339  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3340    SDValue Arg = OutVals[i];
3341    CCValAssign &VA = ArgLocs[i];
3342    MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
3343    ISD::ArgFlagsTy Flags = Outs[i].Flags;
3344
3345    // ByVal Arg.
3346    if (Flags.isByVal()) {
3347      assert(Flags.getByValSize() &&
3348             "ByVal args of size 0 should have been ignored by front-end.");
3349      assert(ByValArg != MipsCCInfo.byval_end());
3350      assert(!isTailCall &&
3351             "Do not tail-call optimize if there is a byval argument.");
3352      passByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3353                   MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle());
3354      ++ByValArg;
3355      continue;
3356    }
3357
3358    // Promote the value if needed.
3359    switch (VA.getLocInfo()) {
3360    default: llvm_unreachable("Unknown loc info!");
3361    case CCValAssign::Full:
3362      if (VA.isRegLoc()) {
3363        if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3364            (ValVT == MVT::f64 && LocVT == MVT::i64))
3365          Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);
3366        else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3367          SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
3368                                   Arg, DAG.getConstant(0, MVT::i32));
3369          SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
3370                                   Arg, DAG.getConstant(1, MVT::i32));
3371          if (!Subtarget->isLittle())
3372            std::swap(Lo, Hi);
3373          unsigned LocRegLo = VA.getLocReg();
3374          unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
3375          RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
3376          RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
3377          continue;
3378        }
3379      }
3380      break;
3381    case CCValAssign::SExt:
3382      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
3383      break;
3384    case CCValAssign::ZExt:
3385      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
3386      break;
3387    case CCValAssign::AExt:
3388      Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
3389      break;
3390    }
3391
3392    // Arguments that can be passed on register must be kept at
3393    // RegsToPass vector
3394    if (VA.isRegLoc()) {
3395      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3396      continue;
3397    }
3398
3399    // Register can't get to this point...
3400    assert(VA.isMemLoc());
3401
3402    // emit ISD::STORE whichs stores the
3403    // parameter value to a stack Location
3404    MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
3405                                         Chain, Arg, dl, isTailCall, DAG));
3406  }
3407
3408  // Transform all store nodes into one single node because all store
3409  // nodes are independent of each other.
3410  if (!MemOpChains.empty())
3411    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3412                        &MemOpChains[0], MemOpChains.size());
3413
3414  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3415  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3416  // node so that legalize doesn't hack it.
3417  bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
3418  bool GlobalOrExternal = false, InternalLinkage = false;
3419  SDValue CalleeLo;
3420
3421  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3422    if (IsPICCall) {
3423      InternalLinkage = G->getGlobal()->hasInternalLinkage();
3424
3425      if (InternalLinkage)
3426        Callee = getAddrLocal(Callee, DAG, HasMips64);
3427      else if (LargeGOT)
3428        Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16,
3429                                       MipsII::MO_CALL_LO16);
3430      else
3431        Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL);
3432    } else
3433      Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0,
3434                                          MipsII::MO_NO_FLAG);
3435    GlobalOrExternal = true;
3436  }
3437  else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3438    if (!IsN64 && !IsPIC) // !N64 && static
3439      Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3440                                            MipsII::MO_NO_FLAG);
3441    else if (LargeGOT)
3442      Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16,
3443                                     MipsII::MO_CALL_LO16);
3444    else // N64 || PIC
3445      Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL);
3446
3447    GlobalOrExternal = true;
3448  }
3449
3450  SDValue JumpTarget = Callee;
3451
3452  // T9 should contain the address of the callee function if
3453  // -reloction-model=pic or it is an indirect call.
3454  if (IsPICCall || !GlobalOrExternal) {
3455    unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
3456    unsigned V0Reg = Mips::V0;
3457    if (needMips16Helper) {
3458      RegsToPass.push_front(std::make_pair(V0Reg, Callee));
3459      JumpTarget = DAG.getExternalSymbol(
3460        mips16HelperFunction, getPointerTy());
3461      JumpTarget = getAddrGlobal(JumpTarget, DAG, MipsII::MO_GOT);
3462    }
3463    else {
3464      RegsToPass.push_front(std::make_pair(T9Reg, Callee));
3465
3466      if (!Subtarget->inMips16Mode())
3467        JumpTarget = SDValue();
3468    }
3469  }
3470
3471  // Insert node "GP copy globalreg" before call to function.
3472  //
3473  // R_MIPS_CALL* operators (emitted when non-internal functions are called
3474  // in PIC mode) allow symbols to be resolved via lazy binding.
3475  // The lazy binding stub requires GP to point to the GOT.
3476  if (IsPICCall && !InternalLinkage) {
3477    unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
3478    EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
3479    RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty)));
3480  }
3481
3482  // Build a sequence of copy-to-reg nodes chained together with token
3483  // chain and flag operands which copy the outgoing args into registers.
3484  // The InFlag in necessary since all emitted instructions must be
3485  // stuck together.
3486  SDValue InFlag;
3487
3488  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3489    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3490                             RegsToPass[i].second, InFlag);
3491    InFlag = Chain.getValue(1);
3492  }
3493
3494  // MipsJmpLink = #chain, #target_address, #opt_in_flags...
3495  //             = Chain, Callee, Reg#1, Reg#2, ...
3496  //
3497  // Returns a chain & a flag for retval copy to use.
3498  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3499  SmallVector<SDValue, 8> Ops(1, Chain);
3500
3501  if (JumpTarget.getNode())
3502    Ops.push_back(JumpTarget);
3503
3504  // Add argument registers to the end of the list so that they are
3505  // known live into the call.
3506  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3507    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3508                                  RegsToPass[i].second.getValueType()));
3509
3510  // Add a register mask operand representing the call-preserved registers.
3511  const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3512  const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3513  assert(Mask && "Missing call preserved mask for calling convention");
3514  Ops.push_back(DAG.getRegisterMask(Mask));
3515
3516  if (InFlag.getNode())
3517    Ops.push_back(InFlag);
3518
3519  if (isTailCall)
3520    return DAG.getNode(MipsISD::TailCall, dl, MVT::Other, &Ops[0], Ops.size());
3521
3522  Chain  = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
3523  InFlag = Chain.getValue(1);
3524
3525  // Create the CALLSEQ_END node.
3526  Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
3527                             DAG.getIntPtrConstant(0, true), InFlag);
3528  InFlag = Chain.getValue(1);
3529
3530  // Handle result values, copying them out of physregs into vregs that we
3531  // return.
3532  return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3533                         Ins, dl, DAG, InVals);
3534}
3535
3536/// LowerCallResult - Lower the result values of a call into the
3537/// appropriate copies out of appropriate physical registers.
3538SDValue
3539MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3540                                    CallingConv::ID CallConv, bool isVarArg,
3541                                    const SmallVectorImpl<ISD::InputArg> &Ins,
3542                                    DebugLoc dl, SelectionDAG &DAG,
3543                                    SmallVectorImpl<SDValue> &InVals) const {
3544  // Assign locations to each value returned by this call.
3545  SmallVector<CCValAssign, 16> RVLocs;
3546  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3547                 getTargetMachine(), RVLocs, *DAG.getContext());
3548
3549  CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
3550
3551  // Copy all of the result registers out of their specified physreg.
3552  for (unsigned i = 0; i != RVLocs.size(); ++i) {
3553    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
3554                               RVLocs[i].getValVT(), InFlag).getValue(1);
3555    InFlag = Chain.getValue(2);
3556    InVals.push_back(Chain.getValue(0));
3557  }
3558
3559  return Chain;
3560}
3561
3562//===----------------------------------------------------------------------===//
3563//             Formal Arguments Calling Convention Implementation
3564//===----------------------------------------------------------------------===//
3565/// LowerFormalArguments - transform physical registers into virtual registers
3566/// and generate load operations for arguments places on the stack.
3567SDValue
3568MipsTargetLowering::LowerFormalArguments(SDValue Chain,
3569                                         CallingConv::ID CallConv,
3570                                         bool isVarArg,
3571                                      const SmallVectorImpl<ISD::InputArg> &Ins,
3572                                         DebugLoc dl, SelectionDAG &DAG,
3573                                         SmallVectorImpl<SDValue> &InVals)
3574                                          const {
3575  MachineFunction &MF = DAG.getMachineFunction();
3576  MachineFrameInfo *MFI = MF.getFrameInfo();
3577  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3578
3579  MipsFI->setVarArgsFrameIndex(0);
3580
3581  // Used with vargs to acumulate store chains.
3582  std::vector<SDValue> OutChains;
3583
3584  // Assign locations to all of the incoming arguments.
3585  SmallVector<CCValAssign, 16> ArgLocs;
3586  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3587                 getTargetMachine(), ArgLocs, *DAG.getContext());
3588  MipsCC MipsCCInfo(CallConv, IsO32, CCInfo);
3589
3590  MipsCCInfo.analyzeFormalArguments(Ins);
3591  MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3592                           MipsCCInfo.hasByValArg());
3593
3594  Function::const_arg_iterator FuncArg =
3595    DAG.getMachineFunction().getFunction()->arg_begin();
3596  unsigned CurArgIdx = 0;
3597  MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
3598
3599  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3600    CCValAssign &VA = ArgLocs[i];
3601    std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
3602    CurArgIdx = Ins[i].OrigArgIndex;
3603    EVT ValVT = VA.getValVT();
3604    ISD::ArgFlagsTy Flags = Ins[i].Flags;
3605    bool IsRegLoc = VA.isRegLoc();
3606
3607    if (Flags.isByVal()) {
3608      assert(Flags.getByValSize() &&
3609             "ByVal args of size 0 should have been ignored by front-end.");
3610      assert(ByValArg != MipsCCInfo.byval_end());
3611      copyByValRegs(Chain, dl, OutChains, DAG, Flags, InVals, &*FuncArg,
3612                    MipsCCInfo, *ByValArg);
3613      ++ByValArg;
3614      continue;
3615    }
3616
3617    // Arguments stored on registers
3618    if (IsRegLoc) {
3619      EVT RegVT = VA.getLocVT();
3620      unsigned ArgReg = VA.getLocReg();
3621      const TargetRegisterClass *RC;
3622
3623      if (RegVT == MVT::i32)
3624        RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass :
3625                                        &Mips::CPURegsRegClass;
3626      else if (RegVT == MVT::i64)
3627        RC = &Mips::CPU64RegsRegClass;
3628      else if (RegVT == MVT::f32)
3629        RC = &Mips::FGR32RegClass;
3630      else if (RegVT == MVT::f64)
3631        RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
3632      else
3633        llvm_unreachable("RegVT not supported by FormalArguments Lowering");
3634
3635      // Transform the arguments stored on
3636      // physical registers into virtual ones
3637      unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3638      SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3639
3640      // If this is an 8 or 16-bit value, it has been passed promoted
3641      // to 32 bits.  Insert an assert[sz]ext to capture this, then
3642      // truncate to the right size.
3643      if (VA.getLocInfo() != CCValAssign::Full) {
3644        unsigned Opcode = 0;
3645        if (VA.getLocInfo() == CCValAssign::SExt)
3646          Opcode = ISD::AssertSext;
3647        else if (VA.getLocInfo() == CCValAssign::ZExt)
3648          Opcode = ISD::AssertZext;
3649        if (Opcode)
3650          ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
3651                                 DAG.getValueType(ValVT));
3652        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
3653      }
3654
3655      // Handle floating point arguments passed in integer registers.
3656      if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3657          (RegVT == MVT::i64 && ValVT == MVT::f64))
3658        ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue);
3659      else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
3660        unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
3661                                  getNextIntArgReg(ArgReg), RC);
3662        SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
3663        if (!Subtarget->isLittle())
3664          std::swap(ArgValue, ArgValue2);
3665        ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
3666                               ArgValue, ArgValue2);
3667      }
3668
3669      InVals.push_back(ArgValue);
3670    } else { // VA.isRegLoc()
3671
3672      // sanity check
3673      assert(VA.isMemLoc());
3674
3675      // The stack pointer offset is relative to the caller stack frame.
3676      int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
3677                                      VA.getLocMemOffset(), true);
3678
3679      // Create load nodes to retrieve arguments from the stack
3680      SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3681      InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN,
3682                                   MachinePointerInfo::getFixedStack(FI),
3683                                   false, false, false, 0));
3684    }
3685  }
3686
3687  // The mips ABIs for returning structs by value requires that we copy
3688  // the sret argument into $v0 for the return. Save the argument into
3689  // a virtual register so that we can access it from the return points.
3690  if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3691    unsigned Reg = MipsFI->getSRetReturnReg();
3692    if (!Reg) {
3693      Reg = MF.getRegInfo().
3694        createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32));
3695      MipsFI->setSRetReturnReg(Reg);
3696    }
3697    SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
3698    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
3699  }
3700
3701  if (isVarArg)
3702    writeVarArgRegs(OutChains, MipsCCInfo, Chain, dl, DAG);
3703
3704  // All stores are grouped in one node to allow the matching between
3705  // the size of Ins and InVals. This only happens when on varg functions
3706  if (!OutChains.empty()) {
3707    OutChains.push_back(Chain);
3708    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3709                        &OutChains[0], OutChains.size());
3710  }
3711
3712  return Chain;
3713}
3714
3715//===----------------------------------------------------------------------===//
3716//               Return Value Calling Convention Implementation
3717//===----------------------------------------------------------------------===//
3718
3719bool
3720MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3721                                   MachineFunction &MF, bool isVarArg,
3722                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
3723                                   LLVMContext &Context) const {
3724  SmallVector<CCValAssign, 16> RVLocs;
3725  CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
3726                 RVLocs, Context);
3727  return CCInfo.CheckReturn(Outs, RetCC_Mips);
3728}
3729
3730SDValue
3731MipsTargetLowering::LowerReturn(SDValue Chain,
3732                                CallingConv::ID CallConv, bool isVarArg,
3733                                const SmallVectorImpl<ISD::OutputArg> &Outs,
3734                                const SmallVectorImpl<SDValue> &OutVals,
3735                                DebugLoc dl, SelectionDAG &DAG) const {
3736
3737  // CCValAssign - represent the assignment of
3738  // the return value to a location
3739  SmallVector<CCValAssign, 16> RVLocs;
3740
3741  // CCState - Info about the registers and stack slot.
3742  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3743                 getTargetMachine(), RVLocs, *DAG.getContext());
3744
3745  // Analize return values.
3746  CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3747
3748  SDValue Flag;
3749  SmallVector<SDValue, 4> RetOps(1, Chain);
3750
3751  // Copy the result values into the output registers.
3752  for (unsigned i = 0; i != RVLocs.size(); ++i) {
3753    CCValAssign &VA = RVLocs[i];
3754    assert(VA.isRegLoc() && "Can only return in registers!");
3755
3756    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
3757
3758    // Guarantee that all emitted copies are stuck together with flags.
3759    Flag = Chain.getValue(1);
3760    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3761  }
3762
3763  // The mips ABIs for returning structs by value requires that we copy
3764  // the sret argument into $v0 for the return. We saved the argument into
3765  // a virtual register in the entry block, so now we copy the value out
3766  // and into $v0.
3767  if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3768    MachineFunction &MF      = DAG.getMachineFunction();
3769    MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3770    unsigned Reg = MipsFI->getSRetReturnReg();
3771
3772    if (!Reg)
3773      llvm_unreachable("sret virtual register not created in the entry block");
3774    SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
3775    unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0;
3776
3777    Chain = DAG.getCopyToReg(Chain, dl, V0, Val, Flag);
3778    Flag = Chain.getValue(1);
3779    RetOps.push_back(DAG.getRegister(V0, getPointerTy()));
3780  }
3781
3782  RetOps[0] = Chain;  // Update chain.
3783
3784  // Add the flag if we have it.
3785  if (Flag.getNode())
3786    RetOps.push_back(Flag);
3787
3788  // Return on Mips is always a "jr $ra"
3789  return DAG.getNode(MipsISD::Ret, dl, MVT::Other, &RetOps[0], RetOps.size());
3790}
3791
3792//===----------------------------------------------------------------------===//
3793//                           Mips Inline Assembly Support
3794//===----------------------------------------------------------------------===//
3795
3796/// getConstraintType - Given a constraint letter, return the type of
3797/// constraint it is for this target.
3798MipsTargetLowering::ConstraintType MipsTargetLowering::
3799getConstraintType(const std::string &Constraint) const
3800{
3801  // Mips specific constrainy
3802  // GCC config/mips/constraints.md
3803  //
3804  // 'd' : An address register. Equivalent to r
3805  //       unless generating MIPS16 code.
3806  // 'y' : Equivalent to r; retained for
3807  //       backwards compatibility.
3808  // 'c' : A register suitable for use in an indirect
3809  //       jump. This will always be $25 for -mabicalls.
3810  // 'l' : The lo register. 1 word storage.
3811  // 'x' : The hilo register pair. Double word storage.
3812  if (Constraint.size() == 1) {
3813    switch (Constraint[0]) {
3814      default : break;
3815      case 'd':
3816      case 'y':
3817      case 'f':
3818      case 'c':
3819      case 'l':
3820      case 'x':
3821        return C_RegisterClass;
3822    }
3823  }
3824  return TargetLowering::getConstraintType(Constraint);
3825}
3826
3827/// Examine constraint type and operand type and determine a weight value.
3828/// This object must already have been set up with the operand type
3829/// and the current alternative constraint selected.
3830TargetLowering::ConstraintWeight
3831MipsTargetLowering::getSingleConstraintMatchWeight(
3832    AsmOperandInfo &info, const char *constraint) const {
3833  ConstraintWeight weight = CW_Invalid;
3834  Value *CallOperandVal = info.CallOperandVal;
3835    // If we don't have a value, we can't do a match,
3836    // but allow it at the lowest weight.
3837  if (CallOperandVal == NULL)
3838    return CW_Default;
3839  Type *type = CallOperandVal->getType();
3840  // Look at the constraint type.
3841  switch (*constraint) {
3842  default:
3843    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3844    break;
3845  case 'd':
3846  case 'y':
3847    if (type->isIntegerTy())
3848      weight = CW_Register;
3849    break;
3850  case 'f':
3851    if (type->isFloatTy())
3852      weight = CW_Register;
3853    break;
3854  case 'c': // $25 for indirect jumps
3855  case 'l': // lo register
3856  case 'x': // hilo register pair
3857      if (type->isIntegerTy())
3858      weight = CW_SpecificReg;
3859      break;
3860  case 'I': // signed 16 bit immediate
3861  case 'J': // integer zero
3862  case 'K': // unsigned 16 bit immediate
3863  case 'L': // signed 32 bit immediate where lower 16 bits are 0
3864  case 'N': // immediate in the range of -65535 to -1 (inclusive)
3865  case 'O': // signed 15 bit immediate (+- 16383)
3866  case 'P': // immediate in the range of 65535 to 1 (inclusive)
3867    if (isa<ConstantInt>(CallOperandVal))
3868      weight = CW_Constant;
3869    break;
3870  }
3871  return weight;
3872}
3873
3874/// Given a register class constraint, like 'r', if this corresponds directly
3875/// to an LLVM register class, return a register of 0 and the register class
3876/// pointer.
3877std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
3878getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
3879{
3880  if (Constraint.size() == 1) {
3881    switch (Constraint[0]) {
3882    case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3883    case 'y': // Same as 'r'. Exists for compatibility.
3884    case 'r':
3885      if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3886        if (Subtarget->inMips16Mode())
3887          return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3888        return std::make_pair(0U, &Mips::CPURegsRegClass);
3889      }
3890      if (VT == MVT::i64 && !HasMips64)
3891        return std::make_pair(0U, &Mips::CPURegsRegClass);
3892      if (VT == MVT::i64 && HasMips64)
3893        return std::make_pair(0U, &Mips::CPU64RegsRegClass);
3894      // This will generate an error message
3895      return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
3896    case 'f':
3897      if (VT == MVT::f32)
3898        return std::make_pair(0U, &Mips::FGR32RegClass);
3899      if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
3900        if (Subtarget->isFP64bit())
3901          return std::make_pair(0U, &Mips::FGR64RegClass);
3902        return std::make_pair(0U, &Mips::AFGR64RegClass);
3903      }
3904      break;
3905    case 'c': // register suitable for indirect jump
3906      if (VT == MVT::i32)
3907        return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass);
3908      assert(VT == MVT::i64 && "Unexpected type.");
3909      return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass);
3910    case 'l': // register suitable for indirect jump
3911      if (VT == MVT::i32)
3912        return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass);
3913      return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass);
3914    case 'x': // register suitable for indirect jump
3915      // Fixme: Not triggering the use of both hi and low
3916      // This will generate an error message
3917      return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
3918    }
3919  }
3920  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3921}
3922
3923/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3924/// vector.  If it is invalid, don't add anything to Ops.
3925void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3926                                                     std::string &Constraint,
3927                                                     std::vector<SDValue>&Ops,
3928                                                     SelectionDAG &DAG) const {
3929  SDValue Result(0, 0);
3930
3931  // Only support length 1 constraints for now.
3932  if (Constraint.length() > 1) return;
3933
3934  char ConstraintLetter = Constraint[0];
3935  switch (ConstraintLetter) {
3936  default: break; // This will fall through to the generic implementation
3937  case 'I': // Signed 16 bit constant
3938    // If this fails, the parent routine will give an error
3939    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3940      EVT Type = Op.getValueType();
3941      int64_t Val = C->getSExtValue();
3942      if (isInt<16>(Val)) {
3943        Result = DAG.getTargetConstant(Val, Type);
3944        break;
3945      }
3946    }
3947    return;
3948  case 'J': // integer zero
3949    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3950      EVT Type = Op.getValueType();
3951      int64_t Val = C->getZExtValue();
3952      if (Val == 0) {
3953        Result = DAG.getTargetConstant(0, Type);
3954        break;
3955      }
3956    }
3957    return;
3958  case 'K': // unsigned 16 bit immediate
3959    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3960      EVT Type = Op.getValueType();
3961      uint64_t Val = (uint64_t)C->getZExtValue();
3962      if (isUInt<16>(Val)) {
3963        Result = DAG.getTargetConstant(Val, Type);
3964        break;
3965      }
3966    }
3967    return;
3968  case 'L': // signed 32 bit immediate where lower 16 bits are 0
3969    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3970      EVT Type = Op.getValueType();
3971      int64_t Val = C->getSExtValue();
3972      if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3973        Result = DAG.getTargetConstant(Val, Type);
3974        break;
3975      }
3976    }
3977    return;
3978  case 'N': // immediate in the range of -65535 to -1 (inclusive)
3979    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3980      EVT Type = Op.getValueType();
3981      int64_t Val = C->getSExtValue();
3982      if ((Val >= -65535) && (Val <= -1)) {
3983        Result = DAG.getTargetConstant(Val, Type);
3984        break;
3985      }
3986    }
3987    return;
3988  case 'O': // signed 15 bit immediate
3989    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3990      EVT Type = Op.getValueType();
3991      int64_t Val = C->getSExtValue();
3992      if ((isInt<15>(Val))) {
3993        Result = DAG.getTargetConstant(Val, Type);
3994        break;
3995      }
3996    }
3997    return;
3998  case 'P': // immediate in the range of 1 to 65535 (inclusive)
3999    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4000      EVT Type = Op.getValueType();
4001      int64_t Val = C->getSExtValue();
4002      if ((Val <= 65535) && (Val >= 1)) {
4003        Result = DAG.getTargetConstant(Val, Type);
4004        break;
4005      }
4006    }
4007    return;
4008  }
4009
4010  if (Result.getNode()) {
4011    Ops.push_back(Result);
4012    return;
4013  }
4014
4015  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4016}
4017
4018bool
4019MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const {
4020  // No global is ever allowed as a base.
4021  if (AM.BaseGV)
4022    return false;
4023
4024  switch (AM.Scale) {
4025  case 0: // "r+i" or just "i", depending on HasBaseReg.
4026    break;
4027  case 1:
4028    if (!AM.HasBaseReg) // allow "r+i".
4029      break;
4030    return false; // disallow "r+r" or "r+r+i".
4031  default:
4032    return false;
4033  }
4034
4035  return true;
4036}
4037
4038bool
4039MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4040  // The Mips target isn't yet aware of offsets.
4041  return false;
4042}
4043
4044EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
4045                                            unsigned SrcAlign,
4046                                            bool IsMemset, bool ZeroMemset,
4047                                            bool MemcpyStrSrc,
4048                                            MachineFunction &MF) const {
4049  if (Subtarget->hasMips64())
4050    return MVT::i64;
4051
4052  return MVT::i32;
4053}
4054
4055bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4056  if (VT != MVT::f32 && VT != MVT::f64)
4057    return false;
4058  if (Imm.isNegZero())
4059    return false;
4060  return Imm.isZero();
4061}
4062
4063unsigned MipsTargetLowering::getJumpTableEncoding() const {
4064  if (IsN64)
4065    return MachineJumpTableInfo::EK_GPRel64BlockAddress;
4066
4067  return TargetLowering::getJumpTableEncoding();
4068}
4069
4070MipsTargetLowering::MipsCC::MipsCC(CallingConv::ID CC, bool IsO32_,
4071                                   CCState &Info)
4072  : CCInfo(Info), CallConv(CC), IsO32(IsO32_) {
4073  // Pre-allocate reserved argument area.
4074  CCInfo.AllocateStack(reservedArgArea(), 1);
4075}
4076
4077void MipsTargetLowering::MipsCC::
4078analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args,
4079                    bool IsVarArg) {
4080  assert((CallConv != CallingConv::Fast || !IsVarArg) &&
4081         "CallingConv::Fast shouldn't be used for vararg functions.");
4082
4083  unsigned NumOpnds = Args.size();
4084  llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn();
4085
4086  for (unsigned I = 0; I != NumOpnds; ++I) {
4087    MVT ArgVT = Args[I].VT;
4088    ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
4089    bool R;
4090
4091    if (ArgFlags.isByVal()) {
4092      handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
4093      continue;
4094    }
4095
4096    if (IsVarArg && !Args[I].IsFixed)
4097      R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
4098    else
4099      R = FixedFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
4100
4101    if (R) {
4102#ifndef NDEBUG
4103      dbgs() << "Call operand #" << I << " has unhandled type "
4104             << EVT(ArgVT).getEVTString();
4105#endif
4106      llvm_unreachable(0);
4107    }
4108  }
4109}
4110
4111void MipsTargetLowering::MipsCC::
4112analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args) {
4113  unsigned NumArgs = Args.size();
4114  llvm::CCAssignFn *FixedFn = fixedArgFn();
4115
4116  for (unsigned I = 0; I != NumArgs; ++I) {
4117    MVT ArgVT = Args[I].VT;
4118    ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
4119
4120    if (ArgFlags.isByVal()) {
4121      handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
4122      continue;
4123    }
4124
4125    if (!FixedFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
4126      continue;
4127
4128#ifndef NDEBUG
4129    dbgs() << "Formal Arg #" << I << " has unhandled type "
4130           << EVT(ArgVT).getEVTString();
4131#endif
4132    llvm_unreachable(0);
4133  }
4134}
4135
4136void
4137MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
4138                                           MVT LocVT,
4139                                           CCValAssign::LocInfo LocInfo,
4140                                           ISD::ArgFlagsTy ArgFlags) {
4141  assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
4142
4143  struct ByValArgInfo ByVal;
4144  unsigned RegSize = regSize();
4145  unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize);
4146  unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize),
4147                            RegSize * 2);
4148
4149  if (useRegsForByval())
4150    allocateRegs(ByVal, ByValSize, Align);
4151
4152  // Allocate space on caller's stack.
4153  ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs,
4154                                       Align);
4155  CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT,
4156                                    LocInfo));
4157  ByValArgs.push_back(ByVal);
4158}
4159
4160unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const {
4161  return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs);
4162}
4163
4164unsigned MipsTargetLowering::MipsCC::reservedArgArea() const {
4165  return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0;
4166}
4167
4168const uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const {
4169  return IsO32 ? O32IntRegs : Mips64IntRegs;
4170}
4171
4172llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const {
4173  if (CallConv == CallingConv::Fast)
4174    return CC_Mips_FastCC;
4175
4176  return IsO32 ? CC_MipsO32 : CC_MipsN;
4177}
4178
4179llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const {
4180  return IsO32 ? CC_MipsO32 : CC_MipsN_VarArg;
4181}
4182
4183const uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const {
4184  return IsO32 ? O32IntRegs : Mips64DPRegs;
4185}
4186
4187void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
4188                                              unsigned ByValSize,
4189                                              unsigned Align) {
4190  unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs();
4191  const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs();
4192  assert(!(ByValSize % RegSize) && !(Align % RegSize) &&
4193         "Byval argument's size and alignment should be a multiple of"
4194         "RegSize.");
4195
4196  ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs);
4197
4198  // If Align > RegSize, the first arg register must be even.
4199  if ((Align > RegSize) && (ByVal.FirstIdx % 2)) {
4200    CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
4201    ++ByVal.FirstIdx;
4202  }
4203
4204  // Mark the registers allocated.
4205  for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs);
4206       ByValSize -= RegSize, ++I, ++ByVal.NumRegs)
4207    CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
4208}
4209
4210void MipsTargetLowering::
4211copyByValRegs(SDValue Chain, DebugLoc DL, std::vector<SDValue> &OutChains,
4212              SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
4213              SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
4214              const MipsCC &CC, const ByValArgInfo &ByVal) const {
4215  MachineFunction &MF = DAG.getMachineFunction();
4216  MachineFrameInfo *MFI = MF.getFrameInfo();
4217  unsigned RegAreaSize = ByVal.NumRegs * CC.regSize();
4218  unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
4219  int FrameObjOffset;
4220
4221  if (RegAreaSize)
4222    FrameObjOffset = (int)CC.reservedArgArea() -
4223      (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize());
4224  else
4225    FrameObjOffset = ByVal.Address;
4226
4227  // Create frame object.
4228  EVT PtrTy = getPointerTy();
4229  int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
4230  SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4231  InVals.push_back(FIN);
4232
4233  if (!ByVal.NumRegs)
4234    return;
4235
4236  // Copy arg registers.
4237  MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
4238  const TargetRegisterClass *RC = getRegClassFor(RegTy);
4239
4240  for (unsigned I = 0; I < ByVal.NumRegs; ++I) {
4241    unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I];
4242    unsigned VReg = AddLiveIn(MF, ArgReg, RC);
4243    unsigned Offset = I * CC.regSize();
4244    SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
4245                                   DAG.getConstant(Offset, PtrTy));
4246    SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
4247                                 StorePtr, MachinePointerInfo(FuncArg, Offset),
4248                                 false, false, 0);
4249    OutChains.push_back(Store);
4250  }
4251}
4252
4253// Copy byVal arg to registers and stack.
4254void MipsTargetLowering::
4255passByValArg(SDValue Chain, DebugLoc DL,
4256             std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
4257             SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
4258             MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
4259             const MipsCC &CC, const ByValArgInfo &ByVal,
4260             const ISD::ArgFlagsTy &Flags, bool isLittle) const {
4261  unsigned ByValSize = Flags.getByValSize();
4262  unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
4263  unsigned RegSize = CC.regSize();
4264  unsigned Alignment = std::min(Flags.getByValAlign(), RegSize);
4265  EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8);
4266
4267  if (ByVal.NumRegs) {
4268    const uint16_t *ArgRegs = CC.intArgRegs();
4269    bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize);
4270    unsigned I = 0;
4271
4272    // Copy words to registers.
4273    for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) {
4274      SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4275                                    DAG.getConstant(Offset, PtrTy));
4276      SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
4277                                    MachinePointerInfo(), false, false, false,
4278                                    Alignment);
4279      MemOpChains.push_back(LoadVal.getValue(1));
4280      unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
4281      RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4282    }
4283
4284    // Return if the struct has been fully copied.
4285    if (ByValSize == Offset)
4286      return;
4287
4288    // Copy the remainder of the byval argument with sub-word loads and shifts.
4289    if (LeftoverBytes) {
4290      assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) &&
4291             "Size of the remainder should be smaller than RegSize.");
4292      SDValue Val;
4293
4294      for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0;
4295           Offset < ByValSize; LoadSize /= 2) {
4296        unsigned RemSize = ByValSize - Offset;
4297
4298        if (RemSize < LoadSize)
4299          continue;
4300
4301        // Load subword.
4302        SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4303                                      DAG.getConstant(Offset, PtrTy));
4304        SDValue LoadVal =
4305          DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr,
4306                         MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
4307                         false, false, Alignment);
4308        MemOpChains.push_back(LoadVal.getValue(1));
4309
4310        // Shift the loaded value.
4311        unsigned Shamt;
4312
4313        if (isLittle)
4314          Shamt = TotalSizeLoaded;
4315        else
4316          Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8;
4317
4318        SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
4319                                    DAG.getConstant(Shamt, MVT::i32));
4320
4321        if (Val.getNode())
4322          Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
4323        else
4324          Val = Shift;
4325
4326        Offset += LoadSize;
4327        TotalSizeLoaded += LoadSize;
4328        Alignment = std::min(Alignment, LoadSize);
4329      }
4330
4331      unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
4332      RegsToPass.push_back(std::make_pair(ArgReg, Val));
4333      return;
4334    }
4335  }
4336
4337  // Copy remainder of byval arg to it with memcpy.
4338  unsigned MemCpySize = ByValSize - Offset;
4339  SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4340                            DAG.getConstant(Offset, PtrTy));
4341  SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
4342                            DAG.getIntPtrConstant(ByVal.Address));
4343  Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
4344                        DAG.getConstant(MemCpySize, PtrTy), Alignment,
4345                        /*isVolatile=*/false, /*AlwaysInline=*/false,
4346                        MachinePointerInfo(0), MachinePointerInfo(0));
4347  MemOpChains.push_back(Chain);
4348}
4349
4350void
4351MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4352                                    const MipsCC &CC, SDValue Chain,
4353                                    DebugLoc DL, SelectionDAG &DAG) const {
4354  unsigned NumRegs = CC.numIntArgRegs();
4355  const uint16_t *ArgRegs = CC.intArgRegs();
4356  const CCState &CCInfo = CC.getCCInfo();
4357  unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
4358  unsigned RegSize = CC.regSize();
4359  MVT RegTy = MVT::getIntegerVT(RegSize * 8);
4360  const TargetRegisterClass *RC = getRegClassFor(RegTy);
4361  MachineFunction &MF = DAG.getMachineFunction();
4362  MachineFrameInfo *MFI = MF.getFrameInfo();
4363  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
4364
4365  // Offset of the first variable argument from stack pointer.
4366  int VaArgOffset;
4367
4368  if (NumRegs == Idx)
4369    VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize);
4370  else
4371    VaArgOffset =
4372      (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
4373
4374  // Record the frame index of the first variable argument
4375  // which is a value necessary to VASTART.
4376  int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
4377  MipsFI->setVarArgsFrameIndex(FI);
4378
4379  // Copy the integer registers that have not been used for argument passing
4380  // to the argument register save area. For O32, the save area is allocated
4381  // in the caller's stack frame, while for N32/64, it is allocated in the
4382  // callee's stack frame.
4383  for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) {
4384    unsigned Reg = AddLiveIn(MF, ArgRegs[I], RC);
4385    SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
4386    FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
4387    SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
4388    SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
4389                                 MachinePointerInfo(), false, false, 0);
4390    cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0);
4391    OutChains.push_back(Store);
4392  }
4393}
4394