MipsISelLowering.cpp revision 4618e0b574bf879d062a39b5867d9c314a4639e0
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-lower" 16#include "MipsISelLowering.h" 17#include "MipsMachineFunction.h" 18#include "MipsTargetMachine.h" 19#include "MipsTargetObjectFile.h" 20#include "MipsSubtarget.h" 21#include "InstPrinter/MipsInstPrinter.h" 22#include "MCTargetDesc/MipsBaseInfo.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/CallingConv.h" 28#include "llvm/ADT/Statistic.h" 29#include "llvm/CodeGen/CallingConvLower.h" 30#include "llvm/CodeGen/MachineFrameInfo.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineRegisterInfo.h" 34#include "llvm/CodeGen/SelectionDAGISel.h" 35#include "llvm/CodeGen/ValueTypes.h" 36#include "llvm/Support/CommandLine.h" 37#include "llvm/Support/Debug.h" 38#include "llvm/Support/ErrorHandling.h" 39#include "llvm/Support/raw_ostream.h" 40 41using namespace llvm; 42 43STATISTIC(NumTailCalls, "Number of tail calls"); 44 45static cl::opt<bool> 46EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden, 47 cl::desc("MIPS: Enable tail calls."), cl::init(false)); 48 49static const uint16_t O32IntRegs[4] = { 50 Mips::A0, Mips::A1, Mips::A2, Mips::A3 51}; 52 53static const uint16_t Mips64IntRegs[8] = { 54 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, 55 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 56}; 57 58static const uint16_t Mips64DPRegs[8] = { 59 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 60 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 61}; 62 63// If I is a shifted mask, set the size (Size) and the first bit of the 64// mask (Pos), and return true. 65// For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 66static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 67 if (!isShiftedMask_64(I)) 68 return false; 69 70 Size = CountPopulation_64(I); 71 Pos = CountTrailingZeros_64(I); 72 return true; 73} 74 75static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) { 76 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 77 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 78} 79 80const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 81 switch (Opcode) { 82 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 83 case MipsISD::TailCall: return "MipsISD::TailCall"; 84 case MipsISD::Hi: return "MipsISD::Hi"; 85 case MipsISD::Lo: return "MipsISD::Lo"; 86 case MipsISD::GPRel: return "MipsISD::GPRel"; 87 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 88 case MipsISD::Ret: return "MipsISD::Ret"; 89 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 90 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 91 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 92 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 93 case MipsISD::FPRound: return "MipsISD::FPRound"; 94 case MipsISD::MAdd: return "MipsISD::MAdd"; 95 case MipsISD::MAddu: return "MipsISD::MAddu"; 96 case MipsISD::MSub: return "MipsISD::MSub"; 97 case MipsISD::MSubu: return "MipsISD::MSubu"; 98 case MipsISD::DivRem: return "MipsISD::DivRem"; 99 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 100 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 101 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 102 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 103 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 104 case MipsISD::Sync: return "MipsISD::Sync"; 105 case MipsISD::Ext: return "MipsISD::Ext"; 106 case MipsISD::Ins: return "MipsISD::Ins"; 107 case MipsISD::LWL: return "MipsISD::LWL"; 108 case MipsISD::LWR: return "MipsISD::LWR"; 109 case MipsISD::SWL: return "MipsISD::SWL"; 110 case MipsISD::SWR: return "MipsISD::SWR"; 111 case MipsISD::LDL: return "MipsISD::LDL"; 112 case MipsISD::LDR: return "MipsISD::LDR"; 113 case MipsISD::SDL: return "MipsISD::SDL"; 114 case MipsISD::SDR: return "MipsISD::SDR"; 115 case MipsISD::EXTP: return "MipsISD::EXTP"; 116 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 117 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 118 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 119 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 120 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 121 case MipsISD::SHILO: return "MipsISD::SHILO"; 122 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 123 case MipsISD::MULT: return "MipsISD::MULT"; 124 case MipsISD::MULTU: return "MipsISD::MULTU"; 125 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSPDSP"; 126 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 127 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 128 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 129 default: return NULL; 130 } 131} 132 133MipsTargetLowering:: 134MipsTargetLowering(MipsTargetMachine &TM) 135 : TargetLowering(TM, new MipsTargetObjectFile()), 136 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 137 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()), 138 IsO32(Subtarget->isABI_O32()) { 139 140 // Mips does not have i1 type, so use i32 for 141 // setcc operations results (slt, sgt, ...). 142 setBooleanContents(ZeroOrOneBooleanContent); 143 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 144 145 // Set up the register classes 146 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass); 147 148 if (HasMips64) 149 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass); 150 151 if (Subtarget->inMips16Mode()) { 152 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); 153 } 154 155 if (Subtarget->hasDSP()) { 156 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; 157 158 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) { 159 addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass); 160 161 // Expand all builtin opcodes. 162 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 163 setOperationAction(Opc, VecTys[i], Expand); 164 165 setOperationAction(ISD::LOAD, VecTys[i], Legal); 166 setOperationAction(ISD::STORE, VecTys[i], Legal); 167 setOperationAction(ISD::BITCAST, VecTys[i], Legal); 168 } 169 } 170 171 if (!TM.Options.UseSoftFloat) { 172 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); 173 174 // When dealing with single precision only, use libcalls 175 if (!Subtarget->isSingleFloat()) { 176 if (HasMips64) 177 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); 178 else 179 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); 180 } 181 } 182 183 // Load extented operations for i1 types must be promoted 184 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 185 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 186 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 187 188 // MIPS doesn't have extending float->double load/store 189 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 190 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 191 192 // Used by legalize types to correctly generate the setcc result. 193 // Without this, every float setcc comes with a AND/OR with the result, 194 // we don't want this, since the fpcmp result goes to a flag register, 195 // which is used implicitly by brcond and select operations. 196 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 197 198 // Mips Custom Operations 199 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 200 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 201 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 202 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 203 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 204 setOperationAction(ISD::SELECT, MVT::f32, Custom); 205 setOperationAction(ISD::SELECT, MVT::f64, Custom); 206 setOperationAction(ISD::SELECT, MVT::i32, Custom); 207 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 208 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 209 setOperationAction(ISD::SETCC, MVT::f32, Custom); 210 setOperationAction(ISD::SETCC, MVT::f64, Custom); 211 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 212 setOperationAction(ISD::VASTART, MVT::Other, Custom); 213 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 214 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 215 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 216 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 217 if (!Subtarget->inMips16Mode()) { 218 setOperationAction(ISD::LOAD, MVT::i32, Custom); 219 setOperationAction(ISD::STORE, MVT::i32, Custom); 220 } 221 222 if (!TM.Options.NoNaNsFPMath) { 223 setOperationAction(ISD::FABS, MVT::f32, Custom); 224 setOperationAction(ISD::FABS, MVT::f64, Custom); 225 } 226 227 if (HasMips64) { 228 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 229 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 230 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 231 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 232 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 233 setOperationAction(ISD::SELECT, MVT::i64, Custom); 234 setOperationAction(ISD::LOAD, MVT::i64, Custom); 235 setOperationAction(ISD::STORE, MVT::i64, Custom); 236 } 237 238 if (!HasMips64) { 239 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 240 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 241 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 242 } 243 244 setOperationAction(ISD::SDIV, MVT::i32, Expand); 245 setOperationAction(ISD::SREM, MVT::i32, Expand); 246 setOperationAction(ISD::UDIV, MVT::i32, Expand); 247 setOperationAction(ISD::UREM, MVT::i32, Expand); 248 setOperationAction(ISD::SDIV, MVT::i64, Expand); 249 setOperationAction(ISD::SREM, MVT::i64, Expand); 250 setOperationAction(ISD::UDIV, MVT::i64, Expand); 251 setOperationAction(ISD::UREM, MVT::i64, Expand); 252 253 // Operations not directly supported by Mips. 254 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 255 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 256 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 258 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 259 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 260 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 261 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 262 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 263 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 264 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 265 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 266 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 267 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 268 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 269 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 270 setOperationAction(ISD::ROTL, MVT::i32, Expand); 271 setOperationAction(ISD::ROTL, MVT::i64, Expand); 272 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 273 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 274 275 if (!Subtarget->hasMips32r2()) 276 setOperationAction(ISD::ROTR, MVT::i32, Expand); 277 278 if (!Subtarget->hasMips64r2()) 279 setOperationAction(ISD::ROTR, MVT::i64, Expand); 280 281 setOperationAction(ISD::FSIN, MVT::f32, Expand); 282 setOperationAction(ISD::FSIN, MVT::f64, Expand); 283 setOperationAction(ISD::FCOS, MVT::f32, Expand); 284 setOperationAction(ISD::FCOS, MVT::f64, Expand); 285 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 286 setOperationAction(ISD::FPOW, MVT::f32, Expand); 287 setOperationAction(ISD::FPOW, MVT::f64, Expand); 288 setOperationAction(ISD::FLOG, MVT::f32, Expand); 289 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 290 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 291 setOperationAction(ISD::FEXP, MVT::f32, Expand); 292 setOperationAction(ISD::FMA, MVT::f32, Expand); 293 setOperationAction(ISD::FMA, MVT::f64, Expand); 294 setOperationAction(ISD::FREM, MVT::f32, Expand); 295 setOperationAction(ISD::FREM, MVT::f64, Expand); 296 297 if (!TM.Options.NoNaNsFPMath) { 298 setOperationAction(ISD::FNEG, MVT::f32, Expand); 299 setOperationAction(ISD::FNEG, MVT::f64, Expand); 300 } 301 302 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 303 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 304 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 305 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 306 307 setOperationAction(ISD::VAARG, MVT::Other, Expand); 308 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 309 setOperationAction(ISD::VAEND, MVT::Other, Expand); 310 311 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); 312 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); 313 314 // Use the default for now 315 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 316 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 317 318 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 319 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 320 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 321 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 322 323 setInsertFencesForAtomic(true); 324 325 if (!Subtarget->hasSEInReg()) { 326 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 327 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 328 } 329 330 if (!Subtarget->hasBitCount()) { 331 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 332 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 333 } 334 335 if (!Subtarget->hasSwap()) { 336 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 337 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 338 } 339 340 if (HasMips64) { 341 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); 342 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom); 343 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom); 344 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 345 } 346 347 setTargetDAGCombine(ISD::ADDE); 348 setTargetDAGCombine(ISD::SUBE); 349 setTargetDAGCombine(ISD::SDIVREM); 350 setTargetDAGCombine(ISD::UDIVREM); 351 setTargetDAGCombine(ISD::SELECT); 352 setTargetDAGCombine(ISD::AND); 353 setTargetDAGCombine(ISD::OR); 354 setTargetDAGCombine(ISD::ADD); 355 356 setMinFunctionAlignment(HasMips64 ? 3 : 2); 357 358 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP); 359 computeRegisterProperties(); 360 361 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0); 362 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1); 363 364 maxStoresPerMemcpy = 16; 365} 366 367bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 368 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 369 370 if (Subtarget->inMips16Mode()) 371 return false; 372 373 switch (SVT) { 374 case MVT::i64: 375 case MVT::i32: 376 return true; 377 default: 378 return false; 379 } 380} 381 382EVT MipsTargetLowering::getSetCCResultType(EVT VT) const { 383 return MVT::i32; 384} 385 386// SelectMadd - 387// Transforms a subgraph in CurDAG if the following pattern is found: 388// (addc multLo, Lo0), (adde multHi, Hi0), 389// where, 390// multHi/Lo: product of multiplication 391// Lo0: initial value of Lo register 392// Hi0: initial value of Hi register 393// Return true if pattern matching was successful. 394static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) { 395 // ADDENode's second operand must be a flag output of an ADDC node in order 396 // for the matching to be successful. 397 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); 398 399 if (ADDCNode->getOpcode() != ISD::ADDC) 400 return false; 401 402 SDValue MultHi = ADDENode->getOperand(0); 403 SDValue MultLo = ADDCNode->getOperand(0); 404 SDNode *MultNode = MultHi.getNode(); 405 unsigned MultOpc = MultHi.getOpcode(); 406 407 // MultHi and MultLo must be generated by the same node, 408 if (MultLo.getNode() != MultNode) 409 return false; 410 411 // and it must be a multiplication. 412 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 413 return false; 414 415 // MultLo amd MultHi must be the first and second output of MultNode 416 // respectively. 417 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 418 return false; 419 420 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 421 // of the values of MultNode, in which case MultNode will be removed in later 422 // phases. 423 // If there exist users other than ADDENode or ADDCNode, this function returns 424 // here, which will result in MultNode being mapped to a single MULT 425 // instruction node rather than a pair of MULT and MADD instructions being 426 // produced. 427 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 428 return false; 429 430 SDValue Chain = CurDAG->getEntryNode(); 431 DebugLoc dl = ADDENode->getDebugLoc(); 432 433 // create MipsMAdd(u) node 434 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 435 436 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue, 437 MultNode->getOperand(0),// Factor 0 438 MultNode->getOperand(1),// Factor 1 439 ADDCNode->getOperand(1),// Lo0 440 ADDENode->getOperand(1));// Hi0 441 442 // create CopyFromReg nodes 443 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 444 MAdd); 445 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 446 Mips::HI, MVT::i32, 447 CopyFromLo.getValue(2)); 448 449 // replace uses of adde and addc here 450 if (!SDValue(ADDCNode, 0).use_empty()) 451 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 452 453 if (!SDValue(ADDENode, 0).use_empty()) 454 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 455 456 return true; 457} 458 459// SelectMsub - 460// Transforms a subgraph in CurDAG if the following pattern is found: 461// (addc Lo0, multLo), (sube Hi0, multHi), 462// where, 463// multHi/Lo: product of multiplication 464// Lo0: initial value of Lo register 465// Hi0: initial value of Hi register 466// Return true if pattern matching was successful. 467static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) { 468 // SUBENode's second operand must be a flag output of an SUBC node in order 469 // for the matching to be successful. 470 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); 471 472 if (SUBCNode->getOpcode() != ISD::SUBC) 473 return false; 474 475 SDValue MultHi = SUBENode->getOperand(1); 476 SDValue MultLo = SUBCNode->getOperand(1); 477 SDNode *MultNode = MultHi.getNode(); 478 unsigned MultOpc = MultHi.getOpcode(); 479 480 // MultHi and MultLo must be generated by the same node, 481 if (MultLo.getNode() != MultNode) 482 return false; 483 484 // and it must be a multiplication. 485 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 486 return false; 487 488 // MultLo amd MultHi must be the first and second output of MultNode 489 // respectively. 490 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 491 return false; 492 493 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 494 // of the values of MultNode, in which case MultNode will be removed in later 495 // phases. 496 // If there exist users other than SUBENode or SUBCNode, this function returns 497 // here, which will result in MultNode being mapped to a single MULT 498 // instruction node rather than a pair of MULT and MSUB instructions being 499 // produced. 500 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 501 return false; 502 503 SDValue Chain = CurDAG->getEntryNode(); 504 DebugLoc dl = SUBENode->getDebugLoc(); 505 506 // create MipsSub(u) node 507 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 508 509 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue, 510 MultNode->getOperand(0),// Factor 0 511 MultNode->getOperand(1),// Factor 1 512 SUBCNode->getOperand(0),// Lo0 513 SUBENode->getOperand(0));// Hi0 514 515 // create CopyFromReg nodes 516 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 517 MSub); 518 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 519 Mips::HI, MVT::i32, 520 CopyFromLo.getValue(2)); 521 522 // replace uses of sube and subc here 523 if (!SDValue(SUBCNode, 0).use_empty()) 524 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 525 526 if (!SDValue(SUBENode, 0).use_empty()) 527 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 528 529 return true; 530} 531 532static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG, 533 TargetLowering::DAGCombinerInfo &DCI, 534 const MipsSubtarget *Subtarget) { 535 if (DCI.isBeforeLegalize()) 536 return SDValue(); 537 538 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 539 SelectMadd(N, &DAG)) 540 return SDValue(N, 0); 541 542 return SDValue(); 543} 544 545static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG, 546 TargetLowering::DAGCombinerInfo &DCI, 547 const MipsSubtarget *Subtarget) { 548 if (DCI.isBeforeLegalize()) 549 return SDValue(); 550 551 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 552 SelectMsub(N, &DAG)) 553 return SDValue(N, 0); 554 555 return SDValue(); 556} 557 558static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG, 559 TargetLowering::DAGCombinerInfo &DCI, 560 const MipsSubtarget *Subtarget) { 561 if (DCI.isBeforeLegalizeOps()) 562 return SDValue(); 563 564 EVT Ty = N->getValueType(0); 565 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64; 566 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64; 567 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 568 MipsISD::DivRemU; 569 DebugLoc dl = N->getDebugLoc(); 570 571 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 572 N->getOperand(0), N->getOperand(1)); 573 SDValue InChain = DAG.getEntryNode(); 574 SDValue InGlue = DivRem; 575 576 // insert MFLO 577 if (N->hasAnyUseOfValue(0)) { 578 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty, 579 InGlue); 580 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 581 InChain = CopyFromLo.getValue(1); 582 InGlue = CopyFromLo.getValue(2); 583 } 584 585 // insert MFHI 586 if (N->hasAnyUseOfValue(1)) { 587 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 588 HI, Ty, InGlue); 589 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 590 } 591 592 return SDValue(); 593} 594 595static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 596 switch (CC) { 597 default: llvm_unreachable("Unknown fp condition code!"); 598 case ISD::SETEQ: 599 case ISD::SETOEQ: return Mips::FCOND_OEQ; 600 case ISD::SETUNE: return Mips::FCOND_UNE; 601 case ISD::SETLT: 602 case ISD::SETOLT: return Mips::FCOND_OLT; 603 case ISD::SETGT: 604 case ISD::SETOGT: return Mips::FCOND_OGT; 605 case ISD::SETLE: 606 case ISD::SETOLE: return Mips::FCOND_OLE; 607 case ISD::SETGE: 608 case ISD::SETOGE: return Mips::FCOND_OGE; 609 case ISD::SETULT: return Mips::FCOND_ULT; 610 case ISD::SETULE: return Mips::FCOND_ULE; 611 case ISD::SETUGT: return Mips::FCOND_UGT; 612 case ISD::SETUGE: return Mips::FCOND_UGE; 613 case ISD::SETUO: return Mips::FCOND_UN; 614 case ISD::SETO: return Mips::FCOND_OR; 615 case ISD::SETNE: 616 case ISD::SETONE: return Mips::FCOND_ONE; 617 case ISD::SETUEQ: return Mips::FCOND_UEQ; 618 } 619} 620 621 622// Returns true if condition code has to be inverted. 623static bool InvertFPCondCode(Mips::CondCode CC) { 624 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 625 return false; 626 627 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 628 "Illegal Condition Code"); 629 630 return true; 631} 632 633// Creates and returns an FPCmp node from a setcc node. 634// Returns Op if setcc is not a floating point comparison. 635static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) { 636 // must be a SETCC node 637 if (Op.getOpcode() != ISD::SETCC) 638 return Op; 639 640 SDValue LHS = Op.getOperand(0); 641 642 if (!LHS.getValueType().isFloatingPoint()) 643 return Op; 644 645 SDValue RHS = Op.getOperand(1); 646 DebugLoc dl = Op.getDebugLoc(); 647 648 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 649 // node if necessary. 650 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 651 652 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 653 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 654} 655 656// Creates and returns a CMovFPT/F node. 657static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 658 SDValue False, DebugLoc DL) { 659 bool invert = InvertFPCondCode((Mips::CondCode) 660 cast<ConstantSDNode>(Cond.getOperand(2)) 661 ->getSExtValue()); 662 663 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 664 True.getValueType(), True, False, Cond); 665} 666 667static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 668 TargetLowering::DAGCombinerInfo &DCI, 669 const MipsSubtarget *Subtarget) { 670 if (DCI.isBeforeLegalizeOps()) 671 return SDValue(); 672 673 SDValue SetCC = N->getOperand(0); 674 675 if ((SetCC.getOpcode() != ISD::SETCC) || 676 !SetCC.getOperand(0).getValueType().isInteger()) 677 return SDValue(); 678 679 SDValue False = N->getOperand(2); 680 EVT FalseTy = False.getValueType(); 681 682 if (!FalseTy.isInteger()) 683 return SDValue(); 684 685 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False); 686 687 if (!CN || CN->getZExtValue()) 688 return SDValue(); 689 690 const DebugLoc DL = N->getDebugLoc(); 691 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 692 SDValue True = N->getOperand(1); 693 694 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 695 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 696 697 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 698} 699 700static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG, 701 TargetLowering::DAGCombinerInfo &DCI, 702 const MipsSubtarget *Subtarget) { 703 // Pattern match EXT. 704 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 705 // => ext $dst, $src, size, pos 706 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 707 return SDValue(); 708 709 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 710 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 711 712 // Op's first operand must be a shift right. 713 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 714 return SDValue(); 715 716 // The second operand of the shift must be an immediate. 717 ConstantSDNode *CN; 718 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 719 return SDValue(); 720 721 uint64_t Pos = CN->getZExtValue(); 722 uint64_t SMPos, SMSize; 723 724 // Op's second operand must be a shifted mask. 725 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 726 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 727 return SDValue(); 728 729 // Return if the shifted mask does not start at bit 0 or the sum of its size 730 // and Pos exceeds the word's size. 731 EVT ValTy = N->getValueType(0); 732 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 733 return SDValue(); 734 735 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy, 736 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), 737 DAG.getConstant(SMSize, MVT::i32)); 738} 739 740static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG, 741 TargetLowering::DAGCombinerInfo &DCI, 742 const MipsSubtarget *Subtarget) { 743 // Pattern match INS. 744 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 745 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 746 // => ins $dst, $src, size, pos, $src1 747 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 748 return SDValue(); 749 750 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 751 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 752 ConstantSDNode *CN; 753 754 // See if Op's first operand matches (and $src1 , mask0). 755 if (And0.getOpcode() != ISD::AND) 756 return SDValue(); 757 758 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 759 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 760 return SDValue(); 761 762 // See if Op's second operand matches (and (shl $src, pos), mask1). 763 if (And1.getOpcode() != ISD::AND) 764 return SDValue(); 765 766 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 767 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 768 return SDValue(); 769 770 // The shift masks must have the same position and size. 771 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 772 return SDValue(); 773 774 SDValue Shl = And1.getOperand(0); 775 if (Shl.getOpcode() != ISD::SHL) 776 return SDValue(); 777 778 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 779 return SDValue(); 780 781 unsigned Shamt = CN->getZExtValue(); 782 783 // Return if the shift amount and the first bit position of mask are not the 784 // same. 785 EVT ValTy = N->getValueType(0); 786 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 787 return SDValue(); 788 789 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0), 790 DAG.getConstant(SMPos0, MVT::i32), 791 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0)); 792} 793 794static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG, 795 TargetLowering::DAGCombinerInfo &DCI, 796 const MipsSubtarget *Subtarget) { 797 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 798 799 if (DCI.isBeforeLegalizeOps()) 800 return SDValue(); 801 802 SDValue Add = N->getOperand(1); 803 804 if (Add.getOpcode() != ISD::ADD) 805 return SDValue(); 806 807 SDValue Lo = Add.getOperand(1); 808 809 if ((Lo.getOpcode() != MipsISD::Lo) || 810 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 811 return SDValue(); 812 813 EVT ValTy = N->getValueType(0); 814 DebugLoc DL = N->getDebugLoc(); 815 816 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 817 Add.getOperand(0)); 818 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 819} 820 821SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 822 const { 823 SelectionDAG &DAG = DCI.DAG; 824 unsigned opc = N->getOpcode(); 825 826 switch (opc) { 827 default: break; 828 case ISD::ADDE: 829 return PerformADDECombine(N, DAG, DCI, Subtarget); 830 case ISD::SUBE: 831 return PerformSUBECombine(N, DAG, DCI, Subtarget); 832 case ISD::SDIVREM: 833 case ISD::UDIVREM: 834 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 835 case ISD::SELECT: 836 return PerformSELECTCombine(N, DAG, DCI, Subtarget); 837 case ISD::AND: 838 return PerformANDCombine(N, DAG, DCI, Subtarget); 839 case ISD::OR: 840 return PerformORCombine(N, DAG, DCI, Subtarget); 841 case ISD::ADD: 842 return PerformADDCombine(N, DAG, DCI, Subtarget); 843 } 844 845 return SDValue(); 846} 847 848void 849MipsTargetLowering::LowerOperationWrapper(SDNode *N, 850 SmallVectorImpl<SDValue> &Results, 851 SelectionDAG &DAG) const { 852 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 853 854 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 855 Results.push_back(Res.getValue(I)); 856} 857 858void 859MipsTargetLowering::ReplaceNodeResults(SDNode *N, 860 SmallVectorImpl<SDValue> &Results, 861 SelectionDAG &DAG) const { 862 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 863 864 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 865 Results.push_back(Res.getValue(I)); 866} 867 868SDValue MipsTargetLowering:: 869LowerOperation(SDValue Op, SelectionDAG &DAG) const 870{ 871 switch (Op.getOpcode()) 872 { 873 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 874 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 875 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 876 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 877 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 878 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 879 case ISD::SELECT: return LowerSELECT(Op, DAG); 880 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 881 case ISD::SETCC: return LowerSETCC(Op, DAG); 882 case ISD::VASTART: return LowerVASTART(Op, DAG); 883 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 884 case ISD::FABS: return LowerFABS(Op, DAG); 885 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 886 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 887 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); 888 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 889 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); 890 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG, true); 891 case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false); 892 case ISD::LOAD: return LowerLOAD(Op, DAG); 893 case ISD::STORE: return LowerSTORE(Op, DAG); 894 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 895 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG); 896 } 897 return SDValue(); 898} 899 900//===----------------------------------------------------------------------===// 901// Lower helper functions 902//===----------------------------------------------------------------------===// 903 904// AddLiveIn - This helper function adds the specified physical register to the 905// MachineFunction as a live in value. It also creates a corresponding 906// virtual register for it. 907static unsigned 908AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 909{ 910 assert(RC->contains(PReg) && "Not the correct regclass!"); 911 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 912 MF.getRegInfo().addLiveIn(PReg, VReg); 913 return VReg; 914} 915 916// Get fp branch code (not opcode) from condition code. 917static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 918 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 919 return Mips::BRANCH_T; 920 921 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 922 "Invalid CondCode."); 923 924 return Mips::BRANCH_F; 925} 926 927/* 928static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, 929 DebugLoc dl, 930 const MipsSubtarget *Subtarget, 931 const TargetInstrInfo *TII, 932 bool isFPCmp, unsigned Opc) { 933 // There is no need to expand CMov instructions if target has 934 // conditional moves. 935 if (Subtarget->hasCondMov()) 936 return BB; 937 938 // To "insert" a SELECT_CC instruction, we actually have to insert the 939 // diamond control-flow pattern. The incoming instruction knows the 940 // destination vreg to set, the condition code register to branch on, the 941 // true/false values to select between, and a branch opcode to use. 942 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 943 MachineFunction::iterator It = BB; 944 ++It; 945 946 // thisMBB: 947 // ... 948 // TrueVal = ... 949 // setcc r1, r2, r3 950 // bNE r1, r0, copy1MBB 951 // fallthrough --> copy0MBB 952 MachineBasicBlock *thisMBB = BB; 953 MachineFunction *F = BB->getParent(); 954 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 955 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 956 F->insert(It, copy0MBB); 957 F->insert(It, sinkMBB); 958 959 // Transfer the remainder of BB and its successor edges to sinkMBB. 960 sinkMBB->splice(sinkMBB->begin(), BB, 961 llvm::next(MachineBasicBlock::iterator(MI)), 962 BB->end()); 963 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 964 965 // Next, add the true and fallthrough blocks as its successors. 966 BB->addSuccessor(copy0MBB); 967 BB->addSuccessor(sinkMBB); 968 969 // Emit the right instruction according to the type of the operands compared 970 if (isFPCmp) 971 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 972 else 973 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 974 .addReg(Mips::ZERO).addMBB(sinkMBB); 975 976 // copy0MBB: 977 // %FalseValue = ... 978 // # fallthrough to sinkMBB 979 BB = copy0MBB; 980 981 // Update machine-CFG edges 982 BB->addSuccessor(sinkMBB); 983 984 // sinkMBB: 985 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 986 // ... 987 BB = sinkMBB; 988 989 if (isFPCmp) 990 BuildMI(*BB, BB->begin(), dl, 991 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 992 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 993 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 994 else 995 BuildMI(*BB, BB->begin(), dl, 996 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 997 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 998 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 999 1000 MI->eraseFromParent(); // The pseudo instruction is gone now. 1001 return BB; 1002} 1003*/ 1004 1005MachineBasicBlock * 1006MipsTargetLowering::EmitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{ 1007 // $bb: 1008 // bposge32_pseudo $vr0 1009 // => 1010 // $bb: 1011 // bposge32 $tbb 1012 // $fbb: 1013 // li $vr2, 0 1014 // b $sink 1015 // $tbb: 1016 // li $vr1, 1 1017 // $sink: 1018 // $vr0 = phi($vr2, $fbb, $vr1, $tbb) 1019 1020 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 1021 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1022 const TargetRegisterClass *RC = &Mips::CPURegsRegClass; 1023 DebugLoc DL = MI->getDebugLoc(); 1024 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1025 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB)); 1026 MachineFunction *F = BB->getParent(); 1027 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); 1028 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); 1029 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); 1030 F->insert(It, FBB); 1031 F->insert(It, TBB); 1032 F->insert(It, Sink); 1033 1034 // Transfer the remainder of BB and its successor edges to Sink. 1035 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), 1036 BB->end()); 1037 Sink->transferSuccessorsAndUpdatePHIs(BB); 1038 1039 // Add successors. 1040 BB->addSuccessor(FBB); 1041 BB->addSuccessor(TBB); 1042 FBB->addSuccessor(Sink); 1043 TBB->addSuccessor(Sink); 1044 1045 // Insert the real bposge32 instruction to $BB. 1046 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB); 1047 1048 // Fill $FBB. 1049 unsigned VR2 = RegInfo.createVirtualRegister(RC); 1050 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) 1051 .addReg(Mips::ZERO).addImm(0); 1052 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 1053 1054 // Fill $TBB. 1055 unsigned VR1 = RegInfo.createVirtualRegister(RC); 1056 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) 1057 .addReg(Mips::ZERO).addImm(1); 1058 1059 // Insert phi function to $Sink. 1060 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 1061 MI->getOperand(0).getReg()) 1062 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB); 1063 1064 MI->eraseFromParent(); // The pseudo instruction is gone now. 1065 return Sink; 1066} 1067 1068MachineBasicBlock * 1069MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1070 MachineBasicBlock *BB) const { 1071 switch (MI->getOpcode()) { 1072 default: llvm_unreachable("Unexpected instr type to insert"); 1073 case Mips::ATOMIC_LOAD_ADD_I8: 1074 case Mips::ATOMIC_LOAD_ADD_I8_P8: 1075 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 1076 case Mips::ATOMIC_LOAD_ADD_I16: 1077 case Mips::ATOMIC_LOAD_ADD_I16_P8: 1078 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 1079 case Mips::ATOMIC_LOAD_ADD_I32: 1080 case Mips::ATOMIC_LOAD_ADD_I32_P8: 1081 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); 1082 case Mips::ATOMIC_LOAD_ADD_I64: 1083 case Mips::ATOMIC_LOAD_ADD_I64_P8: 1084 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu); 1085 1086 case Mips::ATOMIC_LOAD_AND_I8: 1087 case Mips::ATOMIC_LOAD_AND_I8_P8: 1088 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 1089 case Mips::ATOMIC_LOAD_AND_I16: 1090 case Mips::ATOMIC_LOAD_AND_I16_P8: 1091 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 1092 case Mips::ATOMIC_LOAD_AND_I32: 1093 case Mips::ATOMIC_LOAD_AND_I32_P8: 1094 return EmitAtomicBinary(MI, BB, 4, Mips::AND); 1095 case Mips::ATOMIC_LOAD_AND_I64: 1096 case Mips::ATOMIC_LOAD_AND_I64_P8: 1097 return EmitAtomicBinary(MI, BB, 8, Mips::AND64); 1098 1099 case Mips::ATOMIC_LOAD_OR_I8: 1100 case Mips::ATOMIC_LOAD_OR_I8_P8: 1101 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 1102 case Mips::ATOMIC_LOAD_OR_I16: 1103 case Mips::ATOMIC_LOAD_OR_I16_P8: 1104 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 1105 case Mips::ATOMIC_LOAD_OR_I32: 1106 case Mips::ATOMIC_LOAD_OR_I32_P8: 1107 return EmitAtomicBinary(MI, BB, 4, Mips::OR); 1108 case Mips::ATOMIC_LOAD_OR_I64: 1109 case Mips::ATOMIC_LOAD_OR_I64_P8: 1110 return EmitAtomicBinary(MI, BB, 8, Mips::OR64); 1111 1112 case Mips::ATOMIC_LOAD_XOR_I8: 1113 case Mips::ATOMIC_LOAD_XOR_I8_P8: 1114 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 1115 case Mips::ATOMIC_LOAD_XOR_I16: 1116 case Mips::ATOMIC_LOAD_XOR_I16_P8: 1117 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 1118 case Mips::ATOMIC_LOAD_XOR_I32: 1119 case Mips::ATOMIC_LOAD_XOR_I32_P8: 1120 return EmitAtomicBinary(MI, BB, 4, Mips::XOR); 1121 case Mips::ATOMIC_LOAD_XOR_I64: 1122 case Mips::ATOMIC_LOAD_XOR_I64_P8: 1123 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64); 1124 1125 case Mips::ATOMIC_LOAD_NAND_I8: 1126 case Mips::ATOMIC_LOAD_NAND_I8_P8: 1127 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); 1128 case Mips::ATOMIC_LOAD_NAND_I16: 1129 case Mips::ATOMIC_LOAD_NAND_I16_P8: 1130 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); 1131 case Mips::ATOMIC_LOAD_NAND_I32: 1132 case Mips::ATOMIC_LOAD_NAND_I32_P8: 1133 return EmitAtomicBinary(MI, BB, 4, 0, true); 1134 case Mips::ATOMIC_LOAD_NAND_I64: 1135 case Mips::ATOMIC_LOAD_NAND_I64_P8: 1136 return EmitAtomicBinary(MI, BB, 8, 0, true); 1137 1138 case Mips::ATOMIC_LOAD_SUB_I8: 1139 case Mips::ATOMIC_LOAD_SUB_I8_P8: 1140 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 1141 case Mips::ATOMIC_LOAD_SUB_I16: 1142 case Mips::ATOMIC_LOAD_SUB_I16_P8: 1143 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 1144 case Mips::ATOMIC_LOAD_SUB_I32: 1145 case Mips::ATOMIC_LOAD_SUB_I32_P8: 1146 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); 1147 case Mips::ATOMIC_LOAD_SUB_I64: 1148 case Mips::ATOMIC_LOAD_SUB_I64_P8: 1149 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu); 1150 1151 case Mips::ATOMIC_SWAP_I8: 1152 case Mips::ATOMIC_SWAP_I8_P8: 1153 return EmitAtomicBinaryPartword(MI, BB, 1, 0); 1154 case Mips::ATOMIC_SWAP_I16: 1155 case Mips::ATOMIC_SWAP_I16_P8: 1156 return EmitAtomicBinaryPartword(MI, BB, 2, 0); 1157 case Mips::ATOMIC_SWAP_I32: 1158 case Mips::ATOMIC_SWAP_I32_P8: 1159 return EmitAtomicBinary(MI, BB, 4, 0); 1160 case Mips::ATOMIC_SWAP_I64: 1161 case Mips::ATOMIC_SWAP_I64_P8: 1162 return EmitAtomicBinary(MI, BB, 8, 0); 1163 1164 case Mips::ATOMIC_CMP_SWAP_I8: 1165 case Mips::ATOMIC_CMP_SWAP_I8_P8: 1166 return EmitAtomicCmpSwapPartword(MI, BB, 1); 1167 case Mips::ATOMIC_CMP_SWAP_I16: 1168 case Mips::ATOMIC_CMP_SWAP_I16_P8: 1169 return EmitAtomicCmpSwapPartword(MI, BB, 2); 1170 case Mips::ATOMIC_CMP_SWAP_I32: 1171 case Mips::ATOMIC_CMP_SWAP_I32_P8: 1172 return EmitAtomicCmpSwap(MI, BB, 4); 1173 case Mips::ATOMIC_CMP_SWAP_I64: 1174 case Mips::ATOMIC_CMP_SWAP_I64_P8: 1175 return EmitAtomicCmpSwap(MI, BB, 8); 1176 case Mips::BPOSGE32_PSEUDO: 1177 return EmitBPOSGE32(MI, BB); 1178 } 1179} 1180 1181// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1182// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1183MachineBasicBlock * 1184MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 1185 unsigned Size, unsigned BinOpcode, 1186 bool Nand) const { 1187 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 1188 1189 MachineFunction *MF = BB->getParent(); 1190 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1191 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1192 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1193 DebugLoc dl = MI->getDebugLoc(); 1194 unsigned LL, SC, AND, NOR, ZERO, BEQ; 1195 1196 if (Size == 4) { 1197 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1198 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1199 AND = Mips::AND; 1200 NOR = Mips::NOR; 1201 ZERO = Mips::ZERO; 1202 BEQ = Mips::BEQ; 1203 } 1204 else { 1205 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 1206 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 1207 AND = Mips::AND64; 1208 NOR = Mips::NOR64; 1209 ZERO = Mips::ZERO_64; 1210 BEQ = Mips::BEQ64; 1211 } 1212 1213 unsigned OldVal = MI->getOperand(0).getReg(); 1214 unsigned Ptr = MI->getOperand(1).getReg(); 1215 unsigned Incr = MI->getOperand(2).getReg(); 1216 1217 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1218 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1219 unsigned Success = RegInfo.createVirtualRegister(RC); 1220 1221 // insert new blocks after the current block 1222 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1223 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1224 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1225 MachineFunction::iterator It = BB; 1226 ++It; 1227 MF->insert(It, loopMBB); 1228 MF->insert(It, exitMBB); 1229 1230 // Transfer the remainder of BB and its successor edges to exitMBB. 1231 exitMBB->splice(exitMBB->begin(), BB, 1232 llvm::next(MachineBasicBlock::iterator(MI)), 1233 BB->end()); 1234 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1235 1236 // thisMBB: 1237 // ... 1238 // fallthrough --> loopMBB 1239 BB->addSuccessor(loopMBB); 1240 loopMBB->addSuccessor(loopMBB); 1241 loopMBB->addSuccessor(exitMBB); 1242 1243 // loopMBB: 1244 // ll oldval, 0(ptr) 1245 // <binop> storeval, oldval, incr 1246 // sc success, storeval, 0(ptr) 1247 // beq success, $0, loopMBB 1248 BB = loopMBB; 1249 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1250 if (Nand) { 1251 // and andres, oldval, incr 1252 // nor storeval, $0, andres 1253 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1254 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1255 } else if (BinOpcode) { 1256 // <binop> storeval, oldval, incr 1257 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1258 } else { 1259 StoreVal = Incr; 1260 } 1261 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1262 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1263 1264 MI->eraseFromParent(); // The instruction is gone now. 1265 1266 return exitMBB; 1267} 1268 1269MachineBasicBlock * 1270MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, 1271 MachineBasicBlock *BB, 1272 unsigned Size, unsigned BinOpcode, 1273 bool Nand) const { 1274 assert((Size == 1 || Size == 2) && 1275 "Unsupported size for EmitAtomicBinaryPartial."); 1276 1277 MachineFunction *MF = BB->getParent(); 1278 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1279 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1280 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1281 DebugLoc dl = MI->getDebugLoc(); 1282 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1283 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1284 1285 unsigned Dest = MI->getOperand(0).getReg(); 1286 unsigned Ptr = MI->getOperand(1).getReg(); 1287 unsigned Incr = MI->getOperand(2).getReg(); 1288 1289 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1290 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1291 unsigned Mask = RegInfo.createVirtualRegister(RC); 1292 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1293 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1294 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1295 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1296 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1297 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1298 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1299 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1300 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1301 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1302 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1303 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1304 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1305 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1306 unsigned Success = RegInfo.createVirtualRegister(RC); 1307 1308 // insert new blocks after the current block 1309 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1310 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1311 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1312 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1313 MachineFunction::iterator It = BB; 1314 ++It; 1315 MF->insert(It, loopMBB); 1316 MF->insert(It, sinkMBB); 1317 MF->insert(It, exitMBB); 1318 1319 // Transfer the remainder of BB and its successor edges to exitMBB. 1320 exitMBB->splice(exitMBB->begin(), BB, 1321 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1322 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1323 1324 BB->addSuccessor(loopMBB); 1325 loopMBB->addSuccessor(loopMBB); 1326 loopMBB->addSuccessor(sinkMBB); 1327 sinkMBB->addSuccessor(exitMBB); 1328 1329 // thisMBB: 1330 // addiu masklsb2,$0,-4 # 0xfffffffc 1331 // and alignedaddr,ptr,masklsb2 1332 // andi ptrlsb2,ptr,3 1333 // sll shiftamt,ptrlsb2,3 1334 // ori maskupper,$0,255 # 0xff 1335 // sll mask,maskupper,shiftamt 1336 // nor mask2,$0,mask 1337 // sll incr2,incr,shiftamt 1338 1339 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1340 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1341 .addReg(Mips::ZERO).addImm(-4); 1342 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1343 .addReg(Ptr).addReg(MaskLSB2); 1344 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1345 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1346 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1347 .addReg(Mips::ZERO).addImm(MaskImm); 1348 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1349 .addReg(ShiftAmt).addReg(MaskUpper); 1350 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1351 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); 1352 1353 // atomic.load.binop 1354 // loopMBB: 1355 // ll oldval,0(alignedaddr) 1356 // binop binopres,oldval,incr2 1357 // and newval,binopres,mask 1358 // and maskedoldval0,oldval,mask2 1359 // or storeval,maskedoldval0,newval 1360 // sc success,storeval,0(alignedaddr) 1361 // beq success,$0,loopMBB 1362 1363 // atomic.swap 1364 // loopMBB: 1365 // ll oldval,0(alignedaddr) 1366 // and newval,incr2,mask 1367 // and maskedoldval0,oldval,mask2 1368 // or storeval,maskedoldval0,newval 1369 // sc success,storeval,0(alignedaddr) 1370 // beq success,$0,loopMBB 1371 1372 BB = loopMBB; 1373 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1374 if (Nand) { 1375 // and andres, oldval, incr2 1376 // nor binopres, $0, andres 1377 // and newval, binopres, mask 1378 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1379 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes) 1380 .addReg(Mips::ZERO).addReg(AndRes); 1381 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1382 } else if (BinOpcode) { 1383 // <binop> binopres, oldval, incr2 1384 // and newval, binopres, mask 1385 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1386 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1387 } else {// atomic.swap 1388 // and newval, incr2, mask 1389 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1390 } 1391 1392 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1393 .addReg(OldVal).addReg(Mask2); 1394 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1395 .addReg(MaskedOldVal0).addReg(NewVal); 1396 BuildMI(BB, dl, TII->get(SC), Success) 1397 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1398 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1399 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1400 1401 // sinkMBB: 1402 // and maskedoldval1,oldval,mask 1403 // srl srlres,maskedoldval1,shiftamt 1404 // sll sllres,srlres,24 1405 // sra dest,sllres,24 1406 BB = sinkMBB; 1407 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1408 1409 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1410 .addReg(OldVal).addReg(Mask); 1411 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1412 .addReg(ShiftAmt).addReg(MaskedOldVal1); 1413 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1414 .addReg(SrlRes).addImm(ShiftImm); 1415 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1416 .addReg(SllRes).addImm(ShiftImm); 1417 1418 MI->eraseFromParent(); // The instruction is gone now. 1419 1420 return exitMBB; 1421} 1422 1423MachineBasicBlock * 1424MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 1425 MachineBasicBlock *BB, 1426 unsigned Size) const { 1427 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1428 1429 MachineFunction *MF = BB->getParent(); 1430 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1431 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1432 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1433 DebugLoc dl = MI->getDebugLoc(); 1434 unsigned LL, SC, ZERO, BNE, BEQ; 1435 1436 if (Size == 4) { 1437 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1438 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1439 ZERO = Mips::ZERO; 1440 BNE = Mips::BNE; 1441 BEQ = Mips::BEQ; 1442 } 1443 else { 1444 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 1445 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 1446 ZERO = Mips::ZERO_64; 1447 BNE = Mips::BNE64; 1448 BEQ = Mips::BEQ64; 1449 } 1450 1451 unsigned Dest = MI->getOperand(0).getReg(); 1452 unsigned Ptr = MI->getOperand(1).getReg(); 1453 unsigned OldVal = MI->getOperand(2).getReg(); 1454 unsigned NewVal = MI->getOperand(3).getReg(); 1455 1456 unsigned Success = RegInfo.createVirtualRegister(RC); 1457 1458 // insert new blocks after the current block 1459 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1460 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1461 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1462 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1463 MachineFunction::iterator It = BB; 1464 ++It; 1465 MF->insert(It, loop1MBB); 1466 MF->insert(It, loop2MBB); 1467 MF->insert(It, exitMBB); 1468 1469 // Transfer the remainder of BB and its successor edges to exitMBB. 1470 exitMBB->splice(exitMBB->begin(), BB, 1471 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1472 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1473 1474 // thisMBB: 1475 // ... 1476 // fallthrough --> loop1MBB 1477 BB->addSuccessor(loop1MBB); 1478 loop1MBB->addSuccessor(exitMBB); 1479 loop1MBB->addSuccessor(loop2MBB); 1480 loop2MBB->addSuccessor(loop1MBB); 1481 loop2MBB->addSuccessor(exitMBB); 1482 1483 // loop1MBB: 1484 // ll dest, 0(ptr) 1485 // bne dest, oldval, exitMBB 1486 BB = loop1MBB; 1487 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1488 BuildMI(BB, dl, TII->get(BNE)) 1489 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1490 1491 // loop2MBB: 1492 // sc success, newval, 0(ptr) 1493 // beq success, $0, loop1MBB 1494 BB = loop2MBB; 1495 BuildMI(BB, dl, TII->get(SC), Success) 1496 .addReg(NewVal).addReg(Ptr).addImm(0); 1497 BuildMI(BB, dl, TII->get(BEQ)) 1498 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1499 1500 MI->eraseFromParent(); // The instruction is gone now. 1501 1502 return exitMBB; 1503} 1504 1505MachineBasicBlock * 1506MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, 1507 MachineBasicBlock *BB, 1508 unsigned Size) const { 1509 assert((Size == 1 || Size == 2) && 1510 "Unsupported size for EmitAtomicCmpSwapPartial."); 1511 1512 MachineFunction *MF = BB->getParent(); 1513 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1514 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1515 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1516 DebugLoc dl = MI->getDebugLoc(); 1517 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1518 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1519 1520 unsigned Dest = MI->getOperand(0).getReg(); 1521 unsigned Ptr = MI->getOperand(1).getReg(); 1522 unsigned CmpVal = MI->getOperand(2).getReg(); 1523 unsigned NewVal = MI->getOperand(3).getReg(); 1524 1525 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1526 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1527 unsigned Mask = RegInfo.createVirtualRegister(RC); 1528 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1529 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1530 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1531 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1532 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1533 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1534 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1535 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1536 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1537 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1538 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1539 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1540 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1541 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1542 unsigned Success = RegInfo.createVirtualRegister(RC); 1543 1544 // insert new blocks after the current block 1545 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1546 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1547 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1548 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1549 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1550 MachineFunction::iterator It = BB; 1551 ++It; 1552 MF->insert(It, loop1MBB); 1553 MF->insert(It, loop2MBB); 1554 MF->insert(It, sinkMBB); 1555 MF->insert(It, exitMBB); 1556 1557 // Transfer the remainder of BB and its successor edges to exitMBB. 1558 exitMBB->splice(exitMBB->begin(), BB, 1559 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1560 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1561 1562 BB->addSuccessor(loop1MBB); 1563 loop1MBB->addSuccessor(sinkMBB); 1564 loop1MBB->addSuccessor(loop2MBB); 1565 loop2MBB->addSuccessor(loop1MBB); 1566 loop2MBB->addSuccessor(sinkMBB); 1567 sinkMBB->addSuccessor(exitMBB); 1568 1569 // FIXME: computation of newval2 can be moved to loop2MBB. 1570 // thisMBB: 1571 // addiu masklsb2,$0,-4 # 0xfffffffc 1572 // and alignedaddr,ptr,masklsb2 1573 // andi ptrlsb2,ptr,3 1574 // sll shiftamt,ptrlsb2,3 1575 // ori maskupper,$0,255 # 0xff 1576 // sll mask,maskupper,shiftamt 1577 // nor mask2,$0,mask 1578 // andi maskedcmpval,cmpval,255 1579 // sll shiftedcmpval,maskedcmpval,shiftamt 1580 // andi maskednewval,newval,255 1581 // sll shiftednewval,maskednewval,shiftamt 1582 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1583 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1584 .addReg(Mips::ZERO).addImm(-4); 1585 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1586 .addReg(Ptr).addReg(MaskLSB2); 1587 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1588 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1589 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1590 .addReg(Mips::ZERO).addImm(MaskImm); 1591 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1592 .addReg(ShiftAmt).addReg(MaskUpper); 1593 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1594 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) 1595 .addReg(CmpVal).addImm(MaskImm); 1596 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) 1597 .addReg(ShiftAmt).addReg(MaskedCmpVal); 1598 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) 1599 .addReg(NewVal).addImm(MaskImm); 1600 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) 1601 .addReg(ShiftAmt).addReg(MaskedNewVal); 1602 1603 // loop1MBB: 1604 // ll oldval,0(alginedaddr) 1605 // and maskedoldval0,oldval,mask 1606 // bne maskedoldval0,shiftedcmpval,sinkMBB 1607 BB = loop1MBB; 1608 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1609 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1610 .addReg(OldVal).addReg(Mask); 1611 BuildMI(BB, dl, TII->get(Mips::BNE)) 1612 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1613 1614 // loop2MBB: 1615 // and maskedoldval1,oldval,mask2 1616 // or storeval,maskedoldval1,shiftednewval 1617 // sc success,storeval,0(alignedaddr) 1618 // beq success,$0,loop1MBB 1619 BB = loop2MBB; 1620 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1621 .addReg(OldVal).addReg(Mask2); 1622 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1623 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1624 BuildMI(BB, dl, TII->get(SC), Success) 1625 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1626 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1627 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1628 1629 // sinkMBB: 1630 // srl srlres,maskedoldval0,shiftamt 1631 // sll sllres,srlres,24 1632 // sra dest,sllres,24 1633 BB = sinkMBB; 1634 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1635 1636 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1637 .addReg(ShiftAmt).addReg(MaskedOldVal0); 1638 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1639 .addReg(SrlRes).addImm(ShiftImm); 1640 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1641 .addReg(SllRes).addImm(ShiftImm); 1642 1643 MI->eraseFromParent(); // The instruction is gone now. 1644 1645 return exitMBB; 1646} 1647 1648//===----------------------------------------------------------------------===// 1649// Misc Lower Operation implementation 1650//===----------------------------------------------------------------------===// 1651SDValue MipsTargetLowering:: 1652LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1653{ 1654 // The first operand is the chain, the second is the condition, the third is 1655 // the block to branch to if the condition is true. 1656 SDValue Chain = Op.getOperand(0); 1657 SDValue Dest = Op.getOperand(2); 1658 DebugLoc dl = Op.getDebugLoc(); 1659 1660 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 1661 1662 // Return if flag is not set by a floating point comparison. 1663 if (CondRes.getOpcode() != MipsISD::FPCmp) 1664 return Op; 1665 1666 SDValue CCNode = CondRes.getOperand(2); 1667 Mips::CondCode CC = 1668 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1669 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 1670 1671 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 1672 Dest, CondRes); 1673} 1674 1675SDValue MipsTargetLowering:: 1676LowerSELECT(SDValue Op, SelectionDAG &DAG) const 1677{ 1678 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 1679 1680 // Return if flag is not set by a floating point comparison. 1681 if (Cond.getOpcode() != MipsISD::FPCmp) 1682 return Op; 1683 1684 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1685 Op.getDebugLoc()); 1686} 1687 1688SDValue MipsTargetLowering:: 1689LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 1690{ 1691 DebugLoc DL = Op.getDebugLoc(); 1692 EVT Ty = Op.getOperand(0).getValueType(); 1693 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty), 1694 Op.getOperand(0), Op.getOperand(1), 1695 Op.getOperand(4)); 1696 1697 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2), 1698 Op.getOperand(3)); 1699} 1700 1701SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1702 SDValue Cond = CreateFPCmp(DAG, Op); 1703 1704 assert(Cond.getOpcode() == MipsISD::FPCmp && 1705 "Floating point operand expected."); 1706 1707 SDValue True = DAG.getConstant(1, MVT::i32); 1708 SDValue False = DAG.getConstant(0, MVT::i32); 1709 1710 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc()); 1711} 1712 1713SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 1714 SelectionDAG &DAG) const { 1715 // FIXME there isn't actually debug info here 1716 DebugLoc dl = Op.getDebugLoc(); 1717 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1718 1719 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1720 SDVTList VTs = DAG.getVTList(MVT::i32); 1721 1722 const MipsTargetObjectFile &TLOF = 1723 (const MipsTargetObjectFile&)getObjFileLowering(); 1724 1725 // %gp_rel relocation 1726 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1727 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1728 MipsII::MO_GPREL); 1729 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1); 1730 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32); 1731 return DAG.getNode(ISD::ADD, dl, MVT::i32, GPReg, GPRelNode); 1732 } 1733 // %hi/%lo relocation 1734 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1735 MipsII::MO_ABS_HI); 1736 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1737 MipsII::MO_ABS_LO); 1738 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1); 1739 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 1740 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1741 } 1742 1743 EVT ValTy = Op.getValueType(); 1744 bool HasGotOfst = (GV->hasInternalLinkage() || 1745 (GV->hasLocalLinkage() && !isa<Function>(GV))); 1746 unsigned GotFlag = HasMips64 ? 1747 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) : 1748 (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16); 1749 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag); 1750 GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), GA); 1751 SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA, 1752 MachinePointerInfo(), false, false, false, 0); 1753 // On functions and global targets not internal linked only 1754 // a load from got/GP is necessary for PIC to work. 1755 if (!HasGotOfst) 1756 return ResNode; 1757 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, 1758 HasMips64 ? MipsII::MO_GOT_OFST : 1759 MipsII::MO_ABS_LO); 1760 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo); 1761 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo); 1762} 1763 1764SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 1765 SelectionDAG &DAG) const { 1766 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1767 // FIXME there isn't actually debug info here 1768 DebugLoc dl = Op.getDebugLoc(); 1769 1770 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1771 // %hi/%lo relocation 1772 SDValue BAHi = 1773 DAG.getTargetBlockAddress(BA, MVT::i32, 0, MipsII::MO_ABS_HI); 1774 SDValue BALo = 1775 DAG.getTargetBlockAddress(BA, MVT::i32, 0, MipsII::MO_ABS_LO); 1776 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi); 1777 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo); 1778 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1779 } 1780 1781 EVT ValTy = Op.getValueType(); 1782 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1783 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1784 SDValue BAGOTOffset = DAG.getTargetBlockAddress(BA, ValTy, 0, GOTFlag); 1785 BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy, 1786 GetGlobalReg(DAG, ValTy), BAGOTOffset); 1787 SDValue BALOOffset = DAG.getTargetBlockAddress(BA, ValTy, 0, OFSTFlag); 1788 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset, 1789 MachinePointerInfo(), false, false, false, 0); 1790 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset); 1791 return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo); 1792} 1793 1794SDValue MipsTargetLowering:: 1795LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1796{ 1797 // If the relocation model is PIC, use the General Dynamic TLS Model or 1798 // Local Dynamic TLS model, otherwise use the Initial Exec or 1799 // Local Exec TLS Model. 1800 1801 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1802 DebugLoc dl = GA->getDebugLoc(); 1803 const GlobalValue *GV = GA->getGlobal(); 1804 EVT PtrVT = getPointerTy(); 1805 1806 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1807 1808 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1809 // General Dynamic and Local Dynamic TLS Model. 1810 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1811 : MipsII::MO_TLSGD; 1812 1813 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag); 1814 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, 1815 GetGlobalReg(DAG, PtrVT), TGA); 1816 unsigned PtrSize = PtrVT.getSizeInBits(); 1817 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1818 1819 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1820 1821 ArgListTy Args; 1822 ArgListEntry Entry; 1823 Entry.Node = Argument; 1824 Entry.Ty = PtrTy; 1825 Args.push_back(Entry); 1826 1827 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy, 1828 false, false, false, false, 0, CallingConv::C, 1829 /*isTailCall=*/false, /*doesNotRet=*/false, 1830 /*isReturnValueUsed=*/true, 1831 TlsGetAddr, Args, DAG, dl); 1832 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1833 1834 SDValue Ret = CallResult.first; 1835 1836 if (model != TLSModel::LocalDynamic) 1837 return Ret; 1838 1839 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1840 MipsII::MO_DTPREL_HI); 1841 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 1842 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1843 MipsII::MO_DTPREL_LO); 1844 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 1845 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret); 1846 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo); 1847 } 1848 1849 SDValue Offset; 1850 if (model == TLSModel::InitialExec) { 1851 // Initial Exec TLS Model 1852 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1853 MipsII::MO_GOTTPREL); 1854 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT), 1855 TGA); 1856 Offset = DAG.getLoad(PtrVT, dl, 1857 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1858 false, false, false, 0); 1859 } else { 1860 // Local Exec TLS Model 1861 assert(model == TLSModel::LocalExec); 1862 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1863 MipsII::MO_TPREL_HI); 1864 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1865 MipsII::MO_TPREL_LO); 1866 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 1867 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 1868 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1869 } 1870 1871 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT); 1872 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1873} 1874 1875SDValue MipsTargetLowering:: 1876LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1877{ 1878 SDValue HiPart, JTI, JTILo; 1879 // FIXME there isn't actually debug info here 1880 DebugLoc dl = Op.getDebugLoc(); 1881 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1882 EVT PtrVT = Op.getValueType(); 1883 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1884 1885 if (!IsPIC && !IsN64) { 1886 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_HI); 1887 HiPart = DAG.getNode(MipsISD::Hi, dl, PtrVT, JTI); 1888 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO); 1889 } else {// Emit Load from Global Pointer 1890 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1891 unsigned OfstFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1892 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, GOTFlag); 1893 JTI = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT), 1894 JTI); 1895 HiPart = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), JTI, 1896 MachinePointerInfo(), false, false, false, 0); 1897 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OfstFlag); 1898 } 1899 1900 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo); 1901 return DAG.getNode(ISD::ADD, dl, PtrVT, HiPart, Lo); 1902} 1903 1904SDValue MipsTargetLowering:: 1905LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1906{ 1907 SDValue ResNode; 1908 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1909 const Constant *C = N->getConstVal(); 1910 // FIXME there isn't actually debug info here 1911 DebugLoc dl = Op.getDebugLoc(); 1912 1913 // gp_rel relocation 1914 // FIXME: we should reference the constant pool using small data sections, 1915 // but the asm printer currently doesn't support this feature without 1916 // hacking it. This feature should come soon so we can uncomment the 1917 // stuff below. 1918 //if (IsInSmallSection(C->getType())) { 1919 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1920 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1921 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1922 1923 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1924 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1925 N->getOffset(), MipsII::MO_ABS_HI); 1926 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1927 N->getOffset(), MipsII::MO_ABS_LO); 1928 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi); 1929 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1930 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1931 } else { 1932 EVT ValTy = Op.getValueType(); 1933 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1934 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1935 SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(), 1936 N->getOffset(), GOTFlag); 1937 CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), CP); 1938 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP, 1939 MachinePointerInfo::getConstantPool(), false, 1940 false, false, 0); 1941 SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(), 1942 N->getOffset(), OFSTFlag); 1943 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo); 1944 ResNode = DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo); 1945 } 1946 1947 return ResNode; 1948} 1949 1950SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1951 MachineFunction &MF = DAG.getMachineFunction(); 1952 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1953 1954 DebugLoc dl = Op.getDebugLoc(); 1955 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1956 getPointerTy()); 1957 1958 // vastart just stores the address of the VarArgsFrameIndex slot into the 1959 // memory location argument. 1960 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1961 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 1962 MachinePointerInfo(SV), false, false, 0); 1963} 1964 1965static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1966 EVT TyX = Op.getOperand(0).getValueType(); 1967 EVT TyY = Op.getOperand(1).getValueType(); 1968 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1969 SDValue Const31 = DAG.getConstant(31, MVT::i32); 1970 DebugLoc DL = Op.getDebugLoc(); 1971 SDValue Res; 1972 1973 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1974 // to i32. 1975 SDValue X = (TyX == MVT::f32) ? 1976 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1977 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1978 Const1); 1979 SDValue Y = (TyY == MVT::f32) ? 1980 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 1981 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 1982 Const1); 1983 1984 if (HasR2) { 1985 // ext E, Y, 31, 1 ; extract bit31 of Y 1986 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 1987 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 1988 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 1989 } else { 1990 // sll SllX, X, 1 1991 // srl SrlX, SllX, 1 1992 // srl SrlY, Y, 31 1993 // sll SllY, SrlX, 31 1994 // or Or, SrlX, SllY 1995 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1996 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1997 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 1998 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 1999 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2000 } 2001 2002 if (TyX == MVT::f32) 2003 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2004 2005 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2006 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 2007 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2008} 2009 2010static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 2011 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2012 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2013 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2014 SDValue Const1 = DAG.getConstant(1, MVT::i32); 2015 DebugLoc DL = Op.getDebugLoc(); 2016 2017 // Bitcast to integer nodes. 2018 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2019 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2020 2021 if (HasR2) { 2022 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2023 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2024 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2025 DAG.getConstant(WidthY - 1, MVT::i32), Const1); 2026 2027 if (WidthX > WidthY) 2028 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2029 else if (WidthY > WidthX) 2030 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2031 2032 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2033 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X); 2034 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2035 } 2036 2037 // (d)sll SllX, X, 1 2038 // (d)srl SrlX, SllX, 1 2039 // (d)srl SrlY, Y, width(Y)-1 2040 // (d)sll SllY, SrlX, width(Y)-1 2041 // or Or, SrlX, SllY 2042 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2043 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2044 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2045 DAG.getConstant(WidthY - 1, MVT::i32)); 2046 2047 if (WidthX > WidthY) 2048 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2049 else if (WidthY > WidthX) 2050 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2051 2052 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2053 DAG.getConstant(WidthX - 1, MVT::i32)); 2054 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2055 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2056} 2057 2058SDValue 2059MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2060 if (Subtarget->hasMips64()) 2061 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2()); 2062 2063 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2()); 2064} 2065 2066static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 2067 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 2068 DebugLoc DL = Op.getDebugLoc(); 2069 2070 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2071 // to i32. 2072 SDValue X = (Op.getValueType() == MVT::f32) ? 2073 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2074 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2075 Const1); 2076 2077 // Clear MSB. 2078 if (HasR2) 2079 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 2080 DAG.getRegister(Mips::ZERO, MVT::i32), 2081 DAG.getConstant(31, MVT::i32), Const1, X); 2082 else { 2083 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2084 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2085 } 2086 2087 if (Op.getValueType() == MVT::f32) 2088 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 2089 2090 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2091 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 2092 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2093} 2094 2095static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 2096 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 2097 DebugLoc DL = Op.getDebugLoc(); 2098 2099 // Bitcast to integer node. 2100 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 2101 2102 // Clear MSB. 2103 if (HasR2) 2104 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 2105 DAG.getRegister(Mips::ZERO_64, MVT::i64), 2106 DAG.getConstant(63, MVT::i32), Const1, X); 2107 else { 2108 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 2109 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 2110 } 2111 2112 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 2113} 2114 2115SDValue 2116MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const { 2117 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64)) 2118 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2()); 2119 2120 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2()); 2121} 2122 2123SDValue MipsTargetLowering:: 2124LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2125 // check the depth 2126 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2127 "Frame address can only be determined for current frame."); 2128 2129 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2130 MFI->setFrameAddressIsTaken(true); 2131 EVT VT = Op.getValueType(); 2132 DebugLoc dl = Op.getDebugLoc(); 2133 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 2134 IsN64 ? Mips::FP_64 : Mips::FP, VT); 2135 return FrameAddr; 2136} 2137 2138SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op, 2139 SelectionDAG &DAG) const { 2140 // check the depth 2141 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2142 "Return address can be determined only for current frame."); 2143 2144 MachineFunction &MF = DAG.getMachineFunction(); 2145 MachineFrameInfo *MFI = MF.getFrameInfo(); 2146 EVT VT = Op.getValueType(); 2147 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA; 2148 MFI->setReturnAddressIsTaken(true); 2149 2150 // Return RA, which contains the return address. Mark it an implicit live-in. 2151 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2152 return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT); 2153} 2154 2155// TODO: set SType according to the desired memory barrier behavior. 2156SDValue 2157MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const { 2158 unsigned SType = 0; 2159 DebugLoc dl = Op.getDebugLoc(); 2160 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 2161 DAG.getConstant(SType, MVT::i32)); 2162} 2163 2164SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op, 2165 SelectionDAG &DAG) const { 2166 // FIXME: Need pseudo-fence for 'singlethread' fences 2167 // FIXME: Set SType for weaker fences where supported/appropriate. 2168 unsigned SType = 0; 2169 DebugLoc dl = Op.getDebugLoc(); 2170 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 2171 DAG.getConstant(SType, MVT::i32)); 2172} 2173 2174SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op, 2175 SelectionDAG &DAG) const { 2176 DebugLoc DL = Op.getDebugLoc(); 2177 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2178 SDValue Shamt = Op.getOperand(2); 2179 2180 // if shamt < 32: 2181 // lo = (shl lo, shamt) 2182 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2183 // else: 2184 // lo = 0 2185 // hi = (shl lo, shamt[4:0]) 2186 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2187 DAG.getConstant(-1, MVT::i32)); 2188 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, 2189 DAG.getConstant(1, MVT::i32)); 2190 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, 2191 Not); 2192 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); 2193 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 2194 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); 2195 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2196 DAG.getConstant(0x20, MVT::i32)); 2197 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 2198 DAG.getConstant(0, MVT::i32), ShiftLeftLo); 2199 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or); 2200 2201 SDValue Ops[2] = {Lo, Hi}; 2202 return DAG.getMergeValues(Ops, 2, DL); 2203} 2204 2205SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2206 bool IsSRA) const { 2207 DebugLoc DL = Op.getDebugLoc(); 2208 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2209 SDValue Shamt = Op.getOperand(2); 2210 2211 // if shamt < 32: 2212 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2213 // if isSRA: 2214 // hi = (sra hi, shamt) 2215 // else: 2216 // hi = (srl hi, shamt) 2217 // else: 2218 // if isSRA: 2219 // lo = (sra hi, shamt[4:0]) 2220 // hi = (sra hi, 31) 2221 // else: 2222 // lo = (srl hi, shamt[4:0]) 2223 // hi = 0 2224 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2225 DAG.getConstant(-1, MVT::i32)); 2226 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, 2227 DAG.getConstant(1, MVT::i32)); 2228 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not); 2229 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); 2230 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 2231 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, 2232 Hi, Shamt); 2233 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2234 DAG.getConstant(0x20, MVT::i32)); 2235 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi, 2236 DAG.getConstant(31, MVT::i32)); 2237 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or); 2238 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 2239 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32), 2240 ShiftRightHi); 2241 2242 SDValue Ops[2] = {Lo, Hi}; 2243 return DAG.getMergeValues(Ops, 2, DL); 2244} 2245 2246static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2247 SDValue Chain, SDValue Src, unsigned Offset) { 2248 SDValue Ptr = LD->getBasePtr(); 2249 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2250 EVT BasePtrVT = Ptr.getValueType(); 2251 DebugLoc DL = LD->getDebugLoc(); 2252 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2253 2254 if (Offset) 2255 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2256 DAG.getConstant(Offset, BasePtrVT)); 2257 2258 SDValue Ops[] = { Chain, Ptr, Src }; 2259 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2260 LD->getMemOperand()); 2261} 2262 2263// Expand an unaligned 32 or 64-bit integer load node. 2264SDValue MipsTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2265 LoadSDNode *LD = cast<LoadSDNode>(Op); 2266 EVT MemVT = LD->getMemoryVT(); 2267 2268 // Return if load is aligned or if MemVT is neither i32 nor i64. 2269 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2270 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2271 return SDValue(); 2272 2273 bool IsLittle = Subtarget->isLittle(); 2274 EVT VT = Op.getValueType(); 2275 ISD::LoadExtType ExtType = LD->getExtensionType(); 2276 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2277 2278 assert((VT == MVT::i32) || (VT == MVT::i64)); 2279 2280 // Expand 2281 // (set dst, (i64 (load baseptr))) 2282 // to 2283 // (set tmp, (ldl (add baseptr, 7), undef)) 2284 // (set dst, (ldr baseptr, tmp)) 2285 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2286 SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2287 IsLittle ? 7 : 0); 2288 return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2289 IsLittle ? 0 : 7); 2290 } 2291 2292 SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2293 IsLittle ? 3 : 0); 2294 SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2295 IsLittle ? 0 : 3); 2296 2297 // Expand 2298 // (set dst, (i32 (load baseptr))) or 2299 // (set dst, (i64 (sextload baseptr))) or 2300 // (set dst, (i64 (extload baseptr))) 2301 // to 2302 // (set tmp, (lwl (add baseptr, 3), undef)) 2303 // (set dst, (lwr baseptr, tmp)) 2304 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2305 (ExtType == ISD::EXTLOAD)) 2306 return LWR; 2307 2308 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2309 2310 // Expand 2311 // (set dst, (i64 (zextload baseptr))) 2312 // to 2313 // (set tmp0, (lwl (add baseptr, 3), undef)) 2314 // (set tmp1, (lwr baseptr, tmp0)) 2315 // (set tmp2, (shl tmp1, 32)) 2316 // (set dst, (srl tmp2, 32)) 2317 DebugLoc DL = LD->getDebugLoc(); 2318 SDValue Const32 = DAG.getConstant(32, MVT::i32); 2319 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2320 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2321 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2322 return DAG.getMergeValues(Ops, 2, DL); 2323} 2324 2325static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2326 SDValue Chain, unsigned Offset) { 2327 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2328 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2329 DebugLoc DL = SD->getDebugLoc(); 2330 SDVTList VTList = DAG.getVTList(MVT::Other); 2331 2332 if (Offset) 2333 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2334 DAG.getConstant(Offset, BasePtrVT)); 2335 2336 SDValue Ops[] = { Chain, Value, Ptr }; 2337 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2338 SD->getMemOperand()); 2339} 2340 2341// Expand an unaligned 32 or 64-bit integer store node. 2342SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2343 StoreSDNode *SD = cast<StoreSDNode>(Op); 2344 EVT MemVT = SD->getMemoryVT(); 2345 2346 // Return if store is aligned or if MemVT is neither i32 nor i64. 2347 if ((SD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2348 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2349 return SDValue(); 2350 2351 bool IsLittle = Subtarget->isLittle(); 2352 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2353 EVT VT = Value.getValueType(); 2354 2355 // Expand 2356 // (store val, baseptr) or 2357 // (truncstore val, baseptr) 2358 // to 2359 // (swl val, (add baseptr, 3)) 2360 // (swr val, baseptr) 2361 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2362 SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain, 2363 IsLittle ? 3 : 0); 2364 return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2365 } 2366 2367 assert(VT == MVT::i64); 2368 2369 // Expand 2370 // (store val, baseptr) 2371 // to 2372 // (sdl val, (add baseptr, 7)) 2373 // (sdr val, baseptr) 2374 SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2375 return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2376} 2377 2378// This function expands mips intrinsic nodes which have 64-bit input operands 2379// or output values. 2380// 2381// out64 = intrinsic-node in64 2382// => 2383// lo = copy (extract-element (in64, 0)) 2384// hi = copy (extract-element (in64, 1)) 2385// mips-specific-node 2386// v0 = copy lo 2387// v1 = copy hi 2388// out64 = merge-values (v0, v1) 2389// 2390static SDValue LowerDSPIntr(SDValue Op, SelectionDAG &DAG, 2391 unsigned Opc, bool HasI64In, bool HasI64Out) { 2392 DebugLoc DL = Op.getDebugLoc(); 2393 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other; 2394 SDValue Chain = HasChainIn ? Op->getOperand(0) : DAG.getEntryNode(); 2395 SmallVector<SDValue, 3> Ops; 2396 2397 if (HasI64In) { 2398 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, 2399 Op->getOperand(1 + HasChainIn), 2400 DAG.getConstant(0, MVT::i32)); 2401 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, 2402 Op->getOperand(1 + HasChainIn), 2403 DAG.getConstant(1, MVT::i32)); 2404 2405 Chain = DAG.getCopyToReg(Chain, DL, Mips::LO, InLo, SDValue()); 2406 Chain = DAG.getCopyToReg(Chain, DL, Mips::HI, InHi, Chain.getValue(1)); 2407 2408 Ops.push_back(Chain); 2409 Ops.append(Op->op_begin() + HasChainIn + 2, Op->op_end()); 2410 Ops.push_back(Chain.getValue(1)); 2411 } else { 2412 Ops.push_back(Chain); 2413 Ops.append(Op->op_begin() + HasChainIn + 1, Op->op_end()); 2414 } 2415 2416 if (!HasI64Out) 2417 return DAG.getNode(Opc, DL, Op->value_begin(), Op->getNumValues(), 2418 Ops.begin(), Ops.size()); 2419 2420 SDValue Intr = DAG.getNode(Opc, DL, DAG.getVTList(MVT::Other, MVT::Glue), 2421 Ops.begin(), Ops.size()); 2422 SDValue OutLo = DAG.getCopyFromReg(Intr.getValue(0), DL, Mips::LO, MVT::i32, 2423 Intr.getValue(1)); 2424 SDValue OutHi = DAG.getCopyFromReg(OutLo.getValue(1), DL, Mips::HI, MVT::i32, 2425 OutLo.getValue(2)); 2426 SDValue Out = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, OutLo, OutHi); 2427 2428 if (!HasChainIn) 2429 return Out; 2430 2431 SDValue Vals[] = { Out, OutHi.getValue(1) }; 2432 return DAG.getMergeValues(Vals, 2, DL); 2433} 2434 2435SDValue MipsTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 2436 SelectionDAG &DAG) const { 2437 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) { 2438 default: 2439 return SDValue(); 2440 case Intrinsic::mips_shilo: 2441 return LowerDSPIntr(Op, DAG, MipsISD::SHILO, true, true); 2442 case Intrinsic::mips_dpau_h_qbl: 2443 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL, true, true); 2444 case Intrinsic::mips_dpau_h_qbr: 2445 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR, true, true); 2446 case Intrinsic::mips_dpsu_h_qbl: 2447 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL, true, true); 2448 case Intrinsic::mips_dpsu_h_qbr: 2449 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR, true, true); 2450 case Intrinsic::mips_dpa_w_ph: 2451 return LowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH, true, true); 2452 case Intrinsic::mips_dps_w_ph: 2453 return LowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH, true, true); 2454 case Intrinsic::mips_dpax_w_ph: 2455 return LowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH, true, true); 2456 case Intrinsic::mips_dpsx_w_ph: 2457 return LowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH, true, true); 2458 case Intrinsic::mips_mulsa_w_ph: 2459 return LowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH, true, true); 2460 case Intrinsic::mips_mult: 2461 return LowerDSPIntr(Op, DAG, MipsISD::MULT, false, true); 2462 case Intrinsic::mips_multu: 2463 return LowerDSPIntr(Op, DAG, MipsISD::MULTU, false, true); 2464 case Intrinsic::mips_madd: 2465 return LowerDSPIntr(Op, DAG, MipsISD::MADD_DSP, true, true); 2466 case Intrinsic::mips_maddu: 2467 return LowerDSPIntr(Op, DAG, MipsISD::MADDU_DSP, true, true); 2468 case Intrinsic::mips_msub: 2469 return LowerDSPIntr(Op, DAG, MipsISD::MSUB_DSP, true, true); 2470 case Intrinsic::mips_msubu: 2471 return LowerDSPIntr(Op, DAG, MipsISD::MSUBU_DSP, true, true); 2472 } 2473} 2474 2475SDValue MipsTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, 2476 SelectionDAG &DAG) const { 2477 switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) { 2478 default: 2479 return SDValue(); 2480 case Intrinsic::mips_extp: 2481 return LowerDSPIntr(Op, DAG, MipsISD::EXTP, true, false); 2482 case Intrinsic::mips_extpdp: 2483 return LowerDSPIntr(Op, DAG, MipsISD::EXTPDP, true, false); 2484 case Intrinsic::mips_extr_w: 2485 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_W, true, false); 2486 case Intrinsic::mips_extr_r_w: 2487 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W, true, false); 2488 case Intrinsic::mips_extr_rs_w: 2489 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W, true, false); 2490 case Intrinsic::mips_extr_s_h: 2491 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H, true, false); 2492 case Intrinsic::mips_mthlip: 2493 return LowerDSPIntr(Op, DAG, MipsISD::MTHLIP, true, true); 2494 case Intrinsic::mips_mulsaq_s_w_ph: 2495 return LowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH, true, true); 2496 case Intrinsic::mips_maq_s_w_phl: 2497 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL, true, true); 2498 case Intrinsic::mips_maq_s_w_phr: 2499 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR, true, true); 2500 case Intrinsic::mips_maq_sa_w_phl: 2501 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL, true, true); 2502 case Intrinsic::mips_maq_sa_w_phr: 2503 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR, true, true); 2504 case Intrinsic::mips_dpaq_s_w_ph: 2505 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH, true, true); 2506 case Intrinsic::mips_dpsq_s_w_ph: 2507 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH, true, true); 2508 case Intrinsic::mips_dpaq_sa_l_w: 2509 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W, true, true); 2510 case Intrinsic::mips_dpsq_sa_l_w: 2511 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W, true, true); 2512 case Intrinsic::mips_dpaqx_s_w_ph: 2513 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH, true, true); 2514 case Intrinsic::mips_dpaqx_sa_w_ph: 2515 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH, true, true); 2516 case Intrinsic::mips_dpsqx_s_w_ph: 2517 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH, true, true); 2518 case Intrinsic::mips_dpsqx_sa_w_ph: 2519 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH, true, true); 2520 } 2521} 2522 2523//===----------------------------------------------------------------------===// 2524// Calling Convention Implementation 2525//===----------------------------------------------------------------------===// 2526 2527//===----------------------------------------------------------------------===// 2528// TODO: Implement a generic logic using tblgen that can support this. 2529// Mips O32 ABI rules: 2530// --- 2531// i32 - Passed in A0, A1, A2, A3 and stack 2532// f32 - Only passed in f32 registers if no int reg has been used yet to hold 2533// an argument. Otherwise, passed in A1, A2, A3 and stack. 2534// f64 - Only passed in two aliased f32 registers if no int reg has been used 2535// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2536// not used, it must be shadowed. If only A3 is avaiable, shadow it and 2537// go to stack. 2538// 2539// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2540//===----------------------------------------------------------------------===// 2541 2542static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 2543 MVT LocVT, CCValAssign::LocInfo LocInfo, 2544 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2545 2546 static const unsigned IntRegsSize=4, FloatRegsSize=2; 2547 2548 static const uint16_t IntRegs[] = { 2549 Mips::A0, Mips::A1, Mips::A2, Mips::A3 2550 }; 2551 static const uint16_t F32Regs[] = { 2552 Mips::F12, Mips::F14 2553 }; 2554 static const uint16_t F64Regs[] = { 2555 Mips::D6, Mips::D7 2556 }; 2557 2558 // Do not process byval args here. 2559 if (ArgFlags.isByVal()) 2560 return true; 2561 2562 // Promote i8 and i16 2563 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2564 LocVT = MVT::i32; 2565 if (ArgFlags.isSExt()) 2566 LocInfo = CCValAssign::SExt; 2567 else if (ArgFlags.isZExt()) 2568 LocInfo = CCValAssign::ZExt; 2569 else 2570 LocInfo = CCValAssign::AExt; 2571 } 2572 2573 unsigned Reg; 2574 2575 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2576 // is true: function is vararg, argument is 3rd or higher, there is previous 2577 // argument which is not f32 or f64. 2578 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 2579 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 2580 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2581 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2582 2583 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2584 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2585 // If this is the first part of an i64 arg, 2586 // the allocated register must be either A0 or A2. 2587 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2588 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2589 LocVT = MVT::i32; 2590 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2591 // Allocate int register and shadow next int register. If first 2592 // available register is Mips::A1 or Mips::A3, shadow it too. 2593 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2594 if (Reg == Mips::A1 || Reg == Mips::A3) 2595 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2596 State.AllocateReg(IntRegs, IntRegsSize); 2597 LocVT = MVT::i32; 2598 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2599 // we are guaranteed to find an available float register 2600 if (ValVT == MVT::f32) { 2601 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 2602 // Shadow int register 2603 State.AllocateReg(IntRegs, IntRegsSize); 2604 } else { 2605 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 2606 // Shadow int registers 2607 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 2608 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2609 State.AllocateReg(IntRegs, IntRegsSize); 2610 State.AllocateReg(IntRegs, IntRegsSize); 2611 } 2612 } else 2613 llvm_unreachable("Cannot handle this ValVT."); 2614 2615 if (!Reg) { 2616 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2617 OrigAlign); 2618 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2619 } else 2620 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2621 2622 return false; 2623} 2624 2625#include "MipsGenCallingConv.inc" 2626 2627//===----------------------------------------------------------------------===// 2628// Call Calling Convention Implementation 2629//===----------------------------------------------------------------------===// 2630 2631static const unsigned O32IntRegsSize = 4; 2632 2633// Return next O32 integer argument register. 2634static unsigned getNextIntArgReg(unsigned Reg) { 2635 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2636 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2637} 2638 2639/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2640/// for tail call optimization. 2641bool MipsTargetLowering:: 2642IsEligibleForTailCallOptimization(CallingConv::ID CalleeCC, 2643 unsigned NextStackOffset) const { 2644 if (!EnableMipsTailCalls) 2645 return false; 2646 2647 // Do not tail-call optimize if there is an argument passed on stack. 2648 if (IsO32 && (CalleeCC != CallingConv::Fast)) { 2649 if (NextStackOffset > 16) 2650 return false; 2651 } else if (NextStackOffset) 2652 return false; 2653 2654 return true; 2655} 2656 2657/// LowerCall - functions arguments are copied from virtual regs to 2658/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2659SDValue 2660MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2661 SmallVectorImpl<SDValue> &InVals) const { 2662 SelectionDAG &DAG = CLI.DAG; 2663 DebugLoc &dl = CLI.DL; 2664 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 2665 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 2666 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 2667 SDValue Chain = CLI.Chain; 2668 SDValue Callee = CLI.Callee; 2669 bool &isTailCall = CLI.IsTailCall; 2670 CallingConv::ID CallConv = CLI.CallConv; 2671 bool isVarArg = CLI.IsVarArg; 2672 2673 MachineFunction &MF = DAG.getMachineFunction(); 2674 MachineFrameInfo *MFI = MF.getFrameInfo(); 2675 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 2676 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2677 2678 // Analyze operands of the call, assigning locations to each operand. 2679 SmallVector<CCValAssign, 16> ArgLocs; 2680 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2681 getTargetMachine(), ArgLocs, *DAG.getContext()); 2682 MipsCC MipsCCInfo(CallConv, isVarArg, IsO32, CCInfo); 2683 2684 MipsCCInfo.analyzeCallOperands(Outs); 2685 2686 // Get a count of how many bytes are to be pushed on the stack. 2687 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2688 unsigned StackAlignment = TFL->getStackAlignment(); 2689 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment); 2690 2691 // Check if it's really possible to do a tail call. 2692 if (isTailCall) 2693 isTailCall = IsEligibleForTailCallOptimization(CallConv, NextStackOffset); 2694 2695 if (isTailCall) 2696 ++NumTailCalls; 2697 2698 // Chain is the output chain of the last Load/Store or CopyToReg node. 2699 // ByValChain is the output chain of the last Memcpy node created for copying 2700 // byval arguments to the stack. 2701 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 2702 2703 if (!isTailCall) 2704 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal); 2705 2706 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, 2707 IsN64 ? Mips::SP_64 : Mips::SP, 2708 getPointerTy()); 2709 2710 // With EABI is it possible to have 16 args on registers. 2711 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 2712 SmallVector<SDValue, 8> MemOpChains; 2713 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 2714 2715 // Walk the register/memloc assignments, inserting copies/loads. 2716 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2717 SDValue Arg = OutVals[i]; 2718 CCValAssign &VA = ArgLocs[i]; 2719 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2720 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2721 2722 // ByVal Arg. 2723 if (Flags.isByVal()) { 2724 assert(Flags.getByValSize() && 2725 "ByVal args of size 0 should have been ignored by front-end."); 2726 assert(ByValArg != MipsCCInfo.byval_end()); 2727 passByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2728 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle()); 2729 ++ByValArg; 2730 continue; 2731 } 2732 2733 // Promote the value if needed. 2734 switch (VA.getLocInfo()) { 2735 default: llvm_unreachable("Unknown loc info!"); 2736 case CCValAssign::Full: 2737 if (VA.isRegLoc()) { 2738 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2739 (ValVT == MVT::f64 && LocVT == MVT::i64)) 2740 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg); 2741 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2742 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2743 Arg, DAG.getConstant(0, MVT::i32)); 2744 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2745 Arg, DAG.getConstant(1, MVT::i32)); 2746 if (!Subtarget->isLittle()) 2747 std::swap(Lo, Hi); 2748 unsigned LocRegLo = VA.getLocReg(); 2749 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2750 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2751 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2752 continue; 2753 } 2754 } 2755 break; 2756 case CCValAssign::SExt: 2757 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg); 2758 break; 2759 case CCValAssign::ZExt: 2760 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg); 2761 break; 2762 case CCValAssign::AExt: 2763 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg); 2764 break; 2765 } 2766 2767 // Arguments that can be passed on register must be kept at 2768 // RegsToPass vector 2769 if (VA.isRegLoc()) { 2770 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2771 continue; 2772 } 2773 2774 // Register can't get to this point... 2775 assert(VA.isMemLoc()); 2776 2777 // emit ISD::STORE whichs stores the 2778 // parameter value to a stack Location 2779 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, 2780 DAG.getIntPtrConstant(VA.getLocMemOffset())); 2781 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2782 MachinePointerInfo(), false, false, 0)); 2783 } 2784 2785 // Transform all store nodes into one single node because all store 2786 // nodes are independent of each other. 2787 if (!MemOpChains.empty()) 2788 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2789 &MemOpChains[0], MemOpChains.size()); 2790 2791 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2792 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2793 // node so that legalize doesn't hack it. 2794 unsigned char OpFlag; 2795 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25 2796 bool GlobalOrExternal = false; 2797 SDValue CalleeLo; 2798 2799 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2800 if (IsPICCall && G->getGlobal()->hasInternalLinkage()) { 2801 OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE; 2802 unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST; 2803 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0, 2804 OpFlag); 2805 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 2806 0, LoFlag); 2807 } else { 2808 OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG; 2809 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2810 getPointerTy(), 0, OpFlag); 2811 } 2812 2813 GlobalOrExternal = true; 2814 } 2815 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2816 if (IsN64 || (!IsO32 && IsPIC)) 2817 OpFlag = MipsII::MO_GOT_DISP; 2818 else if (!IsPIC) // !N64 && static 2819 OpFlag = MipsII::MO_NO_FLAG; 2820 else // O32 & PIC 2821 OpFlag = MipsII::MO_GOT_CALL; 2822 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2823 OpFlag); 2824 GlobalOrExternal = true; 2825 } 2826 2827 SDValue InFlag; 2828 2829 // Create nodes that load address of callee and copy it to T9 2830 if (IsPICCall) { 2831 if (GlobalOrExternal) { 2832 // Load callee address 2833 Callee = DAG.getNode(MipsISD::Wrapper, dl, getPointerTy(), 2834 GetGlobalReg(DAG, getPointerTy()), Callee); 2835 SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 2836 Callee, MachinePointerInfo::getGOT(), 2837 false, false, false, 0); 2838 2839 // Use GOT+LO if callee has internal linkage. 2840 if (CalleeLo.getNode()) { 2841 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo); 2842 Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo); 2843 } else 2844 Callee = LoadValue; 2845 } 2846 } 2847 2848 // T9 register operand. 2849 SDValue T9; 2850 2851 // T9 should contain the address of the callee function if 2852 // -reloction-model=pic or it is an indirect call. 2853 if (IsPICCall || !GlobalOrExternal) { 2854 // copy to T9 2855 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9; 2856 Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0)); 2857 InFlag = Chain.getValue(1); 2858 2859 if (Subtarget->inMips16Mode()) 2860 T9 = DAG.getRegister(T9Reg, getPointerTy()); 2861 else 2862 Callee = DAG.getRegister(T9Reg, getPointerTy()); 2863 } 2864 2865 // Insert node "GP copy globalreg" before call to function. 2866 // Lazy-binding stubs require GP to point to the GOT. 2867 if (IsPICCall) { 2868 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP; 2869 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 2870 RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty))); 2871 } 2872 2873 // Build a sequence of copy-to-reg nodes chained together with token 2874 // chain and flag operands which copy the outgoing args into registers. 2875 // The InFlag in necessary since all emitted instructions must be 2876 // stuck together. 2877 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2878 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2879 RegsToPass[i].second, InFlag); 2880 InFlag = Chain.getValue(1); 2881 } 2882 2883 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 2884 // = Chain, Callee, Reg#1, Reg#2, ... 2885 // 2886 // Returns a chain & a flag for retval copy to use. 2887 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2888 SmallVector<SDValue, 8> Ops; 2889 Ops.push_back(Chain); 2890 Ops.push_back(Callee); 2891 2892 // Add argument registers to the end of the list so that they are 2893 // known live into the call. 2894 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2895 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2896 RegsToPass[i].second.getValueType())); 2897 2898 // Add T9 register operand. 2899 if (T9.getNode()) 2900 Ops.push_back(T9); 2901 2902 // Add a register mask operand representing the call-preserved registers. 2903 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2904 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2905 assert(Mask && "Missing call preserved mask for calling convention"); 2906 Ops.push_back(DAG.getRegisterMask(Mask)); 2907 2908 if (InFlag.getNode()) 2909 Ops.push_back(InFlag); 2910 2911 if (isTailCall) 2912 return DAG.getNode(MipsISD::TailCall, dl, MVT::Other, &Ops[0], Ops.size()); 2913 2914 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 2915 InFlag = Chain.getValue(1); 2916 2917 // Create the CALLSEQ_END node. 2918 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2919 DAG.getIntPtrConstant(0, true), InFlag); 2920 InFlag = Chain.getValue(1); 2921 2922 // Handle result values, copying them out of physregs into vregs that we 2923 // return. 2924 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2925 Ins, dl, DAG, InVals); 2926} 2927 2928/// LowerCallResult - Lower the result values of a call into the 2929/// appropriate copies out of appropriate physical registers. 2930SDValue 2931MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2932 CallingConv::ID CallConv, bool isVarArg, 2933 const SmallVectorImpl<ISD::InputArg> &Ins, 2934 DebugLoc dl, SelectionDAG &DAG, 2935 SmallVectorImpl<SDValue> &InVals) const { 2936 // Assign locations to each value returned by this call. 2937 SmallVector<CCValAssign, 16> RVLocs; 2938 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2939 getTargetMachine(), RVLocs, *DAG.getContext()); 2940 2941 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 2942 2943 // Copy all of the result registers out of their specified physreg. 2944 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2945 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 2946 RVLocs[i].getValVT(), InFlag).getValue(1); 2947 InFlag = Chain.getValue(2); 2948 InVals.push_back(Chain.getValue(0)); 2949 } 2950 2951 return Chain; 2952} 2953 2954//===----------------------------------------------------------------------===// 2955// Formal Arguments Calling Convention Implementation 2956//===----------------------------------------------------------------------===// 2957/// LowerFormalArguments - transform physical registers into virtual registers 2958/// and generate load operations for arguments places on the stack. 2959SDValue 2960MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2961 CallingConv::ID CallConv, 2962 bool isVarArg, 2963 const SmallVectorImpl<ISD::InputArg> &Ins, 2964 DebugLoc dl, SelectionDAG &DAG, 2965 SmallVectorImpl<SDValue> &InVals) 2966 const { 2967 MachineFunction &MF = DAG.getMachineFunction(); 2968 MachineFrameInfo *MFI = MF.getFrameInfo(); 2969 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2970 2971 MipsFI->setVarArgsFrameIndex(0); 2972 2973 // Used with vargs to acumulate store chains. 2974 std::vector<SDValue> OutChains; 2975 2976 // Assign locations to all of the incoming arguments. 2977 SmallVector<CCValAssign, 16> ArgLocs; 2978 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2979 getTargetMachine(), ArgLocs, *DAG.getContext()); 2980 MipsCC MipsCCInfo(CallConv, isVarArg, IsO32, CCInfo); 2981 2982 MipsCCInfo.analyzeFormalArguments(Ins); 2983 2984 Function::const_arg_iterator FuncArg = 2985 DAG.getMachineFunction().getFunction()->arg_begin(); 2986 unsigned CurArgIdx = 0; 2987 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 2988 2989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2990 CCValAssign &VA = ArgLocs[i]; 2991 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx); 2992 CurArgIdx = Ins[i].OrigArgIndex; 2993 EVT ValVT = VA.getValVT(); 2994 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2995 bool IsRegLoc = VA.isRegLoc(); 2996 2997 if (Flags.isByVal()) { 2998 assert(Flags.getByValSize() && 2999 "ByVal args of size 0 should have been ignored by front-end."); 3000 assert(ByValArg != MipsCCInfo.byval_end()); 3001 copyByValRegs(Chain, dl, OutChains, DAG, Flags, InVals, &*FuncArg, 3002 MipsCCInfo, *ByValArg); 3003 ++ByValArg; 3004 continue; 3005 } 3006 3007 // Arguments stored on registers 3008 if (IsRegLoc) { 3009 EVT RegVT = VA.getLocVT(); 3010 unsigned ArgReg = VA.getLocReg(); 3011 const TargetRegisterClass *RC; 3012 3013 if (RegVT == MVT::i32) 3014 RC = &Mips::CPURegsRegClass; 3015 else if (RegVT == MVT::i64) 3016 RC = &Mips::CPU64RegsRegClass; 3017 else if (RegVT == MVT::f32) 3018 RC = &Mips::FGR32RegClass; 3019 else if (RegVT == MVT::f64) 3020 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; 3021 else 3022 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 3023 3024 // Transform the arguments stored on 3025 // physical registers into virtual ones 3026 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3027 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 3028 3029 // If this is an 8 or 16-bit value, it has been passed promoted 3030 // to 32 bits. Insert an assert[sz]ext to capture this, then 3031 // truncate to the right size. 3032 if (VA.getLocInfo() != CCValAssign::Full) { 3033 unsigned Opcode = 0; 3034 if (VA.getLocInfo() == CCValAssign::SExt) 3035 Opcode = ISD::AssertSext; 3036 else if (VA.getLocInfo() == CCValAssign::ZExt) 3037 Opcode = ISD::AssertZext; 3038 if (Opcode) 3039 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 3040 DAG.getValueType(ValVT)); 3041 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue); 3042 } 3043 3044 // Handle floating point arguments passed in integer registers. 3045 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3046 (RegVT == MVT::i64 && ValVT == MVT::f64)) 3047 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue); 3048 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) { 3049 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 3050 getNextIntArgReg(ArgReg), RC); 3051 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 3052 if (!Subtarget->isLittle()) 3053 std::swap(ArgValue, ArgValue2); 3054 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 3055 ArgValue, ArgValue2); 3056 } 3057 3058 InVals.push_back(ArgValue); 3059 } else { // VA.isRegLoc() 3060 3061 // sanity check 3062 assert(VA.isMemLoc()); 3063 3064 // The stack pointer offset is relative to the caller stack frame. 3065 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 3066 VA.getLocMemOffset(), true); 3067 3068 // Create load nodes to retrieve arguments from the stack 3069 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 3070 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN, 3071 MachinePointerInfo::getFixedStack(FI), 3072 false, false, false, 0)); 3073 } 3074 } 3075 3076 // The mips ABIs for returning structs by value requires that we copy 3077 // the sret argument into $v0 for the return. Save the argument into 3078 // a virtual register so that we can access it from the return points. 3079 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 3080 unsigned Reg = MipsFI->getSRetReturnReg(); 3081 if (!Reg) { 3082 Reg = MF.getRegInfo(). 3083 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32)); 3084 MipsFI->setSRetReturnReg(Reg); 3085 } 3086 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 3087 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 3088 } 3089 3090 if (isVarArg) 3091 writeVarArgRegs(OutChains, MipsCCInfo, Chain, dl, DAG); 3092 3093 // All stores are grouped in one node to allow the matching between 3094 // the size of Ins and InVals. This only happens when on varg functions 3095 if (!OutChains.empty()) { 3096 OutChains.push_back(Chain); 3097 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3098 &OutChains[0], OutChains.size()); 3099 } 3100 3101 return Chain; 3102} 3103 3104//===----------------------------------------------------------------------===// 3105// Return Value Calling Convention Implementation 3106//===----------------------------------------------------------------------===// 3107 3108bool 3109MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3110 MachineFunction &MF, bool isVarArg, 3111 const SmallVectorImpl<ISD::OutputArg> &Outs, 3112 LLVMContext &Context) const { 3113 SmallVector<CCValAssign, 16> RVLocs; 3114 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 3115 RVLocs, Context); 3116 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3117} 3118 3119SDValue 3120MipsTargetLowering::LowerReturn(SDValue Chain, 3121 CallingConv::ID CallConv, bool isVarArg, 3122 const SmallVectorImpl<ISD::OutputArg> &Outs, 3123 const SmallVectorImpl<SDValue> &OutVals, 3124 DebugLoc dl, SelectionDAG &DAG) const { 3125 3126 // CCValAssign - represent the assignment of 3127 // the return value to a location 3128 SmallVector<CCValAssign, 16> RVLocs; 3129 3130 // CCState - Info about the registers and stack slot. 3131 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3132 getTargetMachine(), RVLocs, *DAG.getContext()); 3133 3134 // Analize return values. 3135 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3136 3137 // If this is the first return lowered for this function, add 3138 // the regs to the liveout set for the function. 3139 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 3140 for (unsigned i = 0; i != RVLocs.size(); ++i) 3141 if (RVLocs[i].isRegLoc()) 3142 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 3143 } 3144 3145 SDValue Flag; 3146 3147 // Copy the result values into the output registers. 3148 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3149 CCValAssign &VA = RVLocs[i]; 3150 assert(VA.isRegLoc() && "Can only return in registers!"); 3151 3152 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 3153 3154 // guarantee that all emitted copies are 3155 // stuck together, avoiding something bad 3156 Flag = Chain.getValue(1); 3157 } 3158 3159 // The mips ABIs for returning structs by value requires that we copy 3160 // the sret argument into $v0 for the return. We saved the argument into 3161 // a virtual register in the entry block, so now we copy the value out 3162 // and into $v0. 3163 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 3164 MachineFunction &MF = DAG.getMachineFunction(); 3165 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3166 unsigned Reg = MipsFI->getSRetReturnReg(); 3167 3168 if (!Reg) 3169 llvm_unreachable("sret virtual register not created in the entry block"); 3170 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 3171 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0; 3172 3173 Chain = DAG.getCopyToReg(Chain, dl, V0, Val, Flag); 3174 Flag = Chain.getValue(1); 3175 MF.getRegInfo().addLiveOut(V0); 3176 } 3177 3178 // Return on Mips is always a "jr $ra" 3179 if (Flag.getNode()) 3180 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain, Flag); 3181 3182 // Return Void 3183 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain); 3184} 3185 3186//===----------------------------------------------------------------------===// 3187// Mips Inline Assembly Support 3188//===----------------------------------------------------------------------===// 3189 3190/// getConstraintType - Given a constraint letter, return the type of 3191/// constraint it is for this target. 3192MipsTargetLowering::ConstraintType MipsTargetLowering:: 3193getConstraintType(const std::string &Constraint) const 3194{ 3195 // Mips specific constrainy 3196 // GCC config/mips/constraints.md 3197 // 3198 // 'd' : An address register. Equivalent to r 3199 // unless generating MIPS16 code. 3200 // 'y' : Equivalent to r; retained for 3201 // backwards compatibility. 3202 // 'c' : A register suitable for use in an indirect 3203 // jump. This will always be $25 for -mabicalls. 3204 // 'l' : The lo register. 1 word storage. 3205 // 'x' : The hilo register pair. Double word storage. 3206 if (Constraint.size() == 1) { 3207 switch (Constraint[0]) { 3208 default : break; 3209 case 'd': 3210 case 'y': 3211 case 'f': 3212 case 'c': 3213 case 'l': 3214 case 'x': 3215 return C_RegisterClass; 3216 } 3217 } 3218 return TargetLowering::getConstraintType(Constraint); 3219} 3220 3221/// Examine constraint type and operand type and determine a weight value. 3222/// This object must already have been set up with the operand type 3223/// and the current alternative constraint selected. 3224TargetLowering::ConstraintWeight 3225MipsTargetLowering::getSingleConstraintMatchWeight( 3226 AsmOperandInfo &info, const char *constraint) const { 3227 ConstraintWeight weight = CW_Invalid; 3228 Value *CallOperandVal = info.CallOperandVal; 3229 // If we don't have a value, we can't do a match, 3230 // but allow it at the lowest weight. 3231 if (CallOperandVal == NULL) 3232 return CW_Default; 3233 Type *type = CallOperandVal->getType(); 3234 // Look at the constraint type. 3235 switch (*constraint) { 3236 default: 3237 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3238 break; 3239 case 'd': 3240 case 'y': 3241 if (type->isIntegerTy()) 3242 weight = CW_Register; 3243 break; 3244 case 'f': 3245 if (type->isFloatTy()) 3246 weight = CW_Register; 3247 break; 3248 case 'c': // $25 for indirect jumps 3249 case 'l': // lo register 3250 case 'x': // hilo register pair 3251 if (type->isIntegerTy()) 3252 weight = CW_SpecificReg; 3253 break; 3254 case 'I': // signed 16 bit immediate 3255 case 'J': // integer zero 3256 case 'K': // unsigned 16 bit immediate 3257 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3258 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3259 case 'O': // signed 15 bit immediate (+- 16383) 3260 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3261 if (isa<ConstantInt>(CallOperandVal)) 3262 weight = CW_Constant; 3263 break; 3264 } 3265 return weight; 3266} 3267 3268/// Given a register class constraint, like 'r', if this corresponds directly 3269/// to an LLVM register class, return a register of 0 and the register class 3270/// pointer. 3271std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 3272getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 3273{ 3274 if (Constraint.size() == 1) { 3275 switch (Constraint[0]) { 3276 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3277 case 'y': // Same as 'r'. Exists for compatibility. 3278 case 'r': 3279 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3280 if (Subtarget->inMips16Mode()) 3281 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3282 return std::make_pair(0U, &Mips::CPURegsRegClass); 3283 } 3284 if (VT == MVT::i64 && !HasMips64) 3285 return std::make_pair(0U, &Mips::CPURegsRegClass); 3286 if (VT == MVT::i64 && HasMips64) 3287 return std::make_pair(0U, &Mips::CPU64RegsRegClass); 3288 // This will generate an error message 3289 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 3290 case 'f': 3291 if (VT == MVT::f32) 3292 return std::make_pair(0U, &Mips::FGR32RegClass); 3293 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { 3294 if (Subtarget->isFP64bit()) 3295 return std::make_pair(0U, &Mips::FGR64RegClass); 3296 return std::make_pair(0U, &Mips::AFGR64RegClass); 3297 } 3298 break; 3299 case 'c': // register suitable for indirect jump 3300 if (VT == MVT::i32) 3301 return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass); 3302 assert(VT == MVT::i64 && "Unexpected type."); 3303 return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass); 3304 case 'l': // register suitable for indirect jump 3305 if (VT == MVT::i32) 3306 return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass); 3307 return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass); 3308 case 'x': // register suitable for indirect jump 3309 // Fixme: Not triggering the use of both hi and low 3310 // This will generate an error message 3311 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 3312 } 3313 } 3314 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3315} 3316 3317/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3318/// vector. If it is invalid, don't add anything to Ops. 3319void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3320 std::string &Constraint, 3321 std::vector<SDValue>&Ops, 3322 SelectionDAG &DAG) const { 3323 SDValue Result(0, 0); 3324 3325 // Only support length 1 constraints for now. 3326 if (Constraint.length() > 1) return; 3327 3328 char ConstraintLetter = Constraint[0]; 3329 switch (ConstraintLetter) { 3330 default: break; // This will fall through to the generic implementation 3331 case 'I': // Signed 16 bit constant 3332 // If this fails, the parent routine will give an error 3333 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3334 EVT Type = Op.getValueType(); 3335 int64_t Val = C->getSExtValue(); 3336 if (isInt<16>(Val)) { 3337 Result = DAG.getTargetConstant(Val, Type); 3338 break; 3339 } 3340 } 3341 return; 3342 case 'J': // integer zero 3343 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3344 EVT Type = Op.getValueType(); 3345 int64_t Val = C->getZExtValue(); 3346 if (Val == 0) { 3347 Result = DAG.getTargetConstant(0, Type); 3348 break; 3349 } 3350 } 3351 return; 3352 case 'K': // unsigned 16 bit immediate 3353 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3354 EVT Type = Op.getValueType(); 3355 uint64_t Val = (uint64_t)C->getZExtValue(); 3356 if (isUInt<16>(Val)) { 3357 Result = DAG.getTargetConstant(Val, Type); 3358 break; 3359 } 3360 } 3361 return; 3362 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3363 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3364 EVT Type = Op.getValueType(); 3365 int64_t Val = C->getSExtValue(); 3366 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3367 Result = DAG.getTargetConstant(Val, Type); 3368 break; 3369 } 3370 } 3371 return; 3372 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3373 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3374 EVT Type = Op.getValueType(); 3375 int64_t Val = C->getSExtValue(); 3376 if ((Val >= -65535) && (Val <= -1)) { 3377 Result = DAG.getTargetConstant(Val, Type); 3378 break; 3379 } 3380 } 3381 return; 3382 case 'O': // signed 15 bit immediate 3383 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3384 EVT Type = Op.getValueType(); 3385 int64_t Val = C->getSExtValue(); 3386 if ((isInt<15>(Val))) { 3387 Result = DAG.getTargetConstant(Val, Type); 3388 break; 3389 } 3390 } 3391 return; 3392 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3393 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3394 EVT Type = Op.getValueType(); 3395 int64_t Val = C->getSExtValue(); 3396 if ((Val <= 65535) && (Val >= 1)) { 3397 Result = DAG.getTargetConstant(Val, Type); 3398 break; 3399 } 3400 } 3401 return; 3402 } 3403 3404 if (Result.getNode()) { 3405 Ops.push_back(Result); 3406 return; 3407 } 3408 3409 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3410} 3411 3412bool 3413MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3414 // The Mips target isn't yet aware of offsets. 3415 return false; 3416} 3417 3418EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3419 unsigned SrcAlign, bool IsZeroVal, 3420 bool MemcpyStrSrc, 3421 MachineFunction &MF) const { 3422 if (Subtarget->hasMips64()) 3423 return MVT::i64; 3424 3425 return MVT::i32; 3426} 3427 3428bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3429 if (VT != MVT::f32 && VT != MVT::f64) 3430 return false; 3431 if (Imm.isNegZero()) 3432 return false; 3433 return Imm.isZero(); 3434} 3435 3436unsigned MipsTargetLowering::getJumpTableEncoding() const { 3437 if (IsN64) 3438 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3439 3440 return TargetLowering::getJumpTableEncoding(); 3441} 3442 3443MipsTargetLowering::MipsCC::MipsCC(CallingConv::ID CallConv, bool IsVarArg, 3444 bool IsO32, CCState &Info) : CCInfo(Info) { 3445 UseRegsForByval = true; 3446 3447 if (IsO32) { 3448 RegSize = 4; 3449 NumIntArgRegs = array_lengthof(O32IntRegs); 3450 ReservedArgArea = 16; 3451 IntArgRegs = ShadowRegs = O32IntRegs; 3452 FixedFn = VarFn = CC_MipsO32; 3453 } else { 3454 RegSize = 8; 3455 NumIntArgRegs = array_lengthof(Mips64IntRegs); 3456 ReservedArgArea = 0; 3457 IntArgRegs = Mips64IntRegs; 3458 ShadowRegs = Mips64DPRegs; 3459 FixedFn = CC_MipsN; 3460 VarFn = CC_MipsN_VarArg; 3461 } 3462 3463 if (CallConv == CallingConv::Fast) { 3464 assert(!IsVarArg); 3465 UseRegsForByval = false; 3466 ReservedArgArea = 0; 3467 FixedFn = VarFn = CC_Mips_FastCC; 3468 } 3469 3470 // Pre-allocate reserved argument area. 3471 CCInfo.AllocateStack(ReservedArgArea, 1); 3472} 3473 3474void MipsTargetLowering::MipsCC:: 3475analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args) { 3476 unsigned NumOpnds = Args.size(); 3477 3478 for (unsigned I = 0; I != NumOpnds; ++I) { 3479 MVT ArgVT = Args[I].VT; 3480 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3481 bool R; 3482 3483 if (ArgFlags.isByVal()) { 3484 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3485 continue; 3486 } 3487 3488 if (Args[I].IsFixed) 3489 R = FixedFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 3490 else 3491 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 3492 3493 if (R) { 3494#ifndef NDEBUG 3495 dbgs() << "Call operand #" << I << " has unhandled type " 3496 << EVT(ArgVT).getEVTString(); 3497#endif 3498 llvm_unreachable(0); 3499 } 3500 } 3501} 3502 3503void MipsTargetLowering::MipsCC:: 3504analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args) { 3505 unsigned NumArgs = Args.size(); 3506 3507 for (unsigned I = 0; I != NumArgs; ++I) { 3508 MVT ArgVT = Args[I].VT; 3509 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3510 3511 if (ArgFlags.isByVal()) { 3512 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3513 continue; 3514 } 3515 3516 if (!FixedFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo)) 3517 continue; 3518 3519#ifndef NDEBUG 3520 dbgs() << "Formal Arg #" << I << " has unhandled type " 3521 << EVT(ArgVT).getEVTString(); 3522#endif 3523 llvm_unreachable(0); 3524 } 3525} 3526 3527void 3528MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT, 3529 MVT LocVT, 3530 CCValAssign::LocInfo LocInfo, 3531 ISD::ArgFlagsTy ArgFlags) { 3532 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0."); 3533 3534 struct ByValArgInfo ByVal; 3535 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize); 3536 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize), 3537 RegSize * 2); 3538 3539 if (UseRegsForByval) 3540 allocateRegs(ByVal, ByValSize, Align); 3541 3542 // Allocate space on caller's stack. 3543 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs, 3544 Align); 3545 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT, 3546 LocInfo)); 3547 ByValArgs.push_back(ByVal); 3548} 3549 3550void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal, 3551 unsigned ByValSize, 3552 unsigned Align) { 3553 assert(!(ByValSize % RegSize) && !(Align % RegSize) && 3554 "Byval argument's size and alignment should be a multiple of" 3555 "RegSize."); 3556 3557 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs); 3558 3559 // If Align > RegSize, the first arg register must be even. 3560 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) { 3561 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]); 3562 ++ByVal.FirstIdx; 3563 } 3564 3565 // Mark the registers allocated. 3566 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs); 3567 ByValSize -= RegSize, ++I, ++ByVal.NumRegs) 3568 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]); 3569} 3570 3571void MipsTargetLowering:: 3572copyByValRegs(SDValue Chain, DebugLoc DL, std::vector<SDValue> &OutChains, 3573 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 3574 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 3575 const MipsCC &CC, const ByValArgInfo &ByVal) const { 3576 MachineFunction &MF = DAG.getMachineFunction(); 3577 MachineFrameInfo *MFI = MF.getFrameInfo(); 3578 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize(); 3579 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3580 int FrameObjOffset; 3581 3582 if (RegAreaSize) 3583 FrameObjOffset = (int)CC.reservedArgArea() - 3584 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize()); 3585 else 3586 FrameObjOffset = ByVal.Address; 3587 3588 // Create frame object. 3589 EVT PtrTy = getPointerTy(); 3590 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3591 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3592 InVals.push_back(FIN); 3593 3594 if (!ByVal.NumRegs) 3595 return; 3596 3597 // Copy arg registers. 3598 EVT RegTy = MVT::getIntegerVT(CC.regSize() * 8); 3599 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3600 3601 for (unsigned I = 0; I < ByVal.NumRegs; ++I) { 3602 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I]; 3603 unsigned VReg = AddLiveIn(MF, ArgReg, RC); 3604 unsigned Offset = I * CC.regSize(); 3605 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3606 DAG.getConstant(Offset, PtrTy)); 3607 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3608 StorePtr, MachinePointerInfo(FuncArg, Offset), 3609 false, false, 0); 3610 OutChains.push_back(Store); 3611 } 3612} 3613 3614// Copy byVal arg to registers and stack. 3615void MipsTargetLowering:: 3616passByValArg(SDValue Chain, DebugLoc DL, 3617 SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass, 3618 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, 3619 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 3620 const MipsCC &CC, const ByValArgInfo &ByVal, 3621 const ISD::ArgFlagsTy &Flags, bool isLittle) const { 3622 unsigned ByValSize = Flags.getByValSize(); 3623 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct. 3624 unsigned RegSize = CC.regSize(); 3625 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize); 3626 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8); 3627 3628 if (ByVal.NumRegs) { 3629 const uint16_t *ArgRegs = CC.intArgRegs(); 3630 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize); 3631 unsigned I = 0; 3632 3633 // Copy words to registers. 3634 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) { 3635 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3636 DAG.getConstant(Offset, PtrTy)); 3637 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3638 MachinePointerInfo(), false, false, false, 3639 Alignment); 3640 MemOpChains.push_back(LoadVal.getValue(1)); 3641 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3642 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3643 } 3644 3645 // Return if the struct has been fully copied. 3646 if (ByValSize == Offset) 3647 return; 3648 3649 // Copy the remainder of the byval argument with sub-word loads and shifts. 3650 if (LeftoverBytes) { 3651 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) && 3652 "Size of the remainder should be smaller than RegSize."); 3653 SDValue Val; 3654 3655 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0; 3656 Offset < ByValSize; LoadSize /= 2) { 3657 unsigned RemSize = ByValSize - Offset; 3658 3659 if (RemSize < LoadSize) 3660 continue; 3661 3662 // Load subword. 3663 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3664 DAG.getConstant(Offset, PtrTy)); 3665 SDValue LoadVal = 3666 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, 3667 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8), 3668 false, false, Alignment); 3669 MemOpChains.push_back(LoadVal.getValue(1)); 3670 3671 // Shift the loaded value. 3672 unsigned Shamt; 3673 3674 if (isLittle) 3675 Shamt = TotalSizeLoaded; 3676 else 3677 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8; 3678 3679 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 3680 DAG.getConstant(Shamt, MVT::i32)); 3681 3682 if (Val.getNode()) 3683 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3684 else 3685 Val = Shift; 3686 3687 Offset += LoadSize; 3688 TotalSizeLoaded += LoadSize; 3689 Alignment = std::min(Alignment, LoadSize); 3690 } 3691 3692 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3693 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 3694 return; 3695 } 3696 } 3697 3698 // Copy remainder of byval arg to it with memcpy. 3699 unsigned MemCpySize = ByValSize - Offset; 3700 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3701 DAG.getConstant(Offset, PtrTy)); 3702 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 3703 DAG.getIntPtrConstant(ByVal.Address)); 3704 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 3705 DAG.getConstant(MemCpySize, PtrTy), Alignment, 3706 /*isVolatile=*/false, /*AlwaysInline=*/false, 3707 MachinePointerInfo(0), MachinePointerInfo(0)); 3708 MemOpChains.push_back(Chain); 3709} 3710 3711void 3712MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 3713 const MipsCC &CC, SDValue Chain, 3714 DebugLoc DL, SelectionDAG &DAG) const { 3715 unsigned NumRegs = CC.numIntArgRegs(); 3716 const uint16_t *ArgRegs = CC.intArgRegs(); 3717 const CCState &CCInfo = CC.getCCInfo(); 3718 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs); 3719 unsigned RegSize = CC.regSize(); 3720 EVT RegTy = MVT::getIntegerVT(RegSize * 8); 3721 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3722 MachineFunction &MF = DAG.getMachineFunction(); 3723 MachineFrameInfo *MFI = MF.getFrameInfo(); 3724 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3725 3726 // Offset of the first variable argument from stack pointer. 3727 int VaArgOffset; 3728 3729 if (NumRegs == Idx) 3730 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize); 3731 else 3732 VaArgOffset = 3733 (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx)); 3734 3735 // Record the frame index of the first variable argument 3736 // which is a value necessary to VASTART. 3737 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3738 MipsFI->setVarArgsFrameIndex(FI); 3739 3740 // Copy the integer registers that have not been used for argument passing 3741 // to the argument register save area. For O32, the save area is allocated 3742 // in the caller's stack frame, while for N32/64, it is allocated in the 3743 // callee's stack frame. 3744 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) { 3745 unsigned Reg = AddLiveIn(MF, ArgRegs[I], RC); 3746 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 3747 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3748 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 3749 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, 3750 MachinePointerInfo(), false, false, 0); 3751 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0); 3752 OutChains.push_back(Store); 3753 } 3754} 3755