MipsISelLowering.cpp revision 59be760f61d54e24bae70c4465021a6f0746d278 
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "mips-lower"
16#include "MipsISelLowering.h"
17#include "MipsMachineFunction.h"
18#include "MipsTargetMachine.h"
19#include "MipsTargetObjectFile.h"
20#include "MipsSubtarget.h"
21#include "InstPrinter/MipsInstPrinter.h"
22#include "MCTargetDesc/MipsBaseInfo.h"
23#include "llvm/DerivedTypes.h"
24#include "llvm/Function.h"
25#include "llvm/GlobalVariable.h"
26#include "llvm/Intrinsics.h"
27#include "llvm/CallingConv.h"
28#include "llvm/ADT/Statistic.h"
29#include "llvm/CodeGen/CallingConvLower.h"
30#include "llvm/CodeGen/MachineFrameInfo.h"
31#include "llvm/CodeGen/MachineFunction.h"
32#include "llvm/CodeGen/MachineInstrBuilder.h"
33#include "llvm/CodeGen/MachineRegisterInfo.h"
34#include "llvm/CodeGen/SelectionDAGISel.h"
35#include "llvm/CodeGen/ValueTypes.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
40
41using namespace llvm;
42
43STATISTIC(NumTailCalls, "Number of tail calls");
44
45static cl::opt<bool>
46EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
47                    cl::desc("MIPS: Enable tail calls."), cl::init(false));
48
49static const uint16_t O32IntRegs[4] = {
50  Mips::A0, Mips::A1, Mips::A2, Mips::A3
51};
52
53static const uint16_t Mips64IntRegs[8] = {
54  Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
55  Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
56};
57
58static const uint16_t Mips64DPRegs[8] = {
59  Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
60  Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
61};
62
63// If I is a shifted mask, set the size (Size) and the first bit of the
64// mask (Pos), and return true.
65// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
66static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
67  if (!isShiftedMask_64(I))
68     return false;
69
70  Size = CountPopulation_64(I);
71  Pos = CountTrailingZeros_64(I);
72  return true;
73}
74
75static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) {
76  MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
77  return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
78}
79
80const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
81  switch (Opcode) {
82  case MipsISD::JmpLink:           return "MipsISD::JmpLink";
83  case MipsISD::TailCall:          return "MipsISD::TailCall";
84  case MipsISD::Hi:                return "MipsISD::Hi";
85  case MipsISD::Lo:                return "MipsISD::Lo";
86  case MipsISD::GPRel:             return "MipsISD::GPRel";
87  case MipsISD::ThreadPointer:     return "MipsISD::ThreadPointer";
88  case MipsISD::Ret:               return "MipsISD::Ret";
89  case MipsISD::FPBrcond:          return "MipsISD::FPBrcond";
90  case MipsISD::FPCmp:             return "MipsISD::FPCmp";
91  case MipsISD::CMovFP_T:          return "MipsISD::CMovFP_T";
92  case MipsISD::CMovFP_F:          return "MipsISD::CMovFP_F";
93  case MipsISD::FPRound:           return "MipsISD::FPRound";
94  case MipsISD::MAdd:              return "MipsISD::MAdd";
95  case MipsISD::MAddu:             return "MipsISD::MAddu";
96  case MipsISD::MSub:              return "MipsISD::MSub";
97  case MipsISD::MSubu:             return "MipsISD::MSubu";
98  case MipsISD::DivRem:            return "MipsISD::DivRem";
99  case MipsISD::DivRemU:           return "MipsISD::DivRemU";
100  case MipsISD::BuildPairF64:      return "MipsISD::BuildPairF64";
101  case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
102  case MipsISD::Wrapper:           return "MipsISD::Wrapper";
103  case MipsISD::DynAlloc:          return "MipsISD::DynAlloc";
104  case MipsISD::Sync:              return "MipsISD::Sync";
105  case MipsISD::Ext:               return "MipsISD::Ext";
106  case MipsISD::Ins:               return "MipsISD::Ins";
107  case MipsISD::LWL:               return "MipsISD::LWL";
108  case MipsISD::LWR:               return "MipsISD::LWR";
109  case MipsISD::SWL:               return "MipsISD::SWL";
110  case MipsISD::SWR:               return "MipsISD::SWR";
111  case MipsISD::LDL:               return "MipsISD::LDL";
112  case MipsISD::LDR:               return "MipsISD::LDR";
113  case MipsISD::SDL:               return "MipsISD::SDL";
114  case MipsISD::SDR:               return "MipsISD::SDR";
115  case MipsISD::EXTP:              return "MipsISD::EXTP";
116  case MipsISD::EXTPDP:            return "MipsISD::EXTPDP";
117  case MipsISD::EXTR_S_H:          return "MipsISD::EXTR_S_H";
118  case MipsISD::EXTR_W:            return "MipsISD::EXTR_W";
119  case MipsISD::EXTR_R_W:          return "MipsISD::EXTR_R_W";
120  case MipsISD::EXTR_RS_W:         return "MipsISD::EXTR_RS_W";
121  case MipsISD::SHILO:             return "MipsISD::SHILO";
122  case MipsISD::MTHLIP:            return "MipsISD::MTHLIP";
123  case MipsISD::MULT:              return "MipsISD::MULT";
124  case MipsISD::MULTU:             return "MipsISD::MULTU";
125  case MipsISD::MADD_DSP:          return "MipsISD::MADD_DSPDSP";
126  case MipsISD::MADDU_DSP:         return "MipsISD::MADDU_DSP";
127  case MipsISD::MSUB_DSP:          return "MipsISD::MSUB_DSP";
128  case MipsISD::MSUBU_DSP:         return "MipsISD::MSUBU_DSP";
129  default:                         return NULL;
130  }
131}
132
133MipsTargetLowering::
134MipsTargetLowering(MipsTargetMachine &TM)
135  : TargetLowering(TM, new MipsTargetObjectFile()),
136    Subtarget(&TM.getSubtarget<MipsSubtarget>()),
137    HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
138    IsO32(Subtarget->isABI_O32()) {
139
140  // Mips does not have i1 type, so use i32 for
141  // setcc operations results (slt, sgt, ...).
142  setBooleanContents(ZeroOrOneBooleanContent);
143  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
144
145  // Set up the register classes
146  addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
147
148  if (HasMips64)
149    addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
150
151  if (Subtarget->inMips16Mode()) {
152    addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
153  }
154
155  if (Subtarget->hasDSP()) {
156    MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
157
158    for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
159      addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass);
160
161      // Expand all builtin opcodes.
162      for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
163        setOperationAction(Opc, VecTys[i], Expand);
164
165      setOperationAction(ISD::LOAD, VecTys[i], Legal);
166      setOperationAction(ISD::STORE, VecTys[i], Legal);
167      setOperationAction(ISD::BITCAST, VecTys[i], Legal);
168    }
169  }
170
171  if (!TM.Options.UseSoftFloat) {
172    addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
173
174    // When dealing with single precision only, use libcalls
175    if (!Subtarget->isSingleFloat()) {
176      if (HasMips64)
177        addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
178      else
179        addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
180    }
181  }
182
183  // Load extented operations for i1 types must be promoted
184  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
185  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
186  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
187
188  // MIPS doesn't have extending float->double load/store
189  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
190  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
191
192  // Used by legalize types to correctly generate the setcc result.
193  // Without this, every float setcc comes with a AND/OR with the result,
194  // we don't want this, since the fpcmp result goes to a flag register,
195  // which is used implicitly by brcond and select operations.
196  AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
197
198  // Mips Custom Operations
199  setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);
200  setOperationAction(ISD::BlockAddress,       MVT::i32,   Custom);
201  setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);
202  setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);
203  setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);
204  setOperationAction(ISD::SELECT,             MVT::f32,   Custom);
205  setOperationAction(ISD::SELECT,             MVT::f64,   Custom);
206  setOperationAction(ISD::SELECT,             MVT::i32,   Custom);
207  setOperationAction(ISD::SELECT_CC,          MVT::f32,   Custom);
208  setOperationAction(ISD::SELECT_CC,          MVT::f64,   Custom);
209  setOperationAction(ISD::SETCC,              MVT::f32,   Custom);
210  setOperationAction(ISD::SETCC,              MVT::f64,   Custom);
211  setOperationAction(ISD::BRCOND,             MVT::Other, Custom);
212  setOperationAction(ISD::VASTART,            MVT::Other, Custom);
213  setOperationAction(ISD::FCOPYSIGN,          MVT::f32,   Custom);
214  setOperationAction(ISD::FCOPYSIGN,          MVT::f64,   Custom);
215  if (Subtarget->inMips16Mode()) {
216    setOperationAction(ISD::MEMBARRIER,         MVT::Other, Expand);
217    setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Expand);
218  }
219  else {
220    setOperationAction(ISD::MEMBARRIER,         MVT::Other, Custom);
221    setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Custom);
222  }
223  if (!Subtarget->inMips16Mode()) {
224    setOperationAction(ISD::LOAD,               MVT::i32, Custom);
225    setOperationAction(ISD::STORE,              MVT::i32, Custom);
226  }
227
228  if (!TM.Options.NoNaNsFPMath) {
229    setOperationAction(ISD::FABS,             MVT::f32,   Custom);
230    setOperationAction(ISD::FABS,             MVT::f64,   Custom);
231  }
232
233  if (HasMips64) {
234    setOperationAction(ISD::GlobalAddress,      MVT::i64,   Custom);
235    setOperationAction(ISD::BlockAddress,       MVT::i64,   Custom);
236    setOperationAction(ISD::GlobalTLSAddress,   MVT::i64,   Custom);
237    setOperationAction(ISD::JumpTable,          MVT::i64,   Custom);
238    setOperationAction(ISD::ConstantPool,       MVT::i64,   Custom);
239    setOperationAction(ISD::SELECT,             MVT::i64,   Custom);
240    setOperationAction(ISD::LOAD,               MVT::i64,   Custom);
241    setOperationAction(ISD::STORE,              MVT::i64,   Custom);
242  }
243
244  if (!HasMips64) {
245    setOperationAction(ISD::SHL_PARTS,          MVT::i32,   Custom);
246    setOperationAction(ISD::SRA_PARTS,          MVT::i32,   Custom);
247    setOperationAction(ISD::SRL_PARTS,          MVT::i32,   Custom);
248  }
249
250  setOperationAction(ISD::ADD,                MVT::i32,   Custom);
251  if (HasMips64)
252    setOperationAction(ISD::ADD,                MVT::i64,   Custom);
253
254  setOperationAction(ISD::SDIV, MVT::i32, Expand);
255  setOperationAction(ISD::SREM, MVT::i32, Expand);
256  setOperationAction(ISD::UDIV, MVT::i32, Expand);
257  setOperationAction(ISD::UREM, MVT::i32, Expand);
258  setOperationAction(ISD::SDIV, MVT::i64, Expand);
259  setOperationAction(ISD::SREM, MVT::i64, Expand);
260  setOperationAction(ISD::UDIV, MVT::i64, Expand);
261  setOperationAction(ISD::UREM, MVT::i64, Expand);
262
263  // Operations not directly supported by Mips.
264  setOperationAction(ISD::BR_JT,             MVT::Other, Expand);
265  setOperationAction(ISD::BR_CC,             MVT::Other, Expand);
266  setOperationAction(ISD::SELECT_CC,         MVT::Other, Expand);
267  setOperationAction(ISD::UINT_TO_FP,        MVT::i32,   Expand);
268  setOperationAction(ISD::UINT_TO_FP,        MVT::i64,   Expand);
269  setOperationAction(ISD::FP_TO_UINT,        MVT::i32,   Expand);
270  setOperationAction(ISD::FP_TO_UINT,        MVT::i64,   Expand);
271  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,    Expand);
272  setOperationAction(ISD::CTPOP,             MVT::i32,   Expand);
273  setOperationAction(ISD::CTPOP,             MVT::i64,   Expand);
274  setOperationAction(ISD::CTTZ,              MVT::i32,   Expand);
275  setOperationAction(ISD::CTTZ,              MVT::i64,   Expand);
276  setOperationAction(ISD::CTTZ_ZERO_UNDEF,   MVT::i32,   Expand);
277  setOperationAction(ISD::CTTZ_ZERO_UNDEF,   MVT::i64,   Expand);
278  setOperationAction(ISD::CTLZ_ZERO_UNDEF,   MVT::i32,   Expand);
279  setOperationAction(ISD::CTLZ_ZERO_UNDEF,   MVT::i64,   Expand);
280  setOperationAction(ISD::ROTL,              MVT::i32,   Expand);
281  setOperationAction(ISD::ROTL,              MVT::i64,   Expand);
282  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,  Expand);
283  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64,  Expand);
284
285  if (!Subtarget->hasMips32r2())
286    setOperationAction(ISD::ROTR, MVT::i32,   Expand);
287
288  if (!Subtarget->hasMips64r2())
289    setOperationAction(ISD::ROTR, MVT::i64,   Expand);
290
291  setOperationAction(ISD::FSIN,              MVT::f32,   Expand);
292  setOperationAction(ISD::FSIN,              MVT::f64,   Expand);
293  setOperationAction(ISD::FCOS,              MVT::f32,   Expand);
294  setOperationAction(ISD::FCOS,              MVT::f64,   Expand);
295  setOperationAction(ISD::FPOWI,             MVT::f32,   Expand);
296  setOperationAction(ISD::FPOW,              MVT::f32,   Expand);
297  setOperationAction(ISD::FPOW,              MVT::f64,   Expand);
298  setOperationAction(ISD::FLOG,              MVT::f32,   Expand);
299  setOperationAction(ISD::FLOG2,             MVT::f32,   Expand);
300  setOperationAction(ISD::FLOG10,            MVT::f32,   Expand);
301  setOperationAction(ISD::FEXP,              MVT::f32,   Expand);
302  setOperationAction(ISD::FMA,               MVT::f32,   Expand);
303  setOperationAction(ISD::FMA,               MVT::f64,   Expand);
304  setOperationAction(ISD::FREM,              MVT::f32,   Expand);
305  setOperationAction(ISD::FREM,              MVT::f64,   Expand);
306
307  if (!TM.Options.NoNaNsFPMath) {
308    setOperationAction(ISD::FNEG,             MVT::f32,   Expand);
309    setOperationAction(ISD::FNEG,             MVT::f64,   Expand);
310  }
311
312  setOperationAction(ISD::EXCEPTIONADDR,     MVT::i32, Expand);
313  setOperationAction(ISD::EXCEPTIONADDR,     MVT::i64, Expand);
314  setOperationAction(ISD::EHSELECTION,       MVT::i32, Expand);
315  setOperationAction(ISD::EHSELECTION,       MVT::i64, Expand);
316
317  setOperationAction(ISD::VAARG,             MVT::Other, Expand);
318  setOperationAction(ISD::VACOPY,            MVT::Other, Expand);
319  setOperationAction(ISD::VAEND,             MVT::Other, Expand);
320
321  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
322  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
323
324  // Use the default for now
325  setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);
326  setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);
327
328  setOperationAction(ISD::ATOMIC_LOAD,       MVT::i32,    Expand);
329  setOperationAction(ISD::ATOMIC_LOAD,       MVT::i64,    Expand);
330  setOperationAction(ISD::ATOMIC_STORE,      MVT::i32,    Expand);
331  setOperationAction(ISD::ATOMIC_STORE,      MVT::i64,    Expand);
332
333  if (Subtarget->inMips16Mode()) {
334    setOperationAction(ISD::ATOMIC_CMP_SWAP,       MVT::i32,    Expand);
335    setOperationAction(ISD::ATOMIC_SWAP,           MVT::i32,    Expand);
336    setOperationAction(ISD::ATOMIC_LOAD_ADD,       MVT::i32,    Expand);
337    setOperationAction(ISD::ATOMIC_LOAD_SUB,       MVT::i32,    Expand);
338    setOperationAction(ISD::ATOMIC_LOAD_AND,       MVT::i32,    Expand);
339    setOperationAction(ISD::ATOMIC_LOAD_OR,        MVT::i32,    Expand);
340    setOperationAction(ISD::ATOMIC_LOAD_XOR,       MVT::i32,    Expand);
341    setOperationAction(ISD::ATOMIC_LOAD_NAND,      MVT::i32,    Expand);
342    setOperationAction(ISD::ATOMIC_LOAD_MIN,       MVT::i32,    Expand);
343    setOperationAction(ISD::ATOMIC_LOAD_MAX,       MVT::i32,    Expand);
344    setOperationAction(ISD::ATOMIC_LOAD_UMIN,      MVT::i32,    Expand);
345    setOperationAction(ISD::ATOMIC_LOAD_UMAX,      MVT::i32,    Expand);
346  }
347
348  setInsertFencesForAtomic(true);
349
350  if (!Subtarget->hasSEInReg()) {
351    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
352    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
353  }
354
355  if (!Subtarget->hasBitCount()) {
356    setOperationAction(ISD::CTLZ, MVT::i32, Expand);
357    setOperationAction(ISD::CTLZ, MVT::i64, Expand);
358  }
359
360  if (!Subtarget->hasSwap()) {
361    setOperationAction(ISD::BSWAP, MVT::i32, Expand);
362    setOperationAction(ISD::BSWAP, MVT::i64, Expand);
363  }
364
365  if (HasMips64) {
366    setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
367    setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
368    setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
369    setTruncStoreAction(MVT::i64, MVT::i32, Custom);
370  }
371
372  setTargetDAGCombine(ISD::ADDE);
373  setTargetDAGCombine(ISD::SUBE);
374  setTargetDAGCombine(ISD::SDIVREM);
375  setTargetDAGCombine(ISD::UDIVREM);
376  setTargetDAGCombine(ISD::SELECT);
377  setTargetDAGCombine(ISD::AND);
378  setTargetDAGCombine(ISD::OR);
379  setTargetDAGCombine(ISD::ADD);
380
381  setMinFunctionAlignment(HasMips64 ? 3 : 2);
382
383  setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
384  computeRegisterProperties();
385
386  setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
387  setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
388
389  maxStoresPerMemcpy = 16;
390}
391
392bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
393  MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
394
395  if (Subtarget->inMips16Mode())
396    return false;
397
398  switch (SVT) {
399  case MVT::i64:
400  case MVT::i32:
401    return true;
402  default:
403    return false;
404  }
405}
406
407EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
408  return MVT::i32;
409}
410
411// SelectMadd -
412// Transforms a subgraph in CurDAG if the following pattern is found:
413//  (addc multLo, Lo0), (adde multHi, Hi0),
414// where,
415//  multHi/Lo: product of multiplication
416//  Lo0: initial value of Lo register
417//  Hi0: initial value of Hi register
418// Return true if pattern matching was successful.
419static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) {
420  // ADDENode's second operand must be a flag output of an ADDC node in order
421  // for the matching to be successful.
422  SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
423
424  if (ADDCNode->getOpcode() != ISD::ADDC)
425    return false;
426
427  SDValue MultHi = ADDENode->getOperand(0);
428  SDValue MultLo = ADDCNode->getOperand(0);
429  SDNode *MultNode = MultHi.getNode();
430  unsigned MultOpc = MultHi.getOpcode();
431
432  // MultHi and MultLo must be generated by the same node,
433  if (MultLo.getNode() != MultNode)
434    return false;
435
436  // and it must be a multiplication.
437  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
438    return false;
439
440  // MultLo amd MultHi must be the first and second output of MultNode
441  // respectively.
442  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
443    return false;
444
445  // Transform this to a MADD only if ADDENode and ADDCNode are the only users
446  // of the values of MultNode, in which case MultNode will be removed in later
447  // phases.
448  // If there exist users other than ADDENode or ADDCNode, this function returns
449  // here, which will result in MultNode being mapped to a single MULT
450  // instruction node rather than a pair of MULT and MADD instructions being
451  // produced.
452  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
453    return false;
454
455  SDValue Chain = CurDAG->getEntryNode();
456  DebugLoc dl = ADDENode->getDebugLoc();
457
458  // create MipsMAdd(u) node
459  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
460
461  SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue,
462                                 MultNode->getOperand(0),// Factor 0
463                                 MultNode->getOperand(1),// Factor 1
464                                 ADDCNode->getOperand(1),// Lo0
465                                 ADDENode->getOperand(1));// Hi0
466
467  // create CopyFromReg nodes
468  SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
469                                              MAdd);
470  SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
471                                              Mips::HI, MVT::i32,
472                                              CopyFromLo.getValue(2));
473
474  // replace uses of adde and addc here
475  if (!SDValue(ADDCNode, 0).use_empty())
476    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
477
478  if (!SDValue(ADDENode, 0).use_empty())
479    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
480
481  return true;
482}
483
484// SelectMsub -
485// Transforms a subgraph in CurDAG if the following pattern is found:
486//  (addc Lo0, multLo), (sube Hi0, multHi),
487// where,
488//  multHi/Lo: product of multiplication
489//  Lo0: initial value of Lo register
490//  Hi0: initial value of Hi register
491// Return true if pattern matching was successful.
492static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) {
493  // SUBENode's second operand must be a flag output of an SUBC node in order
494  // for the matching to be successful.
495  SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
496
497  if (SUBCNode->getOpcode() != ISD::SUBC)
498    return false;
499
500  SDValue MultHi = SUBENode->getOperand(1);
501  SDValue MultLo = SUBCNode->getOperand(1);
502  SDNode *MultNode = MultHi.getNode();
503  unsigned MultOpc = MultHi.getOpcode();
504
505  // MultHi and MultLo must be generated by the same node,
506  if (MultLo.getNode() != MultNode)
507    return false;
508
509  // and it must be a multiplication.
510  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
511    return false;
512
513  // MultLo amd MultHi must be the first and second output of MultNode
514  // respectively.
515  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
516    return false;
517
518  // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
519  // of the values of MultNode, in which case MultNode will be removed in later
520  // phases.
521  // If there exist users other than SUBENode or SUBCNode, this function returns
522  // here, which will result in MultNode being mapped to a single MULT
523  // instruction node rather than a pair of MULT and MSUB instructions being
524  // produced.
525  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
526    return false;
527
528  SDValue Chain = CurDAG->getEntryNode();
529  DebugLoc dl = SUBENode->getDebugLoc();
530
531  // create MipsSub(u) node
532  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
533
534  SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue,
535                                 MultNode->getOperand(0),// Factor 0
536                                 MultNode->getOperand(1),// Factor 1
537                                 SUBCNode->getOperand(0),// Lo0
538                                 SUBENode->getOperand(0));// Hi0
539
540  // create CopyFromReg nodes
541  SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
542                                              MSub);
543  SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
544                                              Mips::HI, MVT::i32,
545                                              CopyFromLo.getValue(2));
546
547  // replace uses of sube and subc here
548  if (!SDValue(SUBCNode, 0).use_empty())
549    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
550
551  if (!SDValue(SUBENode, 0).use_empty())
552    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
553
554  return true;
555}
556
557static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG,
558                                  TargetLowering::DAGCombinerInfo &DCI,
559                                  const MipsSubtarget *Subtarget) {
560  if (DCI.isBeforeLegalize())
561    return SDValue();
562
563  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
564      SelectMadd(N, &DAG))
565    return SDValue(N, 0);
566
567  return SDValue();
568}
569
570static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG,
571                                  TargetLowering::DAGCombinerInfo &DCI,
572                                  const MipsSubtarget *Subtarget) {
573  if (DCI.isBeforeLegalize())
574    return SDValue();
575
576  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
577      SelectMsub(N, &DAG))
578    return SDValue(N, 0);
579
580  return SDValue();
581}
582
583static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG,
584                                    TargetLowering::DAGCombinerInfo &DCI,
585                                    const MipsSubtarget *Subtarget) {
586  if (DCI.isBeforeLegalizeOps())
587    return SDValue();
588
589  EVT Ty = N->getValueType(0);
590  unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
591  unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
592  unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
593                                                  MipsISD::DivRemU;
594  DebugLoc dl = N->getDebugLoc();
595
596  SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
597                               N->getOperand(0), N->getOperand(1));
598  SDValue InChain = DAG.getEntryNode();
599  SDValue InGlue = DivRem;
600
601  // insert MFLO
602  if (N->hasAnyUseOfValue(0)) {
603    SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty,
604                                            InGlue);
605    DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
606    InChain = CopyFromLo.getValue(1);
607    InGlue = CopyFromLo.getValue(2);
608  }
609
610  // insert MFHI
611  if (N->hasAnyUseOfValue(1)) {
612    SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
613                                            HI, Ty, InGlue);
614    DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
615  }
616
617  return SDValue();
618}
619
620static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
621  switch (CC) {
622  default: llvm_unreachable("Unknown fp condition code!");
623  case ISD::SETEQ:
624  case ISD::SETOEQ: return Mips::FCOND_OEQ;
625  case ISD::SETUNE: return Mips::FCOND_UNE;
626  case ISD::SETLT:
627  case ISD::SETOLT: return Mips::FCOND_OLT;
628  case ISD::SETGT:
629  case ISD::SETOGT: return Mips::FCOND_OGT;
630  case ISD::SETLE:
631  case ISD::SETOLE: return Mips::FCOND_OLE;
632  case ISD::SETGE:
633  case ISD::SETOGE: return Mips::FCOND_OGE;
634  case ISD::SETULT: return Mips::FCOND_ULT;
635  case ISD::SETULE: return Mips::FCOND_ULE;
636  case ISD::SETUGT: return Mips::FCOND_UGT;
637  case ISD::SETUGE: return Mips::FCOND_UGE;
638  case ISD::SETUO:  return Mips::FCOND_UN;
639  case ISD::SETO:   return Mips::FCOND_OR;
640  case ISD::SETNE:
641  case ISD::SETONE: return Mips::FCOND_ONE;
642  case ISD::SETUEQ: return Mips::FCOND_UEQ;
643  }
644}
645
646
647// Returns true if condition code has to be inverted.
648static bool InvertFPCondCode(Mips::CondCode CC) {
649  if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
650    return false;
651
652  assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
653         "Illegal Condition Code");
654
655  return true;
656}
657
658// Creates and returns an FPCmp node from a setcc node.
659// Returns Op if setcc is not a floating point comparison.
660static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) {
661  // must be a SETCC node
662  if (Op.getOpcode() != ISD::SETCC)
663    return Op;
664
665  SDValue LHS = Op.getOperand(0);
666
667  if (!LHS.getValueType().isFloatingPoint())
668    return Op;
669
670  SDValue RHS = Op.getOperand(1);
671  DebugLoc dl = Op.getDebugLoc();
672
673  // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
674  // node if necessary.
675  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
676
677  return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
678                     DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
679}
680
681// Creates and returns a CMovFPT/F node.
682static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
683                            SDValue False, DebugLoc DL) {
684  bool invert = InvertFPCondCode((Mips::CondCode)
685                                 cast<ConstantSDNode>(Cond.getOperand(2))
686                                 ->getSExtValue());
687
688  return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
689                     True.getValueType(), True, False, Cond);
690}
691
692static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
693                                    TargetLowering::DAGCombinerInfo &DCI,
694                                    const MipsSubtarget *Subtarget) {
695  if (DCI.isBeforeLegalizeOps())
696    return SDValue();
697
698  SDValue SetCC = N->getOperand(0);
699
700  if ((SetCC.getOpcode() != ISD::SETCC) ||
701      !SetCC.getOperand(0).getValueType().isInteger())
702    return SDValue();
703
704  SDValue False = N->getOperand(2);
705  EVT FalseTy = False.getValueType();
706
707  if (!FalseTy.isInteger())
708    return SDValue();
709
710  ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
711
712  if (!CN || CN->getZExtValue())
713    return SDValue();
714
715  const DebugLoc DL = N->getDebugLoc();
716  ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
717  SDValue True = N->getOperand(1);
718
719  SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
720                       SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
721
722  return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
723}
724
725static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG,
726                                 TargetLowering::DAGCombinerInfo &DCI,
727                                 const MipsSubtarget *Subtarget) {
728  // Pattern match EXT.
729  //  $dst = and ((sra or srl) $src , pos), (2**size - 1)
730  //  => ext $dst, $src, size, pos
731  if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
732    return SDValue();
733
734  SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
735  unsigned ShiftRightOpc = ShiftRight.getOpcode();
736
737  // Op's first operand must be a shift right.
738  if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
739    return SDValue();
740
741  // The second operand of the shift must be an immediate.
742  ConstantSDNode *CN;
743  if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
744    return SDValue();
745
746  uint64_t Pos = CN->getZExtValue();
747  uint64_t SMPos, SMSize;
748
749  // Op's second operand must be a shifted mask.
750  if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
751      !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
752    return SDValue();
753
754  // Return if the shifted mask does not start at bit 0 or the sum of its size
755  // and Pos exceeds the word's size.
756  EVT ValTy = N->getValueType(0);
757  if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
758    return SDValue();
759
760  return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy,
761                     ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
762                     DAG.getConstant(SMSize, MVT::i32));
763}
764
765static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG,
766                                TargetLowering::DAGCombinerInfo &DCI,
767                                const MipsSubtarget *Subtarget) {
768  // Pattern match INS.
769  //  $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
770  //  where mask1 = (2**size - 1) << pos, mask0 = ~mask1
771  //  => ins $dst, $src, size, pos, $src1
772  if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
773    return SDValue();
774
775  SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
776  uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
777  ConstantSDNode *CN;
778
779  // See if Op's first operand matches (and $src1 , mask0).
780  if (And0.getOpcode() != ISD::AND)
781    return SDValue();
782
783  if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
784      !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
785    return SDValue();
786
787  // See if Op's second operand matches (and (shl $src, pos), mask1).
788  if (And1.getOpcode() != ISD::AND)
789    return SDValue();
790
791  if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
792      !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
793    return SDValue();
794
795  // The shift masks must have the same position and size.
796  if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
797    return SDValue();
798
799  SDValue Shl = And1.getOperand(0);
800  if (Shl.getOpcode() != ISD::SHL)
801    return SDValue();
802
803  if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
804    return SDValue();
805
806  unsigned Shamt = CN->getZExtValue();
807
808  // Return if the shift amount and the first bit position of mask are not the
809  // same.
810  EVT ValTy = N->getValueType(0);
811  if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
812    return SDValue();
813
814  return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0),
815                     DAG.getConstant(SMPos0, MVT::i32),
816                     DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
817}
818
819static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG,
820                                 TargetLowering::DAGCombinerInfo &DCI,
821                                 const MipsSubtarget *Subtarget) {
822  // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
823
824  if (DCI.isBeforeLegalizeOps())
825    return SDValue();
826
827  SDValue Add = N->getOperand(1);
828
829  if (Add.getOpcode() != ISD::ADD)
830    return SDValue();
831
832  SDValue Lo = Add.getOperand(1);
833
834  if ((Lo.getOpcode() != MipsISD::Lo) ||
835      (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
836    return SDValue();
837
838  EVT ValTy = N->getValueType(0);
839  DebugLoc DL = N->getDebugLoc();
840
841  SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
842                             Add.getOperand(0));
843  return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
844}
845
846SDValue  MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
847  const {
848  SelectionDAG &DAG = DCI.DAG;
849  unsigned opc = N->getOpcode();
850
851  switch (opc) {
852  default: break;
853  case ISD::ADDE:
854    return PerformADDECombine(N, DAG, DCI, Subtarget);
855  case ISD::SUBE:
856    return PerformSUBECombine(N, DAG, DCI, Subtarget);
857  case ISD::SDIVREM:
858  case ISD::UDIVREM:
859    return PerformDivRemCombine(N, DAG, DCI, Subtarget);
860  case ISD::SELECT:
861    return PerformSELECTCombine(N, DAG, DCI, Subtarget);
862  case ISD::AND:
863    return PerformANDCombine(N, DAG, DCI, Subtarget);
864  case ISD::OR:
865    return PerformORCombine(N, DAG, DCI, Subtarget);
866  case ISD::ADD:
867    return PerformADDCombine(N, DAG, DCI, Subtarget);
868  }
869
870  return SDValue();
871}
872
873void
874MipsTargetLowering::LowerOperationWrapper(SDNode *N,
875                                          SmallVectorImpl<SDValue> &Results,
876                                          SelectionDAG &DAG) const {
877  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
878
879  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
880    Results.push_back(Res.getValue(I));
881}
882
883void
884MipsTargetLowering::ReplaceNodeResults(SDNode *N,
885                                       SmallVectorImpl<SDValue> &Results,
886                                       SelectionDAG &DAG) const {
887  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
888
889  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
890    Results.push_back(Res.getValue(I));
891}
892
893SDValue MipsTargetLowering::
894LowerOperation(SDValue Op, SelectionDAG &DAG) const
895{
896  switch (Op.getOpcode())
897  {
898    case ISD::BRCOND:             return LowerBRCOND(Op, DAG);
899    case ISD::ConstantPool:       return LowerConstantPool(Op, DAG);
900    case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
901    case ISD::BlockAddress:       return LowerBlockAddress(Op, DAG);
902    case ISD::GlobalTLSAddress:   return LowerGlobalTLSAddress(Op, DAG);
903    case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
904    case ISD::SELECT:             return LowerSELECT(Op, DAG);
905    case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
906    case ISD::SETCC:              return LowerSETCC(Op, DAG);
907    case ISD::VASTART:            return LowerVASTART(Op, DAG);
908    case ISD::FCOPYSIGN:          return LowerFCOPYSIGN(Op, DAG);
909    case ISD::FABS:               return LowerFABS(Op, DAG);
910    case ISD::FRAMEADDR:          return LowerFRAMEADDR(Op, DAG);
911    case ISD::RETURNADDR:         return LowerRETURNADDR(Op, DAG);
912    case ISD::MEMBARRIER:         return LowerMEMBARRIER(Op, DAG);
913    case ISD::ATOMIC_FENCE:       return LowerATOMIC_FENCE(Op, DAG);
914    case ISD::SHL_PARTS:          return LowerShiftLeftParts(Op, DAG);
915    case ISD::SRA_PARTS:          return LowerShiftRightParts(Op, DAG, true);
916    case ISD::SRL_PARTS:          return LowerShiftRightParts(Op, DAG, false);
917    case ISD::LOAD:               return LowerLOAD(Op, DAG);
918    case ISD::STORE:              return LowerSTORE(Op, DAG);
919    case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
920    case ISD::INTRINSIC_W_CHAIN:  return LowerINTRINSIC_W_CHAIN(Op, DAG);
921    case ISD::ADD:                return LowerADD(Op, DAG);
922  }
923  return SDValue();
924}
925
926//===----------------------------------------------------------------------===//
927//  Lower helper functions
928//===----------------------------------------------------------------------===//
929
930// AddLiveIn - This helper function adds the specified physical register to the
931// MachineFunction as a live in value.  It also creates a corresponding
932// virtual register for it.
933static unsigned
934AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
935{
936  assert(RC->contains(PReg) && "Not the correct regclass!");
937  unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
938  MF.getRegInfo().addLiveIn(PReg, VReg);
939  return VReg;
940}
941
942// Get fp branch code (not opcode) from condition code.
943static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
944  if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
945    return Mips::BRANCH_T;
946
947  assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
948         "Invalid CondCode.");
949
950  return Mips::BRANCH_F;
951}
952
953/*
954static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
955                                        DebugLoc dl,
956                                        const MipsSubtarget *Subtarget,
957                                        const TargetInstrInfo *TII,
958                                        bool isFPCmp, unsigned Opc) {
959  // There is no need to expand CMov instructions if target has
960  // conditional moves.
961  if (Subtarget->hasCondMov())
962    return BB;
963
964  // To "insert" a SELECT_CC instruction, we actually have to insert the
965  // diamond control-flow pattern.  The incoming instruction knows the
966  // destination vreg to set, the condition code register to branch on, the
967  // true/false values to select between, and a branch opcode to use.
968  const BasicBlock *LLVM_BB = BB->getBasicBlock();
969  MachineFunction::iterator It = BB;
970  ++It;
971
972  //  thisMBB:
973  //  ...
974  //   TrueVal = ...
975  //   setcc r1, r2, r3
976  //   bNE   r1, r0, copy1MBB
977  //   fallthrough --> copy0MBB
978  MachineBasicBlock *thisMBB  = BB;
979  MachineFunction *F = BB->getParent();
980  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
981  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
982  F->insert(It, copy0MBB);
983  F->insert(It, sinkMBB);
984
985  // Transfer the remainder of BB and its successor edges to sinkMBB.
986  sinkMBB->splice(sinkMBB->begin(), BB,
987                  llvm::next(MachineBasicBlock::iterator(MI)),
988                  BB->end());
989  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
990
991  // Next, add the true and fallthrough blocks as its successors.
992  BB->addSuccessor(copy0MBB);
993  BB->addSuccessor(sinkMBB);
994
995  // Emit the right instruction according to the type of the operands compared
996  if (isFPCmp)
997    BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
998  else
999    BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
1000      .addReg(Mips::ZERO).addMBB(sinkMBB);
1001
1002  //  copy0MBB:
1003  //   %FalseValue = ...
1004  //   # fallthrough to sinkMBB
1005  BB = copy0MBB;
1006
1007  // Update machine-CFG edges
1008  BB->addSuccessor(sinkMBB);
1009
1010  //  sinkMBB:
1011  //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
1012  //  ...
1013  BB = sinkMBB;
1014
1015  if (isFPCmp)
1016    BuildMI(*BB, BB->begin(), dl,
1017            TII->get(Mips::PHI), MI->getOperand(0).getReg())
1018      .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
1019      .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
1020  else
1021    BuildMI(*BB, BB->begin(), dl,
1022            TII->get(Mips::PHI), MI->getOperand(0).getReg())
1023      .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
1024      .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
1025
1026  MI->eraseFromParent();   // The pseudo instruction is gone now.
1027  return BB;
1028}
1029*/
1030
1031MachineBasicBlock *
1032MipsTargetLowering::EmitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
1033  // $bb:
1034  //  bposge32_pseudo $vr0
1035  //  =>
1036  // $bb:
1037  //  bposge32 $tbb
1038  // $fbb:
1039  //  li $vr2, 0
1040  //  b $sink
1041  // $tbb:
1042  //  li $vr1, 1
1043  // $sink:
1044  //  $vr0 = phi($vr2, $fbb, $vr1, $tbb)
1045
1046  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1047  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1048  const TargetRegisterClass *RC = &Mips::CPURegsRegClass;
1049  DebugLoc DL = MI->getDebugLoc();
1050  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1051  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1052  MachineFunction *F = BB->getParent();
1053  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1054  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1055  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
1056  F->insert(It, FBB);
1057  F->insert(It, TBB);
1058  F->insert(It, Sink);
1059
1060  // Transfer the remainder of BB and its successor edges to Sink.
1061  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1062               BB->end());
1063  Sink->transferSuccessorsAndUpdatePHIs(BB);
1064
1065  // Add successors.
1066  BB->addSuccessor(FBB);
1067  BB->addSuccessor(TBB);
1068  FBB->addSuccessor(Sink);
1069  TBB->addSuccessor(Sink);
1070
1071  // Insert the real bposge32 instruction to $BB.
1072  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
1073
1074  // Fill $FBB.
1075  unsigned VR2 = RegInfo.createVirtualRegister(RC);
1076  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
1077    .addReg(Mips::ZERO).addImm(0);
1078  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1079
1080  // Fill $TBB.
1081  unsigned VR1 = RegInfo.createVirtualRegister(RC);
1082  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
1083    .addReg(Mips::ZERO).addImm(1);
1084
1085  // Insert phi function to $Sink.
1086  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1087          MI->getOperand(0).getReg())
1088    .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
1089
1090  MI->eraseFromParent();   // The pseudo instruction is gone now.
1091  return Sink;
1092}
1093
1094MachineBasicBlock *
1095MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1096                                                MachineBasicBlock *BB) const {
1097  switch (MI->getOpcode()) {
1098  default: llvm_unreachable("Unexpected instr type to insert");
1099  case Mips::ATOMIC_LOAD_ADD_I8:
1100  case Mips::ATOMIC_LOAD_ADD_I8_P8:
1101    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
1102  case Mips::ATOMIC_LOAD_ADD_I16:
1103  case Mips::ATOMIC_LOAD_ADD_I16_P8:
1104    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
1105  case Mips::ATOMIC_LOAD_ADD_I32:
1106  case Mips::ATOMIC_LOAD_ADD_I32_P8:
1107    return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
1108  case Mips::ATOMIC_LOAD_ADD_I64:
1109  case Mips::ATOMIC_LOAD_ADD_I64_P8:
1110    return EmitAtomicBinary(MI, BB, 8, Mips::DADDu);
1111
1112  case Mips::ATOMIC_LOAD_AND_I8:
1113  case Mips::ATOMIC_LOAD_AND_I8_P8:
1114    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
1115  case Mips::ATOMIC_LOAD_AND_I16:
1116  case Mips::ATOMIC_LOAD_AND_I16_P8:
1117    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
1118  case Mips::ATOMIC_LOAD_AND_I32:
1119  case Mips::ATOMIC_LOAD_AND_I32_P8:
1120    return EmitAtomicBinary(MI, BB, 4, Mips::AND);
1121  case Mips::ATOMIC_LOAD_AND_I64:
1122  case Mips::ATOMIC_LOAD_AND_I64_P8:
1123    return EmitAtomicBinary(MI, BB, 8, Mips::AND64);
1124
1125  case Mips::ATOMIC_LOAD_OR_I8:
1126  case Mips::ATOMIC_LOAD_OR_I8_P8:
1127    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
1128  case Mips::ATOMIC_LOAD_OR_I16:
1129  case Mips::ATOMIC_LOAD_OR_I16_P8:
1130    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
1131  case Mips::ATOMIC_LOAD_OR_I32:
1132  case Mips::ATOMIC_LOAD_OR_I32_P8:
1133    return EmitAtomicBinary(MI, BB, 4, Mips::OR);
1134  case Mips::ATOMIC_LOAD_OR_I64:
1135  case Mips::ATOMIC_LOAD_OR_I64_P8:
1136    return EmitAtomicBinary(MI, BB, 8, Mips::OR64);
1137
1138  case Mips::ATOMIC_LOAD_XOR_I8:
1139  case Mips::ATOMIC_LOAD_XOR_I8_P8:
1140    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
1141  case Mips::ATOMIC_LOAD_XOR_I16:
1142  case Mips::ATOMIC_LOAD_XOR_I16_P8:
1143    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
1144  case Mips::ATOMIC_LOAD_XOR_I32:
1145  case Mips::ATOMIC_LOAD_XOR_I32_P8:
1146    return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
1147  case Mips::ATOMIC_LOAD_XOR_I64:
1148  case Mips::ATOMIC_LOAD_XOR_I64_P8:
1149    return EmitAtomicBinary(MI, BB, 8, Mips::XOR64);
1150
1151  case Mips::ATOMIC_LOAD_NAND_I8:
1152  case Mips::ATOMIC_LOAD_NAND_I8_P8:
1153    return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
1154  case Mips::ATOMIC_LOAD_NAND_I16:
1155  case Mips::ATOMIC_LOAD_NAND_I16_P8:
1156    return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
1157  case Mips::ATOMIC_LOAD_NAND_I32:
1158  case Mips::ATOMIC_LOAD_NAND_I32_P8:
1159    return EmitAtomicBinary(MI, BB, 4, 0, true);
1160  case Mips::ATOMIC_LOAD_NAND_I64:
1161  case Mips::ATOMIC_LOAD_NAND_I64_P8:
1162    return EmitAtomicBinary(MI, BB, 8, 0, true);
1163
1164  case Mips::ATOMIC_LOAD_SUB_I8:
1165  case Mips::ATOMIC_LOAD_SUB_I8_P8:
1166    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
1167  case Mips::ATOMIC_LOAD_SUB_I16:
1168  case Mips::ATOMIC_LOAD_SUB_I16_P8:
1169    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
1170  case Mips::ATOMIC_LOAD_SUB_I32:
1171  case Mips::ATOMIC_LOAD_SUB_I32_P8:
1172    return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
1173  case Mips::ATOMIC_LOAD_SUB_I64:
1174  case Mips::ATOMIC_LOAD_SUB_I64_P8:
1175    return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu);
1176
1177  case Mips::ATOMIC_SWAP_I8:
1178  case Mips::ATOMIC_SWAP_I8_P8:
1179    return EmitAtomicBinaryPartword(MI, BB, 1, 0);
1180  case Mips::ATOMIC_SWAP_I16:
1181  case Mips::ATOMIC_SWAP_I16_P8:
1182    return EmitAtomicBinaryPartword(MI, BB, 2, 0);
1183  case Mips::ATOMIC_SWAP_I32:
1184  case Mips::ATOMIC_SWAP_I32_P8:
1185    return EmitAtomicBinary(MI, BB, 4, 0);
1186  case Mips::ATOMIC_SWAP_I64:
1187  case Mips::ATOMIC_SWAP_I64_P8:
1188    return EmitAtomicBinary(MI, BB, 8, 0);
1189
1190  case Mips::ATOMIC_CMP_SWAP_I8:
1191  case Mips::ATOMIC_CMP_SWAP_I8_P8:
1192    return EmitAtomicCmpSwapPartword(MI, BB, 1);
1193  case Mips::ATOMIC_CMP_SWAP_I16:
1194  case Mips::ATOMIC_CMP_SWAP_I16_P8:
1195    return EmitAtomicCmpSwapPartword(MI, BB, 2);
1196  case Mips::ATOMIC_CMP_SWAP_I32:
1197  case Mips::ATOMIC_CMP_SWAP_I32_P8:
1198    return EmitAtomicCmpSwap(MI, BB, 4);
1199  case Mips::ATOMIC_CMP_SWAP_I64:
1200  case Mips::ATOMIC_CMP_SWAP_I64_P8:
1201    return EmitAtomicCmpSwap(MI, BB, 8);
1202  case Mips::BPOSGE32_PSEUDO:
1203    return EmitBPOSGE32(MI, BB);
1204  }
1205}
1206
1207// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1208// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1209MachineBasicBlock *
1210MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
1211                                     unsigned Size, unsigned BinOpcode,
1212                                     bool Nand) const {
1213  assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
1214
1215  MachineFunction *MF = BB->getParent();
1216  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1217  const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1218  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1219  DebugLoc dl = MI->getDebugLoc();
1220  unsigned LL, SC, AND, NOR, ZERO, BEQ;
1221
1222  if (Size == 4) {
1223    LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1224    SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1225    AND = Mips::AND;
1226    NOR = Mips::NOR;
1227    ZERO = Mips::ZERO;
1228    BEQ = Mips::BEQ;
1229  }
1230  else {
1231    LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1232    SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1233    AND = Mips::AND64;
1234    NOR = Mips::NOR64;
1235    ZERO = Mips::ZERO_64;
1236    BEQ = Mips::BEQ64;
1237  }
1238
1239  unsigned OldVal = MI->getOperand(0).getReg();
1240  unsigned Ptr = MI->getOperand(1).getReg();
1241  unsigned Incr = MI->getOperand(2).getReg();
1242
1243  unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1244  unsigned AndRes = RegInfo.createVirtualRegister(RC);
1245  unsigned Success = RegInfo.createVirtualRegister(RC);
1246
1247  // insert new blocks after the current block
1248  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1249  MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1250  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1251  MachineFunction::iterator It = BB;
1252  ++It;
1253  MF->insert(It, loopMBB);
1254  MF->insert(It, exitMBB);
1255
1256  // Transfer the remainder of BB and its successor edges to exitMBB.
1257  exitMBB->splice(exitMBB->begin(), BB,
1258                  llvm::next(MachineBasicBlock::iterator(MI)),
1259                  BB->end());
1260  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1261
1262  //  thisMBB:
1263  //    ...
1264  //    fallthrough --> loopMBB
1265  BB->addSuccessor(loopMBB);
1266  loopMBB->addSuccessor(loopMBB);
1267  loopMBB->addSuccessor(exitMBB);
1268
1269  //  loopMBB:
1270  //    ll oldval, 0(ptr)
1271  //    <binop> storeval, oldval, incr
1272  //    sc success, storeval, 0(ptr)
1273  //    beq success, $0, loopMBB
1274  BB = loopMBB;
1275  BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1276  if (Nand) {
1277    //  and andres, oldval, incr
1278    //  nor storeval, $0, andres
1279    BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1280    BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1281  } else if (BinOpcode) {
1282    //  <binop> storeval, oldval, incr
1283    BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1284  } else {
1285    StoreVal = Incr;
1286  }
1287  BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1288  BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1289
1290  MI->eraseFromParent();   // The instruction is gone now.
1291
1292  return exitMBB;
1293}
1294
1295MachineBasicBlock *
1296MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
1297                                             MachineBasicBlock *BB,
1298                                             unsigned Size, unsigned BinOpcode,
1299                                             bool Nand) const {
1300  assert((Size == 1 || Size == 2) &&
1301      "Unsupported size for EmitAtomicBinaryPartial.");
1302
1303  MachineFunction *MF = BB->getParent();
1304  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1305  const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1306  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1307  DebugLoc dl = MI->getDebugLoc();
1308  unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1309  unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1310
1311  unsigned Dest = MI->getOperand(0).getReg();
1312  unsigned Ptr = MI->getOperand(1).getReg();
1313  unsigned Incr = MI->getOperand(2).getReg();
1314
1315  unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1316  unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1317  unsigned Mask = RegInfo.createVirtualRegister(RC);
1318  unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1319  unsigned NewVal = RegInfo.createVirtualRegister(RC);
1320  unsigned OldVal = RegInfo.createVirtualRegister(RC);
1321  unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1322  unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1323  unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1324  unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1325  unsigned AndRes = RegInfo.createVirtualRegister(RC);
1326  unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1327  unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1328  unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1329  unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1330  unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1331  unsigned SllRes = RegInfo.createVirtualRegister(RC);
1332  unsigned Success = RegInfo.createVirtualRegister(RC);
1333
1334  // insert new blocks after the current block
1335  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1336  MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1337  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1338  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1339  MachineFunction::iterator It = BB;
1340  ++It;
1341  MF->insert(It, loopMBB);
1342  MF->insert(It, sinkMBB);
1343  MF->insert(It, exitMBB);
1344
1345  // Transfer the remainder of BB and its successor edges to exitMBB.
1346  exitMBB->splice(exitMBB->begin(), BB,
1347                  llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1348  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1349
1350  BB->addSuccessor(loopMBB);
1351  loopMBB->addSuccessor(loopMBB);
1352  loopMBB->addSuccessor(sinkMBB);
1353  sinkMBB->addSuccessor(exitMBB);
1354
1355  //  thisMBB:
1356  //    addiu   masklsb2,$0,-4                # 0xfffffffc
1357  //    and     alignedaddr,ptr,masklsb2
1358  //    andi    ptrlsb2,ptr,3
1359  //    sll     shiftamt,ptrlsb2,3
1360  //    ori     maskupper,$0,255               # 0xff
1361  //    sll     mask,maskupper,shiftamt
1362  //    nor     mask2,$0,mask
1363  //    sll     incr2,incr,shiftamt
1364
1365  int64_t MaskImm = (Size == 1) ? 255 : 65535;
1366  BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1367    .addReg(Mips::ZERO).addImm(-4);
1368  BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1369    .addReg(Ptr).addReg(MaskLSB2);
1370  BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1371  BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1372  BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1373    .addReg(Mips::ZERO).addImm(MaskImm);
1374  BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1375    .addReg(ShiftAmt).addReg(MaskUpper);
1376  BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1377  BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
1378
1379  // atomic.load.binop
1380  // loopMBB:
1381  //   ll      oldval,0(alignedaddr)
1382  //   binop   binopres,oldval,incr2
1383  //   and     newval,binopres,mask
1384  //   and     maskedoldval0,oldval,mask2
1385  //   or      storeval,maskedoldval0,newval
1386  //   sc      success,storeval,0(alignedaddr)
1387  //   beq     success,$0,loopMBB
1388
1389  // atomic.swap
1390  // loopMBB:
1391  //   ll      oldval,0(alignedaddr)
1392  //   and     newval,incr2,mask
1393  //   and     maskedoldval0,oldval,mask2
1394  //   or      storeval,maskedoldval0,newval
1395  //   sc      success,storeval,0(alignedaddr)
1396  //   beq     success,$0,loopMBB
1397
1398  BB = loopMBB;
1399  BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1400  if (Nand) {
1401    //  and andres, oldval, incr2
1402    //  nor binopres, $0, andres
1403    //  and newval, binopres, mask
1404    BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1405    BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
1406      .addReg(Mips::ZERO).addReg(AndRes);
1407    BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1408  } else if (BinOpcode) {
1409    //  <binop> binopres, oldval, incr2
1410    //  and newval, binopres, mask
1411    BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1412    BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1413  } else {// atomic.swap
1414    //  and newval, incr2, mask
1415    BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1416  }
1417
1418  BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1419    .addReg(OldVal).addReg(Mask2);
1420  BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1421    .addReg(MaskedOldVal0).addReg(NewVal);
1422  BuildMI(BB, dl, TII->get(SC), Success)
1423    .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1424  BuildMI(BB, dl, TII->get(Mips::BEQ))
1425    .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1426
1427  //  sinkMBB:
1428  //    and     maskedoldval1,oldval,mask
1429  //    srl     srlres,maskedoldval1,shiftamt
1430  //    sll     sllres,srlres,24
1431  //    sra     dest,sllres,24
1432  BB = sinkMBB;
1433  int64_t ShiftImm = (Size == 1) ? 24 : 16;
1434
1435  BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1436    .addReg(OldVal).addReg(Mask);
1437  BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1438      .addReg(ShiftAmt).addReg(MaskedOldVal1);
1439  BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1440      .addReg(SrlRes).addImm(ShiftImm);
1441  BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
1442      .addReg(SllRes).addImm(ShiftImm);
1443
1444  MI->eraseFromParent();   // The instruction is gone now.
1445
1446  return exitMBB;
1447}
1448
1449MachineBasicBlock *
1450MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
1451                                      MachineBasicBlock *BB,
1452                                      unsigned Size) const {
1453  assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1454
1455  MachineFunction *MF = BB->getParent();
1456  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1457  const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1458  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1459  DebugLoc dl = MI->getDebugLoc();
1460  unsigned LL, SC, ZERO, BNE, BEQ;
1461
1462  if (Size == 4) {
1463    LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1464    SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1465    ZERO = Mips::ZERO;
1466    BNE = Mips::BNE;
1467    BEQ = Mips::BEQ;
1468  }
1469  else {
1470    LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1471    SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1472    ZERO = Mips::ZERO_64;
1473    BNE = Mips::BNE64;
1474    BEQ = Mips::BEQ64;
1475  }
1476
1477  unsigned Dest    = MI->getOperand(0).getReg();
1478  unsigned Ptr     = MI->getOperand(1).getReg();
1479  unsigned OldVal  = MI->getOperand(2).getReg();
1480  unsigned NewVal  = MI->getOperand(3).getReg();
1481
1482  unsigned Success = RegInfo.createVirtualRegister(RC);
1483
1484  // insert new blocks after the current block
1485  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1486  MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1487  MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1488  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1489  MachineFunction::iterator It = BB;
1490  ++It;
1491  MF->insert(It, loop1MBB);
1492  MF->insert(It, loop2MBB);
1493  MF->insert(It, exitMBB);
1494
1495  // Transfer the remainder of BB and its successor edges to exitMBB.
1496  exitMBB->splice(exitMBB->begin(), BB,
1497                  llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1498  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1499
1500  //  thisMBB:
1501  //    ...
1502  //    fallthrough --> loop1MBB
1503  BB->addSuccessor(loop1MBB);
1504  loop1MBB->addSuccessor(exitMBB);
1505  loop1MBB->addSuccessor(loop2MBB);
1506  loop2MBB->addSuccessor(loop1MBB);
1507  loop2MBB->addSuccessor(exitMBB);
1508
1509  // loop1MBB:
1510  //   ll dest, 0(ptr)
1511  //   bne dest, oldval, exitMBB
1512  BB = loop1MBB;
1513  BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1514  BuildMI(BB, dl, TII->get(BNE))
1515    .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1516
1517  // loop2MBB:
1518  //   sc success, newval, 0(ptr)
1519  //   beq success, $0, loop1MBB
1520  BB = loop2MBB;
1521  BuildMI(BB, dl, TII->get(SC), Success)
1522    .addReg(NewVal).addReg(Ptr).addImm(0);
1523  BuildMI(BB, dl, TII->get(BEQ))
1524    .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1525
1526  MI->eraseFromParent();   // The instruction is gone now.
1527
1528  return exitMBB;
1529}
1530
1531MachineBasicBlock *
1532MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
1533                                              MachineBasicBlock *BB,
1534                                              unsigned Size) const {
1535  assert((Size == 1 || Size == 2) &&
1536      "Unsupported size for EmitAtomicCmpSwapPartial.");
1537
1538  MachineFunction *MF = BB->getParent();
1539  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1540  const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1541  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1542  DebugLoc dl = MI->getDebugLoc();
1543  unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1544  unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1545
1546  unsigned Dest    = MI->getOperand(0).getReg();
1547  unsigned Ptr     = MI->getOperand(1).getReg();
1548  unsigned CmpVal  = MI->getOperand(2).getReg();
1549  unsigned NewVal  = MI->getOperand(3).getReg();
1550
1551  unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1552  unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1553  unsigned Mask = RegInfo.createVirtualRegister(RC);
1554  unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1555  unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1556  unsigned OldVal = RegInfo.createVirtualRegister(RC);
1557  unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1558  unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1559  unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1560  unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1561  unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1562  unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1563  unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1564  unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1565  unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1566  unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1567  unsigned SllRes = RegInfo.createVirtualRegister(RC);
1568  unsigned Success = RegInfo.createVirtualRegister(RC);
1569
1570  // insert new blocks after the current block
1571  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1572  MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1573  MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1574  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1575  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1576  MachineFunction::iterator It = BB;
1577  ++It;
1578  MF->insert(It, loop1MBB);
1579  MF->insert(It, loop2MBB);
1580  MF->insert(It, sinkMBB);
1581  MF->insert(It, exitMBB);
1582
1583  // Transfer the remainder of BB and its successor edges to exitMBB.
1584  exitMBB->splice(exitMBB->begin(), BB,
1585                  llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1586  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1587
1588  BB->addSuccessor(loop1MBB);
1589  loop1MBB->addSuccessor(sinkMBB);
1590  loop1MBB->addSuccessor(loop2MBB);
1591  loop2MBB->addSuccessor(loop1MBB);
1592  loop2MBB->addSuccessor(sinkMBB);
1593  sinkMBB->addSuccessor(exitMBB);
1594
1595  // FIXME: computation of newval2 can be moved to loop2MBB.
1596  //  thisMBB:
1597  //    addiu   masklsb2,$0,-4                # 0xfffffffc
1598  //    and     alignedaddr,ptr,masklsb2
1599  //    andi    ptrlsb2,ptr,3
1600  //    sll     shiftamt,ptrlsb2,3
1601  //    ori     maskupper,$0,255               # 0xff
1602  //    sll     mask,maskupper,shiftamt
1603  //    nor     mask2,$0,mask
1604  //    andi    maskedcmpval,cmpval,255
1605  //    sll     shiftedcmpval,maskedcmpval,shiftamt
1606  //    andi    maskednewval,newval,255
1607  //    sll     shiftednewval,maskednewval,shiftamt
1608  int64_t MaskImm = (Size == 1) ? 255 : 65535;
1609  BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1610    .addReg(Mips::ZERO).addImm(-4);
1611  BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1612    .addReg(Ptr).addReg(MaskLSB2);
1613  BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1614  BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1615  BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1616    .addReg(Mips::ZERO).addImm(MaskImm);
1617  BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1618    .addReg(ShiftAmt).addReg(MaskUpper);
1619  BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1620  BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
1621    .addReg(CmpVal).addImm(MaskImm);
1622  BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
1623    .addReg(ShiftAmt).addReg(MaskedCmpVal);
1624  BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
1625    .addReg(NewVal).addImm(MaskImm);
1626  BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
1627    .addReg(ShiftAmt).addReg(MaskedNewVal);
1628
1629  //  loop1MBB:
1630  //    ll      oldval,0(alginedaddr)
1631  //    and     maskedoldval0,oldval,mask
1632  //    bne     maskedoldval0,shiftedcmpval,sinkMBB
1633  BB = loop1MBB;
1634  BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1635  BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1636    .addReg(OldVal).addReg(Mask);
1637  BuildMI(BB, dl, TII->get(Mips::BNE))
1638    .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1639
1640  //  loop2MBB:
1641  //    and     maskedoldval1,oldval,mask2
1642  //    or      storeval,maskedoldval1,shiftednewval
1643  //    sc      success,storeval,0(alignedaddr)
1644  //    beq     success,$0,loop1MBB
1645  BB = loop2MBB;
1646  BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1647    .addReg(OldVal).addReg(Mask2);
1648  BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1649    .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1650  BuildMI(BB, dl, TII->get(SC), Success)
1651      .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1652  BuildMI(BB, dl, TII->get(Mips::BEQ))
1653      .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1654
1655  //  sinkMBB:
1656  //    srl     srlres,maskedoldval0,shiftamt
1657  //    sll     sllres,srlres,24
1658  //    sra     dest,sllres,24
1659  BB = sinkMBB;
1660  int64_t ShiftImm = (Size == 1) ? 24 : 16;
1661
1662  BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1663      .addReg(ShiftAmt).addReg(MaskedOldVal0);
1664  BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1665      .addReg(SrlRes).addImm(ShiftImm);
1666  BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
1667      .addReg(SllRes).addImm(ShiftImm);
1668
1669  MI->eraseFromParent();   // The instruction is gone now.
1670
1671  return exitMBB;
1672}
1673
1674//===----------------------------------------------------------------------===//
1675//  Misc Lower Operation implementation
1676//===----------------------------------------------------------------------===//
1677SDValue MipsTargetLowering::
1678LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
1679{
1680  // The first operand is the chain, the second is the condition, the third is
1681  // the block to branch to if the condition is true.
1682  SDValue Chain = Op.getOperand(0);
1683  SDValue Dest = Op.getOperand(2);
1684  DebugLoc dl = Op.getDebugLoc();
1685
1686  SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
1687
1688  // Return if flag is not set by a floating point comparison.
1689  if (CondRes.getOpcode() != MipsISD::FPCmp)
1690    return Op;
1691
1692  SDValue CCNode  = CondRes.getOperand(2);
1693  Mips::CondCode CC =
1694    (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1695  SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
1696
1697  return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
1698                     Dest, CondRes);
1699}
1700
1701SDValue MipsTargetLowering::
1702LowerSELECT(SDValue Op, SelectionDAG &DAG) const
1703{
1704  SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
1705
1706  // Return if flag is not set by a floating point comparison.
1707  if (Cond.getOpcode() != MipsISD::FPCmp)
1708    return Op;
1709
1710  return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1711                      Op.getDebugLoc());
1712}
1713
1714SDValue MipsTargetLowering::
1715LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1716{
1717  DebugLoc DL = Op.getDebugLoc();
1718  EVT Ty = Op.getOperand(0).getValueType();
1719  SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty),
1720                             Op.getOperand(0), Op.getOperand(1),
1721                             Op.getOperand(4));
1722
1723  return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1724                     Op.getOperand(3));
1725}
1726
1727SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1728  SDValue Cond = CreateFPCmp(DAG, Op);
1729
1730  assert(Cond.getOpcode() == MipsISD::FPCmp &&
1731         "Floating point operand expected.");
1732
1733  SDValue True  = DAG.getConstant(1, MVT::i32);
1734  SDValue False = DAG.getConstant(0, MVT::i32);
1735
1736  return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc());
1737}
1738
1739SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
1740                                               SelectionDAG &DAG) const {
1741  // FIXME there isn't actually debug info here
1742  DebugLoc dl = Op.getDebugLoc();
1743  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1744
1745  if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1746    SDVTList VTs = DAG.getVTList(MVT::i32);
1747
1748    const MipsTargetObjectFile &TLOF =
1749      (const MipsTargetObjectFile&)getObjFileLowering();
1750
1751    // %gp_rel relocation
1752    if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1753      SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1754                                              MipsII::MO_GPREL);
1755      SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
1756      SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
1757      return DAG.getNode(ISD::ADD, dl, MVT::i32, GPReg, GPRelNode);
1758    }
1759    // %hi/%lo relocation
1760    SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1761                                              MipsII::MO_ABS_HI);
1762    SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1763                                              MipsII::MO_ABS_LO);
1764    SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
1765    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
1766    return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1767  }
1768
1769  EVT ValTy = Op.getValueType();
1770  bool HasGotOfst = (GV->hasInternalLinkage() ||
1771                     (GV->hasLocalLinkage() && !isa<Function>(GV)));
1772  unsigned GotFlag = HasMips64 ?
1773                     (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) :
1774                     (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16);
1775  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag);
1776  GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), GA);
1777  SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA,
1778                                MachinePointerInfo::getGOT(), false, false,
1779                                false, 0);
1780  // On functions and global targets not internal linked only
1781  // a load from got/GP is necessary for PIC to work.
1782  if (!HasGotOfst)
1783    return ResNode;
1784  SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0,
1785                                            HasMips64 ? MipsII::MO_GOT_OFST :
1786                                                        MipsII::MO_ABS_LO);
1787  SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo);
1788  return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo);
1789}
1790
1791SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
1792                                              SelectionDAG &DAG) const {
1793  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1794  // FIXME there isn't actually debug info here
1795  DebugLoc dl = Op.getDebugLoc();
1796
1797  if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1798    // %hi/%lo relocation
1799    SDValue BAHi =
1800      DAG.getTargetBlockAddress(BA, MVT::i32, 0, MipsII::MO_ABS_HI);
1801    SDValue BALo =
1802      DAG.getTargetBlockAddress(BA, MVT::i32, 0, MipsII::MO_ABS_LO);
1803    SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
1804    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
1805    return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
1806  }
1807
1808  EVT ValTy = Op.getValueType();
1809  unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1810  unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
1811  SDValue BAGOTOffset = DAG.getTargetBlockAddress(BA, ValTy, 0, GOTFlag);
1812  BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy,
1813                            GetGlobalReg(DAG, ValTy), BAGOTOffset);
1814  SDValue BALOOffset = DAG.getTargetBlockAddress(BA, ValTy, 0, OFSTFlag);
1815  SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset,
1816                             MachinePointerInfo::getGOT(), false, false, false,
1817                             0);
1818  SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset);
1819  return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
1820}
1821
1822SDValue MipsTargetLowering::
1823LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1824{
1825  // If the relocation model is PIC, use the General Dynamic TLS Model or
1826  // Local Dynamic TLS model, otherwise use the Initial Exec or
1827  // Local Exec TLS Model.
1828
1829  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1830  DebugLoc dl = GA->getDebugLoc();
1831  const GlobalValue *GV = GA->getGlobal();
1832  EVT PtrVT = getPointerTy();
1833
1834  TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1835
1836  if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1837    // General Dynamic and Local Dynamic TLS Model.
1838    unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1839                                                      : MipsII::MO_TLSGD;
1840
1841    SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag);
1842    SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT,
1843                                   GetGlobalReg(DAG, PtrVT), TGA);
1844    unsigned PtrSize = PtrVT.getSizeInBits();
1845    IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1846
1847    SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1848
1849    ArgListTy Args;
1850    ArgListEntry Entry;
1851    Entry.Node = Argument;
1852    Entry.Ty = PtrTy;
1853    Args.push_back(Entry);
1854
1855    TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
1856                  false, false, false, false, 0, CallingConv::C,
1857                  /*isTailCall=*/false, /*doesNotRet=*/false,
1858                  /*isReturnValueUsed=*/true,
1859                  TlsGetAddr, Args, DAG, dl);
1860    std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1861
1862    SDValue Ret = CallResult.first;
1863
1864    if (model != TLSModel::LocalDynamic)
1865      return Ret;
1866
1867    SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1868                                               MipsII::MO_DTPREL_HI);
1869    SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1870    SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1871                                               MipsII::MO_DTPREL_LO);
1872    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1873    SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret);
1874    return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo);
1875  }
1876
1877  SDValue Offset;
1878  if (model == TLSModel::InitialExec) {
1879    // Initial Exec TLS Model
1880    SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1881                                             MipsII::MO_GOTTPREL);
1882    TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1883                      TGA);
1884    Offset = DAG.getLoad(PtrVT, dl,
1885                         DAG.getEntryNode(), TGA, MachinePointerInfo(),
1886                         false, false, false, 0);
1887  } else {
1888    // Local Exec TLS Model
1889    assert(model == TLSModel::LocalExec);
1890    SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1891                                               MipsII::MO_TPREL_HI);
1892    SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1893                                               MipsII::MO_TPREL_LO);
1894    SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1895    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1896    Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1897  }
1898
1899  SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
1900  return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1901}
1902
1903SDValue MipsTargetLowering::
1904LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1905{
1906  SDValue HiPart, JTI, JTILo;
1907  // FIXME there isn't actually debug info here
1908  DebugLoc dl = Op.getDebugLoc();
1909  bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1910  EVT PtrVT = Op.getValueType();
1911  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1912
1913  if (!IsPIC && !IsN64) {
1914    JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_HI);
1915    HiPart = DAG.getNode(MipsISD::Hi, dl, PtrVT, JTI);
1916    JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO);
1917  } else {// Emit Load from Global Pointer
1918    unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1919    unsigned OfstFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
1920    JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, GOTFlag);
1921    JTI = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1922                      JTI);
1923    HiPart = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), JTI,
1924                         MachinePointerInfo::getGOT(), false, false, false, 0);
1925    JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OfstFlag);
1926  }
1927
1928  SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo);
1929  return DAG.getNode(ISD::ADD, dl, PtrVT, HiPart, Lo);
1930}
1931
1932SDValue MipsTargetLowering::
1933LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1934{
1935  SDValue ResNode;
1936  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1937  const Constant *C = N->getConstVal();
1938  // FIXME there isn't actually debug info here
1939  DebugLoc dl = Op.getDebugLoc();
1940
1941  // gp_rel relocation
1942  // FIXME: we should reference the constant pool using small data sections,
1943  // but the asm printer currently doesn't support this feature without
1944  // hacking it. This feature should come soon so we can uncomment the
1945  // stuff below.
1946  //if (IsInSmallSection(C->getType())) {
1947  //  SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1948  //  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1949  //  ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
1950
1951  if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1952    SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1953                                             N->getOffset(), MipsII::MO_ABS_HI);
1954    SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1955                                             N->getOffset(), MipsII::MO_ABS_LO);
1956    SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
1957    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
1958    ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1959  } else {
1960    EVT ValTy = Op.getValueType();
1961    unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1962    unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
1963    SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1964                                           N->getOffset(), GOTFlag);
1965    CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), CP);
1966    SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP,
1967                               MachinePointerInfo::getGOT(), false,
1968                               false, false, 0);
1969    SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1970                                             N->getOffset(), OFSTFlag);
1971    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo);
1972    ResNode = DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
1973  }
1974
1975  return ResNode;
1976}
1977
1978SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1979  MachineFunction &MF = DAG.getMachineFunction();
1980  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1981
1982  DebugLoc dl = Op.getDebugLoc();
1983  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1984                                 getPointerTy());
1985
1986  // vastart just stores the address of the VarArgsFrameIndex slot into the
1987  // memory location argument.
1988  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1989  return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
1990                      MachinePointerInfo(SV), false, false, 0);
1991}
1992
1993static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1994  EVT TyX = Op.getOperand(0).getValueType();
1995  EVT TyY = Op.getOperand(1).getValueType();
1996  SDValue Const1 = DAG.getConstant(1, MVT::i32);
1997  SDValue Const31 = DAG.getConstant(31, MVT::i32);
1998  DebugLoc DL = Op.getDebugLoc();
1999  SDValue Res;
2000
2001  // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2002  // to i32.
2003  SDValue X = (TyX == MVT::f32) ?
2004    DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2005    DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2006                Const1);
2007  SDValue Y = (TyY == MVT::f32) ?
2008    DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2009    DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2010                Const1);
2011
2012  if (HasR2) {
2013    // ext  E, Y, 31, 1  ; extract bit31 of Y
2014    // ins  X, E, 31, 1  ; insert extracted bit at bit31 of X
2015    SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2016    Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2017  } else {
2018    // sll SllX, X, 1
2019    // srl SrlX, SllX, 1
2020    // srl SrlY, Y, 31
2021    // sll SllY, SrlX, 31
2022    // or  Or, SrlX, SllY
2023    SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2024    SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2025    SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2026    SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2027    Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2028  }
2029
2030  if (TyX == MVT::f32)
2031    return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2032
2033  SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2034                             Op.getOperand(0), DAG.getConstant(0, MVT::i32));
2035  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2036}
2037
2038static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2039  unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2040  unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2041  EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2042  SDValue Const1 = DAG.getConstant(1, MVT::i32);
2043  DebugLoc DL = Op.getDebugLoc();
2044
2045  // Bitcast to integer nodes.
2046  SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2047  SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2048
2049  if (HasR2) {
2050    // ext  E, Y, width(Y) - 1, 1  ; extract bit width(Y)-1 of Y
2051    // ins  X, E, width(X) - 1, 1  ; insert extracted bit at bit width(X)-1 of X
2052    SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2053                            DAG.getConstant(WidthY - 1, MVT::i32), Const1);
2054
2055    if (WidthX > WidthY)
2056      E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2057    else if (WidthY > WidthX)
2058      E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2059
2060    SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2061                            DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
2062    return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2063  }
2064
2065  // (d)sll SllX, X, 1
2066  // (d)srl SrlX, SllX, 1
2067  // (d)srl SrlY, Y, width(Y)-1
2068  // (d)sll SllY, SrlX, width(Y)-1
2069  // or     Or, SrlX, SllY
2070  SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2071  SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2072  SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2073                             DAG.getConstant(WidthY - 1, MVT::i32));
2074
2075  if (WidthX > WidthY)
2076    SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2077  else if (WidthY > WidthX)
2078    SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2079
2080  SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2081                             DAG.getConstant(WidthX - 1, MVT::i32));
2082  SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2083  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2084}
2085
2086SDValue
2087MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2088  if (Subtarget->hasMips64())
2089    return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
2090
2091  return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
2092}
2093
2094static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2095  SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
2096  DebugLoc DL = Op.getDebugLoc();
2097
2098  // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2099  // to i32.
2100  SDValue X = (Op.getValueType() == MVT::f32) ?
2101    DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2102    DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2103                Const1);
2104
2105  // Clear MSB.
2106  if (HasR2)
2107    Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
2108                      DAG.getRegister(Mips::ZERO, MVT::i32),
2109                      DAG.getConstant(31, MVT::i32), Const1, X);
2110  else {
2111    SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2112    Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2113  }
2114
2115  if (Op.getValueType() == MVT::f32)
2116    return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
2117
2118  SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2119                             Op.getOperand(0), DAG.getConstant(0, MVT::i32));
2120  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2121}
2122
2123static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2124  SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
2125  DebugLoc DL = Op.getDebugLoc();
2126
2127  // Bitcast to integer node.
2128  SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
2129
2130  // Clear MSB.
2131  if (HasR2)
2132    Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
2133                      DAG.getRegister(Mips::ZERO_64, MVT::i64),
2134                      DAG.getConstant(63, MVT::i32), Const1, X);
2135  else {
2136    SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
2137    Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2138  }
2139
2140  return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
2141}
2142
2143SDValue
2144MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
2145  if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
2146    return LowerFABS64(Op, DAG, Subtarget->hasMips32r2());
2147
2148  return LowerFABS32(Op, DAG, Subtarget->hasMips32r2());
2149}
2150
2151SDValue MipsTargetLowering::
2152LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2153  // check the depth
2154  assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2155         "Frame address can only be determined for current frame.");
2156
2157  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2158  MFI->setFrameAddressIsTaken(true);
2159  EVT VT = Op.getValueType();
2160  DebugLoc dl = Op.getDebugLoc();
2161  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2162                                         IsN64 ? Mips::FP_64 : Mips::FP, VT);
2163  return FrameAddr;
2164}
2165
2166SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op,
2167                                            SelectionDAG &DAG) const {
2168  // check the depth
2169  assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2170         "Return address can be determined only for current frame.");
2171
2172  MachineFunction &MF = DAG.getMachineFunction();
2173  MachineFrameInfo *MFI = MF.getFrameInfo();
2174  EVT VT = Op.getValueType();
2175  unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
2176  MFI->setReturnAddressIsTaken(true);
2177
2178  // Return RA, which contains the return address. Mark it an implicit live-in.
2179  unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2180  return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT);
2181}
2182
2183// TODO: set SType according to the desired memory barrier behavior.
2184SDValue
2185MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const {
2186  unsigned SType = 0;
2187  DebugLoc dl = Op.getDebugLoc();
2188  return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2189                     DAG.getConstant(SType, MVT::i32));
2190}
2191
2192SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
2193                                              SelectionDAG &DAG) const {
2194  // FIXME: Need pseudo-fence for 'singlethread' fences
2195  // FIXME: Set SType for weaker fences where supported/appropriate.
2196  unsigned SType = 0;
2197  DebugLoc dl = Op.getDebugLoc();
2198  return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2199                     DAG.getConstant(SType, MVT::i32));
2200}
2201
2202SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op,
2203                                                SelectionDAG &DAG) const {
2204  DebugLoc DL = Op.getDebugLoc();
2205  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2206  SDValue Shamt = Op.getOperand(2);
2207
2208  // if shamt < 32:
2209  //  lo = (shl lo, shamt)
2210  //  hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2211  // else:
2212  //  lo = 0
2213  //  hi = (shl lo, shamt[4:0])
2214  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2215                            DAG.getConstant(-1, MVT::i32));
2216  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
2217                                      DAG.getConstant(1, MVT::i32));
2218  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
2219                                     Not);
2220  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
2221  SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2222  SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
2223  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2224                             DAG.getConstant(0x20, MVT::i32));
2225  Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2226                   DAG.getConstant(0, MVT::i32), ShiftLeftLo);
2227  Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
2228
2229  SDValue Ops[2] = {Lo, Hi};
2230  return DAG.getMergeValues(Ops, 2, DL);
2231}
2232
2233SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2234                                                 bool IsSRA) const {
2235  DebugLoc DL = Op.getDebugLoc();
2236  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2237  SDValue Shamt = Op.getOperand(2);
2238
2239  // if shamt < 32:
2240  //  lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2241  //  if isSRA:
2242  //    hi = (sra hi, shamt)
2243  //  else:
2244  //    hi = (srl hi, shamt)
2245  // else:
2246  //  if isSRA:
2247  //   lo = (sra hi, shamt[4:0])
2248  //   hi = (sra hi, 31)
2249  //  else:
2250  //   lo = (srl hi, shamt[4:0])
2251  //   hi = 0
2252  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2253                            DAG.getConstant(-1, MVT::i32));
2254  SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
2255                                     DAG.getConstant(1, MVT::i32));
2256  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
2257  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
2258  SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2259  SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2260                                     Hi, Shamt);
2261  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2262                             DAG.getConstant(0x20, MVT::i32));
2263  SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
2264                                DAG.getConstant(31, MVT::i32));
2265  Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
2266  Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2267                   IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
2268                   ShiftRightHi);
2269
2270  SDValue Ops[2] = {Lo, Hi};
2271  return DAG.getMergeValues(Ops, 2, DL);
2272}
2273
2274static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2275                            SDValue Chain, SDValue Src, unsigned Offset) {
2276  SDValue Ptr = LD->getBasePtr();
2277  EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2278  EVT BasePtrVT = Ptr.getValueType();
2279  DebugLoc DL = LD->getDebugLoc();
2280  SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2281
2282  if (Offset)
2283    Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2284                      DAG.getConstant(Offset, BasePtrVT));
2285
2286  SDValue Ops[] = { Chain, Ptr, Src };
2287  return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2288                                 LD->getMemOperand());
2289}
2290
2291// Expand an unaligned 32 or 64-bit integer load node.
2292SDValue MipsTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2293  LoadSDNode *LD = cast<LoadSDNode>(Op);
2294  EVT MemVT = LD->getMemoryVT();
2295
2296  // Return if load is aligned or if MemVT is neither i32 nor i64.
2297  if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2298      ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2299    return SDValue();
2300
2301  bool IsLittle = Subtarget->isLittle();
2302  EVT VT = Op.getValueType();
2303  ISD::LoadExtType ExtType = LD->getExtensionType();
2304  SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2305
2306  assert((VT == MVT::i32) || (VT == MVT::i64));
2307
2308  // Expand
2309  //  (set dst, (i64 (load baseptr)))
2310  // to
2311  //  (set tmp, (ldl (add baseptr, 7), undef))
2312  //  (set dst, (ldr baseptr, tmp))
2313  if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2314    SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2315                               IsLittle ? 7 : 0);
2316    return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2317                        IsLittle ? 0 : 7);
2318  }
2319
2320  SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2321                             IsLittle ? 3 : 0);
2322  SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2323                             IsLittle ? 0 : 3);
2324
2325  // Expand
2326  //  (set dst, (i32 (load baseptr))) or
2327  //  (set dst, (i64 (sextload baseptr))) or
2328  //  (set dst, (i64 (extload baseptr)))
2329  // to
2330  //  (set tmp, (lwl (add baseptr, 3), undef))
2331  //  (set dst, (lwr baseptr, tmp))
2332  if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2333      (ExtType == ISD::EXTLOAD))
2334    return LWR;
2335
2336  assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2337
2338  // Expand
2339  //  (set dst, (i64 (zextload baseptr)))
2340  // to
2341  //  (set tmp0, (lwl (add baseptr, 3), undef))
2342  //  (set tmp1, (lwr baseptr, tmp0))
2343  //  (set tmp2, (shl tmp1, 32))
2344  //  (set dst, (srl tmp2, 32))
2345  DebugLoc DL = LD->getDebugLoc();
2346  SDValue Const32 = DAG.getConstant(32, MVT::i32);
2347  SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2348  SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2349  SDValue Ops[] = { SRL, LWR.getValue(1) };
2350  return DAG.getMergeValues(Ops, 2, DL);
2351}
2352
2353static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2354                             SDValue Chain, unsigned Offset) {
2355  SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2356  EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2357  DebugLoc DL = SD->getDebugLoc();
2358  SDVTList VTList = DAG.getVTList(MVT::Other);
2359
2360  if (Offset)
2361    Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2362                      DAG.getConstant(Offset, BasePtrVT));
2363
2364  SDValue Ops[] = { Chain, Value, Ptr };
2365  return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2366                                 SD->getMemOperand());
2367}
2368
2369// Expand an unaligned 32 or 64-bit integer store node.
2370SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2371  StoreSDNode *SD = cast<StoreSDNode>(Op);
2372  EVT MemVT = SD->getMemoryVT();
2373
2374  // Return if store is aligned or if MemVT is neither i32 nor i64.
2375  if ((SD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2376      ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2377    return SDValue();
2378
2379  bool IsLittle = Subtarget->isLittle();
2380  SDValue Value = SD->getValue(), Chain = SD->getChain();
2381  EVT VT = Value.getValueType();
2382
2383  // Expand
2384  //  (store val, baseptr) or
2385  //  (truncstore val, baseptr)
2386  // to
2387  //  (swl val, (add baseptr, 3))
2388  //  (swr val, baseptr)
2389  if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2390    SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain,
2391                                IsLittle ? 3 : 0);
2392    return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2393  }
2394
2395  assert(VT == MVT::i64);
2396
2397  // Expand
2398  //  (store val, baseptr)
2399  // to
2400  //  (sdl val, (add baseptr, 7))
2401  //  (sdr val, baseptr)
2402  SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2403  return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2404}
2405
2406// This function expands mips intrinsic nodes which have 64-bit input operands
2407// or output values.
2408//
2409// out64 = intrinsic-node in64
2410// =>
2411// lo = copy (extract-element (in64, 0))
2412// hi = copy (extract-element (in64, 1))
2413// mips-specific-node
2414// v0 = copy lo
2415// v1 = copy hi
2416// out64 = merge-values (v0, v1)
2417//
2418static SDValue LowerDSPIntr(SDValue Op, SelectionDAG &DAG,
2419                            unsigned Opc, bool HasI64In, bool HasI64Out) {
2420  DebugLoc DL = Op.getDebugLoc();
2421  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
2422  SDValue Chain = HasChainIn ? Op->getOperand(0) : DAG.getEntryNode();
2423  SmallVector<SDValue, 3> Ops;
2424
2425  if (HasI64In) {
2426    SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
2427                               Op->getOperand(1 + HasChainIn),
2428                               DAG.getConstant(0, MVT::i32));
2429    SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
2430                               Op->getOperand(1 + HasChainIn),
2431                               DAG.getConstant(1, MVT::i32));
2432
2433    Chain = DAG.getCopyToReg(Chain, DL, Mips::LO, InLo, SDValue());
2434    Chain = DAG.getCopyToReg(Chain, DL, Mips::HI, InHi, Chain.getValue(1));
2435
2436    Ops.push_back(Chain);
2437    Ops.append(Op->op_begin() + HasChainIn + 2, Op->op_end());
2438    Ops.push_back(Chain.getValue(1));
2439  } else {
2440    Ops.push_back(Chain);
2441    Ops.append(Op->op_begin() + HasChainIn + 1, Op->op_end());
2442  }
2443
2444  if (!HasI64Out)
2445    return DAG.getNode(Opc, DL, Op->value_begin(), Op->getNumValues(),
2446                       Ops.begin(), Ops.size());
2447
2448  SDValue Intr = DAG.getNode(Opc, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2449                             Ops.begin(), Ops.size());
2450  SDValue OutLo = DAG.getCopyFromReg(Intr.getValue(0), DL, Mips::LO, MVT::i32,
2451                                     Intr.getValue(1));
2452  SDValue OutHi = DAG.getCopyFromReg(OutLo.getValue(1), DL, Mips::HI, MVT::i32,
2453                                     OutLo.getValue(2));
2454  SDValue Out = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, OutLo, OutHi);
2455
2456  if (!HasChainIn)
2457    return Out;
2458
2459  SDValue Vals[] = { Out, OutHi.getValue(1) };
2460  return DAG.getMergeValues(Vals, 2, DL);
2461}
2462
2463SDValue MipsTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2464                                                    SelectionDAG &DAG) const {
2465  switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
2466  default:
2467    return SDValue();
2468  case Intrinsic::mips_shilo:
2469    return LowerDSPIntr(Op, DAG, MipsISD::SHILO, true, true);
2470  case Intrinsic::mips_dpau_h_qbl:
2471    return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL, true, true);
2472  case Intrinsic::mips_dpau_h_qbr:
2473    return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR, true, true);
2474  case Intrinsic::mips_dpsu_h_qbl:
2475    return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL, true, true);
2476  case Intrinsic::mips_dpsu_h_qbr:
2477    return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR, true, true);
2478  case Intrinsic::mips_dpa_w_ph:
2479    return LowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH, true, true);
2480  case Intrinsic::mips_dps_w_ph:
2481    return LowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH, true, true);
2482  case Intrinsic::mips_dpax_w_ph:
2483    return LowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH, true, true);
2484  case Intrinsic::mips_dpsx_w_ph:
2485    return LowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH, true, true);
2486  case Intrinsic::mips_mulsa_w_ph:
2487    return LowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH, true, true);
2488  case Intrinsic::mips_mult:
2489    return LowerDSPIntr(Op, DAG, MipsISD::MULT, false, true);
2490  case Intrinsic::mips_multu:
2491    return LowerDSPIntr(Op, DAG, MipsISD::MULTU, false, true);
2492  case Intrinsic::mips_madd:
2493    return LowerDSPIntr(Op, DAG, MipsISD::MADD_DSP, true, true);
2494  case Intrinsic::mips_maddu:
2495    return LowerDSPIntr(Op, DAG, MipsISD::MADDU_DSP, true, true);
2496  case Intrinsic::mips_msub:
2497    return LowerDSPIntr(Op, DAG, MipsISD::MSUB_DSP, true, true);
2498  case Intrinsic::mips_msubu:
2499    return LowerDSPIntr(Op, DAG, MipsISD::MSUBU_DSP, true, true);
2500  }
2501}
2502
2503SDValue MipsTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
2504                                                   SelectionDAG &DAG) const {
2505  switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) {
2506  default:
2507    return SDValue();
2508  case Intrinsic::mips_extp:
2509    return LowerDSPIntr(Op, DAG, MipsISD::EXTP, true, false);
2510  case Intrinsic::mips_extpdp:
2511    return LowerDSPIntr(Op, DAG, MipsISD::EXTPDP, true, false);
2512  case Intrinsic::mips_extr_w:
2513    return LowerDSPIntr(Op, DAG, MipsISD::EXTR_W, true, false);
2514  case Intrinsic::mips_extr_r_w:
2515    return LowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W, true, false);
2516  case Intrinsic::mips_extr_rs_w:
2517    return LowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W, true, false);
2518  case Intrinsic::mips_extr_s_h:
2519    return LowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H, true, false);
2520  case Intrinsic::mips_mthlip:
2521    return LowerDSPIntr(Op, DAG, MipsISD::MTHLIP, true, true);
2522  case Intrinsic::mips_mulsaq_s_w_ph:
2523    return LowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH, true, true);
2524  case Intrinsic::mips_maq_s_w_phl:
2525    return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL, true, true);
2526  case Intrinsic::mips_maq_s_w_phr:
2527    return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR, true, true);
2528  case Intrinsic::mips_maq_sa_w_phl:
2529    return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL, true, true);
2530  case Intrinsic::mips_maq_sa_w_phr:
2531    return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR, true, true);
2532  case Intrinsic::mips_dpaq_s_w_ph:
2533    return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH, true, true);
2534  case Intrinsic::mips_dpsq_s_w_ph:
2535    return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH, true, true);
2536  case Intrinsic::mips_dpaq_sa_l_w:
2537    return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W, true, true);
2538  case Intrinsic::mips_dpsq_sa_l_w:
2539    return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W, true, true);
2540  case Intrinsic::mips_dpaqx_s_w_ph:
2541    return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH, true, true);
2542  case Intrinsic::mips_dpaqx_sa_w_ph:
2543    return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH, true, true);
2544  case Intrinsic::mips_dpsqx_s_w_ph:
2545    return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH, true, true);
2546  case Intrinsic::mips_dpsqx_sa_w_ph:
2547    return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH, true, true);
2548  }
2549}
2550
2551SDValue MipsTargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
2552  if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2553      || cast<ConstantSDNode>
2554        (Op->getOperand(0).getOperand(0))->getZExtValue() != 0
2555      || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2556    return SDValue();
2557
2558  // The pattern
2559  //   (add (frameaddr 0), (frame_to_args_offset))
2560  // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
2561  //   (add FrameObject, 0)
2562  // where FrameObject is a fixed StackObject with offset 0 which points to
2563  // the old stack pointer.
2564  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2565  EVT ValTy = Op->getValueType(0);
2566  int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2567  SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
2568  return DAG.getNode(ISD::ADD, Op->getDebugLoc(), ValTy, InArgsAddr,
2569                     DAG.getConstant(0, ValTy));
2570}
2571
2572//===----------------------------------------------------------------------===//
2573//                      Calling Convention Implementation
2574//===----------------------------------------------------------------------===//
2575
2576//===----------------------------------------------------------------------===//
2577// TODO: Implement a generic logic using tblgen that can support this.
2578// Mips O32 ABI rules:
2579// ---
2580// i32 - Passed in A0, A1, A2, A3 and stack
2581// f32 - Only passed in f32 registers if no int reg has been used yet to hold
2582//       an argument. Otherwise, passed in A1, A2, A3 and stack.
2583// f64 - Only passed in two aliased f32 registers if no int reg has been used
2584//       yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2585//       not used, it must be shadowed. If only A3 is avaiable, shadow it and
2586//       go to stack.
2587//
2588//  For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2589//===----------------------------------------------------------------------===//
2590
2591static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
2592                       MVT LocVT, CCValAssign::LocInfo LocInfo,
2593                       ISD::ArgFlagsTy ArgFlags, CCState &State) {
2594
2595  static const unsigned IntRegsSize=4, FloatRegsSize=2;
2596
2597  static const uint16_t IntRegs[] = {
2598      Mips::A0, Mips::A1, Mips::A2, Mips::A3
2599  };
2600  static const uint16_t F32Regs[] = {
2601      Mips::F12, Mips::F14
2602  };
2603  static const uint16_t F64Regs[] = {
2604      Mips::D6, Mips::D7
2605  };
2606
2607  // Do not process byval args here.
2608  if (ArgFlags.isByVal())
2609    return true;
2610
2611  // Promote i8 and i16
2612  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2613    LocVT = MVT::i32;
2614    if (ArgFlags.isSExt())
2615      LocInfo = CCValAssign::SExt;
2616    else if (ArgFlags.isZExt())
2617      LocInfo = CCValAssign::ZExt;
2618    else
2619      LocInfo = CCValAssign::AExt;
2620  }
2621
2622  unsigned Reg;
2623
2624  // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2625  // is true: function is vararg, argument is 3rd or higher, there is previous
2626  // argument which is not f32 or f64.
2627  bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
2628      || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
2629  unsigned OrigAlign = ArgFlags.getOrigAlign();
2630  bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2631
2632  if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2633    Reg = State.AllocateReg(IntRegs, IntRegsSize);
2634    // If this is the first part of an i64 arg,
2635    // the allocated register must be either A0 or A2.
2636    if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2637      Reg = State.AllocateReg(IntRegs, IntRegsSize);
2638    LocVT = MVT::i32;
2639  } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2640    // Allocate int register and shadow next int register. If first
2641    // available register is Mips::A1 or Mips::A3, shadow it too.
2642    Reg = State.AllocateReg(IntRegs, IntRegsSize);
2643    if (Reg == Mips::A1 || Reg == Mips::A3)
2644      Reg = State.AllocateReg(IntRegs, IntRegsSize);
2645    State.AllocateReg(IntRegs, IntRegsSize);
2646    LocVT = MVT::i32;
2647  } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2648    // we are guaranteed to find an available float register
2649    if (ValVT == MVT::f32) {
2650      Reg = State.AllocateReg(F32Regs, FloatRegsSize);
2651      // Shadow int register
2652      State.AllocateReg(IntRegs, IntRegsSize);
2653    } else {
2654      Reg = State.AllocateReg(F64Regs, FloatRegsSize);
2655      // Shadow int registers
2656      unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
2657      if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2658        State.AllocateReg(IntRegs, IntRegsSize);
2659      State.AllocateReg(IntRegs, IntRegsSize);
2660    }
2661  } else
2662    llvm_unreachable("Cannot handle this ValVT.");
2663
2664  if (!Reg) {
2665    unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2666                                          OrigAlign);
2667    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2668  } else
2669    State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2670
2671  return false;
2672}
2673
2674#include "MipsGenCallingConv.inc"
2675
2676//===----------------------------------------------------------------------===//
2677//                  Call Calling Convention Implementation
2678//===----------------------------------------------------------------------===//
2679
2680static const unsigned O32IntRegsSize = 4;
2681
2682// Return next O32 integer argument register.
2683static unsigned getNextIntArgReg(unsigned Reg) {
2684  assert((Reg == Mips::A0) || (Reg == Mips::A2));
2685  return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2686}
2687
2688/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2689/// for tail call optimization.
2690bool MipsTargetLowering::
2691IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
2692                                  unsigned NextStackOffset,
2693                                  const MipsFunctionInfo& FI) const {
2694  if (!EnableMipsTailCalls)
2695    return false;
2696
2697  // No tail call optimization for mips16.
2698  if (Subtarget->inMips16Mode())
2699    return false;
2700
2701  // Return false if either the callee or caller has a byval argument.
2702  if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
2703    return false;
2704
2705  // Return true if the callee's argument area is no larger than the
2706  // caller's.
2707  return NextStackOffset <= FI.getIncomingArgSize();
2708}
2709
2710SDValue
2711MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2712                                   SDValue Chain, SDValue Arg, DebugLoc DL,
2713                                   bool IsTailCall, SelectionDAG &DAG) const {
2714  if (!IsTailCall) {
2715    SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
2716                                 DAG.getIntPtrConstant(Offset));
2717    return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
2718                        false, 0);
2719  }
2720
2721  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2722  int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2723  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2724  return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2725                      /*isVolatile=*/ true, false, 0);
2726}
2727
2728/// LowerCall - functions arguments are copied from virtual regs to
2729/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2730SDValue
2731MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2732                              SmallVectorImpl<SDValue> &InVals) const {
2733  SelectionDAG &DAG                     = CLI.DAG;
2734  DebugLoc &dl                          = CLI.DL;
2735  SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2736  SmallVector<SDValue, 32> &OutVals     = CLI.OutVals;
2737  SmallVector<ISD::InputArg, 32> &Ins   = CLI.Ins;
2738  SDValue Chain                         = CLI.Chain;
2739  SDValue Callee                        = CLI.Callee;
2740  bool &isTailCall                      = CLI.IsTailCall;
2741  CallingConv::ID CallConv              = CLI.CallConv;
2742  bool isVarArg                         = CLI.IsVarArg;
2743
2744  MachineFunction &MF = DAG.getMachineFunction();
2745  MachineFrameInfo *MFI = MF.getFrameInfo();
2746  const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
2747  bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2748
2749  // Analyze operands of the call, assigning locations to each operand.
2750  SmallVector<CCValAssign, 16> ArgLocs;
2751  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2752                 getTargetMachine(), ArgLocs, *DAG.getContext());
2753  MipsCC MipsCCInfo(CallConv, isVarArg, IsO32, CCInfo);
2754
2755  MipsCCInfo.analyzeCallOperands(Outs);
2756
2757  // Get a count of how many bytes are to be pushed on the stack.
2758  unsigned NextStackOffset = CCInfo.getNextStackOffset();
2759
2760  // Check if it's really possible to do a tail call.
2761  if (isTailCall)
2762    isTailCall =
2763      IsEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset,
2764                                        *MF.getInfo<MipsFunctionInfo>());
2765
2766  if (isTailCall)
2767    ++NumTailCalls;
2768
2769  // Chain is the output chain of the last Load/Store or CopyToReg node.
2770  // ByValChain is the output chain of the last Memcpy node created for copying
2771  // byval arguments to the stack.
2772  unsigned StackAlignment = TFL->getStackAlignment();
2773  NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2774  SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
2775
2776  if (!isTailCall)
2777    Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal);
2778
2779  SDValue StackPtr = DAG.getCopyFromReg(Chain, dl,
2780                                        IsN64 ? Mips::SP_64 : Mips::SP,
2781                                        getPointerTy());
2782
2783  // With EABI is it possible to have 16 args on registers.
2784  SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
2785  SmallVector<SDValue, 8> MemOpChains;
2786  MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
2787
2788  // Walk the register/memloc assignments, inserting copies/loads.
2789  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2790    SDValue Arg = OutVals[i];
2791    CCValAssign &VA = ArgLocs[i];
2792    MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2793    ISD::ArgFlagsTy Flags = Outs[i].Flags;
2794
2795    // ByVal Arg.
2796    if (Flags.isByVal()) {
2797      assert(Flags.getByValSize() &&
2798             "ByVal args of size 0 should have been ignored by front-end.");
2799      assert(ByValArg != MipsCCInfo.byval_end());
2800      assert(!isTailCall &&
2801             "Do not tail-call optimize if there is a byval argument.");
2802      passByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2803                   MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle());
2804      ++ByValArg;
2805      continue;
2806    }
2807
2808    // Promote the value if needed.
2809    switch (VA.getLocInfo()) {
2810    default: llvm_unreachable("Unknown loc info!");
2811    case CCValAssign::Full:
2812      if (VA.isRegLoc()) {
2813        if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2814            (ValVT == MVT::f64 && LocVT == MVT::i64))
2815          Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);
2816        else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2817          SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2818                                   Arg, DAG.getConstant(0, MVT::i32));
2819          SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2820                                   Arg, DAG.getConstant(1, MVT::i32));
2821          if (!Subtarget->isLittle())
2822            std::swap(Lo, Hi);
2823          unsigned LocRegLo = VA.getLocReg();
2824          unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2825          RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2826          RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2827          continue;
2828        }
2829      }
2830      break;
2831    case CCValAssign::SExt:
2832      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
2833      break;
2834    case CCValAssign::ZExt:
2835      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
2836      break;
2837    case CCValAssign::AExt:
2838      Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
2839      break;
2840    }
2841
2842    // Arguments that can be passed on register must be kept at
2843    // RegsToPass vector
2844    if (VA.isRegLoc()) {
2845      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2846      continue;
2847    }
2848
2849    // Register can't get to this point...
2850    assert(VA.isMemLoc());
2851
2852    // emit ISD::STORE whichs stores the
2853    // parameter value to a stack Location
2854    MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
2855                                         Chain, Arg, dl, isTailCall, DAG));
2856  }
2857
2858  // Transform all store nodes into one single node because all store
2859  // nodes are independent of each other.
2860  if (!MemOpChains.empty())
2861    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2862                        &MemOpChains[0], MemOpChains.size());
2863
2864  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2865  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2866  // node so that legalize doesn't hack it.
2867  unsigned char OpFlag;
2868  bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
2869  bool GlobalOrExternal = false;
2870  SDValue CalleeLo;
2871
2872  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2873    if (IsPICCall && G->getGlobal()->hasInternalLinkage()) {
2874      OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE;
2875      unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST;
2876      Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0,
2877                                          OpFlag);
2878      CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
2879                                            0, LoFlag);
2880    } else {
2881      OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
2882      Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2883                                          getPointerTy(), 0, OpFlag);
2884    }
2885
2886    GlobalOrExternal = true;
2887  }
2888  else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2889    if (IsN64 || (!IsO32 && IsPIC))
2890      OpFlag = MipsII::MO_GOT_DISP;
2891    else if (!IsPIC) // !N64 && static
2892      OpFlag = MipsII::MO_NO_FLAG;
2893    else // O32 & PIC
2894      OpFlag = MipsII::MO_GOT_CALL;
2895    Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2896                                         OpFlag);
2897    GlobalOrExternal = true;
2898  }
2899
2900  SDValue InFlag;
2901
2902  // Create nodes that load address of callee and copy it to T9
2903  if (IsPICCall) {
2904    if (GlobalOrExternal) {
2905      // Load callee address
2906      Callee = DAG.getNode(MipsISD::Wrapper, dl, getPointerTy(),
2907                           GetGlobalReg(DAG, getPointerTy()), Callee);
2908      SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
2909                                      Callee, MachinePointerInfo::getGOT(),
2910                                      false, false, false, 0);
2911
2912      // Use GOT+LO if callee has internal linkage.
2913      if (CalleeLo.getNode()) {
2914        SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo);
2915        Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo);
2916      } else
2917        Callee = LoadValue;
2918    }
2919  }
2920
2921  // T9 register operand.
2922  SDValue T9;
2923
2924  // T9 should contain the address of the callee function if
2925  // -reloction-model=pic or it is an indirect call.
2926  if (IsPICCall || !GlobalOrExternal) {
2927    // copy to T9
2928    unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
2929    Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0));
2930    InFlag = Chain.getValue(1);
2931
2932    if (Subtarget->inMips16Mode())
2933      T9 = DAG.getRegister(T9Reg, getPointerTy());
2934    else
2935      Callee = DAG.getRegister(T9Reg, getPointerTy());
2936  }
2937
2938  // Insert node "GP copy globalreg" before call to function.
2939  // Lazy-binding stubs require GP to point to the GOT.
2940  if (IsPICCall) {
2941    unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
2942    EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
2943    RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty)));
2944  }
2945
2946  // Build a sequence of copy-to-reg nodes chained together with token
2947  // chain and flag operands which copy the outgoing args into registers.
2948  // The InFlag in necessary since all emitted instructions must be
2949  // stuck together.
2950  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2951    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2952                             RegsToPass[i].second, InFlag);
2953    InFlag = Chain.getValue(1);
2954  }
2955
2956  // MipsJmpLink = #chain, #target_address, #opt_in_flags...
2957  //             = Chain, Callee, Reg#1, Reg#2, ...
2958  //
2959  // Returns a chain & a flag for retval copy to use.
2960  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2961  SmallVector<SDValue, 8> Ops;
2962  Ops.push_back(Chain);
2963  Ops.push_back(Callee);
2964
2965  // Add argument registers to the end of the list so that they are
2966  // known live into the call.
2967  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2968    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2969                                  RegsToPass[i].second.getValueType()));
2970
2971  // Add T9 register operand.
2972  if (T9.getNode())
2973    Ops.push_back(T9);
2974
2975  // Add a register mask operand representing the call-preserved registers.
2976  const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2977  const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2978  assert(Mask && "Missing call preserved mask for calling convention");
2979  Ops.push_back(DAG.getRegisterMask(Mask));
2980
2981  if (InFlag.getNode())
2982    Ops.push_back(InFlag);
2983
2984  if (isTailCall)
2985    return DAG.getNode(MipsISD::TailCall, dl, MVT::Other, &Ops[0], Ops.size());
2986
2987  Chain  = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
2988  InFlag = Chain.getValue(1);
2989
2990  // Create the CALLSEQ_END node.
2991  Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
2992                             DAG.getIntPtrConstant(0, true), InFlag);
2993  InFlag = Chain.getValue(1);
2994
2995  // Handle result values, copying them out of physregs into vregs that we
2996  // return.
2997  return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2998                         Ins, dl, DAG, InVals);
2999}
3000
3001/// LowerCallResult - Lower the result values of a call into the
3002/// appropriate copies out of appropriate physical registers.
3003SDValue
3004MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3005                                    CallingConv::ID CallConv, bool isVarArg,
3006                                    const SmallVectorImpl<ISD::InputArg> &Ins,
3007                                    DebugLoc dl, SelectionDAG &DAG,
3008                                    SmallVectorImpl<SDValue> &InVals) const {
3009  // Assign locations to each value returned by this call.
3010  SmallVector<CCValAssign, 16> RVLocs;
3011  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3012                 getTargetMachine(), RVLocs, *DAG.getContext());
3013
3014  CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
3015
3016  // Copy all of the result registers out of their specified physreg.
3017  for (unsigned i = 0; i != RVLocs.size(); ++i) {
3018    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
3019                               RVLocs[i].getValVT(), InFlag).getValue(1);
3020    InFlag = Chain.getValue(2);
3021    InVals.push_back(Chain.getValue(0));
3022  }
3023
3024  return Chain;
3025}
3026
3027//===----------------------------------------------------------------------===//
3028//             Formal Arguments Calling Convention Implementation
3029//===----------------------------------------------------------------------===//
3030/// LowerFormalArguments - transform physical registers into virtual registers
3031/// and generate load operations for arguments places on the stack.
3032SDValue
3033MipsTargetLowering::LowerFormalArguments(SDValue Chain,
3034                                         CallingConv::ID CallConv,
3035                                         bool isVarArg,
3036                                      const SmallVectorImpl<ISD::InputArg> &Ins,
3037                                         DebugLoc dl, SelectionDAG &DAG,
3038                                         SmallVectorImpl<SDValue> &InVals)
3039                                          const {
3040  MachineFunction &MF = DAG.getMachineFunction();
3041  MachineFrameInfo *MFI = MF.getFrameInfo();
3042  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3043
3044  MipsFI->setVarArgsFrameIndex(0);
3045
3046  // Used with vargs to acumulate store chains.
3047  std::vector<SDValue> OutChains;
3048
3049  // Assign locations to all of the incoming arguments.
3050  SmallVector<CCValAssign, 16> ArgLocs;
3051  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3052                 getTargetMachine(), ArgLocs, *DAG.getContext());
3053  MipsCC MipsCCInfo(CallConv, isVarArg, IsO32, CCInfo);
3054
3055  MipsCCInfo.analyzeFormalArguments(Ins);
3056  MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3057                           MipsCCInfo.hasByValArg());
3058
3059  Function::const_arg_iterator FuncArg =
3060    DAG.getMachineFunction().getFunction()->arg_begin();
3061  unsigned CurArgIdx = 0;
3062  MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
3063
3064  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3065    CCValAssign &VA = ArgLocs[i];
3066    std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
3067    CurArgIdx = Ins[i].OrigArgIndex;
3068    EVT ValVT = VA.getValVT();
3069    ISD::ArgFlagsTy Flags = Ins[i].Flags;
3070    bool IsRegLoc = VA.isRegLoc();
3071
3072    if (Flags.isByVal()) {
3073      assert(Flags.getByValSize() &&
3074             "ByVal args of size 0 should have been ignored by front-end.");
3075      assert(ByValArg != MipsCCInfo.byval_end());
3076      copyByValRegs(Chain, dl, OutChains, DAG, Flags, InVals, &*FuncArg,
3077                    MipsCCInfo, *ByValArg);
3078      ++ByValArg;
3079      continue;
3080    }
3081
3082    // Arguments stored on registers
3083    if (IsRegLoc) {
3084      EVT RegVT = VA.getLocVT();
3085      unsigned ArgReg = VA.getLocReg();
3086      const TargetRegisterClass *RC;
3087
3088      if (RegVT == MVT::i32)
3089        RC = &Mips::CPURegsRegClass;
3090      else if (RegVT == MVT::i64)
3091        RC = &Mips::CPU64RegsRegClass;
3092      else if (RegVT == MVT::f32)
3093        RC = &Mips::FGR32RegClass;
3094      else if (RegVT == MVT::f64)
3095        RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
3096      else
3097        llvm_unreachable("RegVT not supported by FormalArguments Lowering");
3098
3099      // Transform the arguments stored on
3100      // physical registers into virtual ones
3101      unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3102      SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3103
3104      // If this is an 8 or 16-bit value, it has been passed promoted
3105      // to 32 bits.  Insert an assert[sz]ext to capture this, then
3106      // truncate to the right size.
3107      if (VA.getLocInfo() != CCValAssign::Full) {
3108        unsigned Opcode = 0;
3109        if (VA.getLocInfo() == CCValAssign::SExt)
3110          Opcode = ISD::AssertSext;
3111        else if (VA.getLocInfo() == CCValAssign::ZExt)
3112          Opcode = ISD::AssertZext;
3113        if (Opcode)
3114          ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
3115                                 DAG.getValueType(ValVT));
3116        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
3117      }
3118
3119      // Handle floating point arguments passed in integer registers.
3120      if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3121          (RegVT == MVT::i64 && ValVT == MVT::f64))
3122        ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue);
3123      else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
3124        unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
3125                                  getNextIntArgReg(ArgReg), RC);
3126        SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
3127        if (!Subtarget->isLittle())
3128          std::swap(ArgValue, ArgValue2);
3129        ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
3130                               ArgValue, ArgValue2);
3131      }
3132
3133      InVals.push_back(ArgValue);
3134    } else { // VA.isRegLoc()
3135
3136      // sanity check
3137      assert(VA.isMemLoc());
3138
3139      // The stack pointer offset is relative to the caller stack frame.
3140      int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
3141                                      VA.getLocMemOffset(), true);
3142
3143      // Create load nodes to retrieve arguments from the stack
3144      SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3145      InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN,
3146                                   MachinePointerInfo::getFixedStack(FI),
3147                                   false, false, false, 0));
3148    }
3149  }
3150
3151  // The mips ABIs for returning structs by value requires that we copy
3152  // the sret argument into $v0 for the return. Save the argument into
3153  // a virtual register so that we can access it from the return points.
3154  if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3155    unsigned Reg = MipsFI->getSRetReturnReg();
3156    if (!Reg) {
3157      Reg = MF.getRegInfo().
3158        createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32));
3159      MipsFI->setSRetReturnReg(Reg);
3160    }
3161    SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
3162    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
3163  }
3164
3165  if (isVarArg)
3166    writeVarArgRegs(OutChains, MipsCCInfo, Chain, dl, DAG);
3167
3168  // All stores are grouped in one node to allow the matching between
3169  // the size of Ins and InVals. This only happens when on varg functions
3170  if (!OutChains.empty()) {
3171    OutChains.push_back(Chain);
3172    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3173                        &OutChains[0], OutChains.size());
3174  }
3175
3176  return Chain;
3177}
3178
3179//===----------------------------------------------------------------------===//
3180//               Return Value Calling Convention Implementation
3181//===----------------------------------------------------------------------===//
3182
3183bool
3184MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3185                                   MachineFunction &MF, bool isVarArg,
3186                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
3187                                   LLVMContext &Context) const {
3188  SmallVector<CCValAssign, 16> RVLocs;
3189  CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
3190                 RVLocs, Context);
3191  return CCInfo.CheckReturn(Outs, RetCC_Mips);
3192}
3193
3194SDValue
3195MipsTargetLowering::LowerReturn(SDValue Chain,
3196                                CallingConv::ID CallConv, bool isVarArg,
3197                                const SmallVectorImpl<ISD::OutputArg> &Outs,
3198                                const SmallVectorImpl<SDValue> &OutVals,
3199                                DebugLoc dl, SelectionDAG &DAG) const {
3200
3201  // CCValAssign - represent the assignment of
3202  // the return value to a location
3203  SmallVector<CCValAssign, 16> RVLocs;
3204
3205  // CCState - Info about the registers and stack slot.
3206  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3207                 getTargetMachine(), RVLocs, *DAG.getContext());
3208
3209  // Analize return values.
3210  CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3211
3212  // If this is the first return lowered for this function, add
3213  // the regs to the liveout set for the function.
3214  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3215    for (unsigned i = 0; i != RVLocs.size(); ++i)
3216      if (RVLocs[i].isRegLoc())
3217        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3218  }
3219
3220  SDValue Flag;
3221
3222  // Copy the result values into the output registers.
3223  for (unsigned i = 0; i != RVLocs.size(); ++i) {
3224    CCValAssign &VA = RVLocs[i];
3225    assert(VA.isRegLoc() && "Can only return in registers!");
3226
3227    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
3228
3229    // guarantee that all emitted copies are
3230    // stuck together, avoiding something bad
3231    Flag = Chain.getValue(1);
3232  }
3233
3234  // The mips ABIs for returning structs by value requires that we copy
3235  // the sret argument into $v0 for the return. We saved the argument into
3236  // a virtual register in the entry block, so now we copy the value out
3237  // and into $v0.
3238  if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3239    MachineFunction &MF      = DAG.getMachineFunction();
3240    MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3241    unsigned Reg = MipsFI->getSRetReturnReg();
3242
3243    if (!Reg)
3244      llvm_unreachable("sret virtual register not created in the entry block");
3245    SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
3246    unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0;
3247
3248    Chain = DAG.getCopyToReg(Chain, dl, V0, Val, Flag);
3249    Flag = Chain.getValue(1);
3250    MF.getRegInfo().addLiveOut(V0);
3251  }
3252
3253  // Return on Mips is always a "jr $ra"
3254  if (Flag.getNode())
3255    return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain, Flag);
3256
3257  // Return Void
3258  return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain);
3259}
3260
3261//===----------------------------------------------------------------------===//
3262//                           Mips Inline Assembly Support
3263//===----------------------------------------------------------------------===//
3264
3265/// getConstraintType - Given a constraint letter, return the type of
3266/// constraint it is for this target.
3267MipsTargetLowering::ConstraintType MipsTargetLowering::
3268getConstraintType(const std::string &Constraint) const
3269{
3270  // Mips specific constrainy
3271  // GCC config/mips/constraints.md
3272  //
3273  // 'd' : An address register. Equivalent to r
3274  //       unless generating MIPS16 code.
3275  // 'y' : Equivalent to r; retained for
3276  //       backwards compatibility.
3277  // 'c' : A register suitable for use in an indirect
3278  //       jump. This will always be $25 for -mabicalls.
3279  // 'l' : The lo register. 1 word storage.
3280  // 'x' : The hilo register pair. Double word storage.
3281  if (Constraint.size() == 1) {
3282    switch (Constraint[0]) {
3283      default : break;
3284      case 'd':
3285      case 'y':
3286      case 'f':
3287      case 'c':
3288      case 'l':
3289      case 'x':
3290        return C_RegisterClass;
3291    }
3292  }
3293  return TargetLowering::getConstraintType(Constraint);
3294}
3295
3296/// Examine constraint type and operand type and determine a weight value.
3297/// This object must already have been set up with the operand type
3298/// and the current alternative constraint selected.
3299TargetLowering::ConstraintWeight
3300MipsTargetLowering::getSingleConstraintMatchWeight(
3301    AsmOperandInfo &info, const char *constraint) const {
3302  ConstraintWeight weight = CW_Invalid;
3303  Value *CallOperandVal = info.CallOperandVal;
3304    // If we don't have a value, we can't do a match,
3305    // but allow it at the lowest weight.
3306  if (CallOperandVal == NULL)
3307    return CW_Default;
3308  Type *type = CallOperandVal->getType();
3309  // Look at the constraint type.
3310  switch (*constraint) {
3311  default:
3312    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3313    break;
3314  case 'd':
3315  case 'y':
3316    if (type->isIntegerTy())
3317      weight = CW_Register;
3318    break;
3319  case 'f':
3320    if (type->isFloatTy())
3321      weight = CW_Register;
3322    break;
3323  case 'c': // $25 for indirect jumps
3324  case 'l': // lo register
3325  case 'x': // hilo register pair
3326      if (type->isIntegerTy())
3327      weight = CW_SpecificReg;
3328      break;
3329  case 'I': // signed 16 bit immediate
3330  case 'J': // integer zero
3331  case 'K': // unsigned 16 bit immediate
3332  case 'L': // signed 32 bit immediate where lower 16 bits are 0
3333  case 'N': // immediate in the range of -65535 to -1 (inclusive)
3334  case 'O': // signed 15 bit immediate (+- 16383)
3335  case 'P': // immediate in the range of 65535 to 1 (inclusive)
3336    if (isa<ConstantInt>(CallOperandVal))
3337      weight = CW_Constant;
3338    break;
3339  }
3340  return weight;
3341}
3342
3343/// Given a register class constraint, like 'r', if this corresponds directly
3344/// to an LLVM register class, return a register of 0 and the register class
3345/// pointer.
3346std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
3347getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
3348{
3349  if (Constraint.size() == 1) {
3350    switch (Constraint[0]) {
3351    case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3352    case 'y': // Same as 'r'. Exists for compatibility.
3353    case 'r':
3354      if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3355        if (Subtarget->inMips16Mode())
3356          return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3357        return std::make_pair(0U, &Mips::CPURegsRegClass);
3358      }
3359      if (VT == MVT::i64 && !HasMips64)
3360        return std::make_pair(0U, &Mips::CPURegsRegClass);
3361      if (VT == MVT::i64 && HasMips64)
3362        return std::make_pair(0U, &Mips::CPU64RegsRegClass);
3363      // This will generate an error message
3364      return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
3365    case 'f':
3366      if (VT == MVT::f32)
3367        return std::make_pair(0U, &Mips::FGR32RegClass);
3368      if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
3369        if (Subtarget->isFP64bit())
3370          return std::make_pair(0U, &Mips::FGR64RegClass);
3371        return std::make_pair(0U, &Mips::AFGR64RegClass);
3372      }
3373      break;
3374    case 'c': // register suitable for indirect jump
3375      if (VT == MVT::i32)
3376        return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass);
3377      assert(VT == MVT::i64 && "Unexpected type.");
3378      return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass);
3379    case 'l': // register suitable for indirect jump
3380      if (VT == MVT::i32)
3381        return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass);
3382      return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass);
3383    case 'x': // register suitable for indirect jump
3384      // Fixme: Not triggering the use of both hi and low
3385      // This will generate an error message
3386      return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
3387    }
3388  }
3389  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3390}
3391
3392/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3393/// vector.  If it is invalid, don't add anything to Ops.
3394void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3395                                                     std::string &Constraint,
3396                                                     std::vector<SDValue>&Ops,
3397                                                     SelectionDAG &DAG) const {
3398  SDValue Result(0, 0);
3399
3400  // Only support length 1 constraints for now.
3401  if (Constraint.length() > 1) return;
3402
3403  char ConstraintLetter = Constraint[0];
3404  switch (ConstraintLetter) {
3405  default: break; // This will fall through to the generic implementation
3406  case 'I': // Signed 16 bit constant
3407    // If this fails, the parent routine will give an error
3408    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3409      EVT Type = Op.getValueType();
3410      int64_t Val = C->getSExtValue();
3411      if (isInt<16>(Val)) {
3412        Result = DAG.getTargetConstant(Val, Type);
3413        break;
3414      }
3415    }
3416    return;
3417  case 'J': // integer zero
3418    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3419      EVT Type = Op.getValueType();
3420      int64_t Val = C->getZExtValue();
3421      if (Val == 0) {
3422        Result = DAG.getTargetConstant(0, Type);
3423        break;
3424      }
3425    }
3426    return;
3427  case 'K': // unsigned 16 bit immediate
3428    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3429      EVT Type = Op.getValueType();
3430      uint64_t Val = (uint64_t)C->getZExtValue();
3431      if (isUInt<16>(Val)) {
3432        Result = DAG.getTargetConstant(Val, Type);
3433        break;
3434      }
3435    }
3436    return;
3437  case 'L': // signed 32 bit immediate where lower 16 bits are 0
3438    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3439      EVT Type = Op.getValueType();
3440      int64_t Val = C->getSExtValue();
3441      if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3442        Result = DAG.getTargetConstant(Val, Type);
3443        break;
3444      }
3445    }
3446    return;
3447  case 'N': // immediate in the range of -65535 to -1 (inclusive)
3448    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3449      EVT Type = Op.getValueType();
3450      int64_t Val = C->getSExtValue();
3451      if ((Val >= -65535) && (Val <= -1)) {
3452        Result = DAG.getTargetConstant(Val, Type);
3453        break;
3454      }
3455    }
3456    return;
3457  case 'O': // signed 15 bit immediate
3458    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3459      EVT Type = Op.getValueType();
3460      int64_t Val = C->getSExtValue();
3461      if ((isInt<15>(Val))) {
3462        Result = DAG.getTargetConstant(Val, Type);
3463        break;
3464      }
3465    }
3466    return;
3467  case 'P': // immediate in the range of 1 to 65535 (inclusive)
3468    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3469      EVT Type = Op.getValueType();
3470      int64_t Val = C->getSExtValue();
3471      if ((Val <= 65535) && (Val >= 1)) {
3472        Result = DAG.getTargetConstant(Val, Type);
3473        break;
3474      }
3475    }
3476    return;
3477  }
3478
3479  if (Result.getNode()) {
3480    Ops.push_back(Result);
3481    return;
3482  }
3483
3484  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3485}
3486
3487bool
3488MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const {
3489  // No global is ever allowed as a base.
3490  if (AM.BaseGV)
3491    return false;
3492
3493  switch (AM.Scale) {
3494  case 0: // "r+i" or just "i", depending on HasBaseReg.
3495    break;
3496  case 1:
3497    if (!AM.HasBaseReg) // allow "r+i".
3498      break;
3499    return false; // disallow "r+r" or "r+r+i".
3500  default:
3501    return false;
3502  }
3503
3504  return true;
3505}
3506
3507bool
3508MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3509  // The Mips target isn't yet aware of offsets.
3510  return false;
3511}
3512
3513EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3514                                            unsigned SrcAlign, bool IsZeroVal,
3515                                            bool MemcpyStrSrc,
3516                                            MachineFunction &MF) const {
3517  if (Subtarget->hasMips64())
3518    return MVT::i64;
3519
3520  return MVT::i32;
3521}
3522
3523bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3524  if (VT != MVT::f32 && VT != MVT::f64)
3525    return false;
3526  if (Imm.isNegZero())
3527    return false;
3528  return Imm.isZero();
3529}
3530
3531unsigned MipsTargetLowering::getJumpTableEncoding() const {
3532  if (IsN64)
3533    return MachineJumpTableInfo::EK_GPRel64BlockAddress;
3534
3535  return TargetLowering::getJumpTableEncoding();
3536}
3537
3538MipsTargetLowering::MipsCC::MipsCC(CallingConv::ID CallConv, bool IsVarArg,
3539                                   bool IsO32, CCState &Info) : CCInfo(Info) {
3540  UseRegsForByval = true;
3541
3542  if (IsO32) {
3543    RegSize = 4;
3544    NumIntArgRegs = array_lengthof(O32IntRegs);
3545    ReservedArgArea = 16;
3546    IntArgRegs = ShadowRegs = O32IntRegs;
3547    FixedFn = VarFn = CC_MipsO32;
3548  } else {
3549    RegSize = 8;
3550    NumIntArgRegs = array_lengthof(Mips64IntRegs);
3551    ReservedArgArea = 0;
3552    IntArgRegs = Mips64IntRegs;
3553    ShadowRegs = Mips64DPRegs;
3554    FixedFn = CC_MipsN;
3555    VarFn = CC_MipsN_VarArg;
3556  }
3557
3558  if (CallConv == CallingConv::Fast) {
3559    assert(!IsVarArg);
3560    UseRegsForByval = false;
3561    ReservedArgArea = 0;
3562    FixedFn = VarFn = CC_Mips_FastCC;
3563  }
3564
3565  // Pre-allocate reserved argument area.
3566  CCInfo.AllocateStack(ReservedArgArea, 1);
3567}
3568
3569void MipsTargetLowering::MipsCC::
3570analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args) {
3571  unsigned NumOpnds = Args.size();
3572
3573  for (unsigned I = 0; I != NumOpnds; ++I) {
3574    MVT ArgVT = Args[I].VT;
3575    ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3576    bool R;
3577
3578    if (ArgFlags.isByVal()) {
3579      handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
3580      continue;
3581    }
3582
3583    if (Args[I].IsFixed)
3584      R = FixedFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
3585    else
3586      R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
3587
3588    if (R) {
3589#ifndef NDEBUG
3590      dbgs() << "Call operand #" << I << " has unhandled type "
3591             << EVT(ArgVT).getEVTString();
3592#endif
3593      llvm_unreachable(0);
3594    }
3595  }
3596}
3597
3598void MipsTargetLowering::MipsCC::
3599analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args) {
3600  unsigned NumArgs = Args.size();
3601
3602  for (unsigned I = 0; I != NumArgs; ++I) {
3603    MVT ArgVT = Args[I].VT;
3604    ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3605
3606    if (ArgFlags.isByVal()) {
3607      handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
3608      continue;
3609    }
3610
3611    if (!FixedFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
3612      continue;
3613
3614#ifndef NDEBUG
3615    dbgs() << "Formal Arg #" << I << " has unhandled type "
3616           << EVT(ArgVT).getEVTString();
3617#endif
3618    llvm_unreachable(0);
3619  }
3620}
3621
3622void
3623MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
3624                                           MVT LocVT,
3625                                           CCValAssign::LocInfo LocInfo,
3626                                           ISD::ArgFlagsTy ArgFlags) {
3627  assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
3628
3629  struct ByValArgInfo ByVal;
3630  unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize);
3631  unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize),
3632                            RegSize * 2);
3633
3634  if (UseRegsForByval)
3635    allocateRegs(ByVal, ByValSize, Align);
3636
3637  // Allocate space on caller's stack.
3638  ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs,
3639                                       Align);
3640  CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT,
3641                                    LocInfo));
3642  ByValArgs.push_back(ByVal);
3643}
3644
3645void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
3646                                              unsigned ByValSize,
3647                                              unsigned Align) {
3648  assert(!(ByValSize % RegSize) && !(Align % RegSize) &&
3649         "Byval argument's size and alignment should be a multiple of"
3650         "RegSize.");
3651
3652  ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs);
3653
3654  // If Align > RegSize, the first arg register must be even.
3655  if ((Align > RegSize) && (ByVal.FirstIdx % 2)) {
3656    CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
3657    ++ByVal.FirstIdx;
3658  }
3659
3660  // Mark the registers allocated.
3661  for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs);
3662       ByValSize -= RegSize, ++I, ++ByVal.NumRegs)
3663    CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
3664}
3665
3666void MipsTargetLowering::
3667copyByValRegs(SDValue Chain, DebugLoc DL, std::vector<SDValue> &OutChains,
3668              SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
3669              SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
3670              const MipsCC &CC, const ByValArgInfo &ByVal) const {
3671  MachineFunction &MF = DAG.getMachineFunction();
3672  MachineFrameInfo *MFI = MF.getFrameInfo();
3673  unsigned RegAreaSize = ByVal.NumRegs * CC.regSize();
3674  unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
3675  int FrameObjOffset;
3676
3677  if (RegAreaSize)
3678    FrameObjOffset = (int)CC.reservedArgArea() -
3679      (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize());
3680  else
3681    FrameObjOffset = ByVal.Address;
3682
3683  // Create frame object.
3684  EVT PtrTy = getPointerTy();
3685  int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
3686  SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
3687  InVals.push_back(FIN);
3688
3689  if (!ByVal.NumRegs)
3690    return;
3691
3692  // Copy arg registers.
3693  EVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
3694  const TargetRegisterClass *RC = getRegClassFor(RegTy);
3695
3696  for (unsigned I = 0; I < ByVal.NumRegs; ++I) {
3697    unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I];
3698    unsigned VReg = AddLiveIn(MF, ArgReg, RC);
3699    unsigned Offset = I * CC.regSize();
3700    SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3701                                   DAG.getConstant(Offset, PtrTy));
3702    SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
3703                                 StorePtr, MachinePointerInfo(FuncArg, Offset),
3704                                 false, false, 0);
3705    OutChains.push_back(Store);
3706  }
3707}
3708
3709// Copy byVal arg to registers and stack.
3710void MipsTargetLowering::
3711passByValArg(SDValue Chain, DebugLoc DL,
3712             SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass,
3713             SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
3714             MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
3715             const MipsCC &CC, const ByValArgInfo &ByVal,
3716             const ISD::ArgFlagsTy &Flags, bool isLittle) const {
3717  unsigned ByValSize = Flags.getByValSize();
3718  unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
3719  unsigned RegSize = CC.regSize();
3720  unsigned Alignment = std::min(Flags.getByValAlign(), RegSize);
3721  EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8);
3722
3723  if (ByVal.NumRegs) {
3724    const uint16_t *ArgRegs = CC.intArgRegs();
3725    bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize);
3726    unsigned I = 0;
3727
3728    // Copy words to registers.
3729    for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) {
3730      SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3731                                    DAG.getConstant(Offset, PtrTy));
3732      SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
3733                                    MachinePointerInfo(), false, false, false,
3734                                    Alignment);
3735      MemOpChains.push_back(LoadVal.getValue(1));
3736      unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
3737      RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3738    }
3739
3740    // Return if the struct has been fully copied.
3741    if (ByValSize == Offset)
3742      return;
3743
3744    // Copy the remainder of the byval argument with sub-word loads and shifts.
3745    if (LeftoverBytes) {
3746      assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) &&
3747             "Size of the remainder should be smaller than RegSize.");
3748      SDValue Val;
3749
3750      for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0;
3751           Offset < ByValSize; LoadSize /= 2) {
3752        unsigned RemSize = ByValSize - Offset;
3753
3754        if (RemSize < LoadSize)
3755          continue;
3756
3757        // Load subword.
3758        SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3759                                      DAG.getConstant(Offset, PtrTy));
3760        SDValue LoadVal =
3761          DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr,
3762                         MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
3763                         false, false, Alignment);
3764        MemOpChains.push_back(LoadVal.getValue(1));
3765
3766        // Shift the loaded value.
3767        unsigned Shamt;
3768
3769        if (isLittle)
3770          Shamt = TotalSizeLoaded;
3771        else
3772          Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8;
3773
3774        SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3775                                    DAG.getConstant(Shamt, MVT::i32));
3776
3777        if (Val.getNode())
3778          Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3779        else
3780          Val = Shift;
3781
3782        Offset += LoadSize;
3783        TotalSizeLoaded += LoadSize;
3784        Alignment = std::min(Alignment, LoadSize);
3785      }
3786
3787      unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
3788      RegsToPass.push_back(std::make_pair(ArgReg, Val));
3789      return;
3790    }
3791  }
3792
3793  // Copy remainder of byval arg to it with memcpy.
3794  unsigned MemCpySize = ByValSize - Offset;
3795  SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3796                            DAG.getConstant(Offset, PtrTy));
3797  SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3798                            DAG.getIntPtrConstant(ByVal.Address));
3799  Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
3800                        DAG.getConstant(MemCpySize, PtrTy), Alignment,
3801                        /*isVolatile=*/false, /*AlwaysInline=*/false,
3802                        MachinePointerInfo(0), MachinePointerInfo(0));
3803  MemOpChains.push_back(Chain);
3804}
3805
3806void
3807MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3808                                    const MipsCC &CC, SDValue Chain,
3809                                    DebugLoc DL, SelectionDAG &DAG) const {
3810  unsigned NumRegs = CC.numIntArgRegs();
3811  const uint16_t *ArgRegs = CC.intArgRegs();
3812  const CCState &CCInfo = CC.getCCInfo();
3813  unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
3814  unsigned RegSize = CC.regSize();
3815  EVT RegTy = MVT::getIntegerVT(RegSize * 8);
3816  const TargetRegisterClass *RC = getRegClassFor(RegTy);
3817  MachineFunction &MF = DAG.getMachineFunction();
3818  MachineFrameInfo *MFI = MF.getFrameInfo();
3819  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3820
3821  // Offset of the first variable argument from stack pointer.
3822  int VaArgOffset;
3823
3824  if (NumRegs == Idx)
3825    VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize);
3826  else
3827    VaArgOffset =
3828      (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
3829
3830  // Record the frame index of the first variable argument
3831  // which is a value necessary to VASTART.
3832  int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
3833  MipsFI->setVarArgsFrameIndex(FI);
3834
3835  // Copy the integer registers that have not been used for argument passing
3836  // to the argument register save area. For O32, the save area is allocated
3837  // in the caller's stack frame, while for N32/64, it is allocated in the
3838  // callee's stack frame.
3839  for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) {
3840    unsigned Reg = AddLiveIn(MF, ArgRegs[I], RC);
3841    SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
3842    FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
3843    SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
3844    SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
3845                                 MachinePointerInfo(), false, false, 0);
3846    cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0);
3847    OutChains.push_back(Store);
3848  }
3849}
3850