MipsISelLowering.cpp revision 7d71209912bb55856f34df7013382e6dd310983b
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-lower" 16#include "MipsISelLowering.h" 17#include "MipsMachineFunction.h" 18#include "MipsTargetMachine.h" 19#include "MipsTargetObjectFile.h" 20#include "MipsSubtarget.h" 21#include "InstPrinter/MipsInstPrinter.h" 22#include "MCTargetDesc/MipsBaseInfo.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/CallingConv.h" 28#include "llvm/ADT/Statistic.h" 29#include "llvm/CodeGen/CallingConvLower.h" 30#include "llvm/CodeGen/MachineFrameInfo.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineRegisterInfo.h" 34#include "llvm/CodeGen/SelectionDAGISel.h" 35#include "llvm/CodeGen/ValueTypes.h" 36#include "llvm/Support/CommandLine.h" 37#include "llvm/Support/Debug.h" 38#include "llvm/Support/ErrorHandling.h" 39#include "llvm/Support/raw_ostream.h" 40 41using namespace llvm; 42 43STATISTIC(NumTailCalls, "Number of tail calls"); 44 45static cl::opt<bool> 46EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden, 47 cl::desc("MIPS: Enable tail calls."), cl::init(false)); 48 49static const uint16_t O32IntRegs[4] = { 50 Mips::A0, Mips::A1, Mips::A2, Mips::A3 51}; 52 53static const uint16_t Mips64IntRegs[8] = { 54 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, 55 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 56}; 57 58static const uint16_t Mips64DPRegs[8] = { 59 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 60 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 61}; 62 63// If I is a shifted mask, set the size (Size) and the first bit of the 64// mask (Pos), and return true. 65// For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 66static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 67 if (!isShiftedMask_64(I)) 68 return false; 69 70 Size = CountPopulation_64(I); 71 Pos = CountTrailingZeros_64(I); 72 return true; 73} 74 75static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) { 76 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 77 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 78} 79 80const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 81 switch (Opcode) { 82 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 83 case MipsISD::TailCall: return "MipsISD::TailCall"; 84 case MipsISD::Hi: return "MipsISD::Hi"; 85 case MipsISD::Lo: return "MipsISD::Lo"; 86 case MipsISD::GPRel: return "MipsISD::GPRel"; 87 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 88 case MipsISD::Ret: return "MipsISD::Ret"; 89 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 90 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 91 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 92 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 93 case MipsISD::FPRound: return "MipsISD::FPRound"; 94 case MipsISD::MAdd: return "MipsISD::MAdd"; 95 case MipsISD::MAddu: return "MipsISD::MAddu"; 96 case MipsISD::MSub: return "MipsISD::MSub"; 97 case MipsISD::MSubu: return "MipsISD::MSubu"; 98 case MipsISD::DivRem: return "MipsISD::DivRem"; 99 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 100 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 101 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 102 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 103 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 104 case MipsISD::Sync: return "MipsISD::Sync"; 105 case MipsISD::Ext: return "MipsISD::Ext"; 106 case MipsISD::Ins: return "MipsISD::Ins"; 107 case MipsISD::LWL: return "MipsISD::LWL"; 108 case MipsISD::LWR: return "MipsISD::LWR"; 109 case MipsISD::SWL: return "MipsISD::SWL"; 110 case MipsISD::SWR: return "MipsISD::SWR"; 111 case MipsISD::LDL: return "MipsISD::LDL"; 112 case MipsISD::LDR: return "MipsISD::LDR"; 113 case MipsISD::SDL: return "MipsISD::SDL"; 114 case MipsISD::SDR: return "MipsISD::SDR"; 115 case MipsISD::EXTP: return "MipsISD::EXTP"; 116 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 117 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 118 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 119 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 120 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 121 case MipsISD::SHILO: return "MipsISD::SHILO"; 122 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 123 case MipsISD::MULT: return "MipsISD::MULT"; 124 case MipsISD::MULTU: return "MipsISD::MULTU"; 125 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSPDSP"; 126 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 127 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 128 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 129 default: return NULL; 130 } 131} 132 133MipsTargetLowering:: 134MipsTargetLowering(MipsTargetMachine &TM) 135 : TargetLowering(TM, new MipsTargetObjectFile()), 136 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 137 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()), 138 IsO32(Subtarget->isABI_O32()) { 139 140 // Mips does not have i1 type, so use i32 for 141 // setcc operations results (slt, sgt, ...). 142 setBooleanContents(ZeroOrOneBooleanContent); 143 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 144 145 // Set up the register classes 146 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass); 147 148 if (HasMips64) 149 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass); 150 151 if (Subtarget->inMips16Mode()) { 152 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); 153 } 154 155 if (Subtarget->hasDSP()) { 156 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; 157 158 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) { 159 addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass); 160 161 // Expand all builtin opcodes. 162 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 163 setOperationAction(Opc, VecTys[i], Expand); 164 165 setOperationAction(ISD::LOAD, VecTys[i], Legal); 166 setOperationAction(ISD::STORE, VecTys[i], Legal); 167 setOperationAction(ISD::BITCAST, VecTys[i], Legal); 168 } 169 } 170 171 if (!TM.Options.UseSoftFloat) { 172 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); 173 174 // When dealing with single precision only, use libcalls 175 if (!Subtarget->isSingleFloat()) { 176 if (HasMips64) 177 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); 178 else 179 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); 180 } 181 } 182 183 // Load extented operations for i1 types must be promoted 184 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 185 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 186 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 187 188 // MIPS doesn't have extending float->double load/store 189 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 190 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 191 192 // Used by legalize types to correctly generate the setcc result. 193 // Without this, every float setcc comes with a AND/OR with the result, 194 // we don't want this, since the fpcmp result goes to a flag register, 195 // which is used implicitly by brcond and select operations. 196 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 197 198 // Mips Custom Operations 199 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 200 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 201 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 202 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 203 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 204 setOperationAction(ISD::SELECT, MVT::f32, Custom); 205 setOperationAction(ISD::SELECT, MVT::f64, Custom); 206 setOperationAction(ISD::SELECT, MVT::i32, Custom); 207 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 208 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 209 setOperationAction(ISD::SETCC, MVT::f32, Custom); 210 setOperationAction(ISD::SETCC, MVT::f64, Custom); 211 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 212 setOperationAction(ISD::VASTART, MVT::Other, Custom); 213 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 214 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 215 if (Subtarget->inMips16Mode()) { 216 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 217 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 218 } 219 else { 220 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 221 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 222 } 223 if (!Subtarget->inMips16Mode()) { 224 setOperationAction(ISD::LOAD, MVT::i32, Custom); 225 setOperationAction(ISD::STORE, MVT::i32, Custom); 226 } 227 228 if (!TM.Options.NoNaNsFPMath) { 229 setOperationAction(ISD::FABS, MVT::f32, Custom); 230 setOperationAction(ISD::FABS, MVT::f64, Custom); 231 } 232 233 if (HasMips64) { 234 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 235 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 236 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 237 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 238 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 239 setOperationAction(ISD::SELECT, MVT::i64, Custom); 240 setOperationAction(ISD::LOAD, MVT::i64, Custom); 241 setOperationAction(ISD::STORE, MVT::i64, Custom); 242 } 243 244 if (!HasMips64) { 245 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 246 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 247 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 248 } 249 250 setOperationAction(ISD::SDIV, MVT::i32, Expand); 251 setOperationAction(ISD::SREM, MVT::i32, Expand); 252 setOperationAction(ISD::UDIV, MVT::i32, Expand); 253 setOperationAction(ISD::UREM, MVT::i32, Expand); 254 setOperationAction(ISD::SDIV, MVT::i64, Expand); 255 setOperationAction(ISD::SREM, MVT::i64, Expand); 256 setOperationAction(ISD::UDIV, MVT::i64, Expand); 257 setOperationAction(ISD::UREM, MVT::i64, Expand); 258 259 // Operations not directly supported by Mips. 260 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 261 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 262 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 263 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 264 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 265 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 266 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 267 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 268 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 269 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 270 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 271 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 272 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 273 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 274 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 275 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 276 setOperationAction(ISD::ROTL, MVT::i32, Expand); 277 setOperationAction(ISD::ROTL, MVT::i64, Expand); 278 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 279 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 280 281 if (!Subtarget->hasMips32r2()) 282 setOperationAction(ISD::ROTR, MVT::i32, Expand); 283 284 if (!Subtarget->hasMips64r2()) 285 setOperationAction(ISD::ROTR, MVT::i64, Expand); 286 287 setOperationAction(ISD::FSIN, MVT::f32, Expand); 288 setOperationAction(ISD::FSIN, MVT::f64, Expand); 289 setOperationAction(ISD::FCOS, MVT::f32, Expand); 290 setOperationAction(ISD::FCOS, MVT::f64, Expand); 291 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 292 setOperationAction(ISD::FPOW, MVT::f32, Expand); 293 setOperationAction(ISD::FPOW, MVT::f64, Expand); 294 setOperationAction(ISD::FLOG, MVT::f32, Expand); 295 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 296 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 297 setOperationAction(ISD::FEXP, MVT::f32, Expand); 298 setOperationAction(ISD::FMA, MVT::f32, Expand); 299 setOperationAction(ISD::FMA, MVT::f64, Expand); 300 setOperationAction(ISD::FREM, MVT::f32, Expand); 301 setOperationAction(ISD::FREM, MVT::f64, Expand); 302 303 if (!TM.Options.NoNaNsFPMath) { 304 setOperationAction(ISD::FNEG, MVT::f32, Expand); 305 setOperationAction(ISD::FNEG, MVT::f64, Expand); 306 } 307 308 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 309 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 310 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 311 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 312 313 setOperationAction(ISD::VAARG, MVT::Other, Expand); 314 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 315 setOperationAction(ISD::VAEND, MVT::Other, Expand); 316 317 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); 318 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); 319 320 // Use the default for now 321 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 322 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 323 324 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 325 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 326 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 327 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 328 329 if (Subtarget->inMips16Mode()) { 330 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 331 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 332 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 333 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 334 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 335 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 336 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 337 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 338 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); 339 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); 340 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); 341 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); 342 } 343 344 setInsertFencesForAtomic(true); 345 346 if (!Subtarget->hasSEInReg()) { 347 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 348 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 349 } 350 351 if (!Subtarget->hasBitCount()) { 352 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 353 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 354 } 355 356 if (!Subtarget->hasSwap()) { 357 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 358 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 359 } 360 361 if (HasMips64) { 362 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); 363 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom); 364 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom); 365 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 366 } 367 368 setTargetDAGCombine(ISD::ADDE); 369 setTargetDAGCombine(ISD::SUBE); 370 setTargetDAGCombine(ISD::SDIVREM); 371 setTargetDAGCombine(ISD::UDIVREM); 372 setTargetDAGCombine(ISD::SELECT); 373 setTargetDAGCombine(ISD::AND); 374 setTargetDAGCombine(ISD::OR); 375 setTargetDAGCombine(ISD::ADD); 376 377 setMinFunctionAlignment(HasMips64 ? 3 : 2); 378 379 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP); 380 computeRegisterProperties(); 381 382 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0); 383 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1); 384 385 maxStoresPerMemcpy = 16; 386} 387 388bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 389 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 390 391 if (Subtarget->inMips16Mode()) 392 return false; 393 394 switch (SVT) { 395 case MVT::i64: 396 case MVT::i32: 397 return true; 398 default: 399 return false; 400 } 401} 402 403EVT MipsTargetLowering::getSetCCResultType(EVT VT) const { 404 return MVT::i32; 405} 406 407// SelectMadd - 408// Transforms a subgraph in CurDAG if the following pattern is found: 409// (addc multLo, Lo0), (adde multHi, Hi0), 410// where, 411// multHi/Lo: product of multiplication 412// Lo0: initial value of Lo register 413// Hi0: initial value of Hi register 414// Return true if pattern matching was successful. 415static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) { 416 // ADDENode's second operand must be a flag output of an ADDC node in order 417 // for the matching to be successful. 418 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); 419 420 if (ADDCNode->getOpcode() != ISD::ADDC) 421 return false; 422 423 SDValue MultHi = ADDENode->getOperand(0); 424 SDValue MultLo = ADDCNode->getOperand(0); 425 SDNode *MultNode = MultHi.getNode(); 426 unsigned MultOpc = MultHi.getOpcode(); 427 428 // MultHi and MultLo must be generated by the same node, 429 if (MultLo.getNode() != MultNode) 430 return false; 431 432 // and it must be a multiplication. 433 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 434 return false; 435 436 // MultLo amd MultHi must be the first and second output of MultNode 437 // respectively. 438 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 439 return false; 440 441 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 442 // of the values of MultNode, in which case MultNode will be removed in later 443 // phases. 444 // If there exist users other than ADDENode or ADDCNode, this function returns 445 // here, which will result in MultNode being mapped to a single MULT 446 // instruction node rather than a pair of MULT and MADD instructions being 447 // produced. 448 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 449 return false; 450 451 SDValue Chain = CurDAG->getEntryNode(); 452 DebugLoc dl = ADDENode->getDebugLoc(); 453 454 // create MipsMAdd(u) node 455 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 456 457 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue, 458 MultNode->getOperand(0),// Factor 0 459 MultNode->getOperand(1),// Factor 1 460 ADDCNode->getOperand(1),// Lo0 461 ADDENode->getOperand(1));// Hi0 462 463 // create CopyFromReg nodes 464 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 465 MAdd); 466 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 467 Mips::HI, MVT::i32, 468 CopyFromLo.getValue(2)); 469 470 // replace uses of adde and addc here 471 if (!SDValue(ADDCNode, 0).use_empty()) 472 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 473 474 if (!SDValue(ADDENode, 0).use_empty()) 475 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 476 477 return true; 478} 479 480// SelectMsub - 481// Transforms a subgraph in CurDAG if the following pattern is found: 482// (addc Lo0, multLo), (sube Hi0, multHi), 483// where, 484// multHi/Lo: product of multiplication 485// Lo0: initial value of Lo register 486// Hi0: initial value of Hi register 487// Return true if pattern matching was successful. 488static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) { 489 // SUBENode's second operand must be a flag output of an SUBC node in order 490 // for the matching to be successful. 491 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); 492 493 if (SUBCNode->getOpcode() != ISD::SUBC) 494 return false; 495 496 SDValue MultHi = SUBENode->getOperand(1); 497 SDValue MultLo = SUBCNode->getOperand(1); 498 SDNode *MultNode = MultHi.getNode(); 499 unsigned MultOpc = MultHi.getOpcode(); 500 501 // MultHi and MultLo must be generated by the same node, 502 if (MultLo.getNode() != MultNode) 503 return false; 504 505 // and it must be a multiplication. 506 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 507 return false; 508 509 // MultLo amd MultHi must be the first and second output of MultNode 510 // respectively. 511 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 512 return false; 513 514 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 515 // of the values of MultNode, in which case MultNode will be removed in later 516 // phases. 517 // If there exist users other than SUBENode or SUBCNode, this function returns 518 // here, which will result in MultNode being mapped to a single MULT 519 // instruction node rather than a pair of MULT and MSUB instructions being 520 // produced. 521 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 522 return false; 523 524 SDValue Chain = CurDAG->getEntryNode(); 525 DebugLoc dl = SUBENode->getDebugLoc(); 526 527 // create MipsSub(u) node 528 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 529 530 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue, 531 MultNode->getOperand(0),// Factor 0 532 MultNode->getOperand(1),// Factor 1 533 SUBCNode->getOperand(0),// Lo0 534 SUBENode->getOperand(0));// Hi0 535 536 // create CopyFromReg nodes 537 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 538 MSub); 539 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 540 Mips::HI, MVT::i32, 541 CopyFromLo.getValue(2)); 542 543 // replace uses of sube and subc here 544 if (!SDValue(SUBCNode, 0).use_empty()) 545 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 546 547 if (!SDValue(SUBENode, 0).use_empty()) 548 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 549 550 return true; 551} 552 553static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG, 554 TargetLowering::DAGCombinerInfo &DCI, 555 const MipsSubtarget *Subtarget) { 556 if (DCI.isBeforeLegalize()) 557 return SDValue(); 558 559 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 560 SelectMadd(N, &DAG)) 561 return SDValue(N, 0); 562 563 return SDValue(); 564} 565 566static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG, 567 TargetLowering::DAGCombinerInfo &DCI, 568 const MipsSubtarget *Subtarget) { 569 if (DCI.isBeforeLegalize()) 570 return SDValue(); 571 572 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 573 SelectMsub(N, &DAG)) 574 return SDValue(N, 0); 575 576 return SDValue(); 577} 578 579static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG, 580 TargetLowering::DAGCombinerInfo &DCI, 581 const MipsSubtarget *Subtarget) { 582 if (DCI.isBeforeLegalizeOps()) 583 return SDValue(); 584 585 EVT Ty = N->getValueType(0); 586 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64; 587 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64; 588 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 589 MipsISD::DivRemU; 590 DebugLoc dl = N->getDebugLoc(); 591 592 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 593 N->getOperand(0), N->getOperand(1)); 594 SDValue InChain = DAG.getEntryNode(); 595 SDValue InGlue = DivRem; 596 597 // insert MFLO 598 if (N->hasAnyUseOfValue(0)) { 599 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty, 600 InGlue); 601 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 602 InChain = CopyFromLo.getValue(1); 603 InGlue = CopyFromLo.getValue(2); 604 } 605 606 // insert MFHI 607 if (N->hasAnyUseOfValue(1)) { 608 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 609 HI, Ty, InGlue); 610 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 611 } 612 613 return SDValue(); 614} 615 616static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 617 switch (CC) { 618 default: llvm_unreachable("Unknown fp condition code!"); 619 case ISD::SETEQ: 620 case ISD::SETOEQ: return Mips::FCOND_OEQ; 621 case ISD::SETUNE: return Mips::FCOND_UNE; 622 case ISD::SETLT: 623 case ISD::SETOLT: return Mips::FCOND_OLT; 624 case ISD::SETGT: 625 case ISD::SETOGT: return Mips::FCOND_OGT; 626 case ISD::SETLE: 627 case ISD::SETOLE: return Mips::FCOND_OLE; 628 case ISD::SETGE: 629 case ISD::SETOGE: return Mips::FCOND_OGE; 630 case ISD::SETULT: return Mips::FCOND_ULT; 631 case ISD::SETULE: return Mips::FCOND_ULE; 632 case ISD::SETUGT: return Mips::FCOND_UGT; 633 case ISD::SETUGE: return Mips::FCOND_UGE; 634 case ISD::SETUO: return Mips::FCOND_UN; 635 case ISD::SETO: return Mips::FCOND_OR; 636 case ISD::SETNE: 637 case ISD::SETONE: return Mips::FCOND_ONE; 638 case ISD::SETUEQ: return Mips::FCOND_UEQ; 639 } 640} 641 642 643// Returns true if condition code has to be inverted. 644static bool InvertFPCondCode(Mips::CondCode CC) { 645 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 646 return false; 647 648 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 649 "Illegal Condition Code"); 650 651 return true; 652} 653 654// Creates and returns an FPCmp node from a setcc node. 655// Returns Op if setcc is not a floating point comparison. 656static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) { 657 // must be a SETCC node 658 if (Op.getOpcode() != ISD::SETCC) 659 return Op; 660 661 SDValue LHS = Op.getOperand(0); 662 663 if (!LHS.getValueType().isFloatingPoint()) 664 return Op; 665 666 SDValue RHS = Op.getOperand(1); 667 DebugLoc dl = Op.getDebugLoc(); 668 669 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 670 // node if necessary. 671 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 672 673 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 674 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 675} 676 677// Creates and returns a CMovFPT/F node. 678static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 679 SDValue False, DebugLoc DL) { 680 bool invert = InvertFPCondCode((Mips::CondCode) 681 cast<ConstantSDNode>(Cond.getOperand(2)) 682 ->getSExtValue()); 683 684 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 685 True.getValueType(), True, False, Cond); 686} 687 688static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 689 TargetLowering::DAGCombinerInfo &DCI, 690 const MipsSubtarget *Subtarget) { 691 if (DCI.isBeforeLegalizeOps()) 692 return SDValue(); 693 694 SDValue SetCC = N->getOperand(0); 695 696 if ((SetCC.getOpcode() != ISD::SETCC) || 697 !SetCC.getOperand(0).getValueType().isInteger()) 698 return SDValue(); 699 700 SDValue False = N->getOperand(2); 701 EVT FalseTy = False.getValueType(); 702 703 if (!FalseTy.isInteger()) 704 return SDValue(); 705 706 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False); 707 708 if (!CN || CN->getZExtValue()) 709 return SDValue(); 710 711 const DebugLoc DL = N->getDebugLoc(); 712 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 713 SDValue True = N->getOperand(1); 714 715 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 716 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 717 718 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 719} 720 721static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG, 722 TargetLowering::DAGCombinerInfo &DCI, 723 const MipsSubtarget *Subtarget) { 724 // Pattern match EXT. 725 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 726 // => ext $dst, $src, size, pos 727 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 728 return SDValue(); 729 730 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 731 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 732 733 // Op's first operand must be a shift right. 734 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 735 return SDValue(); 736 737 // The second operand of the shift must be an immediate. 738 ConstantSDNode *CN; 739 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 740 return SDValue(); 741 742 uint64_t Pos = CN->getZExtValue(); 743 uint64_t SMPos, SMSize; 744 745 // Op's second operand must be a shifted mask. 746 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 747 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 748 return SDValue(); 749 750 // Return if the shifted mask does not start at bit 0 or the sum of its size 751 // and Pos exceeds the word's size. 752 EVT ValTy = N->getValueType(0); 753 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 754 return SDValue(); 755 756 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy, 757 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), 758 DAG.getConstant(SMSize, MVT::i32)); 759} 760 761static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG, 762 TargetLowering::DAGCombinerInfo &DCI, 763 const MipsSubtarget *Subtarget) { 764 // Pattern match INS. 765 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 766 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 767 // => ins $dst, $src, size, pos, $src1 768 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 769 return SDValue(); 770 771 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 772 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 773 ConstantSDNode *CN; 774 775 // See if Op's first operand matches (and $src1 , mask0). 776 if (And0.getOpcode() != ISD::AND) 777 return SDValue(); 778 779 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 780 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 781 return SDValue(); 782 783 // See if Op's second operand matches (and (shl $src, pos), mask1). 784 if (And1.getOpcode() != ISD::AND) 785 return SDValue(); 786 787 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 788 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 789 return SDValue(); 790 791 // The shift masks must have the same position and size. 792 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 793 return SDValue(); 794 795 SDValue Shl = And1.getOperand(0); 796 if (Shl.getOpcode() != ISD::SHL) 797 return SDValue(); 798 799 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 800 return SDValue(); 801 802 unsigned Shamt = CN->getZExtValue(); 803 804 // Return if the shift amount and the first bit position of mask are not the 805 // same. 806 EVT ValTy = N->getValueType(0); 807 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 808 return SDValue(); 809 810 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0), 811 DAG.getConstant(SMPos0, MVT::i32), 812 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0)); 813} 814 815static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG, 816 TargetLowering::DAGCombinerInfo &DCI, 817 const MipsSubtarget *Subtarget) { 818 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 819 820 if (DCI.isBeforeLegalizeOps()) 821 return SDValue(); 822 823 SDValue Add = N->getOperand(1); 824 825 if (Add.getOpcode() != ISD::ADD) 826 return SDValue(); 827 828 SDValue Lo = Add.getOperand(1); 829 830 if ((Lo.getOpcode() != MipsISD::Lo) || 831 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 832 return SDValue(); 833 834 EVT ValTy = N->getValueType(0); 835 DebugLoc DL = N->getDebugLoc(); 836 837 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 838 Add.getOperand(0)); 839 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 840} 841 842SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 843 const { 844 SelectionDAG &DAG = DCI.DAG; 845 unsigned opc = N->getOpcode(); 846 847 switch (opc) { 848 default: break; 849 case ISD::ADDE: 850 return PerformADDECombine(N, DAG, DCI, Subtarget); 851 case ISD::SUBE: 852 return PerformSUBECombine(N, DAG, DCI, Subtarget); 853 case ISD::SDIVREM: 854 case ISD::UDIVREM: 855 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 856 case ISD::SELECT: 857 return PerformSELECTCombine(N, DAG, DCI, Subtarget); 858 case ISD::AND: 859 return PerformANDCombine(N, DAG, DCI, Subtarget); 860 case ISD::OR: 861 return PerformORCombine(N, DAG, DCI, Subtarget); 862 case ISD::ADD: 863 return PerformADDCombine(N, DAG, DCI, Subtarget); 864 } 865 866 return SDValue(); 867} 868 869void 870MipsTargetLowering::LowerOperationWrapper(SDNode *N, 871 SmallVectorImpl<SDValue> &Results, 872 SelectionDAG &DAG) const { 873 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 874 875 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 876 Results.push_back(Res.getValue(I)); 877} 878 879void 880MipsTargetLowering::ReplaceNodeResults(SDNode *N, 881 SmallVectorImpl<SDValue> &Results, 882 SelectionDAG &DAG) const { 883 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 884 885 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 886 Results.push_back(Res.getValue(I)); 887} 888 889SDValue MipsTargetLowering:: 890LowerOperation(SDValue Op, SelectionDAG &DAG) const 891{ 892 switch (Op.getOpcode()) 893 { 894 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 895 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 896 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 897 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 898 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 899 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 900 case ISD::SELECT: return LowerSELECT(Op, DAG); 901 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 902 case ISD::SETCC: return LowerSETCC(Op, DAG); 903 case ISD::VASTART: return LowerVASTART(Op, DAG); 904 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 905 case ISD::FABS: return LowerFABS(Op, DAG); 906 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 907 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 908 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); 909 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 910 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); 911 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG, true); 912 case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false); 913 case ISD::LOAD: return LowerLOAD(Op, DAG); 914 case ISD::STORE: return LowerSTORE(Op, DAG); 915 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 916 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG); 917 } 918 return SDValue(); 919} 920 921//===----------------------------------------------------------------------===// 922// Lower helper functions 923//===----------------------------------------------------------------------===// 924 925// AddLiveIn - This helper function adds the specified physical register to the 926// MachineFunction as a live in value. It also creates a corresponding 927// virtual register for it. 928static unsigned 929AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 930{ 931 assert(RC->contains(PReg) && "Not the correct regclass!"); 932 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 933 MF.getRegInfo().addLiveIn(PReg, VReg); 934 return VReg; 935} 936 937// Get fp branch code (not opcode) from condition code. 938static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 939 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 940 return Mips::BRANCH_T; 941 942 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 943 "Invalid CondCode."); 944 945 return Mips::BRANCH_F; 946} 947 948/* 949static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, 950 DebugLoc dl, 951 const MipsSubtarget *Subtarget, 952 const TargetInstrInfo *TII, 953 bool isFPCmp, unsigned Opc) { 954 // There is no need to expand CMov instructions if target has 955 // conditional moves. 956 if (Subtarget->hasCondMov()) 957 return BB; 958 959 // To "insert" a SELECT_CC instruction, we actually have to insert the 960 // diamond control-flow pattern. The incoming instruction knows the 961 // destination vreg to set, the condition code register to branch on, the 962 // true/false values to select between, and a branch opcode to use. 963 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 964 MachineFunction::iterator It = BB; 965 ++It; 966 967 // thisMBB: 968 // ... 969 // TrueVal = ... 970 // setcc r1, r2, r3 971 // bNE r1, r0, copy1MBB 972 // fallthrough --> copy0MBB 973 MachineBasicBlock *thisMBB = BB; 974 MachineFunction *F = BB->getParent(); 975 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 976 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 977 F->insert(It, copy0MBB); 978 F->insert(It, sinkMBB); 979 980 // Transfer the remainder of BB and its successor edges to sinkMBB. 981 sinkMBB->splice(sinkMBB->begin(), BB, 982 llvm::next(MachineBasicBlock::iterator(MI)), 983 BB->end()); 984 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 985 986 // Next, add the true and fallthrough blocks as its successors. 987 BB->addSuccessor(copy0MBB); 988 BB->addSuccessor(sinkMBB); 989 990 // Emit the right instruction according to the type of the operands compared 991 if (isFPCmp) 992 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 993 else 994 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 995 .addReg(Mips::ZERO).addMBB(sinkMBB); 996 997 // copy0MBB: 998 // %FalseValue = ... 999 // # fallthrough to sinkMBB 1000 BB = copy0MBB; 1001 1002 // Update machine-CFG edges 1003 BB->addSuccessor(sinkMBB); 1004 1005 // sinkMBB: 1006 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 1007 // ... 1008 BB = sinkMBB; 1009 1010 if (isFPCmp) 1011 BuildMI(*BB, BB->begin(), dl, 1012 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 1013 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 1014 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 1015 else 1016 BuildMI(*BB, BB->begin(), dl, 1017 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 1018 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 1019 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 1020 1021 MI->eraseFromParent(); // The pseudo instruction is gone now. 1022 return BB; 1023} 1024*/ 1025 1026MachineBasicBlock * 1027MipsTargetLowering::EmitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{ 1028 // $bb: 1029 // bposge32_pseudo $vr0 1030 // => 1031 // $bb: 1032 // bposge32 $tbb 1033 // $fbb: 1034 // li $vr2, 0 1035 // b $sink 1036 // $tbb: 1037 // li $vr1, 1 1038 // $sink: 1039 // $vr0 = phi($vr2, $fbb, $vr1, $tbb) 1040 1041 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 1042 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1043 const TargetRegisterClass *RC = &Mips::CPURegsRegClass; 1044 DebugLoc DL = MI->getDebugLoc(); 1045 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1046 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB)); 1047 MachineFunction *F = BB->getParent(); 1048 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); 1049 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); 1050 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); 1051 F->insert(It, FBB); 1052 F->insert(It, TBB); 1053 F->insert(It, Sink); 1054 1055 // Transfer the remainder of BB and its successor edges to Sink. 1056 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), 1057 BB->end()); 1058 Sink->transferSuccessorsAndUpdatePHIs(BB); 1059 1060 // Add successors. 1061 BB->addSuccessor(FBB); 1062 BB->addSuccessor(TBB); 1063 FBB->addSuccessor(Sink); 1064 TBB->addSuccessor(Sink); 1065 1066 // Insert the real bposge32 instruction to $BB. 1067 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB); 1068 1069 // Fill $FBB. 1070 unsigned VR2 = RegInfo.createVirtualRegister(RC); 1071 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) 1072 .addReg(Mips::ZERO).addImm(0); 1073 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 1074 1075 // Fill $TBB. 1076 unsigned VR1 = RegInfo.createVirtualRegister(RC); 1077 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) 1078 .addReg(Mips::ZERO).addImm(1); 1079 1080 // Insert phi function to $Sink. 1081 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 1082 MI->getOperand(0).getReg()) 1083 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB); 1084 1085 MI->eraseFromParent(); // The pseudo instruction is gone now. 1086 return Sink; 1087} 1088 1089MachineBasicBlock * 1090MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1091 MachineBasicBlock *BB) const { 1092 switch (MI->getOpcode()) { 1093 default: llvm_unreachable("Unexpected instr type to insert"); 1094 case Mips::ATOMIC_LOAD_ADD_I8: 1095 case Mips::ATOMIC_LOAD_ADD_I8_P8: 1096 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 1097 case Mips::ATOMIC_LOAD_ADD_I16: 1098 case Mips::ATOMIC_LOAD_ADD_I16_P8: 1099 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 1100 case Mips::ATOMIC_LOAD_ADD_I32: 1101 case Mips::ATOMIC_LOAD_ADD_I32_P8: 1102 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); 1103 case Mips::ATOMIC_LOAD_ADD_I64: 1104 case Mips::ATOMIC_LOAD_ADD_I64_P8: 1105 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu); 1106 1107 case Mips::ATOMIC_LOAD_AND_I8: 1108 case Mips::ATOMIC_LOAD_AND_I8_P8: 1109 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 1110 case Mips::ATOMIC_LOAD_AND_I16: 1111 case Mips::ATOMIC_LOAD_AND_I16_P8: 1112 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 1113 case Mips::ATOMIC_LOAD_AND_I32: 1114 case Mips::ATOMIC_LOAD_AND_I32_P8: 1115 return EmitAtomicBinary(MI, BB, 4, Mips::AND); 1116 case Mips::ATOMIC_LOAD_AND_I64: 1117 case Mips::ATOMIC_LOAD_AND_I64_P8: 1118 return EmitAtomicBinary(MI, BB, 8, Mips::AND64); 1119 1120 case Mips::ATOMIC_LOAD_OR_I8: 1121 case Mips::ATOMIC_LOAD_OR_I8_P8: 1122 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 1123 case Mips::ATOMIC_LOAD_OR_I16: 1124 case Mips::ATOMIC_LOAD_OR_I16_P8: 1125 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 1126 case Mips::ATOMIC_LOAD_OR_I32: 1127 case Mips::ATOMIC_LOAD_OR_I32_P8: 1128 return EmitAtomicBinary(MI, BB, 4, Mips::OR); 1129 case Mips::ATOMIC_LOAD_OR_I64: 1130 case Mips::ATOMIC_LOAD_OR_I64_P8: 1131 return EmitAtomicBinary(MI, BB, 8, Mips::OR64); 1132 1133 case Mips::ATOMIC_LOAD_XOR_I8: 1134 case Mips::ATOMIC_LOAD_XOR_I8_P8: 1135 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 1136 case Mips::ATOMIC_LOAD_XOR_I16: 1137 case Mips::ATOMIC_LOAD_XOR_I16_P8: 1138 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 1139 case Mips::ATOMIC_LOAD_XOR_I32: 1140 case Mips::ATOMIC_LOAD_XOR_I32_P8: 1141 return EmitAtomicBinary(MI, BB, 4, Mips::XOR); 1142 case Mips::ATOMIC_LOAD_XOR_I64: 1143 case Mips::ATOMIC_LOAD_XOR_I64_P8: 1144 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64); 1145 1146 case Mips::ATOMIC_LOAD_NAND_I8: 1147 case Mips::ATOMIC_LOAD_NAND_I8_P8: 1148 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); 1149 case Mips::ATOMIC_LOAD_NAND_I16: 1150 case Mips::ATOMIC_LOAD_NAND_I16_P8: 1151 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); 1152 case Mips::ATOMIC_LOAD_NAND_I32: 1153 case Mips::ATOMIC_LOAD_NAND_I32_P8: 1154 return EmitAtomicBinary(MI, BB, 4, 0, true); 1155 case Mips::ATOMIC_LOAD_NAND_I64: 1156 case Mips::ATOMIC_LOAD_NAND_I64_P8: 1157 return EmitAtomicBinary(MI, BB, 8, 0, true); 1158 1159 case Mips::ATOMIC_LOAD_SUB_I8: 1160 case Mips::ATOMIC_LOAD_SUB_I8_P8: 1161 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 1162 case Mips::ATOMIC_LOAD_SUB_I16: 1163 case Mips::ATOMIC_LOAD_SUB_I16_P8: 1164 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 1165 case Mips::ATOMIC_LOAD_SUB_I32: 1166 case Mips::ATOMIC_LOAD_SUB_I32_P8: 1167 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); 1168 case Mips::ATOMIC_LOAD_SUB_I64: 1169 case Mips::ATOMIC_LOAD_SUB_I64_P8: 1170 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu); 1171 1172 case Mips::ATOMIC_SWAP_I8: 1173 case Mips::ATOMIC_SWAP_I8_P8: 1174 return EmitAtomicBinaryPartword(MI, BB, 1, 0); 1175 case Mips::ATOMIC_SWAP_I16: 1176 case Mips::ATOMIC_SWAP_I16_P8: 1177 return EmitAtomicBinaryPartword(MI, BB, 2, 0); 1178 case Mips::ATOMIC_SWAP_I32: 1179 case Mips::ATOMIC_SWAP_I32_P8: 1180 return EmitAtomicBinary(MI, BB, 4, 0); 1181 case Mips::ATOMIC_SWAP_I64: 1182 case Mips::ATOMIC_SWAP_I64_P8: 1183 return EmitAtomicBinary(MI, BB, 8, 0); 1184 1185 case Mips::ATOMIC_CMP_SWAP_I8: 1186 case Mips::ATOMIC_CMP_SWAP_I8_P8: 1187 return EmitAtomicCmpSwapPartword(MI, BB, 1); 1188 case Mips::ATOMIC_CMP_SWAP_I16: 1189 case Mips::ATOMIC_CMP_SWAP_I16_P8: 1190 return EmitAtomicCmpSwapPartword(MI, BB, 2); 1191 case Mips::ATOMIC_CMP_SWAP_I32: 1192 case Mips::ATOMIC_CMP_SWAP_I32_P8: 1193 return EmitAtomicCmpSwap(MI, BB, 4); 1194 case Mips::ATOMIC_CMP_SWAP_I64: 1195 case Mips::ATOMIC_CMP_SWAP_I64_P8: 1196 return EmitAtomicCmpSwap(MI, BB, 8); 1197 case Mips::BPOSGE32_PSEUDO: 1198 return EmitBPOSGE32(MI, BB); 1199 } 1200} 1201 1202// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1203// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1204MachineBasicBlock * 1205MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 1206 unsigned Size, unsigned BinOpcode, 1207 bool Nand) const { 1208 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 1209 1210 MachineFunction *MF = BB->getParent(); 1211 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1212 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1213 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1214 DebugLoc dl = MI->getDebugLoc(); 1215 unsigned LL, SC, AND, NOR, ZERO, BEQ; 1216 1217 if (Size == 4) { 1218 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1219 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1220 AND = Mips::AND; 1221 NOR = Mips::NOR; 1222 ZERO = Mips::ZERO; 1223 BEQ = Mips::BEQ; 1224 } 1225 else { 1226 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 1227 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 1228 AND = Mips::AND64; 1229 NOR = Mips::NOR64; 1230 ZERO = Mips::ZERO_64; 1231 BEQ = Mips::BEQ64; 1232 } 1233 1234 unsigned OldVal = MI->getOperand(0).getReg(); 1235 unsigned Ptr = MI->getOperand(1).getReg(); 1236 unsigned Incr = MI->getOperand(2).getReg(); 1237 1238 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1239 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1240 unsigned Success = RegInfo.createVirtualRegister(RC); 1241 1242 // insert new blocks after the current block 1243 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1244 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1245 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1246 MachineFunction::iterator It = BB; 1247 ++It; 1248 MF->insert(It, loopMBB); 1249 MF->insert(It, exitMBB); 1250 1251 // Transfer the remainder of BB and its successor edges to exitMBB. 1252 exitMBB->splice(exitMBB->begin(), BB, 1253 llvm::next(MachineBasicBlock::iterator(MI)), 1254 BB->end()); 1255 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1256 1257 // thisMBB: 1258 // ... 1259 // fallthrough --> loopMBB 1260 BB->addSuccessor(loopMBB); 1261 loopMBB->addSuccessor(loopMBB); 1262 loopMBB->addSuccessor(exitMBB); 1263 1264 // loopMBB: 1265 // ll oldval, 0(ptr) 1266 // <binop> storeval, oldval, incr 1267 // sc success, storeval, 0(ptr) 1268 // beq success, $0, loopMBB 1269 BB = loopMBB; 1270 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1271 if (Nand) { 1272 // and andres, oldval, incr 1273 // nor storeval, $0, andres 1274 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1275 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1276 } else if (BinOpcode) { 1277 // <binop> storeval, oldval, incr 1278 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1279 } else { 1280 StoreVal = Incr; 1281 } 1282 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1283 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1284 1285 MI->eraseFromParent(); // The instruction is gone now. 1286 1287 return exitMBB; 1288} 1289 1290MachineBasicBlock * 1291MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, 1292 MachineBasicBlock *BB, 1293 unsigned Size, unsigned BinOpcode, 1294 bool Nand) const { 1295 assert((Size == 1 || Size == 2) && 1296 "Unsupported size for EmitAtomicBinaryPartial."); 1297 1298 MachineFunction *MF = BB->getParent(); 1299 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1300 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1301 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1302 DebugLoc dl = MI->getDebugLoc(); 1303 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1304 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1305 1306 unsigned Dest = MI->getOperand(0).getReg(); 1307 unsigned Ptr = MI->getOperand(1).getReg(); 1308 unsigned Incr = MI->getOperand(2).getReg(); 1309 1310 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1311 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1312 unsigned Mask = RegInfo.createVirtualRegister(RC); 1313 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1314 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1315 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1316 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1317 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1318 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1319 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1320 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1321 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1322 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1323 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1324 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1325 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1326 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1327 unsigned Success = RegInfo.createVirtualRegister(RC); 1328 1329 // insert new blocks after the current block 1330 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1331 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1332 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1333 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1334 MachineFunction::iterator It = BB; 1335 ++It; 1336 MF->insert(It, loopMBB); 1337 MF->insert(It, sinkMBB); 1338 MF->insert(It, exitMBB); 1339 1340 // Transfer the remainder of BB and its successor edges to exitMBB. 1341 exitMBB->splice(exitMBB->begin(), BB, 1342 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1343 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1344 1345 BB->addSuccessor(loopMBB); 1346 loopMBB->addSuccessor(loopMBB); 1347 loopMBB->addSuccessor(sinkMBB); 1348 sinkMBB->addSuccessor(exitMBB); 1349 1350 // thisMBB: 1351 // addiu masklsb2,$0,-4 # 0xfffffffc 1352 // and alignedaddr,ptr,masklsb2 1353 // andi ptrlsb2,ptr,3 1354 // sll shiftamt,ptrlsb2,3 1355 // ori maskupper,$0,255 # 0xff 1356 // sll mask,maskupper,shiftamt 1357 // nor mask2,$0,mask 1358 // sll incr2,incr,shiftamt 1359 1360 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1361 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1362 .addReg(Mips::ZERO).addImm(-4); 1363 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1364 .addReg(Ptr).addReg(MaskLSB2); 1365 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1366 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1367 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1368 .addReg(Mips::ZERO).addImm(MaskImm); 1369 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1370 .addReg(ShiftAmt).addReg(MaskUpper); 1371 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1372 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); 1373 1374 // atomic.load.binop 1375 // loopMBB: 1376 // ll oldval,0(alignedaddr) 1377 // binop binopres,oldval,incr2 1378 // and newval,binopres,mask 1379 // and maskedoldval0,oldval,mask2 1380 // or storeval,maskedoldval0,newval 1381 // sc success,storeval,0(alignedaddr) 1382 // beq success,$0,loopMBB 1383 1384 // atomic.swap 1385 // loopMBB: 1386 // ll oldval,0(alignedaddr) 1387 // and newval,incr2,mask 1388 // and maskedoldval0,oldval,mask2 1389 // or storeval,maskedoldval0,newval 1390 // sc success,storeval,0(alignedaddr) 1391 // beq success,$0,loopMBB 1392 1393 BB = loopMBB; 1394 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1395 if (Nand) { 1396 // and andres, oldval, incr2 1397 // nor binopres, $0, andres 1398 // and newval, binopres, mask 1399 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1400 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes) 1401 .addReg(Mips::ZERO).addReg(AndRes); 1402 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1403 } else if (BinOpcode) { 1404 // <binop> binopres, oldval, incr2 1405 // and newval, binopres, mask 1406 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1407 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1408 } else {// atomic.swap 1409 // and newval, incr2, mask 1410 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1411 } 1412 1413 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1414 .addReg(OldVal).addReg(Mask2); 1415 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1416 .addReg(MaskedOldVal0).addReg(NewVal); 1417 BuildMI(BB, dl, TII->get(SC), Success) 1418 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1419 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1420 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1421 1422 // sinkMBB: 1423 // and maskedoldval1,oldval,mask 1424 // srl srlres,maskedoldval1,shiftamt 1425 // sll sllres,srlres,24 1426 // sra dest,sllres,24 1427 BB = sinkMBB; 1428 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1429 1430 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1431 .addReg(OldVal).addReg(Mask); 1432 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1433 .addReg(ShiftAmt).addReg(MaskedOldVal1); 1434 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1435 .addReg(SrlRes).addImm(ShiftImm); 1436 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1437 .addReg(SllRes).addImm(ShiftImm); 1438 1439 MI->eraseFromParent(); // The instruction is gone now. 1440 1441 return exitMBB; 1442} 1443 1444MachineBasicBlock * 1445MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 1446 MachineBasicBlock *BB, 1447 unsigned Size) const { 1448 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1449 1450 MachineFunction *MF = BB->getParent(); 1451 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1452 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1453 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1454 DebugLoc dl = MI->getDebugLoc(); 1455 unsigned LL, SC, ZERO, BNE, BEQ; 1456 1457 if (Size == 4) { 1458 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1459 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1460 ZERO = Mips::ZERO; 1461 BNE = Mips::BNE; 1462 BEQ = Mips::BEQ; 1463 } 1464 else { 1465 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 1466 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 1467 ZERO = Mips::ZERO_64; 1468 BNE = Mips::BNE64; 1469 BEQ = Mips::BEQ64; 1470 } 1471 1472 unsigned Dest = MI->getOperand(0).getReg(); 1473 unsigned Ptr = MI->getOperand(1).getReg(); 1474 unsigned OldVal = MI->getOperand(2).getReg(); 1475 unsigned NewVal = MI->getOperand(3).getReg(); 1476 1477 unsigned Success = RegInfo.createVirtualRegister(RC); 1478 1479 // insert new blocks after the current block 1480 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1481 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1482 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1483 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1484 MachineFunction::iterator It = BB; 1485 ++It; 1486 MF->insert(It, loop1MBB); 1487 MF->insert(It, loop2MBB); 1488 MF->insert(It, exitMBB); 1489 1490 // Transfer the remainder of BB and its successor edges to exitMBB. 1491 exitMBB->splice(exitMBB->begin(), BB, 1492 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1493 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1494 1495 // thisMBB: 1496 // ... 1497 // fallthrough --> loop1MBB 1498 BB->addSuccessor(loop1MBB); 1499 loop1MBB->addSuccessor(exitMBB); 1500 loop1MBB->addSuccessor(loop2MBB); 1501 loop2MBB->addSuccessor(loop1MBB); 1502 loop2MBB->addSuccessor(exitMBB); 1503 1504 // loop1MBB: 1505 // ll dest, 0(ptr) 1506 // bne dest, oldval, exitMBB 1507 BB = loop1MBB; 1508 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1509 BuildMI(BB, dl, TII->get(BNE)) 1510 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1511 1512 // loop2MBB: 1513 // sc success, newval, 0(ptr) 1514 // beq success, $0, loop1MBB 1515 BB = loop2MBB; 1516 BuildMI(BB, dl, TII->get(SC), Success) 1517 .addReg(NewVal).addReg(Ptr).addImm(0); 1518 BuildMI(BB, dl, TII->get(BEQ)) 1519 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1520 1521 MI->eraseFromParent(); // The instruction is gone now. 1522 1523 return exitMBB; 1524} 1525 1526MachineBasicBlock * 1527MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, 1528 MachineBasicBlock *BB, 1529 unsigned Size) const { 1530 assert((Size == 1 || Size == 2) && 1531 "Unsupported size for EmitAtomicCmpSwapPartial."); 1532 1533 MachineFunction *MF = BB->getParent(); 1534 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1535 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1536 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1537 DebugLoc dl = MI->getDebugLoc(); 1538 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1539 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1540 1541 unsigned Dest = MI->getOperand(0).getReg(); 1542 unsigned Ptr = MI->getOperand(1).getReg(); 1543 unsigned CmpVal = MI->getOperand(2).getReg(); 1544 unsigned NewVal = MI->getOperand(3).getReg(); 1545 1546 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1547 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1548 unsigned Mask = RegInfo.createVirtualRegister(RC); 1549 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1550 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1551 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1552 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1553 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1554 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1555 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1556 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1557 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1558 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1559 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1560 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1561 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1562 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1563 unsigned Success = RegInfo.createVirtualRegister(RC); 1564 1565 // insert new blocks after the current block 1566 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1567 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1568 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1569 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1570 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1571 MachineFunction::iterator It = BB; 1572 ++It; 1573 MF->insert(It, loop1MBB); 1574 MF->insert(It, loop2MBB); 1575 MF->insert(It, sinkMBB); 1576 MF->insert(It, exitMBB); 1577 1578 // Transfer the remainder of BB and its successor edges to exitMBB. 1579 exitMBB->splice(exitMBB->begin(), BB, 1580 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1581 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1582 1583 BB->addSuccessor(loop1MBB); 1584 loop1MBB->addSuccessor(sinkMBB); 1585 loop1MBB->addSuccessor(loop2MBB); 1586 loop2MBB->addSuccessor(loop1MBB); 1587 loop2MBB->addSuccessor(sinkMBB); 1588 sinkMBB->addSuccessor(exitMBB); 1589 1590 // FIXME: computation of newval2 can be moved to loop2MBB. 1591 // thisMBB: 1592 // addiu masklsb2,$0,-4 # 0xfffffffc 1593 // and alignedaddr,ptr,masklsb2 1594 // andi ptrlsb2,ptr,3 1595 // sll shiftamt,ptrlsb2,3 1596 // ori maskupper,$0,255 # 0xff 1597 // sll mask,maskupper,shiftamt 1598 // nor mask2,$0,mask 1599 // andi maskedcmpval,cmpval,255 1600 // sll shiftedcmpval,maskedcmpval,shiftamt 1601 // andi maskednewval,newval,255 1602 // sll shiftednewval,maskednewval,shiftamt 1603 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1604 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1605 .addReg(Mips::ZERO).addImm(-4); 1606 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1607 .addReg(Ptr).addReg(MaskLSB2); 1608 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1609 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1610 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1611 .addReg(Mips::ZERO).addImm(MaskImm); 1612 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1613 .addReg(ShiftAmt).addReg(MaskUpper); 1614 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1615 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) 1616 .addReg(CmpVal).addImm(MaskImm); 1617 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) 1618 .addReg(ShiftAmt).addReg(MaskedCmpVal); 1619 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) 1620 .addReg(NewVal).addImm(MaskImm); 1621 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) 1622 .addReg(ShiftAmt).addReg(MaskedNewVal); 1623 1624 // loop1MBB: 1625 // ll oldval,0(alginedaddr) 1626 // and maskedoldval0,oldval,mask 1627 // bne maskedoldval0,shiftedcmpval,sinkMBB 1628 BB = loop1MBB; 1629 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1630 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1631 .addReg(OldVal).addReg(Mask); 1632 BuildMI(BB, dl, TII->get(Mips::BNE)) 1633 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1634 1635 // loop2MBB: 1636 // and maskedoldval1,oldval,mask2 1637 // or storeval,maskedoldval1,shiftednewval 1638 // sc success,storeval,0(alignedaddr) 1639 // beq success,$0,loop1MBB 1640 BB = loop2MBB; 1641 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1642 .addReg(OldVal).addReg(Mask2); 1643 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1644 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1645 BuildMI(BB, dl, TII->get(SC), Success) 1646 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1647 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1648 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1649 1650 // sinkMBB: 1651 // srl srlres,maskedoldval0,shiftamt 1652 // sll sllres,srlres,24 1653 // sra dest,sllres,24 1654 BB = sinkMBB; 1655 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1656 1657 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1658 .addReg(ShiftAmt).addReg(MaskedOldVal0); 1659 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1660 .addReg(SrlRes).addImm(ShiftImm); 1661 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1662 .addReg(SllRes).addImm(ShiftImm); 1663 1664 MI->eraseFromParent(); // The instruction is gone now. 1665 1666 return exitMBB; 1667} 1668 1669//===----------------------------------------------------------------------===// 1670// Misc Lower Operation implementation 1671//===----------------------------------------------------------------------===// 1672SDValue MipsTargetLowering:: 1673LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1674{ 1675 // The first operand is the chain, the second is the condition, the third is 1676 // the block to branch to if the condition is true. 1677 SDValue Chain = Op.getOperand(0); 1678 SDValue Dest = Op.getOperand(2); 1679 DebugLoc dl = Op.getDebugLoc(); 1680 1681 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 1682 1683 // Return if flag is not set by a floating point comparison. 1684 if (CondRes.getOpcode() != MipsISD::FPCmp) 1685 return Op; 1686 1687 SDValue CCNode = CondRes.getOperand(2); 1688 Mips::CondCode CC = 1689 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1690 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 1691 1692 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 1693 Dest, CondRes); 1694} 1695 1696SDValue MipsTargetLowering:: 1697LowerSELECT(SDValue Op, SelectionDAG &DAG) const 1698{ 1699 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 1700 1701 // Return if flag is not set by a floating point comparison. 1702 if (Cond.getOpcode() != MipsISD::FPCmp) 1703 return Op; 1704 1705 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1706 Op.getDebugLoc()); 1707} 1708 1709SDValue MipsTargetLowering:: 1710LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 1711{ 1712 DebugLoc DL = Op.getDebugLoc(); 1713 EVT Ty = Op.getOperand(0).getValueType(); 1714 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty), 1715 Op.getOperand(0), Op.getOperand(1), 1716 Op.getOperand(4)); 1717 1718 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2), 1719 Op.getOperand(3)); 1720} 1721 1722SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1723 SDValue Cond = CreateFPCmp(DAG, Op); 1724 1725 assert(Cond.getOpcode() == MipsISD::FPCmp && 1726 "Floating point operand expected."); 1727 1728 SDValue True = DAG.getConstant(1, MVT::i32); 1729 SDValue False = DAG.getConstant(0, MVT::i32); 1730 1731 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc()); 1732} 1733 1734SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 1735 SelectionDAG &DAG) const { 1736 // FIXME there isn't actually debug info here 1737 DebugLoc dl = Op.getDebugLoc(); 1738 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1739 1740 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1741 SDVTList VTs = DAG.getVTList(MVT::i32); 1742 1743 const MipsTargetObjectFile &TLOF = 1744 (const MipsTargetObjectFile&)getObjFileLowering(); 1745 1746 // %gp_rel relocation 1747 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1748 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1749 MipsII::MO_GPREL); 1750 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1); 1751 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32); 1752 return DAG.getNode(ISD::ADD, dl, MVT::i32, GPReg, GPRelNode); 1753 } 1754 // %hi/%lo relocation 1755 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1756 MipsII::MO_ABS_HI); 1757 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1758 MipsII::MO_ABS_LO); 1759 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1); 1760 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 1761 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1762 } 1763 1764 EVT ValTy = Op.getValueType(); 1765 bool HasGotOfst = (GV->hasInternalLinkage() || 1766 (GV->hasLocalLinkage() && !isa<Function>(GV))); 1767 unsigned GotFlag = HasMips64 ? 1768 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) : 1769 (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16); 1770 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag); 1771 GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), GA); 1772 SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA, 1773 MachinePointerInfo(), false, false, false, 0); 1774 // On functions and global targets not internal linked only 1775 // a load from got/GP is necessary for PIC to work. 1776 if (!HasGotOfst) 1777 return ResNode; 1778 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, 1779 HasMips64 ? MipsII::MO_GOT_OFST : 1780 MipsII::MO_ABS_LO); 1781 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo); 1782 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo); 1783} 1784 1785SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 1786 SelectionDAG &DAG) const { 1787 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1788 // FIXME there isn't actually debug info here 1789 DebugLoc dl = Op.getDebugLoc(); 1790 1791 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1792 // %hi/%lo relocation 1793 SDValue BAHi = 1794 DAG.getTargetBlockAddress(BA, MVT::i32, 0, MipsII::MO_ABS_HI); 1795 SDValue BALo = 1796 DAG.getTargetBlockAddress(BA, MVT::i32, 0, MipsII::MO_ABS_LO); 1797 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi); 1798 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo); 1799 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1800 } 1801 1802 EVT ValTy = Op.getValueType(); 1803 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1804 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1805 SDValue BAGOTOffset = DAG.getTargetBlockAddress(BA, ValTy, 0, GOTFlag); 1806 BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy, 1807 GetGlobalReg(DAG, ValTy), BAGOTOffset); 1808 SDValue BALOOffset = DAG.getTargetBlockAddress(BA, ValTy, 0, OFSTFlag); 1809 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset, 1810 MachinePointerInfo(), false, false, false, 0); 1811 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset); 1812 return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo); 1813} 1814 1815SDValue MipsTargetLowering:: 1816LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1817{ 1818 // If the relocation model is PIC, use the General Dynamic TLS Model or 1819 // Local Dynamic TLS model, otherwise use the Initial Exec or 1820 // Local Exec TLS Model. 1821 1822 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1823 DebugLoc dl = GA->getDebugLoc(); 1824 const GlobalValue *GV = GA->getGlobal(); 1825 EVT PtrVT = getPointerTy(); 1826 1827 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1828 1829 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1830 // General Dynamic and Local Dynamic TLS Model. 1831 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1832 : MipsII::MO_TLSGD; 1833 1834 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag); 1835 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, 1836 GetGlobalReg(DAG, PtrVT), TGA); 1837 unsigned PtrSize = PtrVT.getSizeInBits(); 1838 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1839 1840 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1841 1842 ArgListTy Args; 1843 ArgListEntry Entry; 1844 Entry.Node = Argument; 1845 Entry.Ty = PtrTy; 1846 Args.push_back(Entry); 1847 1848 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy, 1849 false, false, false, false, 0, CallingConv::C, 1850 /*isTailCall=*/false, /*doesNotRet=*/false, 1851 /*isReturnValueUsed=*/true, 1852 TlsGetAddr, Args, DAG, dl); 1853 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1854 1855 SDValue Ret = CallResult.first; 1856 1857 if (model != TLSModel::LocalDynamic) 1858 return Ret; 1859 1860 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1861 MipsII::MO_DTPREL_HI); 1862 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 1863 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1864 MipsII::MO_DTPREL_LO); 1865 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 1866 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret); 1867 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo); 1868 } 1869 1870 SDValue Offset; 1871 if (model == TLSModel::InitialExec) { 1872 // Initial Exec TLS Model 1873 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1874 MipsII::MO_GOTTPREL); 1875 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT), 1876 TGA); 1877 Offset = DAG.getLoad(PtrVT, dl, 1878 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1879 false, false, false, 0); 1880 } else { 1881 // Local Exec TLS Model 1882 assert(model == TLSModel::LocalExec); 1883 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1884 MipsII::MO_TPREL_HI); 1885 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1886 MipsII::MO_TPREL_LO); 1887 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 1888 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 1889 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1890 } 1891 1892 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT); 1893 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1894} 1895 1896SDValue MipsTargetLowering:: 1897LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1898{ 1899 SDValue HiPart, JTI, JTILo; 1900 // FIXME there isn't actually debug info here 1901 DebugLoc dl = Op.getDebugLoc(); 1902 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1903 EVT PtrVT = Op.getValueType(); 1904 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1905 1906 if (!IsPIC && !IsN64) { 1907 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_HI); 1908 HiPart = DAG.getNode(MipsISD::Hi, dl, PtrVT, JTI); 1909 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO); 1910 } else {// Emit Load from Global Pointer 1911 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1912 unsigned OfstFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1913 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, GOTFlag); 1914 JTI = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT), 1915 JTI); 1916 HiPart = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), JTI, 1917 MachinePointerInfo(), false, false, false, 0); 1918 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OfstFlag); 1919 } 1920 1921 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo); 1922 return DAG.getNode(ISD::ADD, dl, PtrVT, HiPart, Lo); 1923} 1924 1925SDValue MipsTargetLowering:: 1926LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1927{ 1928 SDValue ResNode; 1929 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1930 const Constant *C = N->getConstVal(); 1931 // FIXME there isn't actually debug info here 1932 DebugLoc dl = Op.getDebugLoc(); 1933 1934 // gp_rel relocation 1935 // FIXME: we should reference the constant pool using small data sections, 1936 // but the asm printer currently doesn't support this feature without 1937 // hacking it. This feature should come soon so we can uncomment the 1938 // stuff below. 1939 //if (IsInSmallSection(C->getType())) { 1940 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1941 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1942 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1943 1944 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1945 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1946 N->getOffset(), MipsII::MO_ABS_HI); 1947 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1948 N->getOffset(), MipsII::MO_ABS_LO); 1949 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi); 1950 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1951 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1952 } else { 1953 EVT ValTy = Op.getValueType(); 1954 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1955 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1956 SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(), 1957 N->getOffset(), GOTFlag); 1958 CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), CP); 1959 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP, 1960 MachinePointerInfo::getConstantPool(), false, 1961 false, false, 0); 1962 SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(), 1963 N->getOffset(), OFSTFlag); 1964 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo); 1965 ResNode = DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo); 1966 } 1967 1968 return ResNode; 1969} 1970 1971SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1972 MachineFunction &MF = DAG.getMachineFunction(); 1973 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1974 1975 DebugLoc dl = Op.getDebugLoc(); 1976 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1977 getPointerTy()); 1978 1979 // vastart just stores the address of the VarArgsFrameIndex slot into the 1980 // memory location argument. 1981 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1982 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 1983 MachinePointerInfo(SV), false, false, 0); 1984} 1985 1986static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1987 EVT TyX = Op.getOperand(0).getValueType(); 1988 EVT TyY = Op.getOperand(1).getValueType(); 1989 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1990 SDValue Const31 = DAG.getConstant(31, MVT::i32); 1991 DebugLoc DL = Op.getDebugLoc(); 1992 SDValue Res; 1993 1994 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1995 // to i32. 1996 SDValue X = (TyX == MVT::f32) ? 1997 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1998 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1999 Const1); 2000 SDValue Y = (TyY == MVT::f32) ? 2001 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 2002 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 2003 Const1); 2004 2005 if (HasR2) { 2006 // ext E, Y, 31, 1 ; extract bit31 of Y 2007 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2008 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2009 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2010 } else { 2011 // sll SllX, X, 1 2012 // srl SrlX, SllX, 1 2013 // srl SrlY, Y, 31 2014 // sll SllY, SrlX, 31 2015 // or Or, SrlX, SllY 2016 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2017 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2018 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2019 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2020 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2021 } 2022 2023 if (TyX == MVT::f32) 2024 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2025 2026 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2027 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 2028 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2029} 2030 2031static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 2032 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2033 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2034 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2035 SDValue Const1 = DAG.getConstant(1, MVT::i32); 2036 DebugLoc DL = Op.getDebugLoc(); 2037 2038 // Bitcast to integer nodes. 2039 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2040 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2041 2042 if (HasR2) { 2043 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2044 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2045 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2046 DAG.getConstant(WidthY - 1, MVT::i32), Const1); 2047 2048 if (WidthX > WidthY) 2049 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2050 else if (WidthY > WidthX) 2051 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2052 2053 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2054 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X); 2055 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2056 } 2057 2058 // (d)sll SllX, X, 1 2059 // (d)srl SrlX, SllX, 1 2060 // (d)srl SrlY, Y, width(Y)-1 2061 // (d)sll SllY, SrlX, width(Y)-1 2062 // or Or, SrlX, SllY 2063 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2064 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2065 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2066 DAG.getConstant(WidthY - 1, MVT::i32)); 2067 2068 if (WidthX > WidthY) 2069 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2070 else if (WidthY > WidthX) 2071 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2072 2073 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2074 DAG.getConstant(WidthX - 1, MVT::i32)); 2075 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2076 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2077} 2078 2079SDValue 2080MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2081 if (Subtarget->hasMips64()) 2082 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2()); 2083 2084 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2()); 2085} 2086 2087static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 2088 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 2089 DebugLoc DL = Op.getDebugLoc(); 2090 2091 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2092 // to i32. 2093 SDValue X = (Op.getValueType() == MVT::f32) ? 2094 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2095 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2096 Const1); 2097 2098 // Clear MSB. 2099 if (HasR2) 2100 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 2101 DAG.getRegister(Mips::ZERO, MVT::i32), 2102 DAG.getConstant(31, MVT::i32), Const1, X); 2103 else { 2104 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2105 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2106 } 2107 2108 if (Op.getValueType() == MVT::f32) 2109 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 2110 2111 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2112 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 2113 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2114} 2115 2116static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 2117 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 2118 DebugLoc DL = Op.getDebugLoc(); 2119 2120 // Bitcast to integer node. 2121 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 2122 2123 // Clear MSB. 2124 if (HasR2) 2125 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 2126 DAG.getRegister(Mips::ZERO_64, MVT::i64), 2127 DAG.getConstant(63, MVT::i32), Const1, X); 2128 else { 2129 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 2130 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 2131 } 2132 2133 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 2134} 2135 2136SDValue 2137MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const { 2138 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64)) 2139 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2()); 2140 2141 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2()); 2142} 2143 2144SDValue MipsTargetLowering:: 2145LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2146 // check the depth 2147 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2148 "Frame address can only be determined for current frame."); 2149 2150 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2151 MFI->setFrameAddressIsTaken(true); 2152 EVT VT = Op.getValueType(); 2153 DebugLoc dl = Op.getDebugLoc(); 2154 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 2155 IsN64 ? Mips::FP_64 : Mips::FP, VT); 2156 return FrameAddr; 2157} 2158 2159SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op, 2160 SelectionDAG &DAG) const { 2161 // check the depth 2162 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2163 "Return address can be determined only for current frame."); 2164 2165 MachineFunction &MF = DAG.getMachineFunction(); 2166 MachineFrameInfo *MFI = MF.getFrameInfo(); 2167 EVT VT = Op.getValueType(); 2168 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA; 2169 MFI->setReturnAddressIsTaken(true); 2170 2171 // Return RA, which contains the return address. Mark it an implicit live-in. 2172 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2173 return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT); 2174} 2175 2176// TODO: set SType according to the desired memory barrier behavior. 2177SDValue 2178MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const { 2179 unsigned SType = 0; 2180 DebugLoc dl = Op.getDebugLoc(); 2181 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 2182 DAG.getConstant(SType, MVT::i32)); 2183} 2184 2185SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op, 2186 SelectionDAG &DAG) const { 2187 // FIXME: Need pseudo-fence for 'singlethread' fences 2188 // FIXME: Set SType for weaker fences where supported/appropriate. 2189 unsigned SType = 0; 2190 DebugLoc dl = Op.getDebugLoc(); 2191 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 2192 DAG.getConstant(SType, MVT::i32)); 2193} 2194 2195SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op, 2196 SelectionDAG &DAG) const { 2197 DebugLoc DL = Op.getDebugLoc(); 2198 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2199 SDValue Shamt = Op.getOperand(2); 2200 2201 // if shamt < 32: 2202 // lo = (shl lo, shamt) 2203 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2204 // else: 2205 // lo = 0 2206 // hi = (shl lo, shamt[4:0]) 2207 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2208 DAG.getConstant(-1, MVT::i32)); 2209 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, 2210 DAG.getConstant(1, MVT::i32)); 2211 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, 2212 Not); 2213 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); 2214 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 2215 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); 2216 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2217 DAG.getConstant(0x20, MVT::i32)); 2218 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 2219 DAG.getConstant(0, MVT::i32), ShiftLeftLo); 2220 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or); 2221 2222 SDValue Ops[2] = {Lo, Hi}; 2223 return DAG.getMergeValues(Ops, 2, DL); 2224} 2225 2226SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2227 bool IsSRA) const { 2228 DebugLoc DL = Op.getDebugLoc(); 2229 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2230 SDValue Shamt = Op.getOperand(2); 2231 2232 // if shamt < 32: 2233 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2234 // if isSRA: 2235 // hi = (sra hi, shamt) 2236 // else: 2237 // hi = (srl hi, shamt) 2238 // else: 2239 // if isSRA: 2240 // lo = (sra hi, shamt[4:0]) 2241 // hi = (sra hi, 31) 2242 // else: 2243 // lo = (srl hi, shamt[4:0]) 2244 // hi = 0 2245 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2246 DAG.getConstant(-1, MVT::i32)); 2247 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, 2248 DAG.getConstant(1, MVT::i32)); 2249 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not); 2250 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); 2251 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 2252 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, 2253 Hi, Shamt); 2254 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2255 DAG.getConstant(0x20, MVT::i32)); 2256 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi, 2257 DAG.getConstant(31, MVT::i32)); 2258 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or); 2259 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 2260 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32), 2261 ShiftRightHi); 2262 2263 SDValue Ops[2] = {Lo, Hi}; 2264 return DAG.getMergeValues(Ops, 2, DL); 2265} 2266 2267static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2268 SDValue Chain, SDValue Src, unsigned Offset) { 2269 SDValue Ptr = LD->getBasePtr(); 2270 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2271 EVT BasePtrVT = Ptr.getValueType(); 2272 DebugLoc DL = LD->getDebugLoc(); 2273 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2274 2275 if (Offset) 2276 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2277 DAG.getConstant(Offset, BasePtrVT)); 2278 2279 SDValue Ops[] = { Chain, Ptr, Src }; 2280 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2281 LD->getMemOperand()); 2282} 2283 2284// Expand an unaligned 32 or 64-bit integer load node. 2285SDValue MipsTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2286 LoadSDNode *LD = cast<LoadSDNode>(Op); 2287 EVT MemVT = LD->getMemoryVT(); 2288 2289 // Return if load is aligned or if MemVT is neither i32 nor i64. 2290 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2291 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2292 return SDValue(); 2293 2294 bool IsLittle = Subtarget->isLittle(); 2295 EVT VT = Op.getValueType(); 2296 ISD::LoadExtType ExtType = LD->getExtensionType(); 2297 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2298 2299 assert((VT == MVT::i32) || (VT == MVT::i64)); 2300 2301 // Expand 2302 // (set dst, (i64 (load baseptr))) 2303 // to 2304 // (set tmp, (ldl (add baseptr, 7), undef)) 2305 // (set dst, (ldr baseptr, tmp)) 2306 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2307 SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2308 IsLittle ? 7 : 0); 2309 return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2310 IsLittle ? 0 : 7); 2311 } 2312 2313 SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2314 IsLittle ? 3 : 0); 2315 SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2316 IsLittle ? 0 : 3); 2317 2318 // Expand 2319 // (set dst, (i32 (load baseptr))) or 2320 // (set dst, (i64 (sextload baseptr))) or 2321 // (set dst, (i64 (extload baseptr))) 2322 // to 2323 // (set tmp, (lwl (add baseptr, 3), undef)) 2324 // (set dst, (lwr baseptr, tmp)) 2325 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2326 (ExtType == ISD::EXTLOAD)) 2327 return LWR; 2328 2329 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2330 2331 // Expand 2332 // (set dst, (i64 (zextload baseptr))) 2333 // to 2334 // (set tmp0, (lwl (add baseptr, 3), undef)) 2335 // (set tmp1, (lwr baseptr, tmp0)) 2336 // (set tmp2, (shl tmp1, 32)) 2337 // (set dst, (srl tmp2, 32)) 2338 DebugLoc DL = LD->getDebugLoc(); 2339 SDValue Const32 = DAG.getConstant(32, MVT::i32); 2340 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2341 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2342 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2343 return DAG.getMergeValues(Ops, 2, DL); 2344} 2345 2346static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2347 SDValue Chain, unsigned Offset) { 2348 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2349 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2350 DebugLoc DL = SD->getDebugLoc(); 2351 SDVTList VTList = DAG.getVTList(MVT::Other); 2352 2353 if (Offset) 2354 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2355 DAG.getConstant(Offset, BasePtrVT)); 2356 2357 SDValue Ops[] = { Chain, Value, Ptr }; 2358 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2359 SD->getMemOperand()); 2360} 2361 2362// Expand an unaligned 32 or 64-bit integer store node. 2363SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2364 StoreSDNode *SD = cast<StoreSDNode>(Op); 2365 EVT MemVT = SD->getMemoryVT(); 2366 2367 // Return if store is aligned or if MemVT is neither i32 nor i64. 2368 if ((SD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2369 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2370 return SDValue(); 2371 2372 bool IsLittle = Subtarget->isLittle(); 2373 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2374 EVT VT = Value.getValueType(); 2375 2376 // Expand 2377 // (store val, baseptr) or 2378 // (truncstore val, baseptr) 2379 // to 2380 // (swl val, (add baseptr, 3)) 2381 // (swr val, baseptr) 2382 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2383 SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain, 2384 IsLittle ? 3 : 0); 2385 return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2386 } 2387 2388 assert(VT == MVT::i64); 2389 2390 // Expand 2391 // (store val, baseptr) 2392 // to 2393 // (sdl val, (add baseptr, 7)) 2394 // (sdr val, baseptr) 2395 SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2396 return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2397} 2398 2399// This function expands mips intrinsic nodes which have 64-bit input operands 2400// or output values. 2401// 2402// out64 = intrinsic-node in64 2403// => 2404// lo = copy (extract-element (in64, 0)) 2405// hi = copy (extract-element (in64, 1)) 2406// mips-specific-node 2407// v0 = copy lo 2408// v1 = copy hi 2409// out64 = merge-values (v0, v1) 2410// 2411static SDValue LowerDSPIntr(SDValue Op, SelectionDAG &DAG, 2412 unsigned Opc, bool HasI64In, bool HasI64Out) { 2413 DebugLoc DL = Op.getDebugLoc(); 2414 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other; 2415 SDValue Chain = HasChainIn ? Op->getOperand(0) : DAG.getEntryNode(); 2416 SmallVector<SDValue, 3> Ops; 2417 2418 if (HasI64In) { 2419 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, 2420 Op->getOperand(1 + HasChainIn), 2421 DAG.getConstant(0, MVT::i32)); 2422 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, 2423 Op->getOperand(1 + HasChainIn), 2424 DAG.getConstant(1, MVT::i32)); 2425 2426 Chain = DAG.getCopyToReg(Chain, DL, Mips::LO, InLo, SDValue()); 2427 Chain = DAG.getCopyToReg(Chain, DL, Mips::HI, InHi, Chain.getValue(1)); 2428 2429 Ops.push_back(Chain); 2430 Ops.append(Op->op_begin() + HasChainIn + 2, Op->op_end()); 2431 Ops.push_back(Chain.getValue(1)); 2432 } else { 2433 Ops.push_back(Chain); 2434 Ops.append(Op->op_begin() + HasChainIn + 1, Op->op_end()); 2435 } 2436 2437 if (!HasI64Out) 2438 return DAG.getNode(Opc, DL, Op->value_begin(), Op->getNumValues(), 2439 Ops.begin(), Ops.size()); 2440 2441 SDValue Intr = DAG.getNode(Opc, DL, DAG.getVTList(MVT::Other, MVT::Glue), 2442 Ops.begin(), Ops.size()); 2443 SDValue OutLo = DAG.getCopyFromReg(Intr.getValue(0), DL, Mips::LO, MVT::i32, 2444 Intr.getValue(1)); 2445 SDValue OutHi = DAG.getCopyFromReg(OutLo.getValue(1), DL, Mips::HI, MVT::i32, 2446 OutLo.getValue(2)); 2447 SDValue Out = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, OutLo, OutHi); 2448 2449 if (!HasChainIn) 2450 return Out; 2451 2452 SDValue Vals[] = { Out, OutHi.getValue(1) }; 2453 return DAG.getMergeValues(Vals, 2, DL); 2454} 2455 2456SDValue MipsTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 2457 SelectionDAG &DAG) const { 2458 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) { 2459 default: 2460 return SDValue(); 2461 case Intrinsic::mips_shilo: 2462 return LowerDSPIntr(Op, DAG, MipsISD::SHILO, true, true); 2463 case Intrinsic::mips_dpau_h_qbl: 2464 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL, true, true); 2465 case Intrinsic::mips_dpau_h_qbr: 2466 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR, true, true); 2467 case Intrinsic::mips_dpsu_h_qbl: 2468 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL, true, true); 2469 case Intrinsic::mips_dpsu_h_qbr: 2470 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR, true, true); 2471 case Intrinsic::mips_dpa_w_ph: 2472 return LowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH, true, true); 2473 case Intrinsic::mips_dps_w_ph: 2474 return LowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH, true, true); 2475 case Intrinsic::mips_dpax_w_ph: 2476 return LowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH, true, true); 2477 case Intrinsic::mips_dpsx_w_ph: 2478 return LowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH, true, true); 2479 case Intrinsic::mips_mulsa_w_ph: 2480 return LowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH, true, true); 2481 case Intrinsic::mips_mult: 2482 return LowerDSPIntr(Op, DAG, MipsISD::MULT, false, true); 2483 case Intrinsic::mips_multu: 2484 return LowerDSPIntr(Op, DAG, MipsISD::MULTU, false, true); 2485 case Intrinsic::mips_madd: 2486 return LowerDSPIntr(Op, DAG, MipsISD::MADD_DSP, true, true); 2487 case Intrinsic::mips_maddu: 2488 return LowerDSPIntr(Op, DAG, MipsISD::MADDU_DSP, true, true); 2489 case Intrinsic::mips_msub: 2490 return LowerDSPIntr(Op, DAG, MipsISD::MSUB_DSP, true, true); 2491 case Intrinsic::mips_msubu: 2492 return LowerDSPIntr(Op, DAG, MipsISD::MSUBU_DSP, true, true); 2493 } 2494} 2495 2496SDValue MipsTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, 2497 SelectionDAG &DAG) const { 2498 switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) { 2499 default: 2500 return SDValue(); 2501 case Intrinsic::mips_extp: 2502 return LowerDSPIntr(Op, DAG, MipsISD::EXTP, true, false); 2503 case Intrinsic::mips_extpdp: 2504 return LowerDSPIntr(Op, DAG, MipsISD::EXTPDP, true, false); 2505 case Intrinsic::mips_extr_w: 2506 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_W, true, false); 2507 case Intrinsic::mips_extr_r_w: 2508 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W, true, false); 2509 case Intrinsic::mips_extr_rs_w: 2510 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W, true, false); 2511 case Intrinsic::mips_extr_s_h: 2512 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H, true, false); 2513 case Intrinsic::mips_mthlip: 2514 return LowerDSPIntr(Op, DAG, MipsISD::MTHLIP, true, true); 2515 case Intrinsic::mips_mulsaq_s_w_ph: 2516 return LowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH, true, true); 2517 case Intrinsic::mips_maq_s_w_phl: 2518 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL, true, true); 2519 case Intrinsic::mips_maq_s_w_phr: 2520 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR, true, true); 2521 case Intrinsic::mips_maq_sa_w_phl: 2522 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL, true, true); 2523 case Intrinsic::mips_maq_sa_w_phr: 2524 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR, true, true); 2525 case Intrinsic::mips_dpaq_s_w_ph: 2526 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH, true, true); 2527 case Intrinsic::mips_dpsq_s_w_ph: 2528 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH, true, true); 2529 case Intrinsic::mips_dpaq_sa_l_w: 2530 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W, true, true); 2531 case Intrinsic::mips_dpsq_sa_l_w: 2532 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W, true, true); 2533 case Intrinsic::mips_dpaqx_s_w_ph: 2534 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH, true, true); 2535 case Intrinsic::mips_dpaqx_sa_w_ph: 2536 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH, true, true); 2537 case Intrinsic::mips_dpsqx_s_w_ph: 2538 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH, true, true); 2539 case Intrinsic::mips_dpsqx_sa_w_ph: 2540 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH, true, true); 2541 } 2542} 2543 2544//===----------------------------------------------------------------------===// 2545// Calling Convention Implementation 2546//===----------------------------------------------------------------------===// 2547 2548//===----------------------------------------------------------------------===// 2549// TODO: Implement a generic logic using tblgen that can support this. 2550// Mips O32 ABI rules: 2551// --- 2552// i32 - Passed in A0, A1, A2, A3 and stack 2553// f32 - Only passed in f32 registers if no int reg has been used yet to hold 2554// an argument. Otherwise, passed in A1, A2, A3 and stack. 2555// f64 - Only passed in two aliased f32 registers if no int reg has been used 2556// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2557// not used, it must be shadowed. If only A3 is avaiable, shadow it and 2558// go to stack. 2559// 2560// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2561//===----------------------------------------------------------------------===// 2562 2563static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 2564 MVT LocVT, CCValAssign::LocInfo LocInfo, 2565 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2566 2567 static const unsigned IntRegsSize=4, FloatRegsSize=2; 2568 2569 static const uint16_t IntRegs[] = { 2570 Mips::A0, Mips::A1, Mips::A2, Mips::A3 2571 }; 2572 static const uint16_t F32Regs[] = { 2573 Mips::F12, Mips::F14 2574 }; 2575 static const uint16_t F64Regs[] = { 2576 Mips::D6, Mips::D7 2577 }; 2578 2579 // Do not process byval args here. 2580 if (ArgFlags.isByVal()) 2581 return true; 2582 2583 // Promote i8 and i16 2584 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2585 LocVT = MVT::i32; 2586 if (ArgFlags.isSExt()) 2587 LocInfo = CCValAssign::SExt; 2588 else if (ArgFlags.isZExt()) 2589 LocInfo = CCValAssign::ZExt; 2590 else 2591 LocInfo = CCValAssign::AExt; 2592 } 2593 2594 unsigned Reg; 2595 2596 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2597 // is true: function is vararg, argument is 3rd or higher, there is previous 2598 // argument which is not f32 or f64. 2599 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 2600 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 2601 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2602 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2603 2604 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2605 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2606 // If this is the first part of an i64 arg, 2607 // the allocated register must be either A0 or A2. 2608 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2609 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2610 LocVT = MVT::i32; 2611 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2612 // Allocate int register and shadow next int register. If first 2613 // available register is Mips::A1 or Mips::A3, shadow it too. 2614 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2615 if (Reg == Mips::A1 || Reg == Mips::A3) 2616 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2617 State.AllocateReg(IntRegs, IntRegsSize); 2618 LocVT = MVT::i32; 2619 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2620 // we are guaranteed to find an available float register 2621 if (ValVT == MVT::f32) { 2622 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 2623 // Shadow int register 2624 State.AllocateReg(IntRegs, IntRegsSize); 2625 } else { 2626 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 2627 // Shadow int registers 2628 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 2629 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2630 State.AllocateReg(IntRegs, IntRegsSize); 2631 State.AllocateReg(IntRegs, IntRegsSize); 2632 } 2633 } else 2634 llvm_unreachable("Cannot handle this ValVT."); 2635 2636 if (!Reg) { 2637 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2638 OrigAlign); 2639 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2640 } else 2641 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2642 2643 return false; 2644} 2645 2646#include "MipsGenCallingConv.inc" 2647 2648//===----------------------------------------------------------------------===// 2649// Call Calling Convention Implementation 2650//===----------------------------------------------------------------------===// 2651 2652static const unsigned O32IntRegsSize = 4; 2653 2654// Return next O32 integer argument register. 2655static unsigned getNextIntArgReg(unsigned Reg) { 2656 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2657 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2658} 2659 2660/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2661/// for tail call optimization. 2662bool MipsTargetLowering:: 2663IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, bool IsVarArg, 2664 unsigned NextStackOffset) const { 2665 if (!EnableMipsTailCalls) 2666 return false; 2667 2668 // No tail call optimization for mips16. 2669 if (Subtarget->inMips16Mode()) 2670 return false; 2671 2672 if (MipsCCInfo.hasByValArg() || IsVarArg) 2673 return false; 2674 2675 // Return true if no arguments are passed on stack. 2676 return MipsCCInfo.reservedArgArea() == NextStackOffset; 2677} 2678 2679SDValue 2680MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2681 SDValue Chain, SDValue Arg, DebugLoc DL, 2682 bool IsTailCall, SelectionDAG &DAG) const { 2683 if (!IsTailCall) { 2684 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, 2685 DAG.getIntPtrConstant(Offset)); 2686 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false, 2687 false, 0); 2688 } 2689 2690 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2691 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2692 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2693 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2694 /*isVolatile=*/ true, false, 0); 2695} 2696 2697/// LowerCall - functions arguments are copied from virtual regs to 2698/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2699SDValue 2700MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2701 SmallVectorImpl<SDValue> &InVals) const { 2702 SelectionDAG &DAG = CLI.DAG; 2703 DebugLoc &dl = CLI.DL; 2704 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 2705 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 2706 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 2707 SDValue Chain = CLI.Chain; 2708 SDValue Callee = CLI.Callee; 2709 bool &isTailCall = CLI.IsTailCall; 2710 CallingConv::ID CallConv = CLI.CallConv; 2711 bool isVarArg = CLI.IsVarArg; 2712 2713 MachineFunction &MF = DAG.getMachineFunction(); 2714 MachineFrameInfo *MFI = MF.getFrameInfo(); 2715 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 2716 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2717 2718 // Analyze operands of the call, assigning locations to each operand. 2719 SmallVector<CCValAssign, 16> ArgLocs; 2720 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2721 getTargetMachine(), ArgLocs, *DAG.getContext()); 2722 MipsCC MipsCCInfo(CallConv, isVarArg, IsO32, CCInfo); 2723 2724 MipsCCInfo.analyzeCallOperands(Outs); 2725 2726 // Get a count of how many bytes are to be pushed on the stack. 2727 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2728 unsigned StackAlignment = TFL->getStackAlignment(); 2729 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment); 2730 2731 // Check if it's really possible to do a tail call. 2732 if (isTailCall) 2733 isTailCall = IsEligibleForTailCallOptimization(MipsCCInfo, isVarArg, 2734 NextStackOffset); 2735 2736 if (isTailCall) 2737 ++NumTailCalls; 2738 2739 // Chain is the output chain of the last Load/Store or CopyToReg node. 2740 // ByValChain is the output chain of the last Memcpy node created for copying 2741 // byval arguments to the stack. 2742 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 2743 2744 if (!isTailCall) 2745 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal); 2746 2747 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, 2748 IsN64 ? Mips::SP_64 : Mips::SP, 2749 getPointerTy()); 2750 2751 // With EABI is it possible to have 16 args on registers. 2752 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 2753 SmallVector<SDValue, 8> MemOpChains; 2754 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 2755 2756 // Walk the register/memloc assignments, inserting copies/loads. 2757 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2758 SDValue Arg = OutVals[i]; 2759 CCValAssign &VA = ArgLocs[i]; 2760 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2761 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2762 2763 // ByVal Arg. 2764 if (Flags.isByVal()) { 2765 assert(Flags.getByValSize() && 2766 "ByVal args of size 0 should have been ignored by front-end."); 2767 assert(ByValArg != MipsCCInfo.byval_end()); 2768 passByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2769 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle()); 2770 ++ByValArg; 2771 continue; 2772 } 2773 2774 // Promote the value if needed. 2775 switch (VA.getLocInfo()) { 2776 default: llvm_unreachable("Unknown loc info!"); 2777 case CCValAssign::Full: 2778 if (VA.isRegLoc()) { 2779 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2780 (ValVT == MVT::f64 && LocVT == MVT::i64)) 2781 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg); 2782 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2783 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2784 Arg, DAG.getConstant(0, MVT::i32)); 2785 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2786 Arg, DAG.getConstant(1, MVT::i32)); 2787 if (!Subtarget->isLittle()) 2788 std::swap(Lo, Hi); 2789 unsigned LocRegLo = VA.getLocReg(); 2790 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2791 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2792 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2793 continue; 2794 } 2795 } 2796 break; 2797 case CCValAssign::SExt: 2798 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg); 2799 break; 2800 case CCValAssign::ZExt: 2801 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg); 2802 break; 2803 case CCValAssign::AExt: 2804 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg); 2805 break; 2806 } 2807 2808 // Arguments that can be passed on register must be kept at 2809 // RegsToPass vector 2810 if (VA.isRegLoc()) { 2811 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2812 continue; 2813 } 2814 2815 // Register can't get to this point... 2816 assert(VA.isMemLoc()); 2817 2818 // emit ISD::STORE whichs stores the 2819 // parameter value to a stack Location 2820 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, 2821 DAG.getIntPtrConstant(VA.getLocMemOffset())); 2822 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2823 MachinePointerInfo(), false, false, 0)); 2824 } 2825 2826 // Transform all store nodes into one single node because all store 2827 // nodes are independent of each other. 2828 if (!MemOpChains.empty()) 2829 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2830 &MemOpChains[0], MemOpChains.size()); 2831 2832 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2833 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2834 // node so that legalize doesn't hack it. 2835 unsigned char OpFlag; 2836 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25 2837 bool GlobalOrExternal = false; 2838 SDValue CalleeLo; 2839 2840 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2841 if (IsPICCall && G->getGlobal()->hasInternalLinkage()) { 2842 OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE; 2843 unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST; 2844 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0, 2845 OpFlag); 2846 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 2847 0, LoFlag); 2848 } else { 2849 OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG; 2850 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2851 getPointerTy(), 0, OpFlag); 2852 } 2853 2854 GlobalOrExternal = true; 2855 } 2856 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2857 if (IsN64 || (!IsO32 && IsPIC)) 2858 OpFlag = MipsII::MO_GOT_DISP; 2859 else if (!IsPIC) // !N64 && static 2860 OpFlag = MipsII::MO_NO_FLAG; 2861 else // O32 & PIC 2862 OpFlag = MipsII::MO_GOT_CALL; 2863 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2864 OpFlag); 2865 GlobalOrExternal = true; 2866 } 2867 2868 SDValue InFlag; 2869 2870 // Create nodes that load address of callee and copy it to T9 2871 if (IsPICCall) { 2872 if (GlobalOrExternal) { 2873 // Load callee address 2874 Callee = DAG.getNode(MipsISD::Wrapper, dl, getPointerTy(), 2875 GetGlobalReg(DAG, getPointerTy()), Callee); 2876 SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 2877 Callee, MachinePointerInfo::getGOT(), 2878 false, false, false, 0); 2879 2880 // Use GOT+LO if callee has internal linkage. 2881 if (CalleeLo.getNode()) { 2882 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo); 2883 Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo); 2884 } else 2885 Callee = LoadValue; 2886 } 2887 } 2888 2889 // T9 register operand. 2890 SDValue T9; 2891 2892 // T9 should contain the address of the callee function if 2893 // -reloction-model=pic or it is an indirect call. 2894 if (IsPICCall || !GlobalOrExternal) { 2895 // copy to T9 2896 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9; 2897 Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0)); 2898 InFlag = Chain.getValue(1); 2899 2900 if (Subtarget->inMips16Mode()) 2901 T9 = DAG.getRegister(T9Reg, getPointerTy()); 2902 else 2903 Callee = DAG.getRegister(T9Reg, getPointerTy()); 2904 } 2905 2906 // Insert node "GP copy globalreg" before call to function. 2907 // Lazy-binding stubs require GP to point to the GOT. 2908 if (IsPICCall) { 2909 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP; 2910 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 2911 RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty))); 2912 } 2913 2914 // Build a sequence of copy-to-reg nodes chained together with token 2915 // chain and flag operands which copy the outgoing args into registers. 2916 // The InFlag in necessary since all emitted instructions must be 2917 // stuck together. 2918 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2919 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2920 RegsToPass[i].second, InFlag); 2921 InFlag = Chain.getValue(1); 2922 } 2923 2924 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 2925 // = Chain, Callee, Reg#1, Reg#2, ... 2926 // 2927 // Returns a chain & a flag for retval copy to use. 2928 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2929 SmallVector<SDValue, 8> Ops; 2930 Ops.push_back(Chain); 2931 Ops.push_back(Callee); 2932 2933 // Add argument registers to the end of the list so that they are 2934 // known live into the call. 2935 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2936 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2937 RegsToPass[i].second.getValueType())); 2938 2939 // Add T9 register operand. 2940 if (T9.getNode()) 2941 Ops.push_back(T9); 2942 2943 // Add a register mask operand representing the call-preserved registers. 2944 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2945 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2946 assert(Mask && "Missing call preserved mask for calling convention"); 2947 Ops.push_back(DAG.getRegisterMask(Mask)); 2948 2949 if (InFlag.getNode()) 2950 Ops.push_back(InFlag); 2951 2952 if (isTailCall) 2953 return DAG.getNode(MipsISD::TailCall, dl, MVT::Other, &Ops[0], Ops.size()); 2954 2955 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 2956 InFlag = Chain.getValue(1); 2957 2958 // Create the CALLSEQ_END node. 2959 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2960 DAG.getIntPtrConstant(0, true), InFlag); 2961 InFlag = Chain.getValue(1); 2962 2963 // Handle result values, copying them out of physregs into vregs that we 2964 // return. 2965 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2966 Ins, dl, DAG, InVals); 2967} 2968 2969/// LowerCallResult - Lower the result values of a call into the 2970/// appropriate copies out of appropriate physical registers. 2971SDValue 2972MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2973 CallingConv::ID CallConv, bool isVarArg, 2974 const SmallVectorImpl<ISD::InputArg> &Ins, 2975 DebugLoc dl, SelectionDAG &DAG, 2976 SmallVectorImpl<SDValue> &InVals) const { 2977 // Assign locations to each value returned by this call. 2978 SmallVector<CCValAssign, 16> RVLocs; 2979 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2980 getTargetMachine(), RVLocs, *DAG.getContext()); 2981 2982 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 2983 2984 // Copy all of the result registers out of their specified physreg. 2985 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2986 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 2987 RVLocs[i].getValVT(), InFlag).getValue(1); 2988 InFlag = Chain.getValue(2); 2989 InVals.push_back(Chain.getValue(0)); 2990 } 2991 2992 return Chain; 2993} 2994 2995//===----------------------------------------------------------------------===// 2996// Formal Arguments Calling Convention Implementation 2997//===----------------------------------------------------------------------===// 2998/// LowerFormalArguments - transform physical registers into virtual registers 2999/// and generate load operations for arguments places on the stack. 3000SDValue 3001MipsTargetLowering::LowerFormalArguments(SDValue Chain, 3002 CallingConv::ID CallConv, 3003 bool isVarArg, 3004 const SmallVectorImpl<ISD::InputArg> &Ins, 3005 DebugLoc dl, SelectionDAG &DAG, 3006 SmallVectorImpl<SDValue> &InVals) 3007 const { 3008 MachineFunction &MF = DAG.getMachineFunction(); 3009 MachineFrameInfo *MFI = MF.getFrameInfo(); 3010 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3011 3012 MipsFI->setVarArgsFrameIndex(0); 3013 3014 // Used with vargs to acumulate store chains. 3015 std::vector<SDValue> OutChains; 3016 3017 // Assign locations to all of the incoming arguments. 3018 SmallVector<CCValAssign, 16> ArgLocs; 3019 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3020 getTargetMachine(), ArgLocs, *DAG.getContext()); 3021 MipsCC MipsCCInfo(CallConv, isVarArg, IsO32, CCInfo); 3022 3023 MipsCCInfo.analyzeFormalArguments(Ins); 3024 3025 Function::const_arg_iterator FuncArg = 3026 DAG.getMachineFunction().getFunction()->arg_begin(); 3027 unsigned CurArgIdx = 0; 3028 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 3029 3030 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3031 CCValAssign &VA = ArgLocs[i]; 3032 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx); 3033 CurArgIdx = Ins[i].OrigArgIndex; 3034 EVT ValVT = VA.getValVT(); 3035 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3036 bool IsRegLoc = VA.isRegLoc(); 3037 3038 if (Flags.isByVal()) { 3039 assert(Flags.getByValSize() && 3040 "ByVal args of size 0 should have been ignored by front-end."); 3041 assert(ByValArg != MipsCCInfo.byval_end()); 3042 copyByValRegs(Chain, dl, OutChains, DAG, Flags, InVals, &*FuncArg, 3043 MipsCCInfo, *ByValArg); 3044 ++ByValArg; 3045 continue; 3046 } 3047 3048 // Arguments stored on registers 3049 if (IsRegLoc) { 3050 EVT RegVT = VA.getLocVT(); 3051 unsigned ArgReg = VA.getLocReg(); 3052 const TargetRegisterClass *RC; 3053 3054 if (RegVT == MVT::i32) 3055 RC = &Mips::CPURegsRegClass; 3056 else if (RegVT == MVT::i64) 3057 RC = &Mips::CPU64RegsRegClass; 3058 else if (RegVT == MVT::f32) 3059 RC = &Mips::FGR32RegClass; 3060 else if (RegVT == MVT::f64) 3061 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; 3062 else 3063 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 3064 3065 // Transform the arguments stored on 3066 // physical registers into virtual ones 3067 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3068 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 3069 3070 // If this is an 8 or 16-bit value, it has been passed promoted 3071 // to 32 bits. Insert an assert[sz]ext to capture this, then 3072 // truncate to the right size. 3073 if (VA.getLocInfo() != CCValAssign::Full) { 3074 unsigned Opcode = 0; 3075 if (VA.getLocInfo() == CCValAssign::SExt) 3076 Opcode = ISD::AssertSext; 3077 else if (VA.getLocInfo() == CCValAssign::ZExt) 3078 Opcode = ISD::AssertZext; 3079 if (Opcode) 3080 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 3081 DAG.getValueType(ValVT)); 3082 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue); 3083 } 3084 3085 // Handle floating point arguments passed in integer registers. 3086 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3087 (RegVT == MVT::i64 && ValVT == MVT::f64)) 3088 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue); 3089 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) { 3090 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 3091 getNextIntArgReg(ArgReg), RC); 3092 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 3093 if (!Subtarget->isLittle()) 3094 std::swap(ArgValue, ArgValue2); 3095 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 3096 ArgValue, ArgValue2); 3097 } 3098 3099 InVals.push_back(ArgValue); 3100 } else { // VA.isRegLoc() 3101 3102 // sanity check 3103 assert(VA.isMemLoc()); 3104 3105 // The stack pointer offset is relative to the caller stack frame. 3106 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 3107 VA.getLocMemOffset(), true); 3108 3109 // Create load nodes to retrieve arguments from the stack 3110 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 3111 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN, 3112 MachinePointerInfo::getFixedStack(FI), 3113 false, false, false, 0)); 3114 } 3115 } 3116 3117 // The mips ABIs for returning structs by value requires that we copy 3118 // the sret argument into $v0 for the return. Save the argument into 3119 // a virtual register so that we can access it from the return points. 3120 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 3121 unsigned Reg = MipsFI->getSRetReturnReg(); 3122 if (!Reg) { 3123 Reg = MF.getRegInfo(). 3124 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32)); 3125 MipsFI->setSRetReturnReg(Reg); 3126 } 3127 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 3128 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 3129 } 3130 3131 if (isVarArg) 3132 writeVarArgRegs(OutChains, MipsCCInfo, Chain, dl, DAG); 3133 3134 // All stores are grouped in one node to allow the matching between 3135 // the size of Ins and InVals. This only happens when on varg functions 3136 if (!OutChains.empty()) { 3137 OutChains.push_back(Chain); 3138 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3139 &OutChains[0], OutChains.size()); 3140 } 3141 3142 return Chain; 3143} 3144 3145//===----------------------------------------------------------------------===// 3146// Return Value Calling Convention Implementation 3147//===----------------------------------------------------------------------===// 3148 3149bool 3150MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3151 MachineFunction &MF, bool isVarArg, 3152 const SmallVectorImpl<ISD::OutputArg> &Outs, 3153 LLVMContext &Context) const { 3154 SmallVector<CCValAssign, 16> RVLocs; 3155 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 3156 RVLocs, Context); 3157 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3158} 3159 3160SDValue 3161MipsTargetLowering::LowerReturn(SDValue Chain, 3162 CallingConv::ID CallConv, bool isVarArg, 3163 const SmallVectorImpl<ISD::OutputArg> &Outs, 3164 const SmallVectorImpl<SDValue> &OutVals, 3165 DebugLoc dl, SelectionDAG &DAG) const { 3166 3167 // CCValAssign - represent the assignment of 3168 // the return value to a location 3169 SmallVector<CCValAssign, 16> RVLocs; 3170 3171 // CCState - Info about the registers and stack slot. 3172 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3173 getTargetMachine(), RVLocs, *DAG.getContext()); 3174 3175 // Analize return values. 3176 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3177 3178 // If this is the first return lowered for this function, add 3179 // the regs to the liveout set for the function. 3180 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 3181 for (unsigned i = 0; i != RVLocs.size(); ++i) 3182 if (RVLocs[i].isRegLoc()) 3183 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 3184 } 3185 3186 SDValue Flag; 3187 3188 // Copy the result values into the output registers. 3189 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3190 CCValAssign &VA = RVLocs[i]; 3191 assert(VA.isRegLoc() && "Can only return in registers!"); 3192 3193 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 3194 3195 // guarantee that all emitted copies are 3196 // stuck together, avoiding something bad 3197 Flag = Chain.getValue(1); 3198 } 3199 3200 // The mips ABIs for returning structs by value requires that we copy 3201 // the sret argument into $v0 for the return. We saved the argument into 3202 // a virtual register in the entry block, so now we copy the value out 3203 // and into $v0. 3204 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 3205 MachineFunction &MF = DAG.getMachineFunction(); 3206 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3207 unsigned Reg = MipsFI->getSRetReturnReg(); 3208 3209 if (!Reg) 3210 llvm_unreachable("sret virtual register not created in the entry block"); 3211 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 3212 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0; 3213 3214 Chain = DAG.getCopyToReg(Chain, dl, V0, Val, Flag); 3215 Flag = Chain.getValue(1); 3216 MF.getRegInfo().addLiveOut(V0); 3217 } 3218 3219 // Return on Mips is always a "jr $ra" 3220 if (Flag.getNode()) 3221 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain, Flag); 3222 3223 // Return Void 3224 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain); 3225} 3226 3227//===----------------------------------------------------------------------===// 3228// Mips Inline Assembly Support 3229//===----------------------------------------------------------------------===// 3230 3231/// getConstraintType - Given a constraint letter, return the type of 3232/// constraint it is for this target. 3233MipsTargetLowering::ConstraintType MipsTargetLowering:: 3234getConstraintType(const std::string &Constraint) const 3235{ 3236 // Mips specific constrainy 3237 // GCC config/mips/constraints.md 3238 // 3239 // 'd' : An address register. Equivalent to r 3240 // unless generating MIPS16 code. 3241 // 'y' : Equivalent to r; retained for 3242 // backwards compatibility. 3243 // 'c' : A register suitable for use in an indirect 3244 // jump. This will always be $25 for -mabicalls. 3245 // 'l' : The lo register. 1 word storage. 3246 // 'x' : The hilo register pair. Double word storage. 3247 if (Constraint.size() == 1) { 3248 switch (Constraint[0]) { 3249 default : break; 3250 case 'd': 3251 case 'y': 3252 case 'f': 3253 case 'c': 3254 case 'l': 3255 case 'x': 3256 return C_RegisterClass; 3257 } 3258 } 3259 return TargetLowering::getConstraintType(Constraint); 3260} 3261 3262/// Examine constraint type and operand type and determine a weight value. 3263/// This object must already have been set up with the operand type 3264/// and the current alternative constraint selected. 3265TargetLowering::ConstraintWeight 3266MipsTargetLowering::getSingleConstraintMatchWeight( 3267 AsmOperandInfo &info, const char *constraint) const { 3268 ConstraintWeight weight = CW_Invalid; 3269 Value *CallOperandVal = info.CallOperandVal; 3270 // If we don't have a value, we can't do a match, 3271 // but allow it at the lowest weight. 3272 if (CallOperandVal == NULL) 3273 return CW_Default; 3274 Type *type = CallOperandVal->getType(); 3275 // Look at the constraint type. 3276 switch (*constraint) { 3277 default: 3278 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3279 break; 3280 case 'd': 3281 case 'y': 3282 if (type->isIntegerTy()) 3283 weight = CW_Register; 3284 break; 3285 case 'f': 3286 if (type->isFloatTy()) 3287 weight = CW_Register; 3288 break; 3289 case 'c': // $25 for indirect jumps 3290 case 'l': // lo register 3291 case 'x': // hilo register pair 3292 if (type->isIntegerTy()) 3293 weight = CW_SpecificReg; 3294 break; 3295 case 'I': // signed 16 bit immediate 3296 case 'J': // integer zero 3297 case 'K': // unsigned 16 bit immediate 3298 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3299 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3300 case 'O': // signed 15 bit immediate (+- 16383) 3301 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3302 if (isa<ConstantInt>(CallOperandVal)) 3303 weight = CW_Constant; 3304 break; 3305 } 3306 return weight; 3307} 3308 3309/// Given a register class constraint, like 'r', if this corresponds directly 3310/// to an LLVM register class, return a register of 0 and the register class 3311/// pointer. 3312std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 3313getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 3314{ 3315 if (Constraint.size() == 1) { 3316 switch (Constraint[0]) { 3317 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3318 case 'y': // Same as 'r'. Exists for compatibility. 3319 case 'r': 3320 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3321 if (Subtarget->inMips16Mode()) 3322 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3323 return std::make_pair(0U, &Mips::CPURegsRegClass); 3324 } 3325 if (VT == MVT::i64 && !HasMips64) 3326 return std::make_pair(0U, &Mips::CPURegsRegClass); 3327 if (VT == MVT::i64 && HasMips64) 3328 return std::make_pair(0U, &Mips::CPU64RegsRegClass); 3329 // This will generate an error message 3330 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 3331 case 'f': 3332 if (VT == MVT::f32) 3333 return std::make_pair(0U, &Mips::FGR32RegClass); 3334 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { 3335 if (Subtarget->isFP64bit()) 3336 return std::make_pair(0U, &Mips::FGR64RegClass); 3337 return std::make_pair(0U, &Mips::AFGR64RegClass); 3338 } 3339 break; 3340 case 'c': // register suitable for indirect jump 3341 if (VT == MVT::i32) 3342 return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass); 3343 assert(VT == MVT::i64 && "Unexpected type."); 3344 return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass); 3345 case 'l': // register suitable for indirect jump 3346 if (VT == MVT::i32) 3347 return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass); 3348 return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass); 3349 case 'x': // register suitable for indirect jump 3350 // Fixme: Not triggering the use of both hi and low 3351 // This will generate an error message 3352 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 3353 } 3354 } 3355 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3356} 3357 3358/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3359/// vector. If it is invalid, don't add anything to Ops. 3360void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3361 std::string &Constraint, 3362 std::vector<SDValue>&Ops, 3363 SelectionDAG &DAG) const { 3364 SDValue Result(0, 0); 3365 3366 // Only support length 1 constraints for now. 3367 if (Constraint.length() > 1) return; 3368 3369 char ConstraintLetter = Constraint[0]; 3370 switch (ConstraintLetter) { 3371 default: break; // This will fall through to the generic implementation 3372 case 'I': // Signed 16 bit constant 3373 // If this fails, the parent routine will give an error 3374 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3375 EVT Type = Op.getValueType(); 3376 int64_t Val = C->getSExtValue(); 3377 if (isInt<16>(Val)) { 3378 Result = DAG.getTargetConstant(Val, Type); 3379 break; 3380 } 3381 } 3382 return; 3383 case 'J': // integer zero 3384 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3385 EVT Type = Op.getValueType(); 3386 int64_t Val = C->getZExtValue(); 3387 if (Val == 0) { 3388 Result = DAG.getTargetConstant(0, Type); 3389 break; 3390 } 3391 } 3392 return; 3393 case 'K': // unsigned 16 bit immediate 3394 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3395 EVT Type = Op.getValueType(); 3396 uint64_t Val = (uint64_t)C->getZExtValue(); 3397 if (isUInt<16>(Val)) { 3398 Result = DAG.getTargetConstant(Val, Type); 3399 break; 3400 } 3401 } 3402 return; 3403 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3404 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3405 EVT Type = Op.getValueType(); 3406 int64_t Val = C->getSExtValue(); 3407 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3408 Result = DAG.getTargetConstant(Val, Type); 3409 break; 3410 } 3411 } 3412 return; 3413 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3414 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3415 EVT Type = Op.getValueType(); 3416 int64_t Val = C->getSExtValue(); 3417 if ((Val >= -65535) && (Val <= -1)) { 3418 Result = DAG.getTargetConstant(Val, Type); 3419 break; 3420 } 3421 } 3422 return; 3423 case 'O': // signed 15 bit immediate 3424 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3425 EVT Type = Op.getValueType(); 3426 int64_t Val = C->getSExtValue(); 3427 if ((isInt<15>(Val))) { 3428 Result = DAG.getTargetConstant(Val, Type); 3429 break; 3430 } 3431 } 3432 return; 3433 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3434 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3435 EVT Type = Op.getValueType(); 3436 int64_t Val = C->getSExtValue(); 3437 if ((Val <= 65535) && (Val >= 1)) { 3438 Result = DAG.getTargetConstant(Val, Type); 3439 break; 3440 } 3441 } 3442 return; 3443 } 3444 3445 if (Result.getNode()) { 3446 Ops.push_back(Result); 3447 return; 3448 } 3449 3450 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3451} 3452 3453bool 3454MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3455 // The Mips target isn't yet aware of offsets. 3456 return false; 3457} 3458 3459EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3460 unsigned SrcAlign, bool IsZeroVal, 3461 bool MemcpyStrSrc, 3462 MachineFunction &MF) const { 3463 if (Subtarget->hasMips64()) 3464 return MVT::i64; 3465 3466 return MVT::i32; 3467} 3468 3469bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3470 if (VT != MVT::f32 && VT != MVT::f64) 3471 return false; 3472 if (Imm.isNegZero()) 3473 return false; 3474 return Imm.isZero(); 3475} 3476 3477unsigned MipsTargetLowering::getJumpTableEncoding() const { 3478 if (IsN64) 3479 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3480 3481 return TargetLowering::getJumpTableEncoding(); 3482} 3483 3484MipsTargetLowering::MipsCC::MipsCC(CallingConv::ID CallConv, bool IsVarArg, 3485 bool IsO32, CCState &Info) : CCInfo(Info) { 3486 UseRegsForByval = true; 3487 3488 if (IsO32) { 3489 RegSize = 4; 3490 NumIntArgRegs = array_lengthof(O32IntRegs); 3491 ReservedArgArea = 16; 3492 IntArgRegs = ShadowRegs = O32IntRegs; 3493 FixedFn = VarFn = CC_MipsO32; 3494 } else { 3495 RegSize = 8; 3496 NumIntArgRegs = array_lengthof(Mips64IntRegs); 3497 ReservedArgArea = 0; 3498 IntArgRegs = Mips64IntRegs; 3499 ShadowRegs = Mips64DPRegs; 3500 FixedFn = CC_MipsN; 3501 VarFn = CC_MipsN_VarArg; 3502 } 3503 3504 if (CallConv == CallingConv::Fast) { 3505 assert(!IsVarArg); 3506 UseRegsForByval = false; 3507 ReservedArgArea = 0; 3508 FixedFn = VarFn = CC_Mips_FastCC; 3509 } 3510 3511 // Pre-allocate reserved argument area. 3512 CCInfo.AllocateStack(ReservedArgArea, 1); 3513} 3514 3515void MipsTargetLowering::MipsCC:: 3516analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args) { 3517 unsigned NumOpnds = Args.size(); 3518 3519 for (unsigned I = 0; I != NumOpnds; ++I) { 3520 MVT ArgVT = Args[I].VT; 3521 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3522 bool R; 3523 3524 if (ArgFlags.isByVal()) { 3525 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3526 continue; 3527 } 3528 3529 if (Args[I].IsFixed) 3530 R = FixedFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 3531 else 3532 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 3533 3534 if (R) { 3535#ifndef NDEBUG 3536 dbgs() << "Call operand #" << I << " has unhandled type " 3537 << EVT(ArgVT).getEVTString(); 3538#endif 3539 llvm_unreachable(0); 3540 } 3541 } 3542} 3543 3544void MipsTargetLowering::MipsCC:: 3545analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args) { 3546 unsigned NumArgs = Args.size(); 3547 3548 for (unsigned I = 0; I != NumArgs; ++I) { 3549 MVT ArgVT = Args[I].VT; 3550 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3551 3552 if (ArgFlags.isByVal()) { 3553 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3554 continue; 3555 } 3556 3557 if (!FixedFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo)) 3558 continue; 3559 3560#ifndef NDEBUG 3561 dbgs() << "Formal Arg #" << I << " has unhandled type " 3562 << EVT(ArgVT).getEVTString(); 3563#endif 3564 llvm_unreachable(0); 3565 } 3566} 3567 3568void 3569MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT, 3570 MVT LocVT, 3571 CCValAssign::LocInfo LocInfo, 3572 ISD::ArgFlagsTy ArgFlags) { 3573 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0."); 3574 3575 struct ByValArgInfo ByVal; 3576 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize); 3577 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize), 3578 RegSize * 2); 3579 3580 if (UseRegsForByval) 3581 allocateRegs(ByVal, ByValSize, Align); 3582 3583 // Allocate space on caller's stack. 3584 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs, 3585 Align); 3586 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT, 3587 LocInfo)); 3588 ByValArgs.push_back(ByVal); 3589} 3590 3591void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal, 3592 unsigned ByValSize, 3593 unsigned Align) { 3594 assert(!(ByValSize % RegSize) && !(Align % RegSize) && 3595 "Byval argument's size and alignment should be a multiple of" 3596 "RegSize."); 3597 3598 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs); 3599 3600 // If Align > RegSize, the first arg register must be even. 3601 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) { 3602 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]); 3603 ++ByVal.FirstIdx; 3604 } 3605 3606 // Mark the registers allocated. 3607 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs); 3608 ByValSize -= RegSize, ++I, ++ByVal.NumRegs) 3609 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]); 3610} 3611 3612void MipsTargetLowering:: 3613copyByValRegs(SDValue Chain, DebugLoc DL, std::vector<SDValue> &OutChains, 3614 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 3615 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 3616 const MipsCC &CC, const ByValArgInfo &ByVal) const { 3617 MachineFunction &MF = DAG.getMachineFunction(); 3618 MachineFrameInfo *MFI = MF.getFrameInfo(); 3619 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize(); 3620 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3621 int FrameObjOffset; 3622 3623 if (RegAreaSize) 3624 FrameObjOffset = (int)CC.reservedArgArea() - 3625 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize()); 3626 else 3627 FrameObjOffset = ByVal.Address; 3628 3629 // Create frame object. 3630 EVT PtrTy = getPointerTy(); 3631 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3632 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3633 InVals.push_back(FIN); 3634 3635 if (!ByVal.NumRegs) 3636 return; 3637 3638 // Copy arg registers. 3639 EVT RegTy = MVT::getIntegerVT(CC.regSize() * 8); 3640 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3641 3642 for (unsigned I = 0; I < ByVal.NumRegs; ++I) { 3643 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I]; 3644 unsigned VReg = AddLiveIn(MF, ArgReg, RC); 3645 unsigned Offset = I * CC.regSize(); 3646 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3647 DAG.getConstant(Offset, PtrTy)); 3648 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3649 StorePtr, MachinePointerInfo(FuncArg, Offset), 3650 false, false, 0); 3651 OutChains.push_back(Store); 3652 } 3653} 3654 3655// Copy byVal arg to registers and stack. 3656void MipsTargetLowering:: 3657passByValArg(SDValue Chain, DebugLoc DL, 3658 SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass, 3659 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, 3660 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 3661 const MipsCC &CC, const ByValArgInfo &ByVal, 3662 const ISD::ArgFlagsTy &Flags, bool isLittle) const { 3663 unsigned ByValSize = Flags.getByValSize(); 3664 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct. 3665 unsigned RegSize = CC.regSize(); 3666 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize); 3667 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8); 3668 3669 if (ByVal.NumRegs) { 3670 const uint16_t *ArgRegs = CC.intArgRegs(); 3671 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize); 3672 unsigned I = 0; 3673 3674 // Copy words to registers. 3675 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) { 3676 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3677 DAG.getConstant(Offset, PtrTy)); 3678 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3679 MachinePointerInfo(), false, false, false, 3680 Alignment); 3681 MemOpChains.push_back(LoadVal.getValue(1)); 3682 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3683 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3684 } 3685 3686 // Return if the struct has been fully copied. 3687 if (ByValSize == Offset) 3688 return; 3689 3690 // Copy the remainder of the byval argument with sub-word loads and shifts. 3691 if (LeftoverBytes) { 3692 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) && 3693 "Size of the remainder should be smaller than RegSize."); 3694 SDValue Val; 3695 3696 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0; 3697 Offset < ByValSize; LoadSize /= 2) { 3698 unsigned RemSize = ByValSize - Offset; 3699 3700 if (RemSize < LoadSize) 3701 continue; 3702 3703 // Load subword. 3704 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3705 DAG.getConstant(Offset, PtrTy)); 3706 SDValue LoadVal = 3707 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, 3708 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8), 3709 false, false, Alignment); 3710 MemOpChains.push_back(LoadVal.getValue(1)); 3711 3712 // Shift the loaded value. 3713 unsigned Shamt; 3714 3715 if (isLittle) 3716 Shamt = TotalSizeLoaded; 3717 else 3718 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8; 3719 3720 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 3721 DAG.getConstant(Shamt, MVT::i32)); 3722 3723 if (Val.getNode()) 3724 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3725 else 3726 Val = Shift; 3727 3728 Offset += LoadSize; 3729 TotalSizeLoaded += LoadSize; 3730 Alignment = std::min(Alignment, LoadSize); 3731 } 3732 3733 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3734 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 3735 return; 3736 } 3737 } 3738 3739 // Copy remainder of byval arg to it with memcpy. 3740 unsigned MemCpySize = ByValSize - Offset; 3741 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3742 DAG.getConstant(Offset, PtrTy)); 3743 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 3744 DAG.getIntPtrConstant(ByVal.Address)); 3745 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 3746 DAG.getConstant(MemCpySize, PtrTy), Alignment, 3747 /*isVolatile=*/false, /*AlwaysInline=*/false, 3748 MachinePointerInfo(0), MachinePointerInfo(0)); 3749 MemOpChains.push_back(Chain); 3750} 3751 3752void 3753MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 3754 const MipsCC &CC, SDValue Chain, 3755 DebugLoc DL, SelectionDAG &DAG) const { 3756 unsigned NumRegs = CC.numIntArgRegs(); 3757 const uint16_t *ArgRegs = CC.intArgRegs(); 3758 const CCState &CCInfo = CC.getCCInfo(); 3759 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs); 3760 unsigned RegSize = CC.regSize(); 3761 EVT RegTy = MVT::getIntegerVT(RegSize * 8); 3762 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3763 MachineFunction &MF = DAG.getMachineFunction(); 3764 MachineFrameInfo *MFI = MF.getFrameInfo(); 3765 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3766 3767 // Offset of the first variable argument from stack pointer. 3768 int VaArgOffset; 3769 3770 if (NumRegs == Idx) 3771 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize); 3772 else 3773 VaArgOffset = 3774 (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx)); 3775 3776 // Record the frame index of the first variable argument 3777 // which is a value necessary to VASTART. 3778 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3779 MipsFI->setVarArgsFrameIndex(FI); 3780 3781 // Copy the integer registers that have not been used for argument passing 3782 // to the argument register save area. For O32, the save area is allocated 3783 // in the caller's stack frame, while for N32/64, it is allocated in the 3784 // callee's stack frame. 3785 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) { 3786 unsigned Reg = AddLiveIn(MF, ArgRegs[I], RC); 3787 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 3788 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3789 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 3790 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, 3791 MachinePointerInfo(), false, false, 0); 3792 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0); 3793 OutChains.push_back(Store); 3794 } 3795} 3796