MipsISelLowering.cpp revision c673f9c6fecb0f828845ada7ea5458f66f896283
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14#define DEBUG_TYPE "mips-lower" 15#include "MipsISelLowering.h" 16#include "InstPrinter/MipsInstPrinter.h" 17#include "MCTargetDesc/MipsBaseInfo.h" 18#include "MipsMachineFunction.h" 19#include "MipsSubtarget.h" 20#include "MipsTargetMachine.h" 21#include "MipsTargetObjectFile.h" 22#include "llvm/ADT/Statistic.h" 23#include "llvm/CodeGen/CallingConvLower.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineRegisterInfo.h" 28#include "llvm/CodeGen/SelectionDAGISel.h" 29#include "llvm/CodeGen/ValueTypes.h" 30#include "llvm/IR/CallingConv.h" 31#include "llvm/IR/DerivedTypes.h" 32#include "llvm/IR/GlobalVariable.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/raw_ostream.h" 37#include <cctype> 38 39using namespace llvm; 40 41STATISTIC(NumTailCalls, "Number of tail calls"); 42 43static cl::opt<bool> 44LargeGOT("mxgot", cl::Hidden, 45 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 46 47static cl::opt<bool> 48NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 49 cl::desc("MIPS: Don't trap on integer division by zero."), 50 cl::init(false)); 51 52static const uint16_t O32IntRegs[4] = { 53 Mips::A0, Mips::A1, Mips::A2, Mips::A3 54}; 55 56static const uint16_t Mips64IntRegs[8] = { 57 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, 58 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 59}; 60 61static const uint16_t Mips64DPRegs[8] = { 62 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 63 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 64}; 65 66// If I is a shifted mask, set the size (Size) and the first bit of the 67// mask (Pos), and return true. 68// For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 69static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 70 if (!isShiftedMask_64(I)) 71 return false; 72 73 Size = CountPopulation_64(I); 74 Pos = countTrailingZeros(I); 75 return true; 76} 77 78SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 79 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 80 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 81} 82 83static SDValue getTargetNode(SDValue Op, SelectionDAG &DAG, unsigned Flag) { 84 EVT Ty = Op.getValueType(); 85 86 if (GlobalAddressSDNode *N = dyn_cast<GlobalAddressSDNode>(Op)) 87 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(Op), Ty, 0, 88 Flag); 89 if (ExternalSymbolSDNode *N = dyn_cast<ExternalSymbolSDNode>(Op)) 90 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 91 if (BlockAddressSDNode *N = dyn_cast<BlockAddressSDNode>(Op)) 92 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 93 if (JumpTableSDNode *N = dyn_cast<JumpTableSDNode>(Op)) 94 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 95 if (ConstantPoolSDNode *N = dyn_cast<ConstantPoolSDNode>(Op)) 96 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 97 N->getOffset(), Flag); 98 99 llvm_unreachable("Unexpected node type."); 100 return SDValue(); 101} 102 103static SDValue getAddrNonPIC(SDValue Op, SelectionDAG &DAG) { 104 SDLoc DL(Op); 105 EVT Ty = Op.getValueType(); 106 SDValue Hi = getTargetNode(Op, DAG, MipsII::MO_ABS_HI); 107 SDValue Lo = getTargetNode(Op, DAG, MipsII::MO_ABS_LO); 108 return DAG.getNode(ISD::ADD, DL, Ty, 109 DAG.getNode(MipsISD::Hi, DL, Ty, Hi), 110 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); 111} 112 113SDValue MipsTargetLowering::getAddrLocal(SDValue Op, SelectionDAG &DAG, 114 bool HasMips64) const { 115 SDLoc DL(Op); 116 EVT Ty = Op.getValueType(); 117 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 118 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 119 getTargetNode(Op, DAG, GOTFlag)); 120 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, 121 MachinePointerInfo::getGOT(), false, false, false, 122 0); 123 unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 124 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(Op, DAG, LoFlag)); 125 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); 126} 127 128SDValue MipsTargetLowering::getAddrGlobal(SDValue Op, SelectionDAG &DAG, 129 unsigned Flag) const { 130 SDLoc DL(Op); 131 EVT Ty = Op.getValueType(); 132 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 133 getTargetNode(Op, DAG, Flag)); 134 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Tgt, 135 MachinePointerInfo::getGOT(), false, false, false, 0); 136} 137 138SDValue MipsTargetLowering::getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG, 139 unsigned HiFlag, 140 unsigned LoFlag) const { 141 SDLoc DL(Op); 142 EVT Ty = Op.getValueType(); 143 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(Op, DAG, HiFlag)); 144 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty)); 145 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi, 146 getTargetNode(Op, DAG, LoFlag)); 147 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Wrapper, 148 MachinePointerInfo::getGOT(), false, false, false, 0); 149} 150 151const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 152 switch (Opcode) { 153 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 154 case MipsISD::TailCall: return "MipsISD::TailCall"; 155 case MipsISD::Hi: return "MipsISD::Hi"; 156 case MipsISD::Lo: return "MipsISD::Lo"; 157 case MipsISD::GPRel: return "MipsISD::GPRel"; 158 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 159 case MipsISD::Ret: return "MipsISD::Ret"; 160 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 161 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 162 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 163 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 164 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 165 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 166 case MipsISD::ExtractLOHI: return "MipsISD::ExtractLOHI"; 167 case MipsISD::InsertLOHI: return "MipsISD::InsertLOHI"; 168 case MipsISD::Mult: return "MipsISD::Mult"; 169 case MipsISD::Multu: return "MipsISD::Multu"; 170 case MipsISD::MAdd: return "MipsISD::MAdd"; 171 case MipsISD::MAddu: return "MipsISD::MAddu"; 172 case MipsISD::MSub: return "MipsISD::MSub"; 173 case MipsISD::MSubu: return "MipsISD::MSubu"; 174 case MipsISD::DivRem: return "MipsISD::DivRem"; 175 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 176 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 177 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 178 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 179 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 180 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 181 case MipsISD::Sync: return "MipsISD::Sync"; 182 case MipsISD::Ext: return "MipsISD::Ext"; 183 case MipsISD::Ins: return "MipsISD::Ins"; 184 case MipsISD::LWL: return "MipsISD::LWL"; 185 case MipsISD::LWR: return "MipsISD::LWR"; 186 case MipsISD::SWL: return "MipsISD::SWL"; 187 case MipsISD::SWR: return "MipsISD::SWR"; 188 case MipsISD::LDL: return "MipsISD::LDL"; 189 case MipsISD::LDR: return "MipsISD::LDR"; 190 case MipsISD::SDL: return "MipsISD::SDL"; 191 case MipsISD::SDR: return "MipsISD::SDR"; 192 case MipsISD::EXTP: return "MipsISD::EXTP"; 193 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 194 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 195 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 196 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 197 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 198 case MipsISD::SHILO: return "MipsISD::SHILO"; 199 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 200 case MipsISD::MULT: return "MipsISD::MULT"; 201 case MipsISD::MULTU: return "MipsISD::MULTU"; 202 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 203 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 204 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 205 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 206 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 207 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 208 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 209 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 210 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 211 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 212 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 213 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 214 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 215 default: return NULL; 216 } 217} 218 219MipsTargetLowering:: 220MipsTargetLowering(MipsTargetMachine &TM) 221 : TargetLowering(TM, new MipsTargetObjectFile()), 222 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 223 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()), 224 IsO32(Subtarget->isABI_O32()) { 225 // Mips does not have i1 type, so use i32 for 226 // setcc operations results (slt, sgt, ...). 227 setBooleanContents(ZeroOrOneBooleanContent); 228 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 229 230 // Load extented operations for i1 types must be promoted 231 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 232 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 233 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 234 235 // MIPS doesn't have extending float->double load/store 236 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 237 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 238 239 // Used by legalize types to correctly generate the setcc result. 240 // Without this, every float setcc comes with a AND/OR with the result, 241 // we don't want this, since the fpcmp result goes to a flag register, 242 // which is used implicitly by brcond and select operations. 243 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 244 245 // Mips Custom Operations 246 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 247 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 248 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 249 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 250 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 251 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 252 setOperationAction(ISD::SELECT, MVT::f32, Custom); 253 setOperationAction(ISD::SELECT, MVT::f64, Custom); 254 setOperationAction(ISD::SELECT, MVT::i32, Custom); 255 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 256 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 257 setOperationAction(ISD::SETCC, MVT::f32, Custom); 258 setOperationAction(ISD::SETCC, MVT::f64, Custom); 259 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 260 setOperationAction(ISD::VASTART, MVT::Other, Custom); 261 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 262 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 263 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 264 265 if (!TM.Options.NoNaNsFPMath) { 266 setOperationAction(ISD::FABS, MVT::f32, Custom); 267 setOperationAction(ISD::FABS, MVT::f64, Custom); 268 } 269 270 if (HasMips64) { 271 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 272 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 273 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 274 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 275 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 276 setOperationAction(ISD::SELECT, MVT::i64, Custom); 277 setOperationAction(ISD::LOAD, MVT::i64, Custom); 278 setOperationAction(ISD::STORE, MVT::i64, Custom); 279 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 280 } 281 282 if (!HasMips64) { 283 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 284 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 285 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 286 } 287 288 setOperationAction(ISD::ADD, MVT::i32, Custom); 289 if (HasMips64) 290 setOperationAction(ISD::ADD, MVT::i64, Custom); 291 292 setOperationAction(ISD::SDIV, MVT::i32, Expand); 293 setOperationAction(ISD::SREM, MVT::i32, Expand); 294 setOperationAction(ISD::UDIV, MVT::i32, Expand); 295 setOperationAction(ISD::UREM, MVT::i32, Expand); 296 setOperationAction(ISD::SDIV, MVT::i64, Expand); 297 setOperationAction(ISD::SREM, MVT::i64, Expand); 298 setOperationAction(ISD::UDIV, MVT::i64, Expand); 299 setOperationAction(ISD::UREM, MVT::i64, Expand); 300 301 // Operations not directly supported by Mips. 302 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 303 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 304 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 305 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 306 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 307 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 308 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 309 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 310 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 312 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 313 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 314 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 315 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 316 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 317 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 318 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 319 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 320 setOperationAction(ISD::ROTL, MVT::i32, Expand); 321 setOperationAction(ISD::ROTL, MVT::i64, Expand); 322 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 323 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 324 325 if (!Subtarget->hasMips32r2()) 326 setOperationAction(ISD::ROTR, MVT::i32, Expand); 327 328 if (!Subtarget->hasMips64r2()) 329 setOperationAction(ISD::ROTR, MVT::i64, Expand); 330 331 setOperationAction(ISD::FSIN, MVT::f32, Expand); 332 setOperationAction(ISD::FSIN, MVT::f64, Expand); 333 setOperationAction(ISD::FCOS, MVT::f32, Expand); 334 setOperationAction(ISD::FCOS, MVT::f64, Expand); 335 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 336 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 337 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 338 setOperationAction(ISD::FPOW, MVT::f32, Expand); 339 setOperationAction(ISD::FPOW, MVT::f64, Expand); 340 setOperationAction(ISD::FLOG, MVT::f32, Expand); 341 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 342 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 343 setOperationAction(ISD::FEXP, MVT::f32, Expand); 344 setOperationAction(ISD::FMA, MVT::f32, Expand); 345 setOperationAction(ISD::FMA, MVT::f64, Expand); 346 setOperationAction(ISD::FREM, MVT::f32, Expand); 347 setOperationAction(ISD::FREM, MVT::f64, Expand); 348 349 if (!TM.Options.NoNaNsFPMath) { 350 setOperationAction(ISD::FNEG, MVT::f32, Expand); 351 setOperationAction(ISD::FNEG, MVT::f64, Expand); 352 } 353 354 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 355 356 setOperationAction(ISD::VAARG, MVT::Other, Expand); 357 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 358 setOperationAction(ISD::VAEND, MVT::Other, Expand); 359 360 // Use the default for now 361 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 362 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 363 364 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 365 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 366 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 367 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 368 369 setInsertFencesForAtomic(true); 370 371 if (!Subtarget->hasSEInReg()) { 372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 374 } 375 376 if (!Subtarget->hasBitCount()) { 377 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 378 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 379 } 380 381 if (!Subtarget->hasSwap()) { 382 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 383 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 384 } 385 386 if (HasMips64) { 387 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); 388 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom); 389 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom); 390 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 391 } 392 393 setOperationAction(ISD::TRAP, MVT::Other, Legal); 394 395 setTargetDAGCombine(ISD::SDIVREM); 396 setTargetDAGCombine(ISD::UDIVREM); 397 setTargetDAGCombine(ISD::SELECT); 398 setTargetDAGCombine(ISD::AND); 399 setTargetDAGCombine(ISD::OR); 400 setTargetDAGCombine(ISD::ADD); 401 402 setMinFunctionAlignment(HasMips64 ? 3 : 2); 403 404 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP); 405 406 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0); 407 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1); 408 409 MaxStoresPerMemcpy = 16; 410} 411 412const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) { 413 if (TM.getSubtargetImpl()->inMips16Mode()) 414 return llvm::createMips16TargetLowering(TM); 415 416 return llvm::createMipsSETargetLowering(TM); 417} 418 419EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { 420 if (!VT.isVector()) 421 return MVT::i32; 422 return VT.changeVectorElementTypeToInteger(); 423} 424 425static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 426 TargetLowering::DAGCombinerInfo &DCI, 427 const MipsSubtarget *Subtarget) { 428 if (DCI.isBeforeLegalizeOps()) 429 return SDValue(); 430 431 EVT Ty = N->getValueType(0); 432 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 433 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 434 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 435 MipsISD::DivRemU16; 436 SDLoc DL(N); 437 438 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 439 N->getOperand(0), N->getOperand(1)); 440 SDValue InChain = DAG.getEntryNode(); 441 SDValue InGlue = DivRem; 442 443 // insert MFLO 444 if (N->hasAnyUseOfValue(0)) { 445 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 446 InGlue); 447 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 448 InChain = CopyFromLo.getValue(1); 449 InGlue = CopyFromLo.getValue(2); 450 } 451 452 // insert MFHI 453 if (N->hasAnyUseOfValue(1)) { 454 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 455 HI, Ty, InGlue); 456 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 457 } 458 459 return SDValue(); 460} 461 462static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 463 switch (CC) { 464 default: llvm_unreachable("Unknown fp condition code!"); 465 case ISD::SETEQ: 466 case ISD::SETOEQ: return Mips::FCOND_OEQ; 467 case ISD::SETUNE: return Mips::FCOND_UNE; 468 case ISD::SETLT: 469 case ISD::SETOLT: return Mips::FCOND_OLT; 470 case ISD::SETGT: 471 case ISD::SETOGT: return Mips::FCOND_OGT; 472 case ISD::SETLE: 473 case ISD::SETOLE: return Mips::FCOND_OLE; 474 case ISD::SETGE: 475 case ISD::SETOGE: return Mips::FCOND_OGE; 476 case ISD::SETULT: return Mips::FCOND_ULT; 477 case ISD::SETULE: return Mips::FCOND_ULE; 478 case ISD::SETUGT: return Mips::FCOND_UGT; 479 case ISD::SETUGE: return Mips::FCOND_UGE; 480 case ISD::SETUO: return Mips::FCOND_UN; 481 case ISD::SETO: return Mips::FCOND_OR; 482 case ISD::SETNE: 483 case ISD::SETONE: return Mips::FCOND_ONE; 484 case ISD::SETUEQ: return Mips::FCOND_UEQ; 485 } 486} 487 488 489/// This function returns true if the floating point conditional branches and 490/// conditional moves which use condition code CC should be inverted. 491static bool invertFPCondCodeUser(Mips::CondCode CC) { 492 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 493 return false; 494 495 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 496 "Illegal Condition Code"); 497 498 return true; 499} 500 501// Creates and returns an FPCmp node from a setcc node. 502// Returns Op if setcc is not a floating point comparison. 503static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 504 // must be a SETCC node 505 if (Op.getOpcode() != ISD::SETCC) 506 return Op; 507 508 SDValue LHS = Op.getOperand(0); 509 510 if (!LHS.getValueType().isFloatingPoint()) 511 return Op; 512 513 SDValue RHS = Op.getOperand(1); 514 SDLoc DL(Op); 515 516 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 517 // node if necessary. 518 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 519 520 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 521 DAG.getConstant(condCodeToFCC(CC), MVT::i32)); 522} 523 524// Creates and returns a CMovFPT/F node. 525static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 526 SDValue False, SDLoc DL) { 527 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 528 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 529 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 530 531 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 532 True.getValueType(), True, FCC0, False, Cond); 533} 534 535static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 536 TargetLowering::DAGCombinerInfo &DCI, 537 const MipsSubtarget *Subtarget) { 538 if (DCI.isBeforeLegalizeOps()) 539 return SDValue(); 540 541 SDValue SetCC = N->getOperand(0); 542 543 if ((SetCC.getOpcode() != ISD::SETCC) || 544 !SetCC.getOperand(0).getValueType().isInteger()) 545 return SDValue(); 546 547 SDValue False = N->getOperand(2); 548 EVT FalseTy = False.getValueType(); 549 550 if (!FalseTy.isInteger()) 551 return SDValue(); 552 553 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False); 554 555 if (!CN || CN->getZExtValue()) 556 return SDValue(); 557 558 const SDLoc DL(N); 559 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 560 SDValue True = N->getOperand(1); 561 562 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 563 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 564 565 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 566} 567 568static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 569 TargetLowering::DAGCombinerInfo &DCI, 570 const MipsSubtarget *Subtarget) { 571 // Pattern match EXT. 572 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 573 // => ext $dst, $src, size, pos 574 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 575 return SDValue(); 576 577 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 578 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 579 580 // Op's first operand must be a shift right. 581 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 582 return SDValue(); 583 584 // The second operand of the shift must be an immediate. 585 ConstantSDNode *CN; 586 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 587 return SDValue(); 588 589 uint64_t Pos = CN->getZExtValue(); 590 uint64_t SMPos, SMSize; 591 592 // Op's second operand must be a shifted mask. 593 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 594 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 595 return SDValue(); 596 597 // Return if the shifted mask does not start at bit 0 or the sum of its size 598 // and Pos exceeds the word's size. 599 EVT ValTy = N->getValueType(0); 600 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 601 return SDValue(); 602 603 return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy, 604 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), 605 DAG.getConstant(SMSize, MVT::i32)); 606} 607 608static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 609 TargetLowering::DAGCombinerInfo &DCI, 610 const MipsSubtarget *Subtarget) { 611 // Pattern match INS. 612 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 613 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 614 // => ins $dst, $src, size, pos, $src1 615 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 616 return SDValue(); 617 618 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 619 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 620 ConstantSDNode *CN; 621 622 // See if Op's first operand matches (and $src1 , mask0). 623 if (And0.getOpcode() != ISD::AND) 624 return SDValue(); 625 626 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 627 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 628 return SDValue(); 629 630 // See if Op's second operand matches (and (shl $src, pos), mask1). 631 if (And1.getOpcode() != ISD::AND) 632 return SDValue(); 633 634 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 635 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 636 return SDValue(); 637 638 // The shift masks must have the same position and size. 639 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 640 return SDValue(); 641 642 SDValue Shl = And1.getOperand(0); 643 if (Shl.getOpcode() != ISD::SHL) 644 return SDValue(); 645 646 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 647 return SDValue(); 648 649 unsigned Shamt = CN->getZExtValue(); 650 651 // Return if the shift amount and the first bit position of mask are not the 652 // same. 653 EVT ValTy = N->getValueType(0); 654 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 655 return SDValue(); 656 657 return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0), 658 DAG.getConstant(SMPos0, MVT::i32), 659 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0)); 660} 661 662static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 663 TargetLowering::DAGCombinerInfo &DCI, 664 const MipsSubtarget *Subtarget) { 665 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 666 667 if (DCI.isBeforeLegalizeOps()) 668 return SDValue(); 669 670 SDValue Add = N->getOperand(1); 671 672 if (Add.getOpcode() != ISD::ADD) 673 return SDValue(); 674 675 SDValue Lo = Add.getOperand(1); 676 677 if ((Lo.getOpcode() != MipsISD::Lo) || 678 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 679 return SDValue(); 680 681 EVT ValTy = N->getValueType(0); 682 SDLoc DL(N); 683 684 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 685 Add.getOperand(0)); 686 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 687} 688 689SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 690 const { 691 SelectionDAG &DAG = DCI.DAG; 692 unsigned Opc = N->getOpcode(); 693 694 switch (Opc) { 695 default: break; 696 case ISD::SDIVREM: 697 case ISD::UDIVREM: 698 return performDivRemCombine(N, DAG, DCI, Subtarget); 699 case ISD::SELECT: 700 return performSELECTCombine(N, DAG, DCI, Subtarget); 701 case ISD::AND: 702 return performANDCombine(N, DAG, DCI, Subtarget); 703 case ISD::OR: 704 return performORCombine(N, DAG, DCI, Subtarget); 705 case ISD::ADD: 706 return performADDCombine(N, DAG, DCI, Subtarget); 707 } 708 709 return SDValue(); 710} 711 712void 713MipsTargetLowering::LowerOperationWrapper(SDNode *N, 714 SmallVectorImpl<SDValue> &Results, 715 SelectionDAG &DAG) const { 716 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 717 718 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 719 Results.push_back(Res.getValue(I)); 720} 721 722void 723MipsTargetLowering::ReplaceNodeResults(SDNode *N, 724 SmallVectorImpl<SDValue> &Results, 725 SelectionDAG &DAG) const { 726 return LowerOperationWrapper(N, Results, DAG); 727} 728 729SDValue MipsTargetLowering:: 730LowerOperation(SDValue Op, SelectionDAG &DAG) const 731{ 732 switch (Op.getOpcode()) 733 { 734 case ISD::BR_JT: return lowerBR_JT(Op, DAG); 735 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 736 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 737 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 738 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 739 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 740 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 741 case ISD::SELECT: return lowerSELECT(Op, DAG); 742 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG); 743 case ISD::SETCC: return lowerSETCC(Op, DAG); 744 case ISD::VASTART: return lowerVASTART(Op, DAG); 745 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 746 case ISD::FABS: return lowerFABS(Op, DAG); 747 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 748 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 749 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 750 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 751 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 752 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 753 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 754 case ISD::LOAD: return lowerLOAD(Op, DAG); 755 case ISD::STORE: return lowerSTORE(Op, DAG); 756 case ISD::ADD: return lowerADD(Op, DAG); 757 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 758 } 759 return SDValue(); 760} 761 762//===----------------------------------------------------------------------===// 763// Lower helper functions 764//===----------------------------------------------------------------------===// 765 766// addLiveIn - This helper function adds the specified physical register to the 767// MachineFunction as a live in value. It also creates a corresponding 768// virtual register for it. 769static unsigned 770addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 771{ 772 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 773 MF.getRegInfo().addLiveIn(PReg, VReg); 774 return VReg; 775} 776 777static MachineBasicBlock *expandPseudoDIV(MachineInstr *MI, 778 MachineBasicBlock &MBB, 779 const TargetInstrInfo &TII, 780 bool Is64Bit) { 781 if (NoZeroDivCheck) 782 return &MBB; 783 784 // Insert instruction "teq $divisor_reg, $zero, 7". 785 MachineBasicBlock::iterator I(MI); 786 MachineInstrBuilder MIB; 787 MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ)) 788 .addOperand(MI->getOperand(2)).addReg(Mips::ZERO).addImm(7); 789 790 // Use the 32-bit sub-register if this is a 64-bit division. 791 if (Is64Bit) 792 MIB->getOperand(0).setSubReg(Mips::sub_32); 793 794 return &MBB; 795} 796 797MachineBasicBlock * 798MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 799 MachineBasicBlock *BB) const { 800 switch (MI->getOpcode()) { 801 default: 802 llvm_unreachable("Unexpected instr type to insert"); 803 case Mips::ATOMIC_LOAD_ADD_I8: 804 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 805 case Mips::ATOMIC_LOAD_ADD_I16: 806 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 807 case Mips::ATOMIC_LOAD_ADD_I32: 808 return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 809 case Mips::ATOMIC_LOAD_ADD_I64: 810 return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 811 812 case Mips::ATOMIC_LOAD_AND_I8: 813 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 814 case Mips::ATOMIC_LOAD_AND_I16: 815 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 816 case Mips::ATOMIC_LOAD_AND_I32: 817 return emitAtomicBinary(MI, BB, 4, Mips::AND); 818 case Mips::ATOMIC_LOAD_AND_I64: 819 return emitAtomicBinary(MI, BB, 8, Mips::AND64); 820 821 case Mips::ATOMIC_LOAD_OR_I8: 822 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 823 case Mips::ATOMIC_LOAD_OR_I16: 824 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 825 case Mips::ATOMIC_LOAD_OR_I32: 826 return emitAtomicBinary(MI, BB, 4, Mips::OR); 827 case Mips::ATOMIC_LOAD_OR_I64: 828 return emitAtomicBinary(MI, BB, 8, Mips::OR64); 829 830 case Mips::ATOMIC_LOAD_XOR_I8: 831 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 832 case Mips::ATOMIC_LOAD_XOR_I16: 833 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 834 case Mips::ATOMIC_LOAD_XOR_I32: 835 return emitAtomicBinary(MI, BB, 4, Mips::XOR); 836 case Mips::ATOMIC_LOAD_XOR_I64: 837 return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 838 839 case Mips::ATOMIC_LOAD_NAND_I8: 840 return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 841 case Mips::ATOMIC_LOAD_NAND_I16: 842 return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 843 case Mips::ATOMIC_LOAD_NAND_I32: 844 return emitAtomicBinary(MI, BB, 4, 0, true); 845 case Mips::ATOMIC_LOAD_NAND_I64: 846 return emitAtomicBinary(MI, BB, 8, 0, true); 847 848 case Mips::ATOMIC_LOAD_SUB_I8: 849 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 850 case Mips::ATOMIC_LOAD_SUB_I16: 851 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 852 case Mips::ATOMIC_LOAD_SUB_I32: 853 return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 854 case Mips::ATOMIC_LOAD_SUB_I64: 855 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 856 857 case Mips::ATOMIC_SWAP_I8: 858 return emitAtomicBinaryPartword(MI, BB, 1, 0); 859 case Mips::ATOMIC_SWAP_I16: 860 return emitAtomicBinaryPartword(MI, BB, 2, 0); 861 case Mips::ATOMIC_SWAP_I32: 862 return emitAtomicBinary(MI, BB, 4, 0); 863 case Mips::ATOMIC_SWAP_I64: 864 return emitAtomicBinary(MI, BB, 8, 0); 865 866 case Mips::ATOMIC_CMP_SWAP_I8: 867 return emitAtomicCmpSwapPartword(MI, BB, 1); 868 case Mips::ATOMIC_CMP_SWAP_I16: 869 return emitAtomicCmpSwapPartword(MI, BB, 2); 870 case Mips::ATOMIC_CMP_SWAP_I32: 871 return emitAtomicCmpSwap(MI, BB, 4); 872 case Mips::ATOMIC_CMP_SWAP_I64: 873 return emitAtomicCmpSwap(MI, BB, 8); 874 case Mips::PseudoSDIV: 875 case Mips::PseudoUDIV: 876 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), false); 877 case Mips::PseudoDSDIV: 878 case Mips::PseudoDUDIV: 879 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), true); 880 } 881} 882 883// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 884// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 885MachineBasicBlock * 886MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 887 unsigned Size, unsigned BinOpcode, 888 bool Nand) const { 889 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 890 891 MachineFunction *MF = BB->getParent(); 892 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 893 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 894 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 895 DebugLoc DL = MI->getDebugLoc(); 896 unsigned LL, SC, AND, NOR, ZERO, BEQ; 897 898 if (Size == 4) { 899 LL = Mips::LL; 900 SC = Mips::SC; 901 AND = Mips::AND; 902 NOR = Mips::NOR; 903 ZERO = Mips::ZERO; 904 BEQ = Mips::BEQ; 905 } 906 else { 907 LL = Mips::LLD; 908 SC = Mips::SCD; 909 AND = Mips::AND64; 910 NOR = Mips::NOR64; 911 ZERO = Mips::ZERO_64; 912 BEQ = Mips::BEQ64; 913 } 914 915 unsigned OldVal = MI->getOperand(0).getReg(); 916 unsigned Ptr = MI->getOperand(1).getReg(); 917 unsigned Incr = MI->getOperand(2).getReg(); 918 919 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 920 unsigned AndRes = RegInfo.createVirtualRegister(RC); 921 unsigned Success = RegInfo.createVirtualRegister(RC); 922 923 // insert new blocks after the current block 924 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 925 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 926 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 927 MachineFunction::iterator It = BB; 928 ++It; 929 MF->insert(It, loopMBB); 930 MF->insert(It, exitMBB); 931 932 // Transfer the remainder of BB and its successor edges to exitMBB. 933 exitMBB->splice(exitMBB->begin(), BB, 934 llvm::next(MachineBasicBlock::iterator(MI)), 935 BB->end()); 936 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 937 938 // thisMBB: 939 // ... 940 // fallthrough --> loopMBB 941 BB->addSuccessor(loopMBB); 942 loopMBB->addSuccessor(loopMBB); 943 loopMBB->addSuccessor(exitMBB); 944 945 // loopMBB: 946 // ll oldval, 0(ptr) 947 // <binop> storeval, oldval, incr 948 // sc success, storeval, 0(ptr) 949 // beq success, $0, loopMBB 950 BB = loopMBB; 951 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 952 if (Nand) { 953 // and andres, oldval, incr 954 // nor storeval, $0, andres 955 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 956 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 957 } else if (BinOpcode) { 958 // <binop> storeval, oldval, incr 959 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 960 } else { 961 StoreVal = Incr; 962 } 963 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 964 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 965 966 MI->eraseFromParent(); // The instruction is gone now. 967 968 return exitMBB; 969} 970 971MachineBasicBlock * 972MipsTargetLowering::emitAtomicBinaryPartword(MachineInstr *MI, 973 MachineBasicBlock *BB, 974 unsigned Size, unsigned BinOpcode, 975 bool Nand) const { 976 assert((Size == 1 || Size == 2) && 977 "Unsupported size for EmitAtomicBinaryPartial."); 978 979 MachineFunction *MF = BB->getParent(); 980 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 981 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 982 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 983 DebugLoc DL = MI->getDebugLoc(); 984 985 unsigned Dest = MI->getOperand(0).getReg(); 986 unsigned Ptr = MI->getOperand(1).getReg(); 987 unsigned Incr = MI->getOperand(2).getReg(); 988 989 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 990 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 991 unsigned Mask = RegInfo.createVirtualRegister(RC); 992 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 993 unsigned NewVal = RegInfo.createVirtualRegister(RC); 994 unsigned OldVal = RegInfo.createVirtualRegister(RC); 995 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 996 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 997 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 998 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 999 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1000 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1001 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1002 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1003 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1004 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1005 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1006 unsigned Success = RegInfo.createVirtualRegister(RC); 1007 1008 // insert new blocks after the current block 1009 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1010 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1011 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1012 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1013 MachineFunction::iterator It = BB; 1014 ++It; 1015 MF->insert(It, loopMBB); 1016 MF->insert(It, sinkMBB); 1017 MF->insert(It, exitMBB); 1018 1019 // Transfer the remainder of BB and its successor edges to exitMBB. 1020 exitMBB->splice(exitMBB->begin(), BB, 1021 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1022 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1023 1024 BB->addSuccessor(loopMBB); 1025 loopMBB->addSuccessor(loopMBB); 1026 loopMBB->addSuccessor(sinkMBB); 1027 sinkMBB->addSuccessor(exitMBB); 1028 1029 // thisMBB: 1030 // addiu masklsb2,$0,-4 # 0xfffffffc 1031 // and alignedaddr,ptr,masklsb2 1032 // andi ptrlsb2,ptr,3 1033 // sll shiftamt,ptrlsb2,3 1034 // ori maskupper,$0,255 # 0xff 1035 // sll mask,maskupper,shiftamt 1036 // nor mask2,$0,mask 1037 // sll incr2,incr,shiftamt 1038 1039 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1040 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1041 .addReg(Mips::ZERO).addImm(-4); 1042 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1043 .addReg(Ptr).addReg(MaskLSB2); 1044 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1045 if (Subtarget->isLittle()) { 1046 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1047 } else { 1048 unsigned Off = RegInfo.createVirtualRegister(RC); 1049 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1050 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1051 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1052 } 1053 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1054 .addReg(Mips::ZERO).addImm(MaskImm); 1055 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1056 .addReg(MaskUpper).addReg(ShiftAmt); 1057 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1058 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1059 1060 // atomic.load.binop 1061 // loopMBB: 1062 // ll oldval,0(alignedaddr) 1063 // binop binopres,oldval,incr2 1064 // and newval,binopres,mask 1065 // and maskedoldval0,oldval,mask2 1066 // or storeval,maskedoldval0,newval 1067 // sc success,storeval,0(alignedaddr) 1068 // beq success,$0,loopMBB 1069 1070 // atomic.swap 1071 // loopMBB: 1072 // ll oldval,0(alignedaddr) 1073 // and newval,incr2,mask 1074 // and maskedoldval0,oldval,mask2 1075 // or storeval,maskedoldval0,newval 1076 // sc success,storeval,0(alignedaddr) 1077 // beq success,$0,loopMBB 1078 1079 BB = loopMBB; 1080 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1081 if (Nand) { 1082 // and andres, oldval, incr2 1083 // nor binopres, $0, andres 1084 // and newval, binopres, mask 1085 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1086 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1087 .addReg(Mips::ZERO).addReg(AndRes); 1088 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1089 } else if (BinOpcode) { 1090 // <binop> binopres, oldval, incr2 1091 // and newval, binopres, mask 1092 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1093 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1094 } else {// atomic.swap 1095 // and newval, incr2, mask 1096 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1097 } 1098 1099 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1100 .addReg(OldVal).addReg(Mask2); 1101 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1102 .addReg(MaskedOldVal0).addReg(NewVal); 1103 BuildMI(BB, DL, TII->get(Mips::SC), Success) 1104 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1105 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1106 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1107 1108 // sinkMBB: 1109 // and maskedoldval1,oldval,mask 1110 // srl srlres,maskedoldval1,shiftamt 1111 // sll sllres,srlres,24 1112 // sra dest,sllres,24 1113 BB = sinkMBB; 1114 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1115 1116 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1117 .addReg(OldVal).addReg(Mask); 1118 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1119 .addReg(MaskedOldVal1).addReg(ShiftAmt); 1120 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes) 1121 .addReg(SrlRes).addImm(ShiftImm); 1122 BuildMI(BB, DL, TII->get(Mips::SRA), Dest) 1123 .addReg(SllRes).addImm(ShiftImm); 1124 1125 MI->eraseFromParent(); // The instruction is gone now. 1126 1127 return exitMBB; 1128} 1129 1130MachineBasicBlock * 1131MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI, 1132 MachineBasicBlock *BB, 1133 unsigned Size) const { 1134 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1135 1136 MachineFunction *MF = BB->getParent(); 1137 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1138 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1139 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1140 DebugLoc DL = MI->getDebugLoc(); 1141 unsigned LL, SC, ZERO, BNE, BEQ; 1142 1143 if (Size == 4) { 1144 LL = Mips::LL; 1145 SC = Mips::SC; 1146 ZERO = Mips::ZERO; 1147 BNE = Mips::BNE; 1148 BEQ = Mips::BEQ; 1149 } 1150 else { 1151 LL = Mips::LLD; 1152 SC = Mips::SCD; 1153 ZERO = Mips::ZERO_64; 1154 BNE = Mips::BNE64; 1155 BEQ = Mips::BEQ64; 1156 } 1157 1158 unsigned Dest = MI->getOperand(0).getReg(); 1159 unsigned Ptr = MI->getOperand(1).getReg(); 1160 unsigned OldVal = MI->getOperand(2).getReg(); 1161 unsigned NewVal = MI->getOperand(3).getReg(); 1162 1163 unsigned Success = RegInfo.createVirtualRegister(RC); 1164 1165 // insert new blocks after the current block 1166 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1167 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1168 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1169 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1170 MachineFunction::iterator It = BB; 1171 ++It; 1172 MF->insert(It, loop1MBB); 1173 MF->insert(It, loop2MBB); 1174 MF->insert(It, exitMBB); 1175 1176 // Transfer the remainder of BB and its successor edges to exitMBB. 1177 exitMBB->splice(exitMBB->begin(), BB, 1178 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1179 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1180 1181 // thisMBB: 1182 // ... 1183 // fallthrough --> loop1MBB 1184 BB->addSuccessor(loop1MBB); 1185 loop1MBB->addSuccessor(exitMBB); 1186 loop1MBB->addSuccessor(loop2MBB); 1187 loop2MBB->addSuccessor(loop1MBB); 1188 loop2MBB->addSuccessor(exitMBB); 1189 1190 // loop1MBB: 1191 // ll dest, 0(ptr) 1192 // bne dest, oldval, exitMBB 1193 BB = loop1MBB; 1194 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1195 BuildMI(BB, DL, TII->get(BNE)) 1196 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1197 1198 // loop2MBB: 1199 // sc success, newval, 0(ptr) 1200 // beq success, $0, loop1MBB 1201 BB = loop2MBB; 1202 BuildMI(BB, DL, TII->get(SC), Success) 1203 .addReg(NewVal).addReg(Ptr).addImm(0); 1204 BuildMI(BB, DL, TII->get(BEQ)) 1205 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1206 1207 MI->eraseFromParent(); // The instruction is gone now. 1208 1209 return exitMBB; 1210} 1211 1212MachineBasicBlock * 1213MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, 1214 MachineBasicBlock *BB, 1215 unsigned Size) const { 1216 assert((Size == 1 || Size == 2) && 1217 "Unsupported size for EmitAtomicCmpSwapPartial."); 1218 1219 MachineFunction *MF = BB->getParent(); 1220 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1221 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1222 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1223 DebugLoc DL = MI->getDebugLoc(); 1224 1225 unsigned Dest = MI->getOperand(0).getReg(); 1226 unsigned Ptr = MI->getOperand(1).getReg(); 1227 unsigned CmpVal = MI->getOperand(2).getReg(); 1228 unsigned NewVal = MI->getOperand(3).getReg(); 1229 1230 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1231 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1232 unsigned Mask = RegInfo.createVirtualRegister(RC); 1233 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1234 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1235 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1236 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1237 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1238 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1239 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1240 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1241 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1242 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1243 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1244 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1245 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1246 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1247 unsigned Success = RegInfo.createVirtualRegister(RC); 1248 1249 // insert new blocks after the current block 1250 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1251 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1252 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1253 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1254 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1255 MachineFunction::iterator It = BB; 1256 ++It; 1257 MF->insert(It, loop1MBB); 1258 MF->insert(It, loop2MBB); 1259 MF->insert(It, sinkMBB); 1260 MF->insert(It, exitMBB); 1261 1262 // Transfer the remainder of BB and its successor edges to exitMBB. 1263 exitMBB->splice(exitMBB->begin(), BB, 1264 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1265 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1266 1267 BB->addSuccessor(loop1MBB); 1268 loop1MBB->addSuccessor(sinkMBB); 1269 loop1MBB->addSuccessor(loop2MBB); 1270 loop2MBB->addSuccessor(loop1MBB); 1271 loop2MBB->addSuccessor(sinkMBB); 1272 sinkMBB->addSuccessor(exitMBB); 1273 1274 // FIXME: computation of newval2 can be moved to loop2MBB. 1275 // thisMBB: 1276 // addiu masklsb2,$0,-4 # 0xfffffffc 1277 // and alignedaddr,ptr,masklsb2 1278 // andi ptrlsb2,ptr,3 1279 // sll shiftamt,ptrlsb2,3 1280 // ori maskupper,$0,255 # 0xff 1281 // sll mask,maskupper,shiftamt 1282 // nor mask2,$0,mask 1283 // andi maskedcmpval,cmpval,255 1284 // sll shiftedcmpval,maskedcmpval,shiftamt 1285 // andi maskednewval,newval,255 1286 // sll shiftednewval,maskednewval,shiftamt 1287 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1288 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1289 .addReg(Mips::ZERO).addImm(-4); 1290 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1291 .addReg(Ptr).addReg(MaskLSB2); 1292 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1293 if (Subtarget->isLittle()) { 1294 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1295 } else { 1296 unsigned Off = RegInfo.createVirtualRegister(RC); 1297 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1298 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1299 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1300 } 1301 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1302 .addReg(Mips::ZERO).addImm(MaskImm); 1303 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1304 .addReg(MaskUpper).addReg(ShiftAmt); 1305 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1306 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1307 .addReg(CmpVal).addImm(MaskImm); 1308 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1309 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1310 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1311 .addReg(NewVal).addImm(MaskImm); 1312 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1313 .addReg(MaskedNewVal).addReg(ShiftAmt); 1314 1315 // loop1MBB: 1316 // ll oldval,0(alginedaddr) 1317 // and maskedoldval0,oldval,mask 1318 // bne maskedoldval0,shiftedcmpval,sinkMBB 1319 BB = loop1MBB; 1320 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1321 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1322 .addReg(OldVal).addReg(Mask); 1323 BuildMI(BB, DL, TII->get(Mips::BNE)) 1324 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1325 1326 // loop2MBB: 1327 // and maskedoldval1,oldval,mask2 1328 // or storeval,maskedoldval1,shiftednewval 1329 // sc success,storeval,0(alignedaddr) 1330 // beq success,$0,loop1MBB 1331 BB = loop2MBB; 1332 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1333 .addReg(OldVal).addReg(Mask2); 1334 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1335 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1336 BuildMI(BB, DL, TII->get(Mips::SC), Success) 1337 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1338 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1339 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1340 1341 // sinkMBB: 1342 // srl srlres,maskedoldval0,shiftamt 1343 // sll sllres,srlres,24 1344 // sra dest,sllres,24 1345 BB = sinkMBB; 1346 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1347 1348 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1349 .addReg(MaskedOldVal0).addReg(ShiftAmt); 1350 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes) 1351 .addReg(SrlRes).addImm(ShiftImm); 1352 BuildMI(BB, DL, TII->get(Mips::SRA), Dest) 1353 .addReg(SllRes).addImm(ShiftImm); 1354 1355 MI->eraseFromParent(); // The instruction is gone now. 1356 1357 return exitMBB; 1358} 1359 1360//===----------------------------------------------------------------------===// 1361// Misc Lower Operation implementation 1362//===----------------------------------------------------------------------===// 1363SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 1364 SDValue Chain = Op.getOperand(0); 1365 SDValue Table = Op.getOperand(1); 1366 SDValue Index = Op.getOperand(2); 1367 SDLoc DL(Op); 1368 EVT PTy = getPointerTy(); 1369 unsigned EntrySize = 1370 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout()); 1371 1372 Index = DAG.getNode(ISD::MUL, DL, PTy, Index, 1373 DAG.getConstant(EntrySize, PTy)); 1374 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table); 1375 1376 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 1377 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr, 1378 MachinePointerInfo::getJumpTable(), MemVT, false, false, 1379 0); 1380 Chain = Addr.getValue(1); 1381 1382 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) { 1383 // For PIC, the sequence is: 1384 // BRIND(load(Jumptable + index) + RelocBase) 1385 // RelocBase can be JumpTable, GOT or some sort of global base. 1386 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr, 1387 getPICJumpTableRelocBase(Table, DAG)); 1388 } 1389 1390 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr); 1391} 1392 1393SDValue MipsTargetLowering:: 1394lowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1395{ 1396 // The first operand is the chain, the second is the condition, the third is 1397 // the block to branch to if the condition is true. 1398 SDValue Chain = Op.getOperand(0); 1399 SDValue Dest = Op.getOperand(2); 1400 SDLoc DL(Op); 1401 1402 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1403 1404 // Return if flag is not set by a floating point comparison. 1405 if (CondRes.getOpcode() != MipsISD::FPCmp) 1406 return Op; 1407 1408 SDValue CCNode = CondRes.getOperand(2); 1409 Mips::CondCode CC = 1410 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1411 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1412 SDValue BrCode = DAG.getConstant(Opc, MVT::i32); 1413 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1414 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1415 FCC0, Dest, CondRes); 1416} 1417 1418SDValue MipsTargetLowering:: 1419lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1420{ 1421 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1422 1423 // Return if flag is not set by a floating point comparison. 1424 if (Cond.getOpcode() != MipsISD::FPCmp) 1425 return Op; 1426 1427 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1428 SDLoc(Op)); 1429} 1430 1431SDValue MipsTargetLowering:: 1432lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 1433{ 1434 SDLoc DL(Op); 1435 EVT Ty = Op.getOperand(0).getValueType(); 1436 SDValue Cond = DAG.getNode(ISD::SETCC, DL, 1437 getSetCCResultType(*DAG.getContext(), Ty), 1438 Op.getOperand(0), Op.getOperand(1), 1439 Op.getOperand(4)); 1440 1441 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2), 1442 Op.getOperand(3)); 1443} 1444 1445SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1446 SDValue Cond = createFPCmp(DAG, Op); 1447 1448 assert(Cond.getOpcode() == MipsISD::FPCmp && 1449 "Floating point operand expected."); 1450 1451 SDValue True = DAG.getConstant(1, MVT::i32); 1452 SDValue False = DAG.getConstant(0, MVT::i32); 1453 1454 return createCMovFP(DAG, Cond, True, False, SDLoc(Op)); 1455} 1456 1457SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 1458 SelectionDAG &DAG) const { 1459 // FIXME there isn't actually debug info here 1460 SDLoc DL(Op); 1461 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1462 1463 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1464 const MipsTargetObjectFile &TLOF = 1465 (const MipsTargetObjectFile&)getObjFileLowering(); 1466 1467 // %gp_rel relocation 1468 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1469 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0, 1470 MipsII::MO_GPREL); 1471 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL, 1472 DAG.getVTList(MVT::i32), &GA, 1); 1473 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32); 1474 return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode); 1475 } 1476 1477 // %hi/%lo relocation 1478 return getAddrNonPIC(Op, DAG); 1479 } 1480 1481 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV))) 1482 return getAddrLocal(Op, DAG, HasMips64); 1483 1484 if (LargeGOT) 1485 return getAddrGlobalLargeGOT(Op, DAG, MipsII::MO_GOT_HI16, 1486 MipsII::MO_GOT_LO16); 1487 1488 return getAddrGlobal(Op, DAG, 1489 HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16); 1490} 1491 1492SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 1493 SelectionDAG &DAG) const { 1494 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1495 return getAddrNonPIC(Op, DAG); 1496 1497 return getAddrLocal(Op, DAG, HasMips64); 1498} 1499 1500SDValue MipsTargetLowering:: 1501lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1502{ 1503 // If the relocation model is PIC, use the General Dynamic TLS Model or 1504 // Local Dynamic TLS model, otherwise use the Initial Exec or 1505 // Local Exec TLS Model. 1506 1507 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1508 SDLoc DL(GA); 1509 const GlobalValue *GV = GA->getGlobal(); 1510 EVT PtrVT = getPointerTy(); 1511 1512 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1513 1514 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1515 // General Dynamic and Local Dynamic TLS Model. 1516 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1517 : MipsII::MO_TLSGD; 1518 1519 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 1520 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 1521 getGlobalReg(DAG, PtrVT), TGA); 1522 unsigned PtrSize = PtrVT.getSizeInBits(); 1523 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1524 1525 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1526 1527 ArgListTy Args; 1528 ArgListEntry Entry; 1529 Entry.Node = Argument; 1530 Entry.Ty = PtrTy; 1531 Args.push_back(Entry); 1532 1533 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy, 1534 false, false, false, false, 0, CallingConv::C, 1535 /*IsTailCall=*/false, /*doesNotRet=*/false, 1536 /*isReturnValueUsed=*/true, 1537 TlsGetAddr, Args, DAG, DL); 1538 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1539 1540 SDValue Ret = CallResult.first; 1541 1542 if (model != TLSModel::LocalDynamic) 1543 return Ret; 1544 1545 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1546 MipsII::MO_DTPREL_HI); 1547 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1548 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1549 MipsII::MO_DTPREL_LO); 1550 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1551 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 1552 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 1553 } 1554 1555 SDValue Offset; 1556 if (model == TLSModel::InitialExec) { 1557 // Initial Exec TLS Model 1558 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1559 MipsII::MO_GOTTPREL); 1560 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 1561 TGA); 1562 Offset = DAG.getLoad(PtrVT, DL, 1563 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1564 false, false, false, 0); 1565 } else { 1566 // Local Exec TLS Model 1567 assert(model == TLSModel::LocalExec); 1568 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1569 MipsII::MO_TPREL_HI); 1570 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1571 MipsII::MO_TPREL_LO); 1572 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1573 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1574 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1575 } 1576 1577 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 1578 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 1579} 1580 1581SDValue MipsTargetLowering:: 1582lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1583{ 1584 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1585 return getAddrNonPIC(Op, DAG); 1586 1587 return getAddrLocal(Op, DAG, HasMips64); 1588} 1589 1590SDValue MipsTargetLowering:: 1591lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1592{ 1593 // gp_rel relocation 1594 // FIXME: we should reference the constant pool using small data sections, 1595 // but the asm printer currently doesn't support this feature without 1596 // hacking it. This feature should come soon so we can uncomment the 1597 // stuff below. 1598 //if (IsInSmallSection(C->getType())) { 1599 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1600 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1601 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1602 1603 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1604 return getAddrNonPIC(Op, DAG); 1605 1606 return getAddrLocal(Op, DAG, HasMips64); 1607} 1608 1609SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1610 MachineFunction &MF = DAG.getMachineFunction(); 1611 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1612 1613 SDLoc DL(Op); 1614 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1615 getPointerTy()); 1616 1617 // vastart just stores the address of the VarArgsFrameIndex slot into the 1618 // memory location argument. 1619 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1620 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 1621 MachinePointerInfo(SV), false, false, 0); 1622} 1623 1624static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1625 EVT TyX = Op.getOperand(0).getValueType(); 1626 EVT TyY = Op.getOperand(1).getValueType(); 1627 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1628 SDValue Const31 = DAG.getConstant(31, MVT::i32); 1629 SDLoc DL(Op); 1630 SDValue Res; 1631 1632 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1633 // to i32. 1634 SDValue X = (TyX == MVT::f32) ? 1635 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1636 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1637 Const1); 1638 SDValue Y = (TyY == MVT::f32) ? 1639 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 1640 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 1641 Const1); 1642 1643 if (HasR2) { 1644 // ext E, Y, 31, 1 ; extract bit31 of Y 1645 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 1646 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 1647 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 1648 } else { 1649 // sll SllX, X, 1 1650 // srl SrlX, SllX, 1 1651 // srl SrlY, Y, 31 1652 // sll SllY, SrlX, 31 1653 // or Or, SrlX, SllY 1654 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1655 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1656 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 1657 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 1658 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 1659 } 1660 1661 if (TyX == MVT::f32) 1662 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 1663 1664 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1665 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1666 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1667} 1668 1669static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1670 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 1671 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 1672 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 1673 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1674 SDLoc DL(Op); 1675 1676 // Bitcast to integer nodes. 1677 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 1678 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 1679 1680 if (HasR2) { 1681 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 1682 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 1683 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 1684 DAG.getConstant(WidthY - 1, MVT::i32), Const1); 1685 1686 if (WidthX > WidthY) 1687 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 1688 else if (WidthY > WidthX) 1689 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 1690 1691 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 1692 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X); 1693 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 1694 } 1695 1696 // (d)sll SllX, X, 1 1697 // (d)srl SrlX, SllX, 1 1698 // (d)srl SrlY, Y, width(Y)-1 1699 // (d)sll SllY, SrlX, width(Y)-1 1700 // or Or, SrlX, SllY 1701 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 1702 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 1703 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 1704 DAG.getConstant(WidthY - 1, MVT::i32)); 1705 1706 if (WidthX > WidthY) 1707 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 1708 else if (WidthY > WidthX) 1709 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 1710 1711 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 1712 DAG.getConstant(WidthX - 1, MVT::i32)); 1713 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 1714 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 1715} 1716 1717SDValue 1718MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 1719 if (Subtarget->hasMips64()) 1720 return lowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2()); 1721 1722 return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2()); 1723} 1724 1725static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1726 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1727 SDLoc DL(Op); 1728 1729 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1730 // to i32. 1731 SDValue X = (Op.getValueType() == MVT::f32) ? 1732 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1733 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1734 Const1); 1735 1736 // Clear MSB. 1737 if (HasR2) 1738 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 1739 DAG.getRegister(Mips::ZERO, MVT::i32), 1740 DAG.getConstant(31, MVT::i32), Const1, X); 1741 else { 1742 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1743 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1744 } 1745 1746 if (Op.getValueType() == MVT::f32) 1747 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 1748 1749 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1750 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1751 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1752} 1753 1754static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1755 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1756 SDLoc DL(Op); 1757 1758 // Bitcast to integer node. 1759 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 1760 1761 // Clear MSB. 1762 if (HasR2) 1763 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 1764 DAG.getRegister(Mips::ZERO_64, MVT::i64), 1765 DAG.getConstant(63, MVT::i32), Const1, X); 1766 else { 1767 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 1768 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 1769 } 1770 1771 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 1772} 1773 1774SDValue 1775MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const { 1776 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64)) 1777 return lowerFABS64(Op, DAG, Subtarget->hasMips32r2()); 1778 1779 return lowerFABS32(Op, DAG, Subtarget->hasMips32r2()); 1780} 1781 1782SDValue MipsTargetLowering:: 1783lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1784 // check the depth 1785 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1786 "Frame address can only be determined for current frame."); 1787 1788 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1789 MFI->setFrameAddressIsTaken(true); 1790 EVT VT = Op.getValueType(); 1791 SDLoc DL(Op); 1792 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, 1793 IsN64 ? Mips::FP_64 : Mips::FP, VT); 1794 return FrameAddr; 1795} 1796 1797SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 1798 SelectionDAG &DAG) const { 1799 // check the depth 1800 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1801 "Return address can be determined only for current frame."); 1802 1803 MachineFunction &MF = DAG.getMachineFunction(); 1804 MachineFrameInfo *MFI = MF.getFrameInfo(); 1805 MVT VT = Op.getSimpleValueType(); 1806 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA; 1807 MFI->setReturnAddressIsTaken(true); 1808 1809 // Return RA, which contains the return address. Mark it an implicit live-in. 1810 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 1811 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 1812} 1813 1814// An EH_RETURN is the result of lowering llvm.eh.return which in turn is 1815// generated from __builtin_eh_return (offset, handler) 1816// The effect of this is to adjust the stack pointer by "offset" 1817// and then branch to "handler". 1818SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 1819 const { 1820 MachineFunction &MF = DAG.getMachineFunction(); 1821 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1822 1823 MipsFI->setCallsEhReturn(); 1824 SDValue Chain = Op.getOperand(0); 1825 SDValue Offset = Op.getOperand(1); 1826 SDValue Handler = Op.getOperand(2); 1827 SDLoc DL(Op); 1828 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 1829 1830 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 1831 // EH_RETURN nodes, so that instructions are emitted back-to-back. 1832 unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1; 1833 unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0; 1834 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 1835 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 1836 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 1837 DAG.getRegister(OffsetReg, Ty), 1838 DAG.getRegister(AddrReg, getPointerTy()), 1839 Chain.getValue(1)); 1840} 1841 1842SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 1843 SelectionDAG &DAG) const { 1844 // FIXME: Need pseudo-fence for 'singlethread' fences 1845 // FIXME: Set SType for weaker fences where supported/appropriate. 1846 unsigned SType = 0; 1847 SDLoc DL(Op); 1848 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 1849 DAG.getConstant(SType, MVT::i32)); 1850} 1851 1852SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 1853 SelectionDAG &DAG) const { 1854 SDLoc DL(Op); 1855 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 1856 SDValue Shamt = Op.getOperand(2); 1857 1858 // if shamt < 32: 1859 // lo = (shl lo, shamt) 1860 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 1861 // else: 1862 // lo = 0 1863 // hi = (shl lo, shamt[4:0]) 1864 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 1865 DAG.getConstant(-1, MVT::i32)); 1866 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, 1867 DAG.getConstant(1, MVT::i32)); 1868 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, 1869 Not); 1870 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); 1871 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 1872 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); 1873 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 1874 DAG.getConstant(0x20, MVT::i32)); 1875 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 1876 DAG.getConstant(0, MVT::i32), ShiftLeftLo); 1877 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or); 1878 1879 SDValue Ops[2] = {Lo, Hi}; 1880 return DAG.getMergeValues(Ops, 2, DL); 1881} 1882 1883SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 1884 bool IsSRA) const { 1885 SDLoc DL(Op); 1886 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 1887 SDValue Shamt = Op.getOperand(2); 1888 1889 // if shamt < 32: 1890 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 1891 // if isSRA: 1892 // hi = (sra hi, shamt) 1893 // else: 1894 // hi = (srl hi, shamt) 1895 // else: 1896 // if isSRA: 1897 // lo = (sra hi, shamt[4:0]) 1898 // hi = (sra hi, 31) 1899 // else: 1900 // lo = (srl hi, shamt[4:0]) 1901 // hi = 0 1902 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 1903 DAG.getConstant(-1, MVT::i32)); 1904 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, 1905 DAG.getConstant(1, MVT::i32)); 1906 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not); 1907 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); 1908 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 1909 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, 1910 Hi, Shamt); 1911 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 1912 DAG.getConstant(0x20, MVT::i32)); 1913 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi, 1914 DAG.getConstant(31, MVT::i32)); 1915 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or); 1916 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 1917 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32), 1918 ShiftRightHi); 1919 1920 SDValue Ops[2] = {Lo, Hi}; 1921 return DAG.getMergeValues(Ops, 2, DL); 1922} 1923 1924static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 1925 SDValue Chain, SDValue Src, unsigned Offset) { 1926 SDValue Ptr = LD->getBasePtr(); 1927 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 1928 EVT BasePtrVT = Ptr.getValueType(); 1929 SDLoc DL(LD); 1930 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 1931 1932 if (Offset) 1933 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 1934 DAG.getConstant(Offset, BasePtrVT)); 1935 1936 SDValue Ops[] = { Chain, Ptr, Src }; 1937 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 1938 LD->getMemOperand()); 1939} 1940 1941// Expand an unaligned 32 or 64-bit integer load node. 1942SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 1943 LoadSDNode *LD = cast<LoadSDNode>(Op); 1944 EVT MemVT = LD->getMemoryVT(); 1945 1946 // Return if load is aligned or if MemVT is neither i32 nor i64. 1947 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 1948 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 1949 return SDValue(); 1950 1951 bool IsLittle = Subtarget->isLittle(); 1952 EVT VT = Op.getValueType(); 1953 ISD::LoadExtType ExtType = LD->getExtensionType(); 1954 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 1955 1956 assert((VT == MVT::i32) || (VT == MVT::i64)); 1957 1958 // Expand 1959 // (set dst, (i64 (load baseptr))) 1960 // to 1961 // (set tmp, (ldl (add baseptr, 7), undef)) 1962 // (set dst, (ldr baseptr, tmp)) 1963 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 1964 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 1965 IsLittle ? 7 : 0); 1966 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 1967 IsLittle ? 0 : 7); 1968 } 1969 1970 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 1971 IsLittle ? 3 : 0); 1972 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 1973 IsLittle ? 0 : 3); 1974 1975 // Expand 1976 // (set dst, (i32 (load baseptr))) or 1977 // (set dst, (i64 (sextload baseptr))) or 1978 // (set dst, (i64 (extload baseptr))) 1979 // to 1980 // (set tmp, (lwl (add baseptr, 3), undef)) 1981 // (set dst, (lwr baseptr, tmp)) 1982 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 1983 (ExtType == ISD::EXTLOAD)) 1984 return LWR; 1985 1986 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 1987 1988 // Expand 1989 // (set dst, (i64 (zextload baseptr))) 1990 // to 1991 // (set tmp0, (lwl (add baseptr, 3), undef)) 1992 // (set tmp1, (lwr baseptr, tmp0)) 1993 // (set tmp2, (shl tmp1, 32)) 1994 // (set dst, (srl tmp2, 32)) 1995 SDLoc DL(LD); 1996 SDValue Const32 = DAG.getConstant(32, MVT::i32); 1997 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 1998 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 1999 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2000 return DAG.getMergeValues(Ops, 2, DL); 2001} 2002 2003static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2004 SDValue Chain, unsigned Offset) { 2005 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2006 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2007 SDLoc DL(SD); 2008 SDVTList VTList = DAG.getVTList(MVT::Other); 2009 2010 if (Offset) 2011 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2012 DAG.getConstant(Offset, BasePtrVT)); 2013 2014 SDValue Ops[] = { Chain, Value, Ptr }; 2015 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2016 SD->getMemOperand()); 2017} 2018 2019// Expand an unaligned 32 or 64-bit integer store node. 2020static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2021 bool IsLittle) { 2022 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2023 EVT VT = Value.getValueType(); 2024 2025 // Expand 2026 // (store val, baseptr) or 2027 // (truncstore val, baseptr) 2028 // to 2029 // (swl val, (add baseptr, 3)) 2030 // (swr val, baseptr) 2031 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2032 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2033 IsLittle ? 3 : 0); 2034 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2035 } 2036 2037 assert(VT == MVT::i64); 2038 2039 // Expand 2040 // (store val, baseptr) 2041 // to 2042 // (sdl val, (add baseptr, 7)) 2043 // (sdr val, baseptr) 2044 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2045 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2046} 2047 2048// Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2049static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2050 SDValue Val = SD->getValue(); 2051 2052 if (Val.getOpcode() != ISD::FP_TO_SINT) 2053 return SDValue(); 2054 2055 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2056 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2057 Val.getOperand(0)); 2058 2059 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2060 SD->getPointerInfo(), SD->isVolatile(), 2061 SD->isNonTemporal(), SD->getAlignment()); 2062} 2063 2064SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2065 StoreSDNode *SD = cast<StoreSDNode>(Op); 2066 EVT MemVT = SD->getMemoryVT(); 2067 2068 // Lower unaligned integer stores. 2069 if ((SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2070 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2071 return lowerUnalignedIntStore(SD, DAG, Subtarget->isLittle()); 2072 2073 return lowerFP_TO_SINT_STORE(SD, DAG); 2074} 2075 2076SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const { 2077 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR 2078 || cast<ConstantSDNode> 2079 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0 2080 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET) 2081 return SDValue(); 2082 2083 // The pattern 2084 // (add (frameaddr 0), (frame_to_args_offset)) 2085 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to 2086 // (add FrameObject, 0) 2087 // where FrameObject is a fixed StackObject with offset 0 which points to 2088 // the old stack pointer. 2089 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2090 EVT ValTy = Op->getValueType(0); 2091 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2092 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy); 2093 return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr, 2094 DAG.getConstant(0, ValTy)); 2095} 2096 2097SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2098 SelectionDAG &DAG) const { 2099 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2100 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2101 Op.getOperand(0)); 2102 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2103} 2104 2105//===----------------------------------------------------------------------===// 2106// Calling Convention Implementation 2107//===----------------------------------------------------------------------===// 2108 2109//===----------------------------------------------------------------------===// 2110// TODO: Implement a generic logic using tblgen that can support this. 2111// Mips O32 ABI rules: 2112// --- 2113// i32 - Passed in A0, A1, A2, A3 and stack 2114// f32 - Only passed in f32 registers if no int reg has been used yet to hold 2115// an argument. Otherwise, passed in A1, A2, A3 and stack. 2116// f64 - Only passed in two aliased f32 registers if no int reg has been used 2117// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2118// not used, it must be shadowed. If only A3 is avaiable, shadow it and 2119// go to stack. 2120// 2121// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2122//===----------------------------------------------------------------------===// 2123 2124static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 2125 MVT LocVT, CCValAssign::LocInfo LocInfo, 2126 ISD::ArgFlagsTy ArgFlags, CCState &State, 2127 const uint16_t *F64Regs) { 2128 2129 static const unsigned IntRegsSize=4, FloatRegsSize=2; 2130 2131 static const uint16_t IntRegs[] = { 2132 Mips::A0, Mips::A1, Mips::A2, Mips::A3 2133 }; 2134 static const uint16_t F32Regs[] = { 2135 Mips::F12, Mips::F14 2136 }; 2137 2138 // Do not process byval args here. 2139 if (ArgFlags.isByVal()) 2140 return true; 2141 2142 // Promote i8 and i16 2143 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2144 LocVT = MVT::i32; 2145 if (ArgFlags.isSExt()) 2146 LocInfo = CCValAssign::SExt; 2147 else if (ArgFlags.isZExt()) 2148 LocInfo = CCValAssign::ZExt; 2149 else 2150 LocInfo = CCValAssign::AExt; 2151 } 2152 2153 unsigned Reg; 2154 2155 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2156 // is true: function is vararg, argument is 3rd or higher, there is previous 2157 // argument which is not f32 or f64. 2158 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 2159 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 2160 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2161 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2162 2163 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2164 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2165 // If this is the first part of an i64 arg, 2166 // the allocated register must be either A0 or A2. 2167 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2168 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2169 LocVT = MVT::i32; 2170 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2171 // Allocate int register and shadow next int register. If first 2172 // available register is Mips::A1 or Mips::A3, shadow it too. 2173 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2174 if (Reg == Mips::A1 || Reg == Mips::A3) 2175 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2176 State.AllocateReg(IntRegs, IntRegsSize); 2177 LocVT = MVT::i32; 2178 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2179 // we are guaranteed to find an available float register 2180 if (ValVT == MVT::f32) { 2181 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 2182 // Shadow int register 2183 State.AllocateReg(IntRegs, IntRegsSize); 2184 } else { 2185 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 2186 // Shadow int registers 2187 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 2188 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2189 State.AllocateReg(IntRegs, IntRegsSize); 2190 State.AllocateReg(IntRegs, IntRegsSize); 2191 } 2192 } else 2193 llvm_unreachable("Cannot handle this ValVT."); 2194 2195 if (!Reg) { 2196 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2197 OrigAlign); 2198 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2199 } else 2200 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2201 2202 return false; 2203} 2204 2205static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2206 MVT LocVT, CCValAssign::LocInfo LocInfo, 2207 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2208 static const uint16_t F64Regs[] = { Mips::D6, Mips::D7 }; 2209 2210 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2211} 2212 2213static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2214 MVT LocVT, CCValAssign::LocInfo LocInfo, 2215 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2216 static const uint16_t F64Regs[] = { Mips::D12_64, Mips::D12_64 }; 2217 2218 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2219} 2220 2221#include "MipsGenCallingConv.inc" 2222 2223//===----------------------------------------------------------------------===// 2224// Call Calling Convention Implementation 2225//===----------------------------------------------------------------------===// 2226 2227static const unsigned O32IntRegsSize = 4; 2228 2229// Return next O32 integer argument register. 2230static unsigned getNextIntArgReg(unsigned Reg) { 2231 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2232 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2233} 2234 2235SDValue 2236MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2237 SDValue Chain, SDValue Arg, SDLoc DL, 2238 bool IsTailCall, SelectionDAG &DAG) const { 2239 if (!IsTailCall) { 2240 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, 2241 DAG.getIntPtrConstant(Offset)); 2242 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false, 2243 false, 0); 2244 } 2245 2246 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2247 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2248 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2249 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2250 /*isVolatile=*/ true, false, 0); 2251} 2252 2253void MipsTargetLowering:: 2254getOpndList(SmallVectorImpl<SDValue> &Ops, 2255 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 2256 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2257 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { 2258 // Insert node "GP copy globalreg" before call to function. 2259 // 2260 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2261 // in PIC mode) allow symbols to be resolved via lazy binding. 2262 // The lazy binding stub requires GP to point to the GOT. 2263 if (IsPICCall && !InternalLinkage) { 2264 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP; 2265 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 2266 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2267 } 2268 2269 // Build a sequence of copy-to-reg nodes chained together with token 2270 // chain and flag operands which copy the outgoing args into registers. 2271 // The InFlag in necessary since all emitted instructions must be 2272 // stuck together. 2273 SDValue InFlag; 2274 2275 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2276 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2277 RegsToPass[i].second, InFlag); 2278 InFlag = Chain.getValue(1); 2279 } 2280 2281 // Add argument registers to the end of the list so that they are 2282 // known live into the call. 2283 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2284 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2285 RegsToPass[i].second.getValueType())); 2286 2287 // Add a register mask operand representing the call-preserved registers. 2288 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2289 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv); 2290 assert(Mask && "Missing call preserved mask for calling convention"); 2291 if (Subtarget->inMips16HardFloat()) { 2292 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2293 llvm::StringRef Sym = G->getGlobal()->getName(); 2294 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2295 if (F->hasFnAttribute("__Mips16RetHelper")) { 2296 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2297 } 2298 } 2299 } 2300 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2301 2302 if (InFlag.getNode()) 2303 Ops.push_back(InFlag); 2304} 2305 2306/// LowerCall - functions arguments are copied from virtual regs to 2307/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2308SDValue 2309MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2310 SmallVectorImpl<SDValue> &InVals) const { 2311 SelectionDAG &DAG = CLI.DAG; 2312 SDLoc DL = CLI.DL; 2313 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2314 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2315 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2316 SDValue Chain = CLI.Chain; 2317 SDValue Callee = CLI.Callee; 2318 bool &IsTailCall = CLI.IsTailCall; 2319 CallingConv::ID CallConv = CLI.CallConv; 2320 bool IsVarArg = CLI.IsVarArg; 2321 2322 MachineFunction &MF = DAG.getMachineFunction(); 2323 MachineFrameInfo *MFI = MF.getFrameInfo(); 2324 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 2325 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2326 2327 // Analyze operands of the call, assigning locations to each operand. 2328 SmallVector<CCValAssign, 16> ArgLocs; 2329 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2330 getTargetMachine(), ArgLocs, *DAG.getContext()); 2331 MipsCC::SpecialCallingConvType SpecialCallingConv = 2332 getSpecialCallingConv(Callee); 2333 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo, 2334 SpecialCallingConv); 2335 2336 MipsCCInfo.analyzeCallOperands(Outs, IsVarArg, 2337 Subtarget->mipsSEUsesSoftFloat(), 2338 Callee.getNode(), CLI.Args); 2339 2340 // Get a count of how many bytes are to be pushed on the stack. 2341 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2342 2343 // Check if it's really possible to do a tail call. 2344 if (IsTailCall) 2345 IsTailCall = 2346 isEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset, 2347 *MF.getInfo<MipsFunctionInfo>()); 2348 2349 if (IsTailCall) 2350 ++NumTailCalls; 2351 2352 // Chain is the output chain of the last Load/Store or CopyToReg node. 2353 // ByValChain is the output chain of the last Memcpy node created for copying 2354 // byval arguments to the stack. 2355 unsigned StackAlignment = TFL->getStackAlignment(); 2356 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment); 2357 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 2358 2359 if (!IsTailCall) 2360 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL); 2361 2362 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, 2363 IsN64 ? Mips::SP_64 : Mips::SP, 2364 getPointerTy()); 2365 2366 // With EABI is it possible to have 16 args on registers. 2367 std::deque< std::pair<unsigned, SDValue> > RegsToPass; 2368 SmallVector<SDValue, 8> MemOpChains; 2369 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 2370 2371 // Walk the register/memloc assignments, inserting copies/loads. 2372 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2373 SDValue Arg = OutVals[i]; 2374 CCValAssign &VA = ArgLocs[i]; 2375 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2376 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2377 2378 // ByVal Arg. 2379 if (Flags.isByVal()) { 2380 assert(Flags.getByValSize() && 2381 "ByVal args of size 0 should have been ignored by front-end."); 2382 assert(ByValArg != MipsCCInfo.byval_end()); 2383 assert(!IsTailCall && 2384 "Do not tail-call optimize if there is a byval argument."); 2385 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2386 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle()); 2387 ++ByValArg; 2388 continue; 2389 } 2390 2391 // Promote the value if needed. 2392 switch (VA.getLocInfo()) { 2393 default: llvm_unreachable("Unknown loc info!"); 2394 case CCValAssign::Full: 2395 if (VA.isRegLoc()) { 2396 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2397 (ValVT == MVT::f64 && LocVT == MVT::i64) || 2398 (ValVT == MVT::i64 && LocVT == MVT::f64)) 2399 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2400 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2401 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2402 Arg, DAG.getConstant(0, MVT::i32)); 2403 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2404 Arg, DAG.getConstant(1, MVT::i32)); 2405 if (!Subtarget->isLittle()) 2406 std::swap(Lo, Hi); 2407 unsigned LocRegLo = VA.getLocReg(); 2408 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2409 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2410 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2411 continue; 2412 } 2413 } 2414 break; 2415 case CCValAssign::SExt: 2416 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 2417 break; 2418 case CCValAssign::ZExt: 2419 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 2420 break; 2421 case CCValAssign::AExt: 2422 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 2423 break; 2424 } 2425 2426 // Arguments that can be passed on register must be kept at 2427 // RegsToPass vector 2428 if (VA.isRegLoc()) { 2429 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2430 continue; 2431 } 2432 2433 // Register can't get to this point... 2434 assert(VA.isMemLoc()); 2435 2436 // emit ISD::STORE whichs stores the 2437 // parameter value to a stack Location 2438 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 2439 Chain, Arg, DL, IsTailCall, DAG)); 2440 } 2441 2442 // Transform all store nodes into one single node because all store 2443 // nodes are independent of each other. 2444 if (!MemOpChains.empty()) 2445 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 2446 &MemOpChains[0], MemOpChains.size()); 2447 2448 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2449 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2450 // node so that legalize doesn't hack it. 2451 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25 2452 bool GlobalOrExternal = false, InternalLinkage = false; 2453 SDValue CalleeLo; 2454 2455 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2456 if (IsPICCall) { 2457 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 2458 2459 if (InternalLinkage) 2460 Callee = getAddrLocal(Callee, DAG, HasMips64); 2461 else if (LargeGOT) 2462 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16, 2463 MipsII::MO_CALL_LO16); 2464 else 2465 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL); 2466 } else 2467 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0, 2468 MipsII::MO_NO_FLAG); 2469 GlobalOrExternal = true; 2470 } 2471 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2472 if (!IsN64 && !IsPIC) // !N64 && static 2473 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2474 MipsII::MO_NO_FLAG); 2475 else if (LargeGOT) 2476 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16, 2477 MipsII::MO_CALL_LO16); 2478 else // N64 || PIC 2479 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL); 2480 2481 GlobalOrExternal = true; 2482 } 2483 2484 SmallVector<SDValue, 8> Ops(1, Chain); 2485 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2486 2487 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage, 2488 CLI, Callee, Chain); 2489 2490 if (IsTailCall) 2491 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, &Ops[0], Ops.size()); 2492 2493 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, &Ops[0], Ops.size()); 2494 SDValue InFlag = Chain.getValue(1); 2495 2496 // Create the CALLSEQ_END node. 2497 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2498 DAG.getIntPtrConstant(0, true), InFlag, DL); 2499 InFlag = Chain.getValue(1); 2500 2501 // Handle result values, copying them out of physregs into vregs that we 2502 // return. 2503 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, 2504 Ins, DL, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy); 2505} 2506 2507/// LowerCallResult - Lower the result values of a call into the 2508/// appropriate copies out of appropriate physical registers. 2509SDValue 2510MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2511 CallingConv::ID CallConv, bool IsVarArg, 2512 const SmallVectorImpl<ISD::InputArg> &Ins, 2513 SDLoc DL, SelectionDAG &DAG, 2514 SmallVectorImpl<SDValue> &InVals, 2515 const SDNode *CallNode, 2516 const Type *RetTy) const { 2517 // Assign locations to each value returned by this call. 2518 SmallVector<CCValAssign, 16> RVLocs; 2519 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2520 getTargetMachine(), RVLocs, *DAG.getContext()); 2521 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo); 2522 2523 MipsCCInfo.analyzeCallResult(Ins, Subtarget->mipsSEUsesSoftFloat(), 2524 CallNode, RetTy); 2525 2526 // Copy all of the result registers out of their specified physreg. 2527 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2528 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 2529 RVLocs[i].getLocVT(), InFlag); 2530 Chain = Val.getValue(1); 2531 InFlag = Val.getValue(2); 2532 2533 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) 2534 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val); 2535 2536 InVals.push_back(Val); 2537 } 2538 2539 return Chain; 2540} 2541 2542//===----------------------------------------------------------------------===// 2543// Formal Arguments Calling Convention Implementation 2544//===----------------------------------------------------------------------===// 2545/// LowerFormalArguments - transform physical registers into virtual registers 2546/// and generate load operations for arguments places on the stack. 2547SDValue 2548MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2549 CallingConv::ID CallConv, 2550 bool IsVarArg, 2551 const SmallVectorImpl<ISD::InputArg> &Ins, 2552 SDLoc DL, SelectionDAG &DAG, 2553 SmallVectorImpl<SDValue> &InVals) 2554 const { 2555 MachineFunction &MF = DAG.getMachineFunction(); 2556 MachineFrameInfo *MFI = MF.getFrameInfo(); 2557 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2558 2559 MipsFI->setVarArgsFrameIndex(0); 2560 2561 // Used with vargs to acumulate store chains. 2562 std::vector<SDValue> OutChains; 2563 2564 // Assign locations to all of the incoming arguments. 2565 SmallVector<CCValAssign, 16> ArgLocs; 2566 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2567 getTargetMachine(), ArgLocs, *DAG.getContext()); 2568 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo); 2569 Function::const_arg_iterator FuncArg = 2570 DAG.getMachineFunction().getFunction()->arg_begin(); 2571 bool UseSoftFloat = Subtarget->mipsSEUsesSoftFloat(); 2572 2573 MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg); 2574 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 2575 MipsCCInfo.hasByValArg()); 2576 2577 unsigned CurArgIdx = 0; 2578 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 2579 2580 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2581 CCValAssign &VA = ArgLocs[i]; 2582 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx); 2583 CurArgIdx = Ins[i].OrigArgIndex; 2584 EVT ValVT = VA.getValVT(); 2585 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2586 bool IsRegLoc = VA.isRegLoc(); 2587 2588 if (Flags.isByVal()) { 2589 assert(Flags.getByValSize() && 2590 "ByVal args of size 0 should have been ignored by front-end."); 2591 assert(ByValArg != MipsCCInfo.byval_end()); 2592 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 2593 MipsCCInfo, *ByValArg); 2594 ++ByValArg; 2595 continue; 2596 } 2597 2598 // Arguments stored on registers 2599 if (IsRegLoc) { 2600 EVT RegVT = VA.getLocVT(); 2601 unsigned ArgReg = VA.getLocReg(); 2602 const TargetRegisterClass *RC; 2603 2604 if (RegVT == MVT::i32) 2605 RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass : 2606 &Mips::GPR32RegClass; 2607 else if (RegVT == MVT::i64) 2608 RC = &Mips::GPR64RegClass; 2609 else if (RegVT == MVT::f32) 2610 RC = &Mips::FGR32RegClass; 2611 else if (RegVT == MVT::f64) 2612 RC = Subtarget->isFP64bit() ? &Mips::FGR64RegClass : 2613 &Mips::AFGR64RegClass; 2614 else 2615 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 2616 2617 // Transform the arguments stored on 2618 // physical registers into virtual ones 2619 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2620 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 2621 2622 // If this is an 8 or 16-bit value, it has been passed promoted 2623 // to 32 bits. Insert an assert[sz]ext to capture this, then 2624 // truncate to the right size. 2625 if (VA.getLocInfo() != CCValAssign::Full) { 2626 unsigned Opcode = 0; 2627 if (VA.getLocInfo() == CCValAssign::SExt) 2628 Opcode = ISD::AssertSext; 2629 else if (VA.getLocInfo() == CCValAssign::ZExt) 2630 Opcode = ISD::AssertZext; 2631 if (Opcode) 2632 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue, 2633 DAG.getValueType(ValVT)); 2634 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue); 2635 } 2636 2637 // Handle floating point arguments passed in integer registers and 2638 // long double arguments passed in floating point registers. 2639 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 2640 (RegVT == MVT::i64 && ValVT == MVT::f64) || 2641 (RegVT == MVT::f64 && ValVT == MVT::i64)) 2642 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 2643 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) { 2644 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 2645 getNextIntArgReg(ArgReg), RC); 2646 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 2647 if (!Subtarget->isLittle()) 2648 std::swap(ArgValue, ArgValue2); 2649 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 2650 ArgValue, ArgValue2); 2651 } 2652 2653 InVals.push_back(ArgValue); 2654 } else { // VA.isRegLoc() 2655 2656 // sanity check 2657 assert(VA.isMemLoc()); 2658 2659 // The stack pointer offset is relative to the caller stack frame. 2660 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 2661 VA.getLocMemOffset(), true); 2662 2663 // Create load nodes to retrieve arguments from the stack 2664 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2665 InVals.push_back(DAG.getLoad(ValVT, DL, Chain, FIN, 2666 MachinePointerInfo::getFixedStack(FI), 2667 false, false, false, 0)); 2668 } 2669 } 2670 2671 // The mips ABIs for returning structs by value requires that we copy 2672 // the sret argument into $v0 for the return. Save the argument into 2673 // a virtual register so that we can access it from the return points. 2674 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2675 unsigned Reg = MipsFI->getSRetReturnReg(); 2676 if (!Reg) { 2677 Reg = MF.getRegInfo(). 2678 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32)); 2679 MipsFI->setSRetReturnReg(Reg); 2680 } 2681 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]); 2682 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 2683 } 2684 2685 if (IsVarArg) 2686 writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG); 2687 2688 // All stores are grouped in one node to allow the matching between 2689 // the size of Ins and InVals. This only happens when on varg functions 2690 if (!OutChains.empty()) { 2691 OutChains.push_back(Chain); 2692 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 2693 &OutChains[0], OutChains.size()); 2694 } 2695 2696 return Chain; 2697} 2698 2699//===----------------------------------------------------------------------===// 2700// Return Value Calling Convention Implementation 2701//===----------------------------------------------------------------------===// 2702 2703bool 2704MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 2705 MachineFunction &MF, bool IsVarArg, 2706 const SmallVectorImpl<ISD::OutputArg> &Outs, 2707 LLVMContext &Context) const { 2708 SmallVector<CCValAssign, 16> RVLocs; 2709 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), 2710 RVLocs, Context); 2711 return CCInfo.CheckReturn(Outs, RetCC_Mips); 2712} 2713 2714SDValue 2715MipsTargetLowering::LowerReturn(SDValue Chain, 2716 CallingConv::ID CallConv, bool IsVarArg, 2717 const SmallVectorImpl<ISD::OutputArg> &Outs, 2718 const SmallVectorImpl<SDValue> &OutVals, 2719 SDLoc DL, SelectionDAG &DAG) const { 2720 // CCValAssign - represent the assignment of 2721 // the return value to a location 2722 SmallVector<CCValAssign, 16> RVLocs; 2723 MachineFunction &MF = DAG.getMachineFunction(); 2724 2725 // CCState - Info about the registers and stack slot. 2726 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs, 2727 *DAG.getContext()); 2728 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo); 2729 2730 // Analyze return values. 2731 MipsCCInfo.analyzeReturn(Outs, Subtarget->mipsSEUsesSoftFloat(), 2732 MF.getFunction()->getReturnType()); 2733 2734 SDValue Flag; 2735 SmallVector<SDValue, 4> RetOps(1, Chain); 2736 2737 // Copy the result values into the output registers. 2738 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2739 SDValue Val = OutVals[i]; 2740 CCValAssign &VA = RVLocs[i]; 2741 assert(VA.isRegLoc() && "Can only return in registers!"); 2742 2743 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) 2744 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val); 2745 2746 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 2747 2748 // Guarantee that all emitted copies are stuck together with flags. 2749 Flag = Chain.getValue(1); 2750 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 2751 } 2752 2753 // The mips ABIs for returning structs by value requires that we copy 2754 // the sret argument into $v0 for the return. We saved the argument into 2755 // a virtual register in the entry block, so now we copy the value out 2756 // and into $v0. 2757 if (MF.getFunction()->hasStructRetAttr()) { 2758 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2759 unsigned Reg = MipsFI->getSRetReturnReg(); 2760 2761 if (!Reg) 2762 llvm_unreachable("sret virtual register not created in the entry block"); 2763 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 2764 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0; 2765 2766 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 2767 Flag = Chain.getValue(1); 2768 RetOps.push_back(DAG.getRegister(V0, getPointerTy())); 2769 } 2770 2771 RetOps[0] = Chain; // Update chain. 2772 2773 // Add the flag if we have it. 2774 if (Flag.getNode()) 2775 RetOps.push_back(Flag); 2776 2777 // Return on Mips is always a "jr $ra" 2778 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, &RetOps[0], RetOps.size()); 2779} 2780 2781//===----------------------------------------------------------------------===// 2782// Mips Inline Assembly Support 2783//===----------------------------------------------------------------------===// 2784 2785/// getConstraintType - Given a constraint letter, return the type of 2786/// constraint it is for this target. 2787MipsTargetLowering::ConstraintType MipsTargetLowering:: 2788getConstraintType(const std::string &Constraint) const 2789{ 2790 // Mips specific constrainy 2791 // GCC config/mips/constraints.md 2792 // 2793 // 'd' : An address register. Equivalent to r 2794 // unless generating MIPS16 code. 2795 // 'y' : Equivalent to r; retained for 2796 // backwards compatibility. 2797 // 'c' : A register suitable for use in an indirect 2798 // jump. This will always be $25 for -mabicalls. 2799 // 'l' : The lo register. 1 word storage. 2800 // 'x' : The hilo register pair. Double word storage. 2801 if (Constraint.size() == 1) { 2802 switch (Constraint[0]) { 2803 default : break; 2804 case 'd': 2805 case 'y': 2806 case 'f': 2807 case 'c': 2808 case 'l': 2809 case 'x': 2810 return C_RegisterClass; 2811 case 'R': 2812 return C_Memory; 2813 } 2814 } 2815 return TargetLowering::getConstraintType(Constraint); 2816} 2817 2818/// Examine constraint type and operand type and determine a weight value. 2819/// This object must already have been set up with the operand type 2820/// and the current alternative constraint selected. 2821TargetLowering::ConstraintWeight 2822MipsTargetLowering::getSingleConstraintMatchWeight( 2823 AsmOperandInfo &info, const char *constraint) const { 2824 ConstraintWeight weight = CW_Invalid; 2825 Value *CallOperandVal = info.CallOperandVal; 2826 // If we don't have a value, we can't do a match, 2827 // but allow it at the lowest weight. 2828 if (CallOperandVal == NULL) 2829 return CW_Default; 2830 Type *type = CallOperandVal->getType(); 2831 // Look at the constraint type. 2832 switch (*constraint) { 2833 default: 2834 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 2835 break; 2836 case 'd': 2837 case 'y': 2838 if (type->isIntegerTy()) 2839 weight = CW_Register; 2840 break; 2841 case 'f': 2842 if (type->isFloatTy()) 2843 weight = CW_Register; 2844 break; 2845 case 'c': // $25 for indirect jumps 2846 case 'l': // lo register 2847 case 'x': // hilo register pair 2848 if (type->isIntegerTy()) 2849 weight = CW_SpecificReg; 2850 break; 2851 case 'I': // signed 16 bit immediate 2852 case 'J': // integer zero 2853 case 'K': // unsigned 16 bit immediate 2854 case 'L': // signed 32 bit immediate where lower 16 bits are 0 2855 case 'N': // immediate in the range of -65535 to -1 (inclusive) 2856 case 'O': // signed 15 bit immediate (+- 16383) 2857 case 'P': // immediate in the range of 65535 to 1 (inclusive) 2858 if (isa<ConstantInt>(CallOperandVal)) 2859 weight = CW_Constant; 2860 break; 2861 case 'R': 2862 weight = CW_Memory; 2863 break; 2864 } 2865 return weight; 2866} 2867 2868/// This is a helper function to parse a physical register string and split it 2869/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 2870/// that is returned indicates whether parsing was successful. The second flag 2871/// is true if the numeric part exists. 2872static std::pair<bool, bool> 2873parsePhysicalReg(const StringRef &C, std::string &Prefix, 2874 unsigned long long &Reg) { 2875 if (C.front() != '{' || C.back() != '}') 2876 return std::make_pair(false, false); 2877 2878 // Search for the first numeric character. 2879 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 2880 I = std::find_if(B, E, std::ptr_fun(isdigit)); 2881 2882 Prefix.assign(B, I - B); 2883 2884 // The second flag is set to false if no numeric characters were found. 2885 if (I == E) 2886 return std::make_pair(true, false); 2887 2888 // Parse the numeric characters. 2889 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 2890 true); 2891} 2892 2893std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 2894parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const { 2895 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2896 const TargetRegisterClass *RC; 2897 std::string Prefix; 2898 unsigned long long Reg; 2899 2900 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 2901 2902 if (!R.first) 2903 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); 2904 2905 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 2906 // No numeric characters follow "hi" or "lo". 2907 if (R.second) 2908 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); 2909 2910 RC = TRI->getRegClass(Prefix == "hi" ? 2911 Mips::HI32RegClassID : Mips::LO32RegClassID); 2912 return std::make_pair(*(RC->begin()), RC); 2913 } 2914 2915 if (!R.second) 2916 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); 2917 2918 if (Prefix == "$f") { // Parse $f0-$f31. 2919 // If the size of FP registers is 64-bit or Reg is an even number, select 2920 // the 64-bit register class. Otherwise, select the 32-bit register class. 2921 if (VT == MVT::Other) 2922 VT = (Subtarget->isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 2923 2924 RC= getRegClassFor(VT); 2925 2926 if (RC == &Mips::AFGR64RegClass) { 2927 assert(Reg % 2 == 0); 2928 Reg >>= 1; 2929 } 2930 } else if (Prefix == "$fcc") { // Parse $fcc0-$fcc7. 2931 RC = TRI->getRegClass(Mips::FCCRegClassID); 2932 } else { // Parse $0-$31. 2933 assert(Prefix == "$"); 2934 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 2935 } 2936 2937 assert(Reg < RC->getNumRegs()); 2938 return std::make_pair(*(RC->begin() + Reg), RC); 2939} 2940 2941/// Given a register class constraint, like 'r', if this corresponds directly 2942/// to an LLVM register class, return a register of 0 and the register class 2943/// pointer. 2944std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 2945getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const 2946{ 2947 if (Constraint.size() == 1) { 2948 switch (Constraint[0]) { 2949 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 2950 case 'y': // Same as 'r'. Exists for compatibility. 2951 case 'r': 2952 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 2953 if (Subtarget->inMips16Mode()) 2954 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 2955 return std::make_pair(0U, &Mips::GPR32RegClass); 2956 } 2957 if (VT == MVT::i64 && !HasMips64) 2958 return std::make_pair(0U, &Mips::GPR32RegClass); 2959 if (VT == MVT::i64 && HasMips64) 2960 return std::make_pair(0U, &Mips::GPR64RegClass); 2961 // This will generate an error message 2962 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2963 case 'f': 2964 if (VT == MVT::f32) 2965 return std::make_pair(0U, &Mips::FGR32RegClass); 2966 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { 2967 if (Subtarget->isFP64bit()) 2968 return std::make_pair(0U, &Mips::FGR64RegClass); 2969 return std::make_pair(0U, &Mips::AFGR64RegClass); 2970 } 2971 break; 2972 case 'c': // register suitable for indirect jump 2973 if (VT == MVT::i32) 2974 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 2975 assert(VT == MVT::i64 && "Unexpected type."); 2976 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 2977 case 'l': // register suitable for indirect jump 2978 if (VT == MVT::i32) 2979 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 2980 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 2981 case 'x': // register suitable for indirect jump 2982 // Fixme: Not triggering the use of both hi and low 2983 // This will generate an error message 2984 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2985 } 2986 } 2987 2988 std::pair<unsigned, const TargetRegisterClass *> R; 2989 R = parseRegForInlineAsmConstraint(Constraint, VT); 2990 2991 if (R.second) 2992 return R; 2993 2994 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 2995} 2996 2997/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2998/// vector. If it is invalid, don't add anything to Ops. 2999void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3000 std::string &Constraint, 3001 std::vector<SDValue>&Ops, 3002 SelectionDAG &DAG) const { 3003 SDValue Result(0, 0); 3004 3005 // Only support length 1 constraints for now. 3006 if (Constraint.length() > 1) return; 3007 3008 char ConstraintLetter = Constraint[0]; 3009 switch (ConstraintLetter) { 3010 default: break; // This will fall through to the generic implementation 3011 case 'I': // Signed 16 bit constant 3012 // If this fails, the parent routine will give an error 3013 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3014 EVT Type = Op.getValueType(); 3015 int64_t Val = C->getSExtValue(); 3016 if (isInt<16>(Val)) { 3017 Result = DAG.getTargetConstant(Val, Type); 3018 break; 3019 } 3020 } 3021 return; 3022 case 'J': // integer zero 3023 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3024 EVT Type = Op.getValueType(); 3025 int64_t Val = C->getZExtValue(); 3026 if (Val == 0) { 3027 Result = DAG.getTargetConstant(0, Type); 3028 break; 3029 } 3030 } 3031 return; 3032 case 'K': // unsigned 16 bit immediate 3033 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3034 EVT Type = Op.getValueType(); 3035 uint64_t Val = (uint64_t)C->getZExtValue(); 3036 if (isUInt<16>(Val)) { 3037 Result = DAG.getTargetConstant(Val, Type); 3038 break; 3039 } 3040 } 3041 return; 3042 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3043 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3044 EVT Type = Op.getValueType(); 3045 int64_t Val = C->getSExtValue(); 3046 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3047 Result = DAG.getTargetConstant(Val, Type); 3048 break; 3049 } 3050 } 3051 return; 3052 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3053 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3054 EVT Type = Op.getValueType(); 3055 int64_t Val = C->getSExtValue(); 3056 if ((Val >= -65535) && (Val <= -1)) { 3057 Result = DAG.getTargetConstant(Val, Type); 3058 break; 3059 } 3060 } 3061 return; 3062 case 'O': // signed 15 bit immediate 3063 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3064 EVT Type = Op.getValueType(); 3065 int64_t Val = C->getSExtValue(); 3066 if ((isInt<15>(Val))) { 3067 Result = DAG.getTargetConstant(Val, Type); 3068 break; 3069 } 3070 } 3071 return; 3072 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3073 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3074 EVT Type = Op.getValueType(); 3075 int64_t Val = C->getSExtValue(); 3076 if ((Val <= 65535) && (Val >= 1)) { 3077 Result = DAG.getTargetConstant(Val, Type); 3078 break; 3079 } 3080 } 3081 return; 3082 } 3083 3084 if (Result.getNode()) { 3085 Ops.push_back(Result); 3086 return; 3087 } 3088 3089 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3090} 3091 3092bool 3093MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const { 3094 // No global is ever allowed as a base. 3095 if (AM.BaseGV) 3096 return false; 3097 3098 switch (AM.Scale) { 3099 case 0: // "r+i" or just "i", depending on HasBaseReg. 3100 break; 3101 case 1: 3102 if (!AM.HasBaseReg) // allow "r+i". 3103 break; 3104 return false; // disallow "r+r" or "r+r+i". 3105 default: 3106 return false; 3107 } 3108 3109 return true; 3110} 3111 3112bool 3113MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3114 // The Mips target isn't yet aware of offsets. 3115 return false; 3116} 3117 3118EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3119 unsigned SrcAlign, 3120 bool IsMemset, bool ZeroMemset, 3121 bool MemcpyStrSrc, 3122 MachineFunction &MF) const { 3123 if (Subtarget->hasMips64()) 3124 return MVT::i64; 3125 3126 return MVT::i32; 3127} 3128 3129bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3130 if (VT != MVT::f32 && VT != MVT::f64) 3131 return false; 3132 if (Imm.isNegZero()) 3133 return false; 3134 return Imm.isZero(); 3135} 3136 3137unsigned MipsTargetLowering::getJumpTableEncoding() const { 3138 if (IsN64) 3139 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3140 3141 return TargetLowering::getJumpTableEncoding(); 3142} 3143 3144/// This function returns true if CallSym is a long double emulation routine. 3145static bool isF128SoftLibCall(const char *CallSym) { 3146 const char *const LibCalls[] = 3147 {"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2", 3148 "__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi", 3149 "__fixunstfti", "__floatditf", "__floatsitf", "__floattitf", 3150 "__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2", 3151 "__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3", 3152 "__trunctfdf2", "__trunctfsf2", "__unordtf2", 3153 "ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl", 3154 "log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl", 3155 "truncl"}; 3156 3157 const char * const *End = LibCalls + array_lengthof(LibCalls); 3158 3159 // Check that LibCalls is sorted alphabetically. 3160 MipsTargetLowering::LTStr Comp; 3161 3162#ifndef NDEBUG 3163 for (const char * const *I = LibCalls; I < End - 1; ++I) 3164 assert(Comp(*I, *(I + 1))); 3165#endif 3166 3167 return std::binary_search(LibCalls, End, CallSym, Comp); 3168} 3169 3170/// This function returns true if Ty is fp128 or i128 which was originally a 3171/// fp128. 3172static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) { 3173 if (Ty->isFP128Ty()) 3174 return true; 3175 3176 const ExternalSymbolSDNode *ES = 3177 dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode); 3178 3179 // If the Ty is i128 and the function being called is a long double emulation 3180 // routine, then the original type is f128. 3181 return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol())); 3182} 3183 3184MipsTargetLowering::MipsCC::SpecialCallingConvType 3185 MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const { 3186 MipsCC::SpecialCallingConvType SpecialCallingConv = 3187 MipsCC::NoSpecialCallingConv;; 3188 if (Subtarget->inMips16HardFloat()) { 3189 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3190 llvm::StringRef Sym = G->getGlobal()->getName(); 3191 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 3192 if (F->hasFnAttribute("__Mips16RetHelper")) { 3193 SpecialCallingConv = MipsCC::Mips16RetHelperConv; 3194 } 3195 } 3196 } 3197 return SpecialCallingConv; 3198} 3199 3200MipsTargetLowering::MipsCC::MipsCC( 3201 CallingConv::ID CC, bool IsO32_, bool IsFP64_, CCState &Info, 3202 MipsCC::SpecialCallingConvType SpecialCallingConv_) 3203 : CCInfo(Info), CallConv(CC), IsO32(IsO32_), IsFP64(IsFP64_), 3204 SpecialCallingConv(SpecialCallingConv_){ 3205 // Pre-allocate reserved argument area. 3206 CCInfo.AllocateStack(reservedArgArea(), 1); 3207} 3208 3209 3210void MipsTargetLowering::MipsCC:: 3211analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args, 3212 bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode, 3213 std::vector<ArgListEntry> &FuncArgs) { 3214 assert((CallConv != CallingConv::Fast || !IsVarArg) && 3215 "CallingConv::Fast shouldn't be used for vararg functions."); 3216 3217 unsigned NumOpnds = Args.size(); 3218 llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn(); 3219 3220 for (unsigned I = 0; I != NumOpnds; ++I) { 3221 MVT ArgVT = Args[I].VT; 3222 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3223 bool R; 3224 3225 if (ArgFlags.isByVal()) { 3226 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3227 continue; 3228 } 3229 3230 if (IsVarArg && !Args[I].IsFixed) 3231 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 3232 else { 3233 MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode, 3234 IsSoftFloat); 3235 R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo); 3236 } 3237 3238 if (R) { 3239#ifndef NDEBUG 3240 dbgs() << "Call operand #" << I << " has unhandled type " 3241 << EVT(ArgVT).getEVTString(); 3242#endif 3243 llvm_unreachable(0); 3244 } 3245 } 3246} 3247 3248void MipsTargetLowering::MipsCC:: 3249analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args, 3250 bool IsSoftFloat, Function::const_arg_iterator FuncArg) { 3251 unsigned NumArgs = Args.size(); 3252 llvm::CCAssignFn *FixedFn = fixedArgFn(); 3253 unsigned CurArgIdx = 0; 3254 3255 for (unsigned I = 0; I != NumArgs; ++I) { 3256 MVT ArgVT = Args[I].VT; 3257 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3258 std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx); 3259 CurArgIdx = Args[I].OrigArgIndex; 3260 3261 if (ArgFlags.isByVal()) { 3262 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3263 continue; 3264 } 3265 3266 MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), 0, IsSoftFloat); 3267 3268 if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo)) 3269 continue; 3270 3271#ifndef NDEBUG 3272 dbgs() << "Formal Arg #" << I << " has unhandled type " 3273 << EVT(ArgVT).getEVTString(); 3274#endif 3275 llvm_unreachable(0); 3276 } 3277} 3278 3279template<typename Ty> 3280void MipsTargetLowering::MipsCC:: 3281analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat, 3282 const SDNode *CallNode, const Type *RetTy) const { 3283 CCAssignFn *Fn; 3284 3285 if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode)) 3286 Fn = RetCC_F128Soft; 3287 else 3288 Fn = RetCC_Mips; 3289 3290 for (unsigned I = 0, E = RetVals.size(); I < E; ++I) { 3291 MVT VT = RetVals[I].VT; 3292 ISD::ArgFlagsTy Flags = RetVals[I].Flags; 3293 MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat); 3294 3295 if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) { 3296#ifndef NDEBUG 3297 dbgs() << "Call result #" << I << " has unhandled type " 3298 << EVT(VT).getEVTString() << '\n'; 3299#endif 3300 llvm_unreachable(0); 3301 } 3302 } 3303} 3304 3305void MipsTargetLowering::MipsCC:: 3306analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat, 3307 const SDNode *CallNode, const Type *RetTy) const { 3308 analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy); 3309} 3310 3311void MipsTargetLowering::MipsCC:: 3312analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat, 3313 const Type *RetTy) const { 3314 analyzeReturn(Outs, IsSoftFloat, 0, RetTy); 3315} 3316 3317void 3318MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT, 3319 MVT LocVT, 3320 CCValAssign::LocInfo LocInfo, 3321 ISD::ArgFlagsTy ArgFlags) { 3322 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0."); 3323 3324 struct ByValArgInfo ByVal; 3325 unsigned RegSize = regSize(); 3326 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize); 3327 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize), 3328 RegSize * 2); 3329 3330 if (useRegsForByval()) 3331 allocateRegs(ByVal, ByValSize, Align); 3332 3333 // Allocate space on caller's stack. 3334 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs, 3335 Align); 3336 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT, 3337 LocInfo)); 3338 ByValArgs.push_back(ByVal); 3339} 3340 3341unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const { 3342 return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs); 3343} 3344 3345unsigned MipsTargetLowering::MipsCC::reservedArgArea() const { 3346 return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0; 3347} 3348 3349const uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const { 3350 return IsO32 ? O32IntRegs : Mips64IntRegs; 3351} 3352 3353llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const { 3354 if (CallConv == CallingConv::Fast) 3355 return CC_Mips_FastCC; 3356 3357 if (SpecialCallingConv == Mips16RetHelperConv) 3358 return CC_Mips16RetHelper; 3359 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN; 3360} 3361 3362llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const { 3363 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN_VarArg; 3364} 3365 3366const uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const { 3367 return IsO32 ? O32IntRegs : Mips64DPRegs; 3368} 3369 3370void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal, 3371 unsigned ByValSize, 3372 unsigned Align) { 3373 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs(); 3374 const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs(); 3375 assert(!(ByValSize % RegSize) && !(Align % RegSize) && 3376 "Byval argument's size and alignment should be a multiple of" 3377 "RegSize."); 3378 3379 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs); 3380 3381 // If Align > RegSize, the first arg register must be even. 3382 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) { 3383 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]); 3384 ++ByVal.FirstIdx; 3385 } 3386 3387 // Mark the registers allocated. 3388 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs); 3389 ByValSize -= RegSize, ++I, ++ByVal.NumRegs) 3390 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]); 3391} 3392 3393MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy, 3394 const SDNode *CallNode, 3395 bool IsSoftFloat) const { 3396 if (IsSoftFloat || IsO32) 3397 return VT; 3398 3399 // Check if the original type was fp128. 3400 if (originalTypeIsF128(OrigTy, CallNode)) { 3401 assert(VT == MVT::i64); 3402 return MVT::f64; 3403 } 3404 3405 return VT; 3406} 3407 3408void MipsTargetLowering:: 3409copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, 3410 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 3411 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 3412 const MipsCC &CC, const ByValArgInfo &ByVal) const { 3413 MachineFunction &MF = DAG.getMachineFunction(); 3414 MachineFrameInfo *MFI = MF.getFrameInfo(); 3415 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize(); 3416 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3417 int FrameObjOffset; 3418 3419 if (RegAreaSize) 3420 FrameObjOffset = (int)CC.reservedArgArea() - 3421 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize()); 3422 else 3423 FrameObjOffset = ByVal.Address; 3424 3425 // Create frame object. 3426 EVT PtrTy = getPointerTy(); 3427 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3428 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3429 InVals.push_back(FIN); 3430 3431 if (!ByVal.NumRegs) 3432 return; 3433 3434 // Copy arg registers. 3435 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8); 3436 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3437 3438 for (unsigned I = 0; I < ByVal.NumRegs; ++I) { 3439 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I]; 3440 unsigned VReg = addLiveIn(MF, ArgReg, RC); 3441 unsigned Offset = I * CC.regSize(); 3442 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3443 DAG.getConstant(Offset, PtrTy)); 3444 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3445 StorePtr, MachinePointerInfo(FuncArg, Offset), 3446 false, false, 0); 3447 OutChains.push_back(Store); 3448 } 3449} 3450 3451// Copy byVal arg to registers and stack. 3452void MipsTargetLowering:: 3453passByValArg(SDValue Chain, SDLoc DL, 3454 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 3455 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 3456 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 3457 const MipsCC &CC, const ByValArgInfo &ByVal, 3458 const ISD::ArgFlagsTy &Flags, bool isLittle) const { 3459 unsigned ByValSize = Flags.getByValSize(); 3460 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct. 3461 unsigned RegSize = CC.regSize(); 3462 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize); 3463 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8); 3464 3465 if (ByVal.NumRegs) { 3466 const uint16_t *ArgRegs = CC.intArgRegs(); 3467 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize); 3468 unsigned I = 0; 3469 3470 // Copy words to registers. 3471 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) { 3472 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3473 DAG.getConstant(Offset, PtrTy)); 3474 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3475 MachinePointerInfo(), false, false, false, 3476 Alignment); 3477 MemOpChains.push_back(LoadVal.getValue(1)); 3478 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3479 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3480 } 3481 3482 // Return if the struct has been fully copied. 3483 if (ByValSize == Offset) 3484 return; 3485 3486 // Copy the remainder of the byval argument with sub-word loads and shifts. 3487 if (LeftoverBytes) { 3488 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) && 3489 "Size of the remainder should be smaller than RegSize."); 3490 SDValue Val; 3491 3492 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0; 3493 Offset < ByValSize; LoadSize /= 2) { 3494 unsigned RemSize = ByValSize - Offset; 3495 3496 if (RemSize < LoadSize) 3497 continue; 3498 3499 // Load subword. 3500 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3501 DAG.getConstant(Offset, PtrTy)); 3502 SDValue LoadVal = 3503 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, 3504 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8), 3505 false, false, Alignment); 3506 MemOpChains.push_back(LoadVal.getValue(1)); 3507 3508 // Shift the loaded value. 3509 unsigned Shamt; 3510 3511 if (isLittle) 3512 Shamt = TotalSizeLoaded; 3513 else 3514 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8; 3515 3516 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 3517 DAG.getConstant(Shamt, MVT::i32)); 3518 3519 if (Val.getNode()) 3520 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3521 else 3522 Val = Shift; 3523 3524 Offset += LoadSize; 3525 TotalSizeLoaded += LoadSize; 3526 Alignment = std::min(Alignment, LoadSize); 3527 } 3528 3529 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3530 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 3531 return; 3532 } 3533 } 3534 3535 // Copy remainder of byval arg to it with memcpy. 3536 unsigned MemCpySize = ByValSize - Offset; 3537 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3538 DAG.getConstant(Offset, PtrTy)); 3539 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 3540 DAG.getIntPtrConstant(ByVal.Address)); 3541 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 3542 DAG.getConstant(MemCpySize, PtrTy), Alignment, 3543 /*isVolatile=*/false, /*AlwaysInline=*/false, 3544 MachinePointerInfo(0), MachinePointerInfo(0)); 3545 MemOpChains.push_back(Chain); 3546} 3547 3548void 3549MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 3550 const MipsCC &CC, SDValue Chain, 3551 SDLoc DL, SelectionDAG &DAG) const { 3552 unsigned NumRegs = CC.numIntArgRegs(); 3553 const uint16_t *ArgRegs = CC.intArgRegs(); 3554 const CCState &CCInfo = CC.getCCInfo(); 3555 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs); 3556 unsigned RegSize = CC.regSize(); 3557 MVT RegTy = MVT::getIntegerVT(RegSize * 8); 3558 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3559 MachineFunction &MF = DAG.getMachineFunction(); 3560 MachineFrameInfo *MFI = MF.getFrameInfo(); 3561 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3562 3563 // Offset of the first variable argument from stack pointer. 3564 int VaArgOffset; 3565 3566 if (NumRegs == Idx) 3567 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize); 3568 else 3569 VaArgOffset = 3570 (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx)); 3571 3572 // Record the frame index of the first variable argument 3573 // which is a value necessary to VASTART. 3574 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3575 MipsFI->setVarArgsFrameIndex(FI); 3576 3577 // Copy the integer registers that have not been used for argument passing 3578 // to the argument register save area. For O32, the save area is allocated 3579 // in the caller's stack frame, while for N32/64, it is allocated in the 3580 // callee's stack frame. 3581 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) { 3582 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 3583 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 3584 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3585 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 3586 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, 3587 MachinePointerInfo(), false, false, 0); 3588 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0); 3589 OutChains.push_back(Store); 3590 } 3591} 3592