MipsISelLowering.cpp revision d5a336cdb5ed691b0288c8d4aa4c5b1899b7e39b
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14#define DEBUG_TYPE "mips-lower" 15#include <set> 16#include "MipsISelLowering.h" 17#include "InstPrinter/MipsInstPrinter.h" 18#include "MCTargetDesc/MipsBaseInfo.h" 19#include "MipsMachineFunction.h" 20#include "MipsSubtarget.h" 21#include "MipsTargetMachine.h" 22#include "MipsTargetObjectFile.h" 23#include "llvm/ADT/Statistic.h" 24#include "llvm/CodeGen/CallingConvLower.h" 25#include "llvm/CodeGen/MachineFrameInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/MachineInstrBuilder.h" 28#include "llvm/CodeGen/MachineRegisterInfo.h" 29#include "llvm/CodeGen/SelectionDAGISel.h" 30#include "llvm/CodeGen/ValueTypes.h" 31#include "llvm/IR/CallingConv.h" 32#include "llvm/IR/DerivedTypes.h" 33#include "llvm/IR/Function.h" 34#include "llvm/IR/GlobalVariable.h" 35#include "llvm/IR/Intrinsics.h" 36#include "llvm/Support/CommandLine.h" 37#include "llvm/Support/Debug.h" 38#include "llvm/Support/ErrorHandling.h" 39#include "llvm/Support/raw_ostream.h" 40 41using namespace llvm; 42 43STATISTIC(NumTailCalls, "Number of tail calls"); 44 45static cl::opt<bool> 46EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden, 47 cl::desc("MIPS: Enable tail calls."), cl::init(false)); 48 49static cl::opt<bool> 50LargeGOT("mxgot", cl::Hidden, 51 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 52 53static cl::opt<bool> 54Mips16HardFloat("mips16-hard-float", cl::NotHidden, 55 cl::desc("MIPS: mips16 hard float enable."), 56 cl::init(false)); 57 58 59 60static const uint16_t O32IntRegs[4] = { 61 Mips::A0, Mips::A1, Mips::A2, Mips::A3 62}; 63 64static const uint16_t Mips64IntRegs[8] = { 65 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, 66 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 67}; 68 69static const uint16_t Mips64DPRegs[8] = { 70 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 71 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 72}; 73 74// If I is a shifted mask, set the size (Size) and the first bit of the 75// mask (Pos), and return true. 76// For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 77static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 78 if (!isShiftedMask_64(I)) 79 return false; 80 81 Size = CountPopulation_64(I); 82 Pos = CountTrailingZeros_64(I); 83 return true; 84} 85 86static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) { 87 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 88 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 89} 90 91static SDValue getTargetNode(SDValue Op, SelectionDAG &DAG, unsigned Flag) { 92 EVT Ty = Op.getValueType(); 93 94 if (GlobalAddressSDNode *N = dyn_cast<GlobalAddressSDNode>(Op)) 95 return DAG.getTargetGlobalAddress(N->getGlobal(), Op.getDebugLoc(), Ty, 0, 96 Flag); 97 if (ExternalSymbolSDNode *N = dyn_cast<ExternalSymbolSDNode>(Op)) 98 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 99 if (BlockAddressSDNode *N = dyn_cast<BlockAddressSDNode>(Op)) 100 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 101 if (JumpTableSDNode *N = dyn_cast<JumpTableSDNode>(Op)) 102 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 103 if (ConstantPoolSDNode *N = dyn_cast<ConstantPoolSDNode>(Op)) 104 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 105 N->getOffset(), Flag); 106 107 llvm_unreachable("Unexpected node type."); 108 return SDValue(); 109} 110 111static SDValue getAddrNonPIC(SDValue Op, SelectionDAG &DAG) { 112 DebugLoc DL = Op.getDebugLoc(); 113 EVT Ty = Op.getValueType(); 114 SDValue Hi = getTargetNode(Op, DAG, MipsII::MO_ABS_HI); 115 SDValue Lo = getTargetNode(Op, DAG, MipsII::MO_ABS_LO); 116 return DAG.getNode(ISD::ADD, DL, Ty, 117 DAG.getNode(MipsISD::Hi, DL, Ty, Hi), 118 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); 119} 120 121static SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) { 122 DebugLoc DL = Op.getDebugLoc(); 123 EVT Ty = Op.getValueType(); 124 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 125 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, GetGlobalReg(DAG, Ty), 126 getTargetNode(Op, DAG, GOTFlag)); 127 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, 128 MachinePointerInfo::getGOT(), false, false, false, 129 0); 130 unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 131 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(Op, DAG, LoFlag)); 132 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); 133} 134 135static SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) { 136 DebugLoc DL = Op.getDebugLoc(); 137 EVT Ty = Op.getValueType(); 138 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, GetGlobalReg(DAG, Ty), 139 getTargetNode(Op, DAG, Flag)); 140 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Tgt, 141 MachinePointerInfo::getGOT(), false, false, false, 0); 142} 143 144static SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG, 145 unsigned HiFlag, unsigned LoFlag) { 146 DebugLoc DL = Op.getDebugLoc(); 147 EVT Ty = Op.getValueType(); 148 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(Op, DAG, HiFlag)); 149 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, GetGlobalReg(DAG, Ty)); 150 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi, 151 getTargetNode(Op, DAG, LoFlag)); 152 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Wrapper, 153 MachinePointerInfo::getGOT(), false, false, false, 0); 154} 155 156const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 157 switch (Opcode) { 158 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 159 case MipsISD::TailCall: return "MipsISD::TailCall"; 160 case MipsISD::Hi: return "MipsISD::Hi"; 161 case MipsISD::Lo: return "MipsISD::Lo"; 162 case MipsISD::GPRel: return "MipsISD::GPRel"; 163 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 164 case MipsISD::Ret: return "MipsISD::Ret"; 165 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 166 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 167 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 168 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 169 case MipsISD::FPRound: return "MipsISD::FPRound"; 170 case MipsISD::MAdd: return "MipsISD::MAdd"; 171 case MipsISD::MAddu: return "MipsISD::MAddu"; 172 case MipsISD::MSub: return "MipsISD::MSub"; 173 case MipsISD::MSubu: return "MipsISD::MSubu"; 174 case MipsISD::DivRem: return "MipsISD::DivRem"; 175 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 176 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 177 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 178 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 179 case MipsISD::Sync: return "MipsISD::Sync"; 180 case MipsISD::Ext: return "MipsISD::Ext"; 181 case MipsISD::Ins: return "MipsISD::Ins"; 182 case MipsISD::LWL: return "MipsISD::LWL"; 183 case MipsISD::LWR: return "MipsISD::LWR"; 184 case MipsISD::SWL: return "MipsISD::SWL"; 185 case MipsISD::SWR: return "MipsISD::SWR"; 186 case MipsISD::LDL: return "MipsISD::LDL"; 187 case MipsISD::LDR: return "MipsISD::LDR"; 188 case MipsISD::SDL: return "MipsISD::SDL"; 189 case MipsISD::SDR: return "MipsISD::SDR"; 190 case MipsISD::EXTP: return "MipsISD::EXTP"; 191 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 192 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 193 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 194 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 195 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 196 case MipsISD::SHILO: return "MipsISD::SHILO"; 197 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 198 case MipsISD::MULT: return "MipsISD::MULT"; 199 case MipsISD::MULTU: return "MipsISD::MULTU"; 200 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSPDSP"; 201 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 202 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 203 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 204 default: return NULL; 205 } 206} 207 208namespace { 209 struct eqstr { 210 bool operator()(const char *s1, const char *s2) const 211 { 212 return strcmp(s1, s2) == 0; 213 } 214 }; 215 216 std::set<const char*, eqstr> noHelperNeeded; 217 218 const char* addToNoHelperNeeded(const char* s) { 219 noHelperNeeded.insert(s); 220 return s; 221 } 222 223} 224 225void MipsTargetLowering::setMips16HardFloatLibCalls() { 226 setLibcallName(RTLIB::ADD_F32, addToNoHelperNeeded("__mips16_addsf3")); 227 setLibcallName(RTLIB::ADD_F64, addToNoHelperNeeded("__mips16_adddf3")); 228 setLibcallName(RTLIB::SUB_F32, addToNoHelperNeeded("__mips16_subsf3")); 229 setLibcallName(RTLIB::SUB_F64, addToNoHelperNeeded("__mips16_subdf3")); 230 setLibcallName(RTLIB::MUL_F32, addToNoHelperNeeded("__mips16_mulsf3")); 231 setLibcallName(RTLIB::MUL_F64, addToNoHelperNeeded("__mips16_muldf3")); 232 setLibcallName(RTLIB::DIV_F32, addToNoHelperNeeded("__mips16_divsf3")); 233 setLibcallName(RTLIB::DIV_F64, addToNoHelperNeeded("__mips16_divdf3")); 234 setLibcallName(RTLIB::FPEXT_F32_F64, 235 addToNoHelperNeeded("__mips16_extendsfdf2")); 236 setLibcallName(RTLIB::FPROUND_F64_F32, 237 addToNoHelperNeeded("__mips16_truncdfsf2")); 238 setLibcallName(RTLIB::FPTOSINT_F32_I32, 239 addToNoHelperNeeded("__mips16_fix_truncsfsi")); 240 setLibcallName(RTLIB::FPTOSINT_F64_I32, 241 addToNoHelperNeeded("__mips16_fix_truncdfsi")); 242 setLibcallName(RTLIB::SINTTOFP_I32_F32, 243 addToNoHelperNeeded("__mips16_floatsisf")); 244 setLibcallName(RTLIB::SINTTOFP_I32_F64, 245 addToNoHelperNeeded("__mips16_floatsidf")); 246 setLibcallName(RTLIB::UINTTOFP_I32_F32, 247 addToNoHelperNeeded("__mips16_floatunsisf")); 248 setLibcallName(RTLIB::UINTTOFP_I32_F64, 249 addToNoHelperNeeded("__mips16_floatunsidf")); 250 setLibcallName(RTLIB::OEQ_F32, addToNoHelperNeeded("__mips16_eqsf2")); 251 setLibcallName(RTLIB::OEQ_F64, addToNoHelperNeeded("__mips16_eqdf2")); 252 setLibcallName(RTLIB::UNE_F32, addToNoHelperNeeded("__mips16_nesf2")); 253 setLibcallName(RTLIB::UNE_F64, addToNoHelperNeeded("__mips16_nedf2")); 254 setLibcallName(RTLIB::OGE_F32, addToNoHelperNeeded("__mips16_gesf2")); 255 setLibcallName(RTLIB::OGE_F64, addToNoHelperNeeded("__mips16_gedf2")); 256 setLibcallName(RTLIB::OLT_F32, addToNoHelperNeeded("__mips16_ltsf2")); 257 setLibcallName(RTLIB::OLT_F64, addToNoHelperNeeded("__mips16_ltdf2")); 258 setLibcallName(RTLIB::OLE_F32, addToNoHelperNeeded("__mips16_lesf2")); 259 setLibcallName(RTLIB::OLE_F64, addToNoHelperNeeded("__mips16_ledf2")); 260 setLibcallName(RTLIB::OGT_F32, addToNoHelperNeeded("__mips16_gtsf2")); 261 setLibcallName(RTLIB::OGT_F64, addToNoHelperNeeded("__mips16_gtdf2")); 262 setLibcallName(RTLIB::UO_F32, addToNoHelperNeeded("__mips16_unordsf2")); 263 setLibcallName(RTLIB::UO_F64, addToNoHelperNeeded("__mips16_unorddf2")); 264 setLibcallName(RTLIB::O_F32, addToNoHelperNeeded("__mips16_unordsf2")); 265 setLibcallName(RTLIB::O_F64, addToNoHelperNeeded("__mips16_unorddf2")); 266} 267 268MipsTargetLowering:: 269MipsTargetLowering(MipsTargetMachine &TM) 270 : TargetLowering(TM, new MipsTargetObjectFile()), 271 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 272 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()), 273 IsO32(Subtarget->isABI_O32()) { 274 275 // Mips does not have i1 type, so use i32 for 276 // setcc operations results (slt, sgt, ...). 277 setBooleanContents(ZeroOrOneBooleanContent); 278 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 279 280 // Set up the register classes 281 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass); 282 283 if (HasMips64) 284 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass); 285 286 if (Subtarget->inMips16Mode()) { 287 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); 288 if (Mips16HardFloat) 289 setMips16HardFloatLibCalls(); 290 } 291 292 if (Subtarget->hasDSP()) { 293 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; 294 295 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) { 296 addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass); 297 298 // Expand all builtin opcodes. 299 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 300 setOperationAction(Opc, VecTys[i], Expand); 301 302 setOperationAction(ISD::LOAD, VecTys[i], Legal); 303 setOperationAction(ISD::STORE, VecTys[i], Legal); 304 setOperationAction(ISD::BITCAST, VecTys[i], Legal); 305 } 306 } 307 308 if (!TM.Options.UseSoftFloat) { 309 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); 310 311 // When dealing with single precision only, use libcalls 312 if (!Subtarget->isSingleFloat()) { 313 if (HasMips64) 314 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); 315 else 316 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); 317 } 318 } 319 320 // Load extented operations for i1 types must be promoted 321 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 322 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 323 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 324 325 // MIPS doesn't have extending float->double load/store 326 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 327 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 328 329 // Used by legalize types to correctly generate the setcc result. 330 // Without this, every float setcc comes with a AND/OR with the result, 331 // we don't want this, since the fpcmp result goes to a flag register, 332 // which is used implicitly by brcond and select operations. 333 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 334 335 // Mips Custom Operations 336 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 337 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 338 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 339 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 340 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 341 setOperationAction(ISD::SELECT, MVT::f32, Custom); 342 setOperationAction(ISD::SELECT, MVT::f64, Custom); 343 setOperationAction(ISD::SELECT, MVT::i32, Custom); 344 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 345 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 346 setOperationAction(ISD::SETCC, MVT::f32, Custom); 347 setOperationAction(ISD::SETCC, MVT::f64, Custom); 348 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 349 setOperationAction(ISD::VASTART, MVT::Other, Custom); 350 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 351 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 352 if (Subtarget->inMips16Mode()) { 353 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 354 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 355 } 356 else { 357 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 358 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 359 } 360 if (!Subtarget->inMips16Mode()) { 361 setOperationAction(ISD::LOAD, MVT::i32, Custom); 362 setOperationAction(ISD::STORE, MVT::i32, Custom); 363 } 364 365 if (!TM.Options.NoNaNsFPMath) { 366 setOperationAction(ISD::FABS, MVT::f32, Custom); 367 setOperationAction(ISD::FABS, MVT::f64, Custom); 368 } 369 370 if (HasMips64) { 371 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 372 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 373 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 374 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 375 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 376 setOperationAction(ISD::SELECT, MVT::i64, Custom); 377 setOperationAction(ISD::LOAD, MVT::i64, Custom); 378 setOperationAction(ISD::STORE, MVT::i64, Custom); 379 } 380 381 if (!HasMips64) { 382 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 383 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 384 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 385 } 386 387 setOperationAction(ISD::ADD, MVT::i32, Custom); 388 if (HasMips64) 389 setOperationAction(ISD::ADD, MVT::i64, Custom); 390 391 setOperationAction(ISD::SDIV, MVT::i32, Expand); 392 setOperationAction(ISD::SREM, MVT::i32, Expand); 393 setOperationAction(ISD::UDIV, MVT::i32, Expand); 394 setOperationAction(ISD::UREM, MVT::i32, Expand); 395 setOperationAction(ISD::SDIV, MVT::i64, Expand); 396 setOperationAction(ISD::SREM, MVT::i64, Expand); 397 setOperationAction(ISD::UDIV, MVT::i64, Expand); 398 setOperationAction(ISD::UREM, MVT::i64, Expand); 399 400 // Operations not directly supported by Mips. 401 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 402 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 403 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 404 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 405 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 406 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 407 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 408 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 409 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 410 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 411 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 412 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 413 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 414 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 416 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 417 setOperationAction(ISD::ROTL, MVT::i32, Expand); 418 setOperationAction(ISD::ROTL, MVT::i64, Expand); 419 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 420 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 421 422 if (!Subtarget->hasMips32r2()) 423 setOperationAction(ISD::ROTR, MVT::i32, Expand); 424 425 if (!Subtarget->hasMips64r2()) 426 setOperationAction(ISD::ROTR, MVT::i64, Expand); 427 428 setOperationAction(ISD::FSIN, MVT::f32, Expand); 429 setOperationAction(ISD::FSIN, MVT::f64, Expand); 430 setOperationAction(ISD::FCOS, MVT::f32, Expand); 431 setOperationAction(ISD::FCOS, MVT::f64, Expand); 432 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 433 setOperationAction(ISD::FPOW, MVT::f32, Expand); 434 setOperationAction(ISD::FPOW, MVT::f64, Expand); 435 setOperationAction(ISD::FLOG, MVT::f32, Expand); 436 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 437 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 438 setOperationAction(ISD::FEXP, MVT::f32, Expand); 439 setOperationAction(ISD::FMA, MVT::f32, Expand); 440 setOperationAction(ISD::FMA, MVT::f64, Expand); 441 setOperationAction(ISD::FREM, MVT::f32, Expand); 442 setOperationAction(ISD::FREM, MVT::f64, Expand); 443 444 if (!TM.Options.NoNaNsFPMath) { 445 setOperationAction(ISD::FNEG, MVT::f32, Expand); 446 setOperationAction(ISD::FNEG, MVT::f64, Expand); 447 } 448 449 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 450 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 451 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 452 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 453 454 setOperationAction(ISD::VAARG, MVT::Other, Expand); 455 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 456 setOperationAction(ISD::VAEND, MVT::Other, Expand); 457 458 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); 459 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); 460 461 // Use the default for now 462 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 463 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 464 465 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 466 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 467 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 468 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 469 470 if (Subtarget->inMips16Mode()) { 471 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 472 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 473 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 474 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 475 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 476 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 477 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 478 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 479 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); 480 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); 481 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); 482 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); 483 } 484 485 setInsertFencesForAtomic(true); 486 487 if (!Subtarget->hasSEInReg()) { 488 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 489 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 490 } 491 492 if (!Subtarget->hasBitCount()) { 493 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 494 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 495 } 496 497 if (!Subtarget->hasSwap()) { 498 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 499 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 500 } 501 502 if (HasMips64) { 503 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); 504 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom); 505 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom); 506 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 507 } 508 509 setTargetDAGCombine(ISD::ADDE); 510 setTargetDAGCombine(ISD::SUBE); 511 setTargetDAGCombine(ISD::SDIVREM); 512 setTargetDAGCombine(ISD::UDIVREM); 513 setTargetDAGCombine(ISD::SELECT); 514 setTargetDAGCombine(ISD::AND); 515 setTargetDAGCombine(ISD::OR); 516 setTargetDAGCombine(ISD::ADD); 517 518 setMinFunctionAlignment(HasMips64 ? 3 : 2); 519 520 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP); 521 computeRegisterProperties(); 522 523 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0); 524 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1); 525 526 maxStoresPerMemcpy = 16; 527} 528 529bool 530MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const { 531 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 532 533 if (Subtarget->inMips16Mode()) 534 return false; 535 536 switch (SVT) { 537 case MVT::i64: 538 case MVT::i32: 539 if (Fast) 540 *Fast = true; 541 return true; 542 default: 543 return false; 544 } 545} 546 547EVT MipsTargetLowering::getSetCCResultType(EVT VT) const { 548 if (!VT.isVector()) 549 return MVT::i32; 550 return VT.changeVectorElementTypeToInteger(); 551} 552 553// SelectMadd - 554// Transforms a subgraph in CurDAG if the following pattern is found: 555// (addc multLo, Lo0), (adde multHi, Hi0), 556// where, 557// multHi/Lo: product of multiplication 558// Lo0: initial value of Lo register 559// Hi0: initial value of Hi register 560// Return true if pattern matching was successful. 561static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) { 562 // ADDENode's second operand must be a flag output of an ADDC node in order 563 // for the matching to be successful. 564 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); 565 566 if (ADDCNode->getOpcode() != ISD::ADDC) 567 return false; 568 569 SDValue MultHi = ADDENode->getOperand(0); 570 SDValue MultLo = ADDCNode->getOperand(0); 571 SDNode *MultNode = MultHi.getNode(); 572 unsigned MultOpc = MultHi.getOpcode(); 573 574 // MultHi and MultLo must be generated by the same node, 575 if (MultLo.getNode() != MultNode) 576 return false; 577 578 // and it must be a multiplication. 579 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 580 return false; 581 582 // MultLo amd MultHi must be the first and second output of MultNode 583 // respectively. 584 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 585 return false; 586 587 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 588 // of the values of MultNode, in which case MultNode will be removed in later 589 // phases. 590 // If there exist users other than ADDENode or ADDCNode, this function returns 591 // here, which will result in MultNode being mapped to a single MULT 592 // instruction node rather than a pair of MULT and MADD instructions being 593 // produced. 594 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 595 return false; 596 597 SDValue Chain = CurDAG->getEntryNode(); 598 DebugLoc dl = ADDENode->getDebugLoc(); 599 600 // create MipsMAdd(u) node 601 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 602 603 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue, 604 MultNode->getOperand(0),// Factor 0 605 MultNode->getOperand(1),// Factor 1 606 ADDCNode->getOperand(1),// Lo0 607 ADDENode->getOperand(1));// Hi0 608 609 // create CopyFromReg nodes 610 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 611 MAdd); 612 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 613 Mips::HI, MVT::i32, 614 CopyFromLo.getValue(2)); 615 616 // replace uses of adde and addc here 617 if (!SDValue(ADDCNode, 0).use_empty()) 618 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 619 620 if (!SDValue(ADDENode, 0).use_empty()) 621 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 622 623 return true; 624} 625 626// SelectMsub - 627// Transforms a subgraph in CurDAG if the following pattern is found: 628// (addc Lo0, multLo), (sube Hi0, multHi), 629// where, 630// multHi/Lo: product of multiplication 631// Lo0: initial value of Lo register 632// Hi0: initial value of Hi register 633// Return true if pattern matching was successful. 634static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) { 635 // SUBENode's second operand must be a flag output of an SUBC node in order 636 // for the matching to be successful. 637 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); 638 639 if (SUBCNode->getOpcode() != ISD::SUBC) 640 return false; 641 642 SDValue MultHi = SUBENode->getOperand(1); 643 SDValue MultLo = SUBCNode->getOperand(1); 644 SDNode *MultNode = MultHi.getNode(); 645 unsigned MultOpc = MultHi.getOpcode(); 646 647 // MultHi and MultLo must be generated by the same node, 648 if (MultLo.getNode() != MultNode) 649 return false; 650 651 // and it must be a multiplication. 652 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 653 return false; 654 655 // MultLo amd MultHi must be the first and second output of MultNode 656 // respectively. 657 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 658 return false; 659 660 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 661 // of the values of MultNode, in which case MultNode will be removed in later 662 // phases. 663 // If there exist users other than SUBENode or SUBCNode, this function returns 664 // here, which will result in MultNode being mapped to a single MULT 665 // instruction node rather than a pair of MULT and MSUB instructions being 666 // produced. 667 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 668 return false; 669 670 SDValue Chain = CurDAG->getEntryNode(); 671 DebugLoc dl = SUBENode->getDebugLoc(); 672 673 // create MipsSub(u) node 674 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 675 676 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue, 677 MultNode->getOperand(0),// Factor 0 678 MultNode->getOperand(1),// Factor 1 679 SUBCNode->getOperand(0),// Lo0 680 SUBENode->getOperand(0));// Hi0 681 682 // create CopyFromReg nodes 683 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 684 MSub); 685 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 686 Mips::HI, MVT::i32, 687 CopyFromLo.getValue(2)); 688 689 // replace uses of sube and subc here 690 if (!SDValue(SUBCNode, 0).use_empty()) 691 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 692 693 if (!SDValue(SUBENode, 0).use_empty()) 694 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 695 696 return true; 697} 698 699static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG, 700 TargetLowering::DAGCombinerInfo &DCI, 701 const MipsSubtarget *Subtarget) { 702 if (DCI.isBeforeLegalize()) 703 return SDValue(); 704 705 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 706 SelectMadd(N, &DAG)) 707 return SDValue(N, 0); 708 709 return SDValue(); 710} 711 712static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG, 713 TargetLowering::DAGCombinerInfo &DCI, 714 const MipsSubtarget *Subtarget) { 715 if (DCI.isBeforeLegalize()) 716 return SDValue(); 717 718 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 719 SelectMsub(N, &DAG)) 720 return SDValue(N, 0); 721 722 return SDValue(); 723} 724 725static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG, 726 TargetLowering::DAGCombinerInfo &DCI, 727 const MipsSubtarget *Subtarget) { 728 if (DCI.isBeforeLegalizeOps()) 729 return SDValue(); 730 731 EVT Ty = N->getValueType(0); 732 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64; 733 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64; 734 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 735 MipsISD::DivRemU; 736 DebugLoc dl = N->getDebugLoc(); 737 738 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 739 N->getOperand(0), N->getOperand(1)); 740 SDValue InChain = DAG.getEntryNode(); 741 SDValue InGlue = DivRem; 742 743 // insert MFLO 744 if (N->hasAnyUseOfValue(0)) { 745 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty, 746 InGlue); 747 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 748 InChain = CopyFromLo.getValue(1); 749 InGlue = CopyFromLo.getValue(2); 750 } 751 752 // insert MFHI 753 if (N->hasAnyUseOfValue(1)) { 754 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 755 HI, Ty, InGlue); 756 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 757 } 758 759 return SDValue(); 760} 761 762static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 763 switch (CC) { 764 default: llvm_unreachable("Unknown fp condition code!"); 765 case ISD::SETEQ: 766 case ISD::SETOEQ: return Mips::FCOND_OEQ; 767 case ISD::SETUNE: return Mips::FCOND_UNE; 768 case ISD::SETLT: 769 case ISD::SETOLT: return Mips::FCOND_OLT; 770 case ISD::SETGT: 771 case ISD::SETOGT: return Mips::FCOND_OGT; 772 case ISD::SETLE: 773 case ISD::SETOLE: return Mips::FCOND_OLE; 774 case ISD::SETGE: 775 case ISD::SETOGE: return Mips::FCOND_OGE; 776 case ISD::SETULT: return Mips::FCOND_ULT; 777 case ISD::SETULE: return Mips::FCOND_ULE; 778 case ISD::SETUGT: return Mips::FCOND_UGT; 779 case ISD::SETUGE: return Mips::FCOND_UGE; 780 case ISD::SETUO: return Mips::FCOND_UN; 781 case ISD::SETO: return Mips::FCOND_OR; 782 case ISD::SETNE: 783 case ISD::SETONE: return Mips::FCOND_ONE; 784 case ISD::SETUEQ: return Mips::FCOND_UEQ; 785 } 786} 787 788 789// Returns true if condition code has to be inverted. 790static bool InvertFPCondCode(Mips::CondCode CC) { 791 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 792 return false; 793 794 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 795 "Illegal Condition Code"); 796 797 return true; 798} 799 800// Creates and returns an FPCmp node from a setcc node. 801// Returns Op if setcc is not a floating point comparison. 802static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) { 803 // must be a SETCC node 804 if (Op.getOpcode() != ISD::SETCC) 805 return Op; 806 807 SDValue LHS = Op.getOperand(0); 808 809 if (!LHS.getValueType().isFloatingPoint()) 810 return Op; 811 812 SDValue RHS = Op.getOperand(1); 813 DebugLoc dl = Op.getDebugLoc(); 814 815 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 816 // node if necessary. 817 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 818 819 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 820 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 821} 822 823// Creates and returns a CMovFPT/F node. 824static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 825 SDValue False, DebugLoc DL) { 826 bool invert = InvertFPCondCode((Mips::CondCode) 827 cast<ConstantSDNode>(Cond.getOperand(2)) 828 ->getSExtValue()); 829 830 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 831 True.getValueType(), True, False, Cond); 832} 833 834static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 835 TargetLowering::DAGCombinerInfo &DCI, 836 const MipsSubtarget *Subtarget) { 837 if (DCI.isBeforeLegalizeOps()) 838 return SDValue(); 839 840 SDValue SetCC = N->getOperand(0); 841 842 if ((SetCC.getOpcode() != ISD::SETCC) || 843 !SetCC.getOperand(0).getValueType().isInteger()) 844 return SDValue(); 845 846 SDValue False = N->getOperand(2); 847 EVT FalseTy = False.getValueType(); 848 849 if (!FalseTy.isInteger()) 850 return SDValue(); 851 852 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False); 853 854 if (!CN || CN->getZExtValue()) 855 return SDValue(); 856 857 const DebugLoc DL = N->getDebugLoc(); 858 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 859 SDValue True = N->getOperand(1); 860 861 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 862 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 863 864 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 865} 866 867static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG, 868 TargetLowering::DAGCombinerInfo &DCI, 869 const MipsSubtarget *Subtarget) { 870 // Pattern match EXT. 871 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 872 // => ext $dst, $src, size, pos 873 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 874 return SDValue(); 875 876 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 877 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 878 879 // Op's first operand must be a shift right. 880 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 881 return SDValue(); 882 883 // The second operand of the shift must be an immediate. 884 ConstantSDNode *CN; 885 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 886 return SDValue(); 887 888 uint64_t Pos = CN->getZExtValue(); 889 uint64_t SMPos, SMSize; 890 891 // Op's second operand must be a shifted mask. 892 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 893 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 894 return SDValue(); 895 896 // Return if the shifted mask does not start at bit 0 or the sum of its size 897 // and Pos exceeds the word's size. 898 EVT ValTy = N->getValueType(0); 899 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 900 return SDValue(); 901 902 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy, 903 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), 904 DAG.getConstant(SMSize, MVT::i32)); 905} 906 907static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG, 908 TargetLowering::DAGCombinerInfo &DCI, 909 const MipsSubtarget *Subtarget) { 910 // Pattern match INS. 911 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 912 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 913 // => ins $dst, $src, size, pos, $src1 914 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 915 return SDValue(); 916 917 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 918 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 919 ConstantSDNode *CN; 920 921 // See if Op's first operand matches (and $src1 , mask0). 922 if (And0.getOpcode() != ISD::AND) 923 return SDValue(); 924 925 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 926 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 927 return SDValue(); 928 929 // See if Op's second operand matches (and (shl $src, pos), mask1). 930 if (And1.getOpcode() != ISD::AND) 931 return SDValue(); 932 933 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 934 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 935 return SDValue(); 936 937 // The shift masks must have the same position and size. 938 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 939 return SDValue(); 940 941 SDValue Shl = And1.getOperand(0); 942 if (Shl.getOpcode() != ISD::SHL) 943 return SDValue(); 944 945 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 946 return SDValue(); 947 948 unsigned Shamt = CN->getZExtValue(); 949 950 // Return if the shift amount and the first bit position of mask are not the 951 // same. 952 EVT ValTy = N->getValueType(0); 953 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 954 return SDValue(); 955 956 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0), 957 DAG.getConstant(SMPos0, MVT::i32), 958 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0)); 959} 960 961static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG, 962 TargetLowering::DAGCombinerInfo &DCI, 963 const MipsSubtarget *Subtarget) { 964 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 965 966 if (DCI.isBeforeLegalizeOps()) 967 return SDValue(); 968 969 SDValue Add = N->getOperand(1); 970 971 if (Add.getOpcode() != ISD::ADD) 972 return SDValue(); 973 974 SDValue Lo = Add.getOperand(1); 975 976 if ((Lo.getOpcode() != MipsISD::Lo) || 977 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 978 return SDValue(); 979 980 EVT ValTy = N->getValueType(0); 981 DebugLoc DL = N->getDebugLoc(); 982 983 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 984 Add.getOperand(0)); 985 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 986} 987 988SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 989 const { 990 SelectionDAG &DAG = DCI.DAG; 991 unsigned opc = N->getOpcode(); 992 993 switch (opc) { 994 default: break; 995 case ISD::ADDE: 996 return PerformADDECombine(N, DAG, DCI, Subtarget); 997 case ISD::SUBE: 998 return PerformSUBECombine(N, DAG, DCI, Subtarget); 999 case ISD::SDIVREM: 1000 case ISD::UDIVREM: 1001 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 1002 case ISD::SELECT: 1003 return PerformSELECTCombine(N, DAG, DCI, Subtarget); 1004 case ISD::AND: 1005 return PerformANDCombine(N, DAG, DCI, Subtarget); 1006 case ISD::OR: 1007 return PerformORCombine(N, DAG, DCI, Subtarget); 1008 case ISD::ADD: 1009 return PerformADDCombine(N, DAG, DCI, Subtarget); 1010 } 1011 1012 return SDValue(); 1013} 1014 1015void 1016MipsTargetLowering::LowerOperationWrapper(SDNode *N, 1017 SmallVectorImpl<SDValue> &Results, 1018 SelectionDAG &DAG) const { 1019 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 1020 1021 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 1022 Results.push_back(Res.getValue(I)); 1023} 1024 1025void 1026MipsTargetLowering::ReplaceNodeResults(SDNode *N, 1027 SmallVectorImpl<SDValue> &Results, 1028 SelectionDAG &DAG) const { 1029 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 1030 1031 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 1032 Results.push_back(Res.getValue(I)); 1033} 1034 1035SDValue MipsTargetLowering:: 1036LowerOperation(SDValue Op, SelectionDAG &DAG) const 1037{ 1038 switch (Op.getOpcode()) 1039 { 1040 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 1041 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1042 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 1043 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 1044 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 1045 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 1046 case ISD::SELECT: return LowerSELECT(Op, DAG); 1047 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 1048 case ISD::SETCC: return LowerSETCC(Op, DAG); 1049 case ISD::VASTART: return LowerVASTART(Op, DAG); 1050 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 1051 case ISD::FABS: return LowerFABS(Op, DAG); 1052 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 1053 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 1054 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); 1055 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 1056 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); 1057 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG, true); 1058 case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false); 1059 case ISD::LOAD: return LowerLOAD(Op, DAG); 1060 case ISD::STORE: return LowerSTORE(Op, DAG); 1061 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 1062 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG); 1063 case ISD::ADD: return LowerADD(Op, DAG); 1064 } 1065 return SDValue(); 1066} 1067 1068//===----------------------------------------------------------------------===// 1069// Lower helper functions 1070//===----------------------------------------------------------------------===// 1071 1072// AddLiveIn - This helper function adds the specified physical register to the 1073// MachineFunction as a live in value. It also creates a corresponding 1074// virtual register for it. 1075static unsigned 1076AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 1077{ 1078 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 1079 MF.getRegInfo().addLiveIn(PReg, VReg); 1080 return VReg; 1081} 1082 1083// Get fp branch code (not opcode) from condition code. 1084static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 1085 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 1086 return Mips::BRANCH_T; 1087 1088 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 1089 "Invalid CondCode."); 1090 1091 return Mips::BRANCH_F; 1092} 1093 1094/* 1095static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, 1096 DebugLoc dl, 1097 const MipsSubtarget *Subtarget, 1098 const TargetInstrInfo *TII, 1099 bool isFPCmp, unsigned Opc) { 1100 // There is no need to expand CMov instructions if target has 1101 // conditional moves. 1102 if (Subtarget->hasCondMov()) 1103 return BB; 1104 1105 // To "insert" a SELECT_CC instruction, we actually have to insert the 1106 // diamond control-flow pattern. The incoming instruction knows the 1107 // destination vreg to set, the condition code register to branch on, the 1108 // true/false values to select between, and a branch opcode to use. 1109 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1110 MachineFunction::iterator It = BB; 1111 ++It; 1112 1113 // thisMBB: 1114 // ... 1115 // TrueVal = ... 1116 // setcc r1, r2, r3 1117 // bNE r1, r0, copy1MBB 1118 // fallthrough --> copy0MBB 1119 MachineBasicBlock *thisMBB = BB; 1120 MachineFunction *F = BB->getParent(); 1121 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1122 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1123 F->insert(It, copy0MBB); 1124 F->insert(It, sinkMBB); 1125 1126 // Transfer the remainder of BB and its successor edges to sinkMBB. 1127 sinkMBB->splice(sinkMBB->begin(), BB, 1128 llvm::next(MachineBasicBlock::iterator(MI)), 1129 BB->end()); 1130 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1131 1132 // Next, add the true and fallthrough blocks as its successors. 1133 BB->addSuccessor(copy0MBB); 1134 BB->addSuccessor(sinkMBB); 1135 1136 // Emit the right instruction according to the type of the operands compared 1137 if (isFPCmp) 1138 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 1139 else 1140 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 1141 .addReg(Mips::ZERO).addMBB(sinkMBB); 1142 1143 // copy0MBB: 1144 // %FalseValue = ... 1145 // # fallthrough to sinkMBB 1146 BB = copy0MBB; 1147 1148 // Update machine-CFG edges 1149 BB->addSuccessor(sinkMBB); 1150 1151 // sinkMBB: 1152 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 1153 // ... 1154 BB = sinkMBB; 1155 1156 if (isFPCmp) 1157 BuildMI(*BB, BB->begin(), dl, 1158 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 1159 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 1160 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 1161 else 1162 BuildMI(*BB, BB->begin(), dl, 1163 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 1164 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 1165 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 1166 1167 MI->eraseFromParent(); // The pseudo instruction is gone now. 1168 return BB; 1169} 1170*/ 1171 1172MachineBasicBlock * 1173MipsTargetLowering::EmitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{ 1174 // $bb: 1175 // bposge32_pseudo $vr0 1176 // => 1177 // $bb: 1178 // bposge32 $tbb 1179 // $fbb: 1180 // li $vr2, 0 1181 // b $sink 1182 // $tbb: 1183 // li $vr1, 1 1184 // $sink: 1185 // $vr0 = phi($vr2, $fbb, $vr1, $tbb) 1186 1187 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 1188 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1189 const TargetRegisterClass *RC = &Mips::CPURegsRegClass; 1190 DebugLoc DL = MI->getDebugLoc(); 1191 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1192 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB)); 1193 MachineFunction *F = BB->getParent(); 1194 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); 1195 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); 1196 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); 1197 F->insert(It, FBB); 1198 F->insert(It, TBB); 1199 F->insert(It, Sink); 1200 1201 // Transfer the remainder of BB and its successor edges to Sink. 1202 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), 1203 BB->end()); 1204 Sink->transferSuccessorsAndUpdatePHIs(BB); 1205 1206 // Add successors. 1207 BB->addSuccessor(FBB); 1208 BB->addSuccessor(TBB); 1209 FBB->addSuccessor(Sink); 1210 TBB->addSuccessor(Sink); 1211 1212 // Insert the real bposge32 instruction to $BB. 1213 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB); 1214 1215 // Fill $FBB. 1216 unsigned VR2 = RegInfo.createVirtualRegister(RC); 1217 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) 1218 .addReg(Mips::ZERO).addImm(0); 1219 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 1220 1221 // Fill $TBB. 1222 unsigned VR1 = RegInfo.createVirtualRegister(RC); 1223 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) 1224 .addReg(Mips::ZERO).addImm(1); 1225 1226 // Insert phi function to $Sink. 1227 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 1228 MI->getOperand(0).getReg()) 1229 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB); 1230 1231 MI->eraseFromParent(); // The pseudo instruction is gone now. 1232 return Sink; 1233} 1234 1235MachineBasicBlock * 1236MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1237 MachineBasicBlock *BB) const { 1238 switch (MI->getOpcode()) { 1239 default: llvm_unreachable("Unexpected instr type to insert"); 1240 case Mips::ATOMIC_LOAD_ADD_I8: 1241 case Mips::ATOMIC_LOAD_ADD_I8_P8: 1242 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 1243 case Mips::ATOMIC_LOAD_ADD_I16: 1244 case Mips::ATOMIC_LOAD_ADD_I16_P8: 1245 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 1246 case Mips::ATOMIC_LOAD_ADD_I32: 1247 case Mips::ATOMIC_LOAD_ADD_I32_P8: 1248 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); 1249 case Mips::ATOMIC_LOAD_ADD_I64: 1250 case Mips::ATOMIC_LOAD_ADD_I64_P8: 1251 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu); 1252 1253 case Mips::ATOMIC_LOAD_AND_I8: 1254 case Mips::ATOMIC_LOAD_AND_I8_P8: 1255 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 1256 case Mips::ATOMIC_LOAD_AND_I16: 1257 case Mips::ATOMIC_LOAD_AND_I16_P8: 1258 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 1259 case Mips::ATOMIC_LOAD_AND_I32: 1260 case Mips::ATOMIC_LOAD_AND_I32_P8: 1261 return EmitAtomicBinary(MI, BB, 4, Mips::AND); 1262 case Mips::ATOMIC_LOAD_AND_I64: 1263 case Mips::ATOMIC_LOAD_AND_I64_P8: 1264 return EmitAtomicBinary(MI, BB, 8, Mips::AND64); 1265 1266 case Mips::ATOMIC_LOAD_OR_I8: 1267 case Mips::ATOMIC_LOAD_OR_I8_P8: 1268 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 1269 case Mips::ATOMIC_LOAD_OR_I16: 1270 case Mips::ATOMIC_LOAD_OR_I16_P8: 1271 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 1272 case Mips::ATOMIC_LOAD_OR_I32: 1273 case Mips::ATOMIC_LOAD_OR_I32_P8: 1274 return EmitAtomicBinary(MI, BB, 4, Mips::OR); 1275 case Mips::ATOMIC_LOAD_OR_I64: 1276 case Mips::ATOMIC_LOAD_OR_I64_P8: 1277 return EmitAtomicBinary(MI, BB, 8, Mips::OR64); 1278 1279 case Mips::ATOMIC_LOAD_XOR_I8: 1280 case Mips::ATOMIC_LOAD_XOR_I8_P8: 1281 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 1282 case Mips::ATOMIC_LOAD_XOR_I16: 1283 case Mips::ATOMIC_LOAD_XOR_I16_P8: 1284 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 1285 case Mips::ATOMIC_LOAD_XOR_I32: 1286 case Mips::ATOMIC_LOAD_XOR_I32_P8: 1287 return EmitAtomicBinary(MI, BB, 4, Mips::XOR); 1288 case Mips::ATOMIC_LOAD_XOR_I64: 1289 case Mips::ATOMIC_LOAD_XOR_I64_P8: 1290 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64); 1291 1292 case Mips::ATOMIC_LOAD_NAND_I8: 1293 case Mips::ATOMIC_LOAD_NAND_I8_P8: 1294 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); 1295 case Mips::ATOMIC_LOAD_NAND_I16: 1296 case Mips::ATOMIC_LOAD_NAND_I16_P8: 1297 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); 1298 case Mips::ATOMIC_LOAD_NAND_I32: 1299 case Mips::ATOMIC_LOAD_NAND_I32_P8: 1300 return EmitAtomicBinary(MI, BB, 4, 0, true); 1301 case Mips::ATOMIC_LOAD_NAND_I64: 1302 case Mips::ATOMIC_LOAD_NAND_I64_P8: 1303 return EmitAtomicBinary(MI, BB, 8, 0, true); 1304 1305 case Mips::ATOMIC_LOAD_SUB_I8: 1306 case Mips::ATOMIC_LOAD_SUB_I8_P8: 1307 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 1308 case Mips::ATOMIC_LOAD_SUB_I16: 1309 case Mips::ATOMIC_LOAD_SUB_I16_P8: 1310 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 1311 case Mips::ATOMIC_LOAD_SUB_I32: 1312 case Mips::ATOMIC_LOAD_SUB_I32_P8: 1313 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); 1314 case Mips::ATOMIC_LOAD_SUB_I64: 1315 case Mips::ATOMIC_LOAD_SUB_I64_P8: 1316 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu); 1317 1318 case Mips::ATOMIC_SWAP_I8: 1319 case Mips::ATOMIC_SWAP_I8_P8: 1320 return EmitAtomicBinaryPartword(MI, BB, 1, 0); 1321 case Mips::ATOMIC_SWAP_I16: 1322 case Mips::ATOMIC_SWAP_I16_P8: 1323 return EmitAtomicBinaryPartword(MI, BB, 2, 0); 1324 case Mips::ATOMIC_SWAP_I32: 1325 case Mips::ATOMIC_SWAP_I32_P8: 1326 return EmitAtomicBinary(MI, BB, 4, 0); 1327 case Mips::ATOMIC_SWAP_I64: 1328 case Mips::ATOMIC_SWAP_I64_P8: 1329 return EmitAtomicBinary(MI, BB, 8, 0); 1330 1331 case Mips::ATOMIC_CMP_SWAP_I8: 1332 case Mips::ATOMIC_CMP_SWAP_I8_P8: 1333 return EmitAtomicCmpSwapPartword(MI, BB, 1); 1334 case Mips::ATOMIC_CMP_SWAP_I16: 1335 case Mips::ATOMIC_CMP_SWAP_I16_P8: 1336 return EmitAtomicCmpSwapPartword(MI, BB, 2); 1337 case Mips::ATOMIC_CMP_SWAP_I32: 1338 case Mips::ATOMIC_CMP_SWAP_I32_P8: 1339 return EmitAtomicCmpSwap(MI, BB, 4); 1340 case Mips::ATOMIC_CMP_SWAP_I64: 1341 case Mips::ATOMIC_CMP_SWAP_I64_P8: 1342 return EmitAtomicCmpSwap(MI, BB, 8); 1343 case Mips::BPOSGE32_PSEUDO: 1344 return EmitBPOSGE32(MI, BB); 1345 } 1346} 1347 1348// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1349// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1350MachineBasicBlock * 1351MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 1352 unsigned Size, unsigned BinOpcode, 1353 bool Nand) const { 1354 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 1355 1356 MachineFunction *MF = BB->getParent(); 1357 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1358 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1359 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1360 DebugLoc dl = MI->getDebugLoc(); 1361 unsigned LL, SC, AND, NOR, ZERO, BEQ; 1362 1363 if (Size == 4) { 1364 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1365 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1366 AND = Mips::AND; 1367 NOR = Mips::NOR; 1368 ZERO = Mips::ZERO; 1369 BEQ = Mips::BEQ; 1370 } 1371 else { 1372 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 1373 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 1374 AND = Mips::AND64; 1375 NOR = Mips::NOR64; 1376 ZERO = Mips::ZERO_64; 1377 BEQ = Mips::BEQ64; 1378 } 1379 1380 unsigned OldVal = MI->getOperand(0).getReg(); 1381 unsigned Ptr = MI->getOperand(1).getReg(); 1382 unsigned Incr = MI->getOperand(2).getReg(); 1383 1384 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1385 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1386 unsigned Success = RegInfo.createVirtualRegister(RC); 1387 1388 // insert new blocks after the current block 1389 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1390 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1391 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1392 MachineFunction::iterator It = BB; 1393 ++It; 1394 MF->insert(It, loopMBB); 1395 MF->insert(It, exitMBB); 1396 1397 // Transfer the remainder of BB and its successor edges to exitMBB. 1398 exitMBB->splice(exitMBB->begin(), BB, 1399 llvm::next(MachineBasicBlock::iterator(MI)), 1400 BB->end()); 1401 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1402 1403 // thisMBB: 1404 // ... 1405 // fallthrough --> loopMBB 1406 BB->addSuccessor(loopMBB); 1407 loopMBB->addSuccessor(loopMBB); 1408 loopMBB->addSuccessor(exitMBB); 1409 1410 // loopMBB: 1411 // ll oldval, 0(ptr) 1412 // <binop> storeval, oldval, incr 1413 // sc success, storeval, 0(ptr) 1414 // beq success, $0, loopMBB 1415 BB = loopMBB; 1416 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1417 if (Nand) { 1418 // and andres, oldval, incr 1419 // nor storeval, $0, andres 1420 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1421 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1422 } else if (BinOpcode) { 1423 // <binop> storeval, oldval, incr 1424 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1425 } else { 1426 StoreVal = Incr; 1427 } 1428 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1429 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1430 1431 MI->eraseFromParent(); // The instruction is gone now. 1432 1433 return exitMBB; 1434} 1435 1436MachineBasicBlock * 1437MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, 1438 MachineBasicBlock *BB, 1439 unsigned Size, unsigned BinOpcode, 1440 bool Nand) const { 1441 assert((Size == 1 || Size == 2) && 1442 "Unsupported size for EmitAtomicBinaryPartial."); 1443 1444 MachineFunction *MF = BB->getParent(); 1445 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1446 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1447 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1448 DebugLoc dl = MI->getDebugLoc(); 1449 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1450 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1451 1452 unsigned Dest = MI->getOperand(0).getReg(); 1453 unsigned Ptr = MI->getOperand(1).getReg(); 1454 unsigned Incr = MI->getOperand(2).getReg(); 1455 1456 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1457 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1458 unsigned Mask = RegInfo.createVirtualRegister(RC); 1459 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1460 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1461 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1462 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1463 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1464 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1465 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1466 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1467 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1468 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1469 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1470 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1471 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1472 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1473 unsigned Success = RegInfo.createVirtualRegister(RC); 1474 1475 // insert new blocks after the current block 1476 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1477 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1478 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1479 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1480 MachineFunction::iterator It = BB; 1481 ++It; 1482 MF->insert(It, loopMBB); 1483 MF->insert(It, sinkMBB); 1484 MF->insert(It, exitMBB); 1485 1486 // Transfer the remainder of BB and its successor edges to exitMBB. 1487 exitMBB->splice(exitMBB->begin(), BB, 1488 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1489 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1490 1491 BB->addSuccessor(loopMBB); 1492 loopMBB->addSuccessor(loopMBB); 1493 loopMBB->addSuccessor(sinkMBB); 1494 sinkMBB->addSuccessor(exitMBB); 1495 1496 // thisMBB: 1497 // addiu masklsb2,$0,-4 # 0xfffffffc 1498 // and alignedaddr,ptr,masklsb2 1499 // andi ptrlsb2,ptr,3 1500 // sll shiftamt,ptrlsb2,3 1501 // ori maskupper,$0,255 # 0xff 1502 // sll mask,maskupper,shiftamt 1503 // nor mask2,$0,mask 1504 // sll incr2,incr,shiftamt 1505 1506 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1507 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1508 .addReg(Mips::ZERO).addImm(-4); 1509 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1510 .addReg(Ptr).addReg(MaskLSB2); 1511 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1512 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1513 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1514 .addReg(Mips::ZERO).addImm(MaskImm); 1515 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1516 .addReg(ShiftAmt).addReg(MaskUpper); 1517 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1518 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); 1519 1520 // atomic.load.binop 1521 // loopMBB: 1522 // ll oldval,0(alignedaddr) 1523 // binop binopres,oldval,incr2 1524 // and newval,binopres,mask 1525 // and maskedoldval0,oldval,mask2 1526 // or storeval,maskedoldval0,newval 1527 // sc success,storeval,0(alignedaddr) 1528 // beq success,$0,loopMBB 1529 1530 // atomic.swap 1531 // loopMBB: 1532 // ll oldval,0(alignedaddr) 1533 // and newval,incr2,mask 1534 // and maskedoldval0,oldval,mask2 1535 // or storeval,maskedoldval0,newval 1536 // sc success,storeval,0(alignedaddr) 1537 // beq success,$0,loopMBB 1538 1539 BB = loopMBB; 1540 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1541 if (Nand) { 1542 // and andres, oldval, incr2 1543 // nor binopres, $0, andres 1544 // and newval, binopres, mask 1545 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1546 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes) 1547 .addReg(Mips::ZERO).addReg(AndRes); 1548 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1549 } else if (BinOpcode) { 1550 // <binop> binopres, oldval, incr2 1551 // and newval, binopres, mask 1552 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1553 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1554 } else {// atomic.swap 1555 // and newval, incr2, mask 1556 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1557 } 1558 1559 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1560 .addReg(OldVal).addReg(Mask2); 1561 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1562 .addReg(MaskedOldVal0).addReg(NewVal); 1563 BuildMI(BB, dl, TII->get(SC), Success) 1564 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1565 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1566 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1567 1568 // sinkMBB: 1569 // and maskedoldval1,oldval,mask 1570 // srl srlres,maskedoldval1,shiftamt 1571 // sll sllres,srlres,24 1572 // sra dest,sllres,24 1573 BB = sinkMBB; 1574 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1575 1576 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1577 .addReg(OldVal).addReg(Mask); 1578 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1579 .addReg(ShiftAmt).addReg(MaskedOldVal1); 1580 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1581 .addReg(SrlRes).addImm(ShiftImm); 1582 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1583 .addReg(SllRes).addImm(ShiftImm); 1584 1585 MI->eraseFromParent(); // The instruction is gone now. 1586 1587 return exitMBB; 1588} 1589 1590MachineBasicBlock * 1591MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 1592 MachineBasicBlock *BB, 1593 unsigned Size) const { 1594 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1595 1596 MachineFunction *MF = BB->getParent(); 1597 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1598 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1599 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1600 DebugLoc dl = MI->getDebugLoc(); 1601 unsigned LL, SC, ZERO, BNE, BEQ; 1602 1603 if (Size == 4) { 1604 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1605 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1606 ZERO = Mips::ZERO; 1607 BNE = Mips::BNE; 1608 BEQ = Mips::BEQ; 1609 } 1610 else { 1611 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 1612 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 1613 ZERO = Mips::ZERO_64; 1614 BNE = Mips::BNE64; 1615 BEQ = Mips::BEQ64; 1616 } 1617 1618 unsigned Dest = MI->getOperand(0).getReg(); 1619 unsigned Ptr = MI->getOperand(1).getReg(); 1620 unsigned OldVal = MI->getOperand(2).getReg(); 1621 unsigned NewVal = MI->getOperand(3).getReg(); 1622 1623 unsigned Success = RegInfo.createVirtualRegister(RC); 1624 1625 // insert new blocks after the current block 1626 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1627 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1628 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1629 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1630 MachineFunction::iterator It = BB; 1631 ++It; 1632 MF->insert(It, loop1MBB); 1633 MF->insert(It, loop2MBB); 1634 MF->insert(It, exitMBB); 1635 1636 // Transfer the remainder of BB and its successor edges to exitMBB. 1637 exitMBB->splice(exitMBB->begin(), BB, 1638 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1639 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1640 1641 // thisMBB: 1642 // ... 1643 // fallthrough --> loop1MBB 1644 BB->addSuccessor(loop1MBB); 1645 loop1MBB->addSuccessor(exitMBB); 1646 loop1MBB->addSuccessor(loop2MBB); 1647 loop2MBB->addSuccessor(loop1MBB); 1648 loop2MBB->addSuccessor(exitMBB); 1649 1650 // loop1MBB: 1651 // ll dest, 0(ptr) 1652 // bne dest, oldval, exitMBB 1653 BB = loop1MBB; 1654 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1655 BuildMI(BB, dl, TII->get(BNE)) 1656 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1657 1658 // loop2MBB: 1659 // sc success, newval, 0(ptr) 1660 // beq success, $0, loop1MBB 1661 BB = loop2MBB; 1662 BuildMI(BB, dl, TII->get(SC), Success) 1663 .addReg(NewVal).addReg(Ptr).addImm(0); 1664 BuildMI(BB, dl, TII->get(BEQ)) 1665 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1666 1667 MI->eraseFromParent(); // The instruction is gone now. 1668 1669 return exitMBB; 1670} 1671 1672MachineBasicBlock * 1673MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, 1674 MachineBasicBlock *BB, 1675 unsigned Size) const { 1676 assert((Size == 1 || Size == 2) && 1677 "Unsupported size for EmitAtomicCmpSwapPartial."); 1678 1679 MachineFunction *MF = BB->getParent(); 1680 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1681 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1682 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1683 DebugLoc dl = MI->getDebugLoc(); 1684 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1685 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1686 1687 unsigned Dest = MI->getOperand(0).getReg(); 1688 unsigned Ptr = MI->getOperand(1).getReg(); 1689 unsigned CmpVal = MI->getOperand(2).getReg(); 1690 unsigned NewVal = MI->getOperand(3).getReg(); 1691 1692 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1693 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1694 unsigned Mask = RegInfo.createVirtualRegister(RC); 1695 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1696 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1697 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1698 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1699 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1700 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1701 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1702 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1703 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1704 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1705 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1706 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1707 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1708 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1709 unsigned Success = RegInfo.createVirtualRegister(RC); 1710 1711 // insert new blocks after the current block 1712 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1713 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1714 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1715 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1716 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1717 MachineFunction::iterator It = BB; 1718 ++It; 1719 MF->insert(It, loop1MBB); 1720 MF->insert(It, loop2MBB); 1721 MF->insert(It, sinkMBB); 1722 MF->insert(It, exitMBB); 1723 1724 // Transfer the remainder of BB and its successor edges to exitMBB. 1725 exitMBB->splice(exitMBB->begin(), BB, 1726 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1727 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1728 1729 BB->addSuccessor(loop1MBB); 1730 loop1MBB->addSuccessor(sinkMBB); 1731 loop1MBB->addSuccessor(loop2MBB); 1732 loop2MBB->addSuccessor(loop1MBB); 1733 loop2MBB->addSuccessor(sinkMBB); 1734 sinkMBB->addSuccessor(exitMBB); 1735 1736 // FIXME: computation of newval2 can be moved to loop2MBB. 1737 // thisMBB: 1738 // addiu masklsb2,$0,-4 # 0xfffffffc 1739 // and alignedaddr,ptr,masklsb2 1740 // andi ptrlsb2,ptr,3 1741 // sll shiftamt,ptrlsb2,3 1742 // ori maskupper,$0,255 # 0xff 1743 // sll mask,maskupper,shiftamt 1744 // nor mask2,$0,mask 1745 // andi maskedcmpval,cmpval,255 1746 // sll shiftedcmpval,maskedcmpval,shiftamt 1747 // andi maskednewval,newval,255 1748 // sll shiftednewval,maskednewval,shiftamt 1749 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1750 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1751 .addReg(Mips::ZERO).addImm(-4); 1752 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1753 .addReg(Ptr).addReg(MaskLSB2); 1754 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1755 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1756 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1757 .addReg(Mips::ZERO).addImm(MaskImm); 1758 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1759 .addReg(ShiftAmt).addReg(MaskUpper); 1760 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1761 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) 1762 .addReg(CmpVal).addImm(MaskImm); 1763 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) 1764 .addReg(ShiftAmt).addReg(MaskedCmpVal); 1765 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) 1766 .addReg(NewVal).addImm(MaskImm); 1767 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) 1768 .addReg(ShiftAmt).addReg(MaskedNewVal); 1769 1770 // loop1MBB: 1771 // ll oldval,0(alginedaddr) 1772 // and maskedoldval0,oldval,mask 1773 // bne maskedoldval0,shiftedcmpval,sinkMBB 1774 BB = loop1MBB; 1775 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1776 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1777 .addReg(OldVal).addReg(Mask); 1778 BuildMI(BB, dl, TII->get(Mips::BNE)) 1779 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1780 1781 // loop2MBB: 1782 // and maskedoldval1,oldval,mask2 1783 // or storeval,maskedoldval1,shiftednewval 1784 // sc success,storeval,0(alignedaddr) 1785 // beq success,$0,loop1MBB 1786 BB = loop2MBB; 1787 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1788 .addReg(OldVal).addReg(Mask2); 1789 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1790 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1791 BuildMI(BB, dl, TII->get(SC), Success) 1792 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1793 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1794 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1795 1796 // sinkMBB: 1797 // srl srlres,maskedoldval0,shiftamt 1798 // sll sllres,srlres,24 1799 // sra dest,sllres,24 1800 BB = sinkMBB; 1801 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1802 1803 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1804 .addReg(ShiftAmt).addReg(MaskedOldVal0); 1805 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1806 .addReg(SrlRes).addImm(ShiftImm); 1807 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1808 .addReg(SllRes).addImm(ShiftImm); 1809 1810 MI->eraseFromParent(); // The instruction is gone now. 1811 1812 return exitMBB; 1813} 1814 1815//===----------------------------------------------------------------------===// 1816// Misc Lower Operation implementation 1817//===----------------------------------------------------------------------===// 1818SDValue MipsTargetLowering:: 1819LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1820{ 1821 // The first operand is the chain, the second is the condition, the third is 1822 // the block to branch to if the condition is true. 1823 SDValue Chain = Op.getOperand(0); 1824 SDValue Dest = Op.getOperand(2); 1825 DebugLoc dl = Op.getDebugLoc(); 1826 1827 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 1828 1829 // Return if flag is not set by a floating point comparison. 1830 if (CondRes.getOpcode() != MipsISD::FPCmp) 1831 return Op; 1832 1833 SDValue CCNode = CondRes.getOperand(2); 1834 Mips::CondCode CC = 1835 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1836 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 1837 1838 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 1839 Dest, CondRes); 1840} 1841 1842SDValue MipsTargetLowering:: 1843LowerSELECT(SDValue Op, SelectionDAG &DAG) const 1844{ 1845 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 1846 1847 // Return if flag is not set by a floating point comparison. 1848 if (Cond.getOpcode() != MipsISD::FPCmp) 1849 return Op; 1850 1851 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1852 Op.getDebugLoc()); 1853} 1854 1855SDValue MipsTargetLowering:: 1856LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 1857{ 1858 DebugLoc DL = Op.getDebugLoc(); 1859 EVT Ty = Op.getOperand(0).getValueType(); 1860 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty), 1861 Op.getOperand(0), Op.getOperand(1), 1862 Op.getOperand(4)); 1863 1864 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2), 1865 Op.getOperand(3)); 1866} 1867 1868SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1869 SDValue Cond = CreateFPCmp(DAG, Op); 1870 1871 assert(Cond.getOpcode() == MipsISD::FPCmp && 1872 "Floating point operand expected."); 1873 1874 SDValue True = DAG.getConstant(1, MVT::i32); 1875 SDValue False = DAG.getConstant(0, MVT::i32); 1876 1877 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc()); 1878} 1879 1880SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 1881 SelectionDAG &DAG) const { 1882 // FIXME there isn't actually debug info here 1883 DebugLoc dl = Op.getDebugLoc(); 1884 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1885 1886 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1887 const MipsTargetObjectFile &TLOF = 1888 (const MipsTargetObjectFile&)getObjFileLowering(); 1889 1890 // %gp_rel relocation 1891 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1892 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1893 MipsII::MO_GPREL); 1894 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, 1895 DAG.getVTList(MVT::i32), &GA, 1); 1896 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32); 1897 return DAG.getNode(ISD::ADD, dl, MVT::i32, GPReg, GPRelNode); 1898 } 1899 1900 // %hi/%lo relocation 1901 return getAddrNonPIC(Op, DAG); 1902 } 1903 1904 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV))) 1905 return getAddrLocal(Op, DAG, HasMips64); 1906 1907 if (LargeGOT) 1908 return getAddrGlobalLargeGOT(Op, DAG, MipsII::MO_GOT_HI16, 1909 MipsII::MO_GOT_LO16); 1910 1911 return getAddrGlobal(Op, DAG, 1912 HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16); 1913} 1914 1915SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 1916 SelectionDAG &DAG) const { 1917 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1918 return getAddrNonPIC(Op, DAG); 1919 1920 return getAddrLocal(Op, DAG, HasMips64); 1921} 1922 1923SDValue MipsTargetLowering:: 1924LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1925{ 1926 // If the relocation model is PIC, use the General Dynamic TLS Model or 1927 // Local Dynamic TLS model, otherwise use the Initial Exec or 1928 // Local Exec TLS Model. 1929 1930 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1931 DebugLoc dl = GA->getDebugLoc(); 1932 const GlobalValue *GV = GA->getGlobal(); 1933 EVT PtrVT = getPointerTy(); 1934 1935 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1936 1937 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1938 // General Dynamic and Local Dynamic TLS Model. 1939 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1940 : MipsII::MO_TLSGD; 1941 1942 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag); 1943 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, 1944 GetGlobalReg(DAG, PtrVT), TGA); 1945 unsigned PtrSize = PtrVT.getSizeInBits(); 1946 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1947 1948 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1949 1950 ArgListTy Args; 1951 ArgListEntry Entry; 1952 Entry.Node = Argument; 1953 Entry.Ty = PtrTy; 1954 Args.push_back(Entry); 1955 1956 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy, 1957 false, false, false, false, 0, CallingConv::C, 1958 /*isTailCall=*/false, /*doesNotRet=*/false, 1959 /*isReturnValueUsed=*/true, 1960 TlsGetAddr, Args, DAG, dl); 1961 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1962 1963 SDValue Ret = CallResult.first; 1964 1965 if (model != TLSModel::LocalDynamic) 1966 return Ret; 1967 1968 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1969 MipsII::MO_DTPREL_HI); 1970 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 1971 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1972 MipsII::MO_DTPREL_LO); 1973 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 1974 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret); 1975 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo); 1976 } 1977 1978 SDValue Offset; 1979 if (model == TLSModel::InitialExec) { 1980 // Initial Exec TLS Model 1981 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1982 MipsII::MO_GOTTPREL); 1983 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT), 1984 TGA); 1985 Offset = DAG.getLoad(PtrVT, dl, 1986 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1987 false, false, false, 0); 1988 } else { 1989 // Local Exec TLS Model 1990 assert(model == TLSModel::LocalExec); 1991 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1992 MipsII::MO_TPREL_HI); 1993 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1994 MipsII::MO_TPREL_LO); 1995 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 1996 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 1997 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1998 } 1999 2000 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT); 2001 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 2002} 2003 2004SDValue MipsTargetLowering:: 2005LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 2006{ 2007 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 2008 return getAddrNonPIC(Op, DAG); 2009 2010 return getAddrLocal(Op, DAG, HasMips64); 2011} 2012 2013SDValue MipsTargetLowering:: 2014LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 2015{ 2016 // gp_rel relocation 2017 // FIXME: we should reference the constant pool using small data sections, 2018 // but the asm printer currently doesn't support this feature without 2019 // hacking it. This feature should come soon so we can uncomment the 2020 // stuff below. 2021 //if (IsInSmallSection(C->getType())) { 2022 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 2023 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 2024 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 2025 2026 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 2027 return getAddrNonPIC(Op, DAG); 2028 2029 return getAddrLocal(Op, DAG, HasMips64); 2030} 2031 2032SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 2033 MachineFunction &MF = DAG.getMachineFunction(); 2034 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2035 2036 DebugLoc dl = Op.getDebugLoc(); 2037 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 2038 getPointerTy()); 2039 2040 // vastart just stores the address of the VarArgsFrameIndex slot into the 2041 // memory location argument. 2042 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2043 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 2044 MachinePointerInfo(SV), false, false, 0); 2045} 2046 2047static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 2048 EVT TyX = Op.getOperand(0).getValueType(); 2049 EVT TyY = Op.getOperand(1).getValueType(); 2050 SDValue Const1 = DAG.getConstant(1, MVT::i32); 2051 SDValue Const31 = DAG.getConstant(31, MVT::i32); 2052 DebugLoc DL = Op.getDebugLoc(); 2053 SDValue Res; 2054 2055 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2056 // to i32. 2057 SDValue X = (TyX == MVT::f32) ? 2058 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2059 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2060 Const1); 2061 SDValue Y = (TyY == MVT::f32) ? 2062 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 2063 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 2064 Const1); 2065 2066 if (HasR2) { 2067 // ext E, Y, 31, 1 ; extract bit31 of Y 2068 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2069 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2070 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2071 } else { 2072 // sll SllX, X, 1 2073 // srl SrlX, SllX, 1 2074 // srl SrlY, Y, 31 2075 // sll SllY, SrlX, 31 2076 // or Or, SrlX, SllY 2077 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2078 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2079 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2080 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2081 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2082 } 2083 2084 if (TyX == MVT::f32) 2085 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2086 2087 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2088 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 2089 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2090} 2091 2092static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 2093 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2094 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2095 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2096 SDValue Const1 = DAG.getConstant(1, MVT::i32); 2097 DebugLoc DL = Op.getDebugLoc(); 2098 2099 // Bitcast to integer nodes. 2100 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2101 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2102 2103 if (HasR2) { 2104 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2105 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2106 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2107 DAG.getConstant(WidthY - 1, MVT::i32), Const1); 2108 2109 if (WidthX > WidthY) 2110 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2111 else if (WidthY > WidthX) 2112 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2113 2114 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2115 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X); 2116 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2117 } 2118 2119 // (d)sll SllX, X, 1 2120 // (d)srl SrlX, SllX, 1 2121 // (d)srl SrlY, Y, width(Y)-1 2122 // (d)sll SllY, SrlX, width(Y)-1 2123 // or Or, SrlX, SllY 2124 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2125 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2126 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2127 DAG.getConstant(WidthY - 1, MVT::i32)); 2128 2129 if (WidthX > WidthY) 2130 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2131 else if (WidthY > WidthX) 2132 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2133 2134 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2135 DAG.getConstant(WidthX - 1, MVT::i32)); 2136 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2137 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2138} 2139 2140SDValue 2141MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2142 if (Subtarget->hasMips64()) 2143 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2()); 2144 2145 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2()); 2146} 2147 2148static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 2149 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 2150 DebugLoc DL = Op.getDebugLoc(); 2151 2152 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2153 // to i32. 2154 SDValue X = (Op.getValueType() == MVT::f32) ? 2155 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2156 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2157 Const1); 2158 2159 // Clear MSB. 2160 if (HasR2) 2161 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 2162 DAG.getRegister(Mips::ZERO, MVT::i32), 2163 DAG.getConstant(31, MVT::i32), Const1, X); 2164 else { 2165 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2166 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2167 } 2168 2169 if (Op.getValueType() == MVT::f32) 2170 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 2171 2172 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2173 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 2174 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2175} 2176 2177static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 2178 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 2179 DebugLoc DL = Op.getDebugLoc(); 2180 2181 // Bitcast to integer node. 2182 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 2183 2184 // Clear MSB. 2185 if (HasR2) 2186 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 2187 DAG.getRegister(Mips::ZERO_64, MVT::i64), 2188 DAG.getConstant(63, MVT::i32), Const1, X); 2189 else { 2190 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 2191 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 2192 } 2193 2194 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 2195} 2196 2197SDValue 2198MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const { 2199 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64)) 2200 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2()); 2201 2202 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2()); 2203} 2204 2205SDValue MipsTargetLowering:: 2206LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2207 // check the depth 2208 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2209 "Frame address can only be determined for current frame."); 2210 2211 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2212 MFI->setFrameAddressIsTaken(true); 2213 EVT VT = Op.getValueType(); 2214 DebugLoc dl = Op.getDebugLoc(); 2215 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 2216 IsN64 ? Mips::FP_64 : Mips::FP, VT); 2217 return FrameAddr; 2218} 2219 2220SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op, 2221 SelectionDAG &DAG) const { 2222 // check the depth 2223 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2224 "Return address can be determined only for current frame."); 2225 2226 MachineFunction &MF = DAG.getMachineFunction(); 2227 MachineFrameInfo *MFI = MF.getFrameInfo(); 2228 MVT VT = Op.getSimpleValueType(); 2229 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA; 2230 MFI->setReturnAddressIsTaken(true); 2231 2232 // Return RA, which contains the return address. Mark it an implicit live-in. 2233 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2234 return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT); 2235} 2236 2237// TODO: set SType according to the desired memory barrier behavior. 2238SDValue 2239MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const { 2240 unsigned SType = 0; 2241 DebugLoc dl = Op.getDebugLoc(); 2242 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 2243 DAG.getConstant(SType, MVT::i32)); 2244} 2245 2246SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op, 2247 SelectionDAG &DAG) const { 2248 // FIXME: Need pseudo-fence for 'singlethread' fences 2249 // FIXME: Set SType for weaker fences where supported/appropriate. 2250 unsigned SType = 0; 2251 DebugLoc dl = Op.getDebugLoc(); 2252 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 2253 DAG.getConstant(SType, MVT::i32)); 2254} 2255 2256SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op, 2257 SelectionDAG &DAG) const { 2258 DebugLoc DL = Op.getDebugLoc(); 2259 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2260 SDValue Shamt = Op.getOperand(2); 2261 2262 // if shamt < 32: 2263 // lo = (shl lo, shamt) 2264 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2265 // else: 2266 // lo = 0 2267 // hi = (shl lo, shamt[4:0]) 2268 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2269 DAG.getConstant(-1, MVT::i32)); 2270 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, 2271 DAG.getConstant(1, MVT::i32)); 2272 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, 2273 Not); 2274 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); 2275 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 2276 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); 2277 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2278 DAG.getConstant(0x20, MVT::i32)); 2279 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 2280 DAG.getConstant(0, MVT::i32), ShiftLeftLo); 2281 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or); 2282 2283 SDValue Ops[2] = {Lo, Hi}; 2284 return DAG.getMergeValues(Ops, 2, DL); 2285} 2286 2287SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2288 bool IsSRA) const { 2289 DebugLoc DL = Op.getDebugLoc(); 2290 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2291 SDValue Shamt = Op.getOperand(2); 2292 2293 // if shamt < 32: 2294 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2295 // if isSRA: 2296 // hi = (sra hi, shamt) 2297 // else: 2298 // hi = (srl hi, shamt) 2299 // else: 2300 // if isSRA: 2301 // lo = (sra hi, shamt[4:0]) 2302 // hi = (sra hi, 31) 2303 // else: 2304 // lo = (srl hi, shamt[4:0]) 2305 // hi = 0 2306 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2307 DAG.getConstant(-1, MVT::i32)); 2308 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, 2309 DAG.getConstant(1, MVT::i32)); 2310 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not); 2311 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); 2312 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 2313 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, 2314 Hi, Shamt); 2315 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2316 DAG.getConstant(0x20, MVT::i32)); 2317 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi, 2318 DAG.getConstant(31, MVT::i32)); 2319 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or); 2320 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 2321 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32), 2322 ShiftRightHi); 2323 2324 SDValue Ops[2] = {Lo, Hi}; 2325 return DAG.getMergeValues(Ops, 2, DL); 2326} 2327 2328static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2329 SDValue Chain, SDValue Src, unsigned Offset) { 2330 SDValue Ptr = LD->getBasePtr(); 2331 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2332 EVT BasePtrVT = Ptr.getValueType(); 2333 DebugLoc DL = LD->getDebugLoc(); 2334 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2335 2336 if (Offset) 2337 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2338 DAG.getConstant(Offset, BasePtrVT)); 2339 2340 SDValue Ops[] = { Chain, Ptr, Src }; 2341 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2342 LD->getMemOperand()); 2343} 2344 2345// Expand an unaligned 32 or 64-bit integer load node. 2346SDValue MipsTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2347 LoadSDNode *LD = cast<LoadSDNode>(Op); 2348 EVT MemVT = LD->getMemoryVT(); 2349 2350 // Return if load is aligned or if MemVT is neither i32 nor i64. 2351 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2352 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2353 return SDValue(); 2354 2355 bool IsLittle = Subtarget->isLittle(); 2356 EVT VT = Op.getValueType(); 2357 ISD::LoadExtType ExtType = LD->getExtensionType(); 2358 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2359 2360 assert((VT == MVT::i32) || (VT == MVT::i64)); 2361 2362 // Expand 2363 // (set dst, (i64 (load baseptr))) 2364 // to 2365 // (set tmp, (ldl (add baseptr, 7), undef)) 2366 // (set dst, (ldr baseptr, tmp)) 2367 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2368 SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2369 IsLittle ? 7 : 0); 2370 return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2371 IsLittle ? 0 : 7); 2372 } 2373 2374 SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2375 IsLittle ? 3 : 0); 2376 SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2377 IsLittle ? 0 : 3); 2378 2379 // Expand 2380 // (set dst, (i32 (load baseptr))) or 2381 // (set dst, (i64 (sextload baseptr))) or 2382 // (set dst, (i64 (extload baseptr))) 2383 // to 2384 // (set tmp, (lwl (add baseptr, 3), undef)) 2385 // (set dst, (lwr baseptr, tmp)) 2386 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2387 (ExtType == ISD::EXTLOAD)) 2388 return LWR; 2389 2390 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2391 2392 // Expand 2393 // (set dst, (i64 (zextload baseptr))) 2394 // to 2395 // (set tmp0, (lwl (add baseptr, 3), undef)) 2396 // (set tmp1, (lwr baseptr, tmp0)) 2397 // (set tmp2, (shl tmp1, 32)) 2398 // (set dst, (srl tmp2, 32)) 2399 DebugLoc DL = LD->getDebugLoc(); 2400 SDValue Const32 = DAG.getConstant(32, MVT::i32); 2401 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2402 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2403 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2404 return DAG.getMergeValues(Ops, 2, DL); 2405} 2406 2407static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2408 SDValue Chain, unsigned Offset) { 2409 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2410 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2411 DebugLoc DL = SD->getDebugLoc(); 2412 SDVTList VTList = DAG.getVTList(MVT::Other); 2413 2414 if (Offset) 2415 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2416 DAG.getConstant(Offset, BasePtrVT)); 2417 2418 SDValue Ops[] = { Chain, Value, Ptr }; 2419 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2420 SD->getMemOperand()); 2421} 2422 2423// Expand an unaligned 32 or 64-bit integer store node. 2424SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2425 StoreSDNode *SD = cast<StoreSDNode>(Op); 2426 EVT MemVT = SD->getMemoryVT(); 2427 2428 // Return if store is aligned or if MemVT is neither i32 nor i64. 2429 if ((SD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2430 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2431 return SDValue(); 2432 2433 bool IsLittle = Subtarget->isLittle(); 2434 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2435 EVT VT = Value.getValueType(); 2436 2437 // Expand 2438 // (store val, baseptr) or 2439 // (truncstore val, baseptr) 2440 // to 2441 // (swl val, (add baseptr, 3)) 2442 // (swr val, baseptr) 2443 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2444 SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain, 2445 IsLittle ? 3 : 0); 2446 return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2447 } 2448 2449 assert(VT == MVT::i64); 2450 2451 // Expand 2452 // (store val, baseptr) 2453 // to 2454 // (sdl val, (add baseptr, 7)) 2455 // (sdr val, baseptr) 2456 SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2457 return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2458} 2459 2460// This function expands mips intrinsic nodes which have 64-bit input operands 2461// or output values. 2462// 2463// out64 = intrinsic-node in64 2464// => 2465// lo = copy (extract-element (in64, 0)) 2466// hi = copy (extract-element (in64, 1)) 2467// mips-specific-node 2468// v0 = copy lo 2469// v1 = copy hi 2470// out64 = merge-values (v0, v1) 2471// 2472static SDValue LowerDSPIntr(SDValue Op, SelectionDAG &DAG, 2473 unsigned Opc, bool HasI64In, bool HasI64Out) { 2474 DebugLoc DL = Op.getDebugLoc(); 2475 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other; 2476 SDValue Chain = HasChainIn ? Op->getOperand(0) : DAG.getEntryNode(); 2477 SmallVector<SDValue, 3> Ops; 2478 2479 if (HasI64In) { 2480 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, 2481 Op->getOperand(1 + HasChainIn), 2482 DAG.getConstant(0, MVT::i32)); 2483 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, 2484 Op->getOperand(1 + HasChainIn), 2485 DAG.getConstant(1, MVT::i32)); 2486 2487 Chain = DAG.getCopyToReg(Chain, DL, Mips::LO, InLo, SDValue()); 2488 Chain = DAG.getCopyToReg(Chain, DL, Mips::HI, InHi, Chain.getValue(1)); 2489 2490 Ops.push_back(Chain); 2491 Ops.append(Op->op_begin() + HasChainIn + 2, Op->op_end()); 2492 Ops.push_back(Chain.getValue(1)); 2493 } else { 2494 Ops.push_back(Chain); 2495 Ops.append(Op->op_begin() + HasChainIn + 1, Op->op_end()); 2496 } 2497 2498 if (!HasI64Out) 2499 return DAG.getNode(Opc, DL, Op->value_begin(), Op->getNumValues(), 2500 Ops.begin(), Ops.size()); 2501 2502 SDValue Intr = DAG.getNode(Opc, DL, DAG.getVTList(MVT::Other, MVT::Glue), 2503 Ops.begin(), Ops.size()); 2504 SDValue OutLo = DAG.getCopyFromReg(Intr.getValue(0), DL, Mips::LO, MVT::i32, 2505 Intr.getValue(1)); 2506 SDValue OutHi = DAG.getCopyFromReg(OutLo.getValue(1), DL, Mips::HI, MVT::i32, 2507 OutLo.getValue(2)); 2508 SDValue Out = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, OutLo, OutHi); 2509 2510 if (!HasChainIn) 2511 return Out; 2512 2513 SDValue Vals[] = { Out, OutHi.getValue(1) }; 2514 return DAG.getMergeValues(Vals, 2, DL); 2515} 2516 2517SDValue MipsTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 2518 SelectionDAG &DAG) const { 2519 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) { 2520 default: 2521 return SDValue(); 2522 case Intrinsic::mips_shilo: 2523 return LowerDSPIntr(Op, DAG, MipsISD::SHILO, true, true); 2524 case Intrinsic::mips_dpau_h_qbl: 2525 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL, true, true); 2526 case Intrinsic::mips_dpau_h_qbr: 2527 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR, true, true); 2528 case Intrinsic::mips_dpsu_h_qbl: 2529 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL, true, true); 2530 case Intrinsic::mips_dpsu_h_qbr: 2531 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR, true, true); 2532 case Intrinsic::mips_dpa_w_ph: 2533 return LowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH, true, true); 2534 case Intrinsic::mips_dps_w_ph: 2535 return LowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH, true, true); 2536 case Intrinsic::mips_dpax_w_ph: 2537 return LowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH, true, true); 2538 case Intrinsic::mips_dpsx_w_ph: 2539 return LowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH, true, true); 2540 case Intrinsic::mips_mulsa_w_ph: 2541 return LowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH, true, true); 2542 case Intrinsic::mips_mult: 2543 return LowerDSPIntr(Op, DAG, MipsISD::MULT, false, true); 2544 case Intrinsic::mips_multu: 2545 return LowerDSPIntr(Op, DAG, MipsISD::MULTU, false, true); 2546 case Intrinsic::mips_madd: 2547 return LowerDSPIntr(Op, DAG, MipsISD::MADD_DSP, true, true); 2548 case Intrinsic::mips_maddu: 2549 return LowerDSPIntr(Op, DAG, MipsISD::MADDU_DSP, true, true); 2550 case Intrinsic::mips_msub: 2551 return LowerDSPIntr(Op, DAG, MipsISD::MSUB_DSP, true, true); 2552 case Intrinsic::mips_msubu: 2553 return LowerDSPIntr(Op, DAG, MipsISD::MSUBU_DSP, true, true); 2554 } 2555} 2556 2557SDValue MipsTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, 2558 SelectionDAG &DAG) const { 2559 switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) { 2560 default: 2561 return SDValue(); 2562 case Intrinsic::mips_extp: 2563 return LowerDSPIntr(Op, DAG, MipsISD::EXTP, true, false); 2564 case Intrinsic::mips_extpdp: 2565 return LowerDSPIntr(Op, DAG, MipsISD::EXTPDP, true, false); 2566 case Intrinsic::mips_extr_w: 2567 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_W, true, false); 2568 case Intrinsic::mips_extr_r_w: 2569 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W, true, false); 2570 case Intrinsic::mips_extr_rs_w: 2571 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W, true, false); 2572 case Intrinsic::mips_extr_s_h: 2573 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H, true, false); 2574 case Intrinsic::mips_mthlip: 2575 return LowerDSPIntr(Op, DAG, MipsISD::MTHLIP, true, true); 2576 case Intrinsic::mips_mulsaq_s_w_ph: 2577 return LowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH, true, true); 2578 case Intrinsic::mips_maq_s_w_phl: 2579 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL, true, true); 2580 case Intrinsic::mips_maq_s_w_phr: 2581 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR, true, true); 2582 case Intrinsic::mips_maq_sa_w_phl: 2583 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL, true, true); 2584 case Intrinsic::mips_maq_sa_w_phr: 2585 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR, true, true); 2586 case Intrinsic::mips_dpaq_s_w_ph: 2587 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH, true, true); 2588 case Intrinsic::mips_dpsq_s_w_ph: 2589 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH, true, true); 2590 case Intrinsic::mips_dpaq_sa_l_w: 2591 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W, true, true); 2592 case Intrinsic::mips_dpsq_sa_l_w: 2593 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W, true, true); 2594 case Intrinsic::mips_dpaqx_s_w_ph: 2595 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH, true, true); 2596 case Intrinsic::mips_dpaqx_sa_w_ph: 2597 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH, true, true); 2598 case Intrinsic::mips_dpsqx_s_w_ph: 2599 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH, true, true); 2600 case Intrinsic::mips_dpsqx_sa_w_ph: 2601 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH, true, true); 2602 } 2603} 2604 2605SDValue MipsTargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 2606 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR 2607 || cast<ConstantSDNode> 2608 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0 2609 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET) 2610 return SDValue(); 2611 2612 // The pattern 2613 // (add (frameaddr 0), (frame_to_args_offset)) 2614 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to 2615 // (add FrameObject, 0) 2616 // where FrameObject is a fixed StackObject with offset 0 which points to 2617 // the old stack pointer. 2618 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2619 EVT ValTy = Op->getValueType(0); 2620 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2621 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy); 2622 return DAG.getNode(ISD::ADD, Op->getDebugLoc(), ValTy, InArgsAddr, 2623 DAG.getConstant(0, ValTy)); 2624} 2625 2626//===----------------------------------------------------------------------===// 2627// Calling Convention Implementation 2628//===----------------------------------------------------------------------===// 2629 2630//===----------------------------------------------------------------------===// 2631// TODO: Implement a generic logic using tblgen that can support this. 2632// Mips O32 ABI rules: 2633// --- 2634// i32 - Passed in A0, A1, A2, A3 and stack 2635// f32 - Only passed in f32 registers if no int reg has been used yet to hold 2636// an argument. Otherwise, passed in A1, A2, A3 and stack. 2637// f64 - Only passed in two aliased f32 registers if no int reg has been used 2638// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2639// not used, it must be shadowed. If only A3 is avaiable, shadow it and 2640// go to stack. 2641// 2642// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2643//===----------------------------------------------------------------------===// 2644 2645static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 2646 MVT LocVT, CCValAssign::LocInfo LocInfo, 2647 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2648 2649 static const unsigned IntRegsSize=4, FloatRegsSize=2; 2650 2651 static const uint16_t IntRegs[] = { 2652 Mips::A0, Mips::A1, Mips::A2, Mips::A3 2653 }; 2654 static const uint16_t F32Regs[] = { 2655 Mips::F12, Mips::F14 2656 }; 2657 static const uint16_t F64Regs[] = { 2658 Mips::D6, Mips::D7 2659 }; 2660 2661 // Do not process byval args here. 2662 if (ArgFlags.isByVal()) 2663 return true; 2664 2665 // Promote i8 and i16 2666 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2667 LocVT = MVT::i32; 2668 if (ArgFlags.isSExt()) 2669 LocInfo = CCValAssign::SExt; 2670 else if (ArgFlags.isZExt()) 2671 LocInfo = CCValAssign::ZExt; 2672 else 2673 LocInfo = CCValAssign::AExt; 2674 } 2675 2676 unsigned Reg; 2677 2678 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2679 // is true: function is vararg, argument is 3rd or higher, there is previous 2680 // argument which is not f32 or f64. 2681 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 2682 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 2683 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2684 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2685 2686 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2687 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2688 // If this is the first part of an i64 arg, 2689 // the allocated register must be either A0 or A2. 2690 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2691 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2692 LocVT = MVT::i32; 2693 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2694 // Allocate int register and shadow next int register. If first 2695 // available register is Mips::A1 or Mips::A3, shadow it too. 2696 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2697 if (Reg == Mips::A1 || Reg == Mips::A3) 2698 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2699 State.AllocateReg(IntRegs, IntRegsSize); 2700 LocVT = MVT::i32; 2701 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2702 // we are guaranteed to find an available float register 2703 if (ValVT == MVT::f32) { 2704 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 2705 // Shadow int register 2706 State.AllocateReg(IntRegs, IntRegsSize); 2707 } else { 2708 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 2709 // Shadow int registers 2710 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 2711 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2712 State.AllocateReg(IntRegs, IntRegsSize); 2713 State.AllocateReg(IntRegs, IntRegsSize); 2714 } 2715 } else 2716 llvm_unreachable("Cannot handle this ValVT."); 2717 2718 if (!Reg) { 2719 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2720 OrigAlign); 2721 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2722 } else 2723 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2724 2725 return false; 2726} 2727 2728#include "MipsGenCallingConv.inc" 2729 2730//===----------------------------------------------------------------------===// 2731// Call Calling Convention Implementation 2732//===----------------------------------------------------------------------===// 2733 2734static const unsigned O32IntRegsSize = 4; 2735 2736// Return next O32 integer argument register. 2737static unsigned getNextIntArgReg(unsigned Reg) { 2738 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2739 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2740} 2741 2742/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2743/// for tail call optimization. 2744bool MipsTargetLowering:: 2745IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 2746 unsigned NextStackOffset, 2747 const MipsFunctionInfo& FI) const { 2748 if (!EnableMipsTailCalls) 2749 return false; 2750 2751 // No tail call optimization for mips16. 2752 if (Subtarget->inMips16Mode()) 2753 return false; 2754 2755 // Return false if either the callee or caller has a byval argument. 2756 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg()) 2757 return false; 2758 2759 // Return true if the callee's argument area is no larger than the 2760 // caller's. 2761 return NextStackOffset <= FI.getIncomingArgSize(); 2762} 2763 2764SDValue 2765MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2766 SDValue Chain, SDValue Arg, DebugLoc DL, 2767 bool IsTailCall, SelectionDAG &DAG) const { 2768 if (!IsTailCall) { 2769 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, 2770 DAG.getIntPtrConstant(Offset)); 2771 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false, 2772 false, 0); 2773 } 2774 2775 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2776 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2777 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2778 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2779 /*isVolatile=*/ true, false, 0); 2780} 2781 2782// 2783// The Mips16 hard float is a crazy quilt inherited from gcc. I have a much 2784// cleaner way to do all of this but it will have to wait until the traditional 2785// gcc mechanism is completed. 2786// 2787// For Pic, in order for Mips16 code to call Mips32 code which according the abi 2788// have either arguments or returned values placed in floating point registers, 2789// we use a set of helper functions. (This includes functions which return type 2790// complex which on Mips are returned in a pair of floating point registers). 2791// 2792// This is an encoding that we inherited from gcc. 2793// In Mips traditional O32, N32 ABI, floating point numbers are passed in 2794// floating point argument registers 1,2 only when the first and optionally 2795// the second arguments are float (sf) or double (df). 2796// For Mips16 we are only concerned with the situations where floating point 2797// arguments are being passed in floating point registers by the ABI, because 2798// Mips16 mode code cannot execute floating point instructions to load those 2799// values and hence helper functions are needed. 2800// The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df) 2801// the helper function suffixs for these are: 2802// 0, 1, 5, 9, 2, 6, 10 2803// this suffix can then be calculated as follows: 2804// for a given argument Arg: 2805// Arg1x, Arg2x = 1 : Arg is sf 2806// 2 : Arg is df 2807// 0: Arg is neither sf or df 2808// So this stub is the string for number Arg1x + Arg2x*4. 2809// However not all numbers between 0 and 10 are possible, we check anyway and 2810// assert if the impossible exists. 2811// 2812 2813unsigned int MipsTargetLowering::getMips16HelperFunctionStubNumber 2814 (ArgListTy &Args) const { 2815 unsigned int resultNum = 0; 2816 if (Args.size() >= 1) { 2817 Type *t = Args[0].Ty; 2818 if (t->isFloatTy()) { 2819 resultNum = 1; 2820 } 2821 else if (t->isDoubleTy()) { 2822 resultNum = 2; 2823 } 2824 } 2825 if (resultNum) { 2826 if (Args.size() >=2) { 2827 Type *t = Args[1].Ty; 2828 if (t->isFloatTy()) { 2829 resultNum += 4; 2830 } 2831 else if (t->isDoubleTy()) { 2832 resultNum += 8; 2833 } 2834 } 2835 } 2836 return resultNum; 2837} 2838 2839// 2840// prefixs are attached to stub numbers depending on the return type . 2841// return type: float sf_ 2842// double df_ 2843// single complex sc_ 2844// double complext dc_ 2845// others NO PREFIX 2846// 2847// 2848// The full name of a helper function is__mips16_call_stub + 2849// return type dependent prefix + stub number 2850// 2851// 2852// This is something that probably should be in a different source file and 2853// perhaps done differently but my main purpose is to not waste runtime 2854// on something that we can enumerate in the source. Another possibility is 2855// to have a python script to generate these mapping tables. This will do 2856// for now. There are a whole series of helper function mapping arrays, one 2857// for each return type class as outlined above. There there are 11 possible 2858// entries. Ones with 0 are ones which should never be selected 2859// 2860// All the arrays are similar except for ones which return neither 2861// sf, df, sc, dc, in which only care about ones which have sf or df as a 2862// first parameter. 2863// 2864#define P_ "__mips16_call_stub_" 2865#define MAX_STUB_NUMBER 10 2866#define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10" 2867#define T P "0" , T1 2868#define P P_ 2869static char const * vMips16Helper[MAX_STUB_NUMBER+1] = 2870 {0, T1 }; 2871#undef P 2872#define P P_ "sf_" 2873static char const * sfMips16Helper[MAX_STUB_NUMBER+1] = 2874 { T }; 2875#undef P 2876#define P P_ "df_" 2877static char const * dfMips16Helper[MAX_STUB_NUMBER+1] = 2878 { T }; 2879#undef P 2880#define P P_ "sc_" 2881static char const * scMips16Helper[MAX_STUB_NUMBER+1] = 2882 { T }; 2883#undef P 2884#define P P_ "dc_" 2885static char const * dcMips16Helper[MAX_STUB_NUMBER+1] = 2886 { T }; 2887#undef P 2888#undef P_ 2889 2890 2891const char* MipsTargetLowering:: 2892 getMips16HelperFunction 2893 (Type* RetTy, ArgListTy &Args, bool &needHelper) const { 2894 const unsigned int maxStubNum = 10; 2895 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args); 2896 assert(stubNum <= maxStubNum); 2897#ifdef NDEBUG 2898 const bool validStubNum[maxStubNum+1] = 2899 {true, true, true, false, false, true, true, false, false, true, true}; 2900 assert(validStubNum[stubNum]); 2901#endif 2902 const char *result; 2903 if (RetTy->isFloatTy()) { 2904 result = sfMips16Helper[stubNum]; 2905 } 2906 else if (RetTy ->isDoubleTy()) { 2907 result = dfMips16Helper[stubNum]; 2908 } 2909 else if (RetTy->isStructTy()) { 2910 // check if it's complex 2911 if (RetTy->getNumContainedTypes() == 2) { 2912 if ((RetTy->getContainedType(0)->isFloatTy()) && 2913 (RetTy->getContainedType(1)->isFloatTy())) { 2914 result = scMips16Helper[stubNum]; 2915 } 2916 else if ((RetTy->getContainedType(0)->isDoubleTy()) && 2917 (RetTy->getContainedType(1)->isDoubleTy())) { 2918 result = dcMips16Helper[stubNum]; 2919 } 2920 } 2921 } 2922 else { 2923 if (stubNum == 0) { 2924 needHelper = false; 2925 return ""; 2926 } 2927 result = vMips16Helper[stubNum]; 2928 } 2929 needHelper = true; 2930 return result; 2931} 2932 2933/// LowerCall - functions arguments are copied from virtual regs to 2934/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2935SDValue 2936MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2937 SmallVectorImpl<SDValue> &InVals) const { 2938 SelectionDAG &DAG = CLI.DAG; 2939 DebugLoc &dl = CLI.DL; 2940 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 2941 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 2942 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 2943 SDValue Chain = CLI.Chain; 2944 SDValue Callee = CLI.Callee; 2945 bool &isTailCall = CLI.IsTailCall; 2946 CallingConv::ID CallConv = CLI.CallConv; 2947 bool isVarArg = CLI.IsVarArg; 2948 2949 const char* mips16HelperFunction = 0; 2950 bool needMips16Helper = false; 2951 2952 if (Subtarget->inMips16Mode() && getTargetMachine().Options.UseSoftFloat && 2953 Mips16HardFloat) { 2954 // 2955 // currently we don't have symbols tagged with the mips16 or mips32 2956 // qualifier so we will assume that we don't know what kind it is. 2957 // and generate the helper 2958 // 2959 bool lookupHelper = true; 2960 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2961 if (noHelperNeeded.find(S->getSymbol()) != noHelperNeeded.end()) { 2962 lookupHelper = false; 2963 } 2964 } 2965 if (lookupHelper) mips16HelperFunction = 2966 getMips16HelperFunction(CLI.RetTy, CLI.Args, needMips16Helper); 2967 2968 } 2969 MachineFunction &MF = DAG.getMachineFunction(); 2970 MachineFrameInfo *MFI = MF.getFrameInfo(); 2971 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 2972 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2973 2974 // Analyze operands of the call, assigning locations to each operand. 2975 SmallVector<CCValAssign, 16> ArgLocs; 2976 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2977 getTargetMachine(), ArgLocs, *DAG.getContext()); 2978 MipsCC MipsCCInfo(CallConv, isVarArg, IsO32, CCInfo); 2979 2980 MipsCCInfo.analyzeCallOperands(Outs); 2981 2982 // Get a count of how many bytes are to be pushed on the stack. 2983 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2984 2985 // Check if it's really possible to do a tail call. 2986 if (isTailCall) 2987 isTailCall = 2988 IsEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset, 2989 *MF.getInfo<MipsFunctionInfo>()); 2990 2991 if (isTailCall) 2992 ++NumTailCalls; 2993 2994 // Chain is the output chain of the last Load/Store or CopyToReg node. 2995 // ByValChain is the output chain of the last Memcpy node created for copying 2996 // byval arguments to the stack. 2997 unsigned StackAlignment = TFL->getStackAlignment(); 2998 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment); 2999 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 3000 3001 if (!isTailCall) 3002 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal); 3003 3004 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, 3005 IsN64 ? Mips::SP_64 : Mips::SP, 3006 getPointerTy()); 3007 3008 // With EABI is it possible to have 16 args on registers. 3009 std::deque< std::pair<unsigned, SDValue> > RegsToPass; 3010 SmallVector<SDValue, 8> MemOpChains; 3011 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 3012 3013 // Walk the register/memloc assignments, inserting copies/loads. 3014 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3015 SDValue Arg = OutVals[i]; 3016 CCValAssign &VA = ArgLocs[i]; 3017 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 3018 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3019 3020 // ByVal Arg. 3021 if (Flags.isByVal()) { 3022 assert(Flags.getByValSize() && 3023 "ByVal args of size 0 should have been ignored by front-end."); 3024 assert(ByValArg != MipsCCInfo.byval_end()); 3025 assert(!isTailCall && 3026 "Do not tail-call optimize if there is a byval argument."); 3027 passByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 3028 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle()); 3029 ++ByValArg; 3030 continue; 3031 } 3032 3033 // Promote the value if needed. 3034 switch (VA.getLocInfo()) { 3035 default: llvm_unreachable("Unknown loc info!"); 3036 case CCValAssign::Full: 3037 if (VA.isRegLoc()) { 3038 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 3039 (ValVT == MVT::f64 && LocVT == MVT::i64)) 3040 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg); 3041 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 3042 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 3043 Arg, DAG.getConstant(0, MVT::i32)); 3044 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 3045 Arg, DAG.getConstant(1, MVT::i32)); 3046 if (!Subtarget->isLittle()) 3047 std::swap(Lo, Hi); 3048 unsigned LocRegLo = VA.getLocReg(); 3049 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 3050 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 3051 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 3052 continue; 3053 } 3054 } 3055 break; 3056 case CCValAssign::SExt: 3057 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg); 3058 break; 3059 case CCValAssign::ZExt: 3060 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg); 3061 break; 3062 case CCValAssign::AExt: 3063 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg); 3064 break; 3065 } 3066 3067 // Arguments that can be passed on register must be kept at 3068 // RegsToPass vector 3069 if (VA.isRegLoc()) { 3070 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3071 continue; 3072 } 3073 3074 // Register can't get to this point... 3075 assert(VA.isMemLoc()); 3076 3077 // emit ISD::STORE whichs stores the 3078 // parameter value to a stack Location 3079 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 3080 Chain, Arg, dl, isTailCall, DAG)); 3081 } 3082 3083 // Transform all store nodes into one single node because all store 3084 // nodes are independent of each other. 3085 if (!MemOpChains.empty()) 3086 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3087 &MemOpChains[0], MemOpChains.size()); 3088 3089 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 3090 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 3091 // node so that legalize doesn't hack it. 3092 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25 3093 bool GlobalOrExternal = false, InternalLinkage = false; 3094 SDValue CalleeLo; 3095 3096 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3097 if (IsPICCall) { 3098 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 3099 3100 if (InternalLinkage) 3101 Callee = getAddrLocal(Callee, DAG, HasMips64); 3102 else if (LargeGOT) 3103 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16, 3104 MipsII::MO_CALL_LO16); 3105 else 3106 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL); 3107 } else 3108 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0, 3109 MipsII::MO_NO_FLAG); 3110 GlobalOrExternal = true; 3111 } 3112 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3113 if (!IsN64 && !IsPIC) // !N64 && static 3114 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 3115 MipsII::MO_NO_FLAG); 3116 else if (LargeGOT) 3117 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16, 3118 MipsII::MO_CALL_LO16); 3119 else if (HasMips64) 3120 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_DISP); 3121 else // O32 & PIC 3122 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL); 3123 3124 GlobalOrExternal = true; 3125 } 3126 3127 SDValue JumpTarget = Callee; 3128 3129 // T9 should contain the address of the callee function if 3130 // -reloction-model=pic or it is an indirect call. 3131 if (IsPICCall || !GlobalOrExternal) { 3132 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9; 3133 unsigned V0Reg = Mips::V0; 3134 if (needMips16Helper) { 3135 RegsToPass.push_front(std::make_pair(V0Reg, Callee)); 3136 JumpTarget = DAG.getExternalSymbol( 3137 mips16HelperFunction, getPointerTy()); 3138 JumpTarget = getAddrGlobal(JumpTarget, DAG, MipsII::MO_GOT); 3139 } 3140 else { 3141 RegsToPass.push_front(std::make_pair(T9Reg, Callee)); 3142 3143 if (!Subtarget->inMips16Mode()) 3144 JumpTarget = SDValue(); 3145 } 3146 } 3147 3148 // Insert node "GP copy globalreg" before call to function. 3149 // 3150 // R_MIPS_CALL* operators (emitted when non-internal functions are called 3151 // in PIC mode) allow symbols to be resolved via lazy binding. 3152 // The lazy binding stub requires GP to point to the GOT. 3153 if (IsPICCall && !InternalLinkage) { 3154 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP; 3155 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 3156 RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty))); 3157 } 3158 3159 // Build a sequence of copy-to-reg nodes chained together with token 3160 // chain and flag operands which copy the outgoing args into registers. 3161 // The InFlag in necessary since all emitted instructions must be 3162 // stuck together. 3163 SDValue InFlag; 3164 3165 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3166 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3167 RegsToPass[i].second, InFlag); 3168 InFlag = Chain.getValue(1); 3169 } 3170 3171 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 3172 // = Chain, Callee, Reg#1, Reg#2, ... 3173 // 3174 // Returns a chain & a flag for retval copy to use. 3175 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 3176 SmallVector<SDValue, 8> Ops(1, Chain); 3177 3178 if (JumpTarget.getNode()) 3179 Ops.push_back(JumpTarget); 3180 3181 // Add argument registers to the end of the list so that they are 3182 // known live into the call. 3183 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 3184 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 3185 RegsToPass[i].second.getValueType())); 3186 3187 // Add a register mask operand representing the call-preserved registers. 3188 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 3189 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 3190 assert(Mask && "Missing call preserved mask for calling convention"); 3191 Ops.push_back(DAG.getRegisterMask(Mask)); 3192 3193 if (InFlag.getNode()) 3194 Ops.push_back(InFlag); 3195 3196 if (isTailCall) 3197 return DAG.getNode(MipsISD::TailCall, dl, MVT::Other, &Ops[0], Ops.size()); 3198 3199 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 3200 InFlag = Chain.getValue(1); 3201 3202 // Create the CALLSEQ_END node. 3203 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 3204 DAG.getIntPtrConstant(0, true), InFlag); 3205 InFlag = Chain.getValue(1); 3206 3207 // Handle result values, copying them out of physregs into vregs that we 3208 // return. 3209 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 3210 Ins, dl, DAG, InVals); 3211} 3212 3213/// LowerCallResult - Lower the result values of a call into the 3214/// appropriate copies out of appropriate physical registers. 3215SDValue 3216MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 3217 CallingConv::ID CallConv, bool isVarArg, 3218 const SmallVectorImpl<ISD::InputArg> &Ins, 3219 DebugLoc dl, SelectionDAG &DAG, 3220 SmallVectorImpl<SDValue> &InVals) const { 3221 // Assign locations to each value returned by this call. 3222 SmallVector<CCValAssign, 16> RVLocs; 3223 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3224 getTargetMachine(), RVLocs, *DAG.getContext()); 3225 3226 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 3227 3228 // Copy all of the result registers out of their specified physreg. 3229 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3230 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 3231 RVLocs[i].getValVT(), InFlag).getValue(1); 3232 InFlag = Chain.getValue(2); 3233 InVals.push_back(Chain.getValue(0)); 3234 } 3235 3236 return Chain; 3237} 3238 3239//===----------------------------------------------------------------------===// 3240// Formal Arguments Calling Convention Implementation 3241//===----------------------------------------------------------------------===// 3242/// LowerFormalArguments - transform physical registers into virtual registers 3243/// and generate load operations for arguments places on the stack. 3244SDValue 3245MipsTargetLowering::LowerFormalArguments(SDValue Chain, 3246 CallingConv::ID CallConv, 3247 bool isVarArg, 3248 const SmallVectorImpl<ISD::InputArg> &Ins, 3249 DebugLoc dl, SelectionDAG &DAG, 3250 SmallVectorImpl<SDValue> &InVals) 3251 const { 3252 MachineFunction &MF = DAG.getMachineFunction(); 3253 MachineFrameInfo *MFI = MF.getFrameInfo(); 3254 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3255 3256 MipsFI->setVarArgsFrameIndex(0); 3257 3258 // Used with vargs to acumulate store chains. 3259 std::vector<SDValue> OutChains; 3260 3261 // Assign locations to all of the incoming arguments. 3262 SmallVector<CCValAssign, 16> ArgLocs; 3263 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3264 getTargetMachine(), ArgLocs, *DAG.getContext()); 3265 MipsCC MipsCCInfo(CallConv, isVarArg, IsO32, CCInfo); 3266 3267 MipsCCInfo.analyzeFormalArguments(Ins); 3268 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3269 MipsCCInfo.hasByValArg()); 3270 3271 Function::const_arg_iterator FuncArg = 3272 DAG.getMachineFunction().getFunction()->arg_begin(); 3273 unsigned CurArgIdx = 0; 3274 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 3275 3276 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3277 CCValAssign &VA = ArgLocs[i]; 3278 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx); 3279 CurArgIdx = Ins[i].OrigArgIndex; 3280 EVT ValVT = VA.getValVT(); 3281 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3282 bool IsRegLoc = VA.isRegLoc(); 3283 3284 if (Flags.isByVal()) { 3285 assert(Flags.getByValSize() && 3286 "ByVal args of size 0 should have been ignored by front-end."); 3287 assert(ByValArg != MipsCCInfo.byval_end()); 3288 copyByValRegs(Chain, dl, OutChains, DAG, Flags, InVals, &*FuncArg, 3289 MipsCCInfo, *ByValArg); 3290 ++ByValArg; 3291 continue; 3292 } 3293 3294 // Arguments stored on registers 3295 if (IsRegLoc) { 3296 EVT RegVT = VA.getLocVT(); 3297 unsigned ArgReg = VA.getLocReg(); 3298 const TargetRegisterClass *RC; 3299 3300 if (RegVT == MVT::i32) 3301 RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass : 3302 &Mips::CPURegsRegClass; 3303 else if (RegVT == MVT::i64) 3304 RC = &Mips::CPU64RegsRegClass; 3305 else if (RegVT == MVT::f32) 3306 RC = &Mips::FGR32RegClass; 3307 else if (RegVT == MVT::f64) 3308 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; 3309 else 3310 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 3311 3312 // Transform the arguments stored on 3313 // physical registers into virtual ones 3314 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3315 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 3316 3317 // If this is an 8 or 16-bit value, it has been passed promoted 3318 // to 32 bits. Insert an assert[sz]ext to capture this, then 3319 // truncate to the right size. 3320 if (VA.getLocInfo() != CCValAssign::Full) { 3321 unsigned Opcode = 0; 3322 if (VA.getLocInfo() == CCValAssign::SExt) 3323 Opcode = ISD::AssertSext; 3324 else if (VA.getLocInfo() == CCValAssign::ZExt) 3325 Opcode = ISD::AssertZext; 3326 if (Opcode) 3327 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 3328 DAG.getValueType(ValVT)); 3329 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue); 3330 } 3331 3332 // Handle floating point arguments passed in integer registers. 3333 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3334 (RegVT == MVT::i64 && ValVT == MVT::f64)) 3335 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue); 3336 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) { 3337 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 3338 getNextIntArgReg(ArgReg), RC); 3339 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 3340 if (!Subtarget->isLittle()) 3341 std::swap(ArgValue, ArgValue2); 3342 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 3343 ArgValue, ArgValue2); 3344 } 3345 3346 InVals.push_back(ArgValue); 3347 } else { // VA.isRegLoc() 3348 3349 // sanity check 3350 assert(VA.isMemLoc()); 3351 3352 // The stack pointer offset is relative to the caller stack frame. 3353 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 3354 VA.getLocMemOffset(), true); 3355 3356 // Create load nodes to retrieve arguments from the stack 3357 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 3358 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN, 3359 MachinePointerInfo::getFixedStack(FI), 3360 false, false, false, 0)); 3361 } 3362 } 3363 3364 // The mips ABIs for returning structs by value requires that we copy 3365 // the sret argument into $v0 for the return. Save the argument into 3366 // a virtual register so that we can access it from the return points. 3367 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 3368 unsigned Reg = MipsFI->getSRetReturnReg(); 3369 if (!Reg) { 3370 Reg = MF.getRegInfo(). 3371 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32)); 3372 MipsFI->setSRetReturnReg(Reg); 3373 } 3374 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 3375 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 3376 } 3377 3378 if (isVarArg) 3379 writeVarArgRegs(OutChains, MipsCCInfo, Chain, dl, DAG); 3380 3381 // All stores are grouped in one node to allow the matching between 3382 // the size of Ins and InVals. This only happens when on varg functions 3383 if (!OutChains.empty()) { 3384 OutChains.push_back(Chain); 3385 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3386 &OutChains[0], OutChains.size()); 3387 } 3388 3389 return Chain; 3390} 3391 3392//===----------------------------------------------------------------------===// 3393// Return Value Calling Convention Implementation 3394//===----------------------------------------------------------------------===// 3395 3396bool 3397MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3398 MachineFunction &MF, bool isVarArg, 3399 const SmallVectorImpl<ISD::OutputArg> &Outs, 3400 LLVMContext &Context) const { 3401 SmallVector<CCValAssign, 16> RVLocs; 3402 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 3403 RVLocs, Context); 3404 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3405} 3406 3407SDValue 3408MipsTargetLowering::LowerReturn(SDValue Chain, 3409 CallingConv::ID CallConv, bool isVarArg, 3410 const SmallVectorImpl<ISD::OutputArg> &Outs, 3411 const SmallVectorImpl<SDValue> &OutVals, 3412 DebugLoc dl, SelectionDAG &DAG) const { 3413 3414 // CCValAssign - represent the assignment of 3415 // the return value to a location 3416 SmallVector<CCValAssign, 16> RVLocs; 3417 3418 // CCState - Info about the registers and stack slot. 3419 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3420 getTargetMachine(), RVLocs, *DAG.getContext()); 3421 3422 // Analize return values. 3423 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3424 3425 // If this is the first return lowered for this function, add 3426 // the regs to the liveout set for the function. 3427 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 3428 for (unsigned i = 0; i != RVLocs.size(); ++i) 3429 if (RVLocs[i].isRegLoc()) 3430 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 3431 } 3432 3433 SDValue Flag; 3434 3435 // Copy the result values into the output registers. 3436 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3437 CCValAssign &VA = RVLocs[i]; 3438 assert(VA.isRegLoc() && "Can only return in registers!"); 3439 3440 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 3441 3442 // guarantee that all emitted copies are 3443 // stuck together, avoiding something bad 3444 Flag = Chain.getValue(1); 3445 } 3446 3447 // The mips ABIs for returning structs by value requires that we copy 3448 // the sret argument into $v0 for the return. We saved the argument into 3449 // a virtual register in the entry block, so now we copy the value out 3450 // and into $v0. 3451 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 3452 MachineFunction &MF = DAG.getMachineFunction(); 3453 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3454 unsigned Reg = MipsFI->getSRetReturnReg(); 3455 3456 if (!Reg) 3457 llvm_unreachable("sret virtual register not created in the entry block"); 3458 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 3459 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0; 3460 3461 Chain = DAG.getCopyToReg(Chain, dl, V0, Val, Flag); 3462 Flag = Chain.getValue(1); 3463 MF.getRegInfo().addLiveOut(V0); 3464 } 3465 3466 // Return on Mips is always a "jr $ra" 3467 if (Flag.getNode()) 3468 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain, Flag); 3469 3470 // Return Void 3471 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain); 3472} 3473 3474//===----------------------------------------------------------------------===// 3475// Mips Inline Assembly Support 3476//===----------------------------------------------------------------------===// 3477 3478/// getConstraintType - Given a constraint letter, return the type of 3479/// constraint it is for this target. 3480MipsTargetLowering::ConstraintType MipsTargetLowering:: 3481getConstraintType(const std::string &Constraint) const 3482{ 3483 // Mips specific constrainy 3484 // GCC config/mips/constraints.md 3485 // 3486 // 'd' : An address register. Equivalent to r 3487 // unless generating MIPS16 code. 3488 // 'y' : Equivalent to r; retained for 3489 // backwards compatibility. 3490 // 'c' : A register suitable for use in an indirect 3491 // jump. This will always be $25 for -mabicalls. 3492 // 'l' : The lo register. 1 word storage. 3493 // 'x' : The hilo register pair. Double word storage. 3494 if (Constraint.size() == 1) { 3495 switch (Constraint[0]) { 3496 default : break; 3497 case 'd': 3498 case 'y': 3499 case 'f': 3500 case 'c': 3501 case 'l': 3502 case 'x': 3503 return C_RegisterClass; 3504 } 3505 } 3506 return TargetLowering::getConstraintType(Constraint); 3507} 3508 3509/// Examine constraint type and operand type and determine a weight value. 3510/// This object must already have been set up with the operand type 3511/// and the current alternative constraint selected. 3512TargetLowering::ConstraintWeight 3513MipsTargetLowering::getSingleConstraintMatchWeight( 3514 AsmOperandInfo &info, const char *constraint) const { 3515 ConstraintWeight weight = CW_Invalid; 3516 Value *CallOperandVal = info.CallOperandVal; 3517 // If we don't have a value, we can't do a match, 3518 // but allow it at the lowest weight. 3519 if (CallOperandVal == NULL) 3520 return CW_Default; 3521 Type *type = CallOperandVal->getType(); 3522 // Look at the constraint type. 3523 switch (*constraint) { 3524 default: 3525 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3526 break; 3527 case 'd': 3528 case 'y': 3529 if (type->isIntegerTy()) 3530 weight = CW_Register; 3531 break; 3532 case 'f': 3533 if (type->isFloatTy()) 3534 weight = CW_Register; 3535 break; 3536 case 'c': // $25 for indirect jumps 3537 case 'l': // lo register 3538 case 'x': // hilo register pair 3539 if (type->isIntegerTy()) 3540 weight = CW_SpecificReg; 3541 break; 3542 case 'I': // signed 16 bit immediate 3543 case 'J': // integer zero 3544 case 'K': // unsigned 16 bit immediate 3545 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3546 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3547 case 'O': // signed 15 bit immediate (+- 16383) 3548 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3549 if (isa<ConstantInt>(CallOperandVal)) 3550 weight = CW_Constant; 3551 break; 3552 } 3553 return weight; 3554} 3555 3556/// Given a register class constraint, like 'r', if this corresponds directly 3557/// to an LLVM register class, return a register of 0 and the register class 3558/// pointer. 3559std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 3560getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 3561{ 3562 if (Constraint.size() == 1) { 3563 switch (Constraint[0]) { 3564 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3565 case 'y': // Same as 'r'. Exists for compatibility. 3566 case 'r': 3567 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3568 if (Subtarget->inMips16Mode()) 3569 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3570 return std::make_pair(0U, &Mips::CPURegsRegClass); 3571 } 3572 if (VT == MVT::i64 && !HasMips64) 3573 return std::make_pair(0U, &Mips::CPURegsRegClass); 3574 if (VT == MVT::i64 && HasMips64) 3575 return std::make_pair(0U, &Mips::CPU64RegsRegClass); 3576 // This will generate an error message 3577 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 3578 case 'f': 3579 if (VT == MVT::f32) 3580 return std::make_pair(0U, &Mips::FGR32RegClass); 3581 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { 3582 if (Subtarget->isFP64bit()) 3583 return std::make_pair(0U, &Mips::FGR64RegClass); 3584 return std::make_pair(0U, &Mips::AFGR64RegClass); 3585 } 3586 break; 3587 case 'c': // register suitable for indirect jump 3588 if (VT == MVT::i32) 3589 return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass); 3590 assert(VT == MVT::i64 && "Unexpected type."); 3591 return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass); 3592 case 'l': // register suitable for indirect jump 3593 if (VT == MVT::i32) 3594 return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass); 3595 return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass); 3596 case 'x': // register suitable for indirect jump 3597 // Fixme: Not triggering the use of both hi and low 3598 // This will generate an error message 3599 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 3600 } 3601 } 3602 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3603} 3604 3605/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3606/// vector. If it is invalid, don't add anything to Ops. 3607void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3608 std::string &Constraint, 3609 std::vector<SDValue>&Ops, 3610 SelectionDAG &DAG) const { 3611 SDValue Result(0, 0); 3612 3613 // Only support length 1 constraints for now. 3614 if (Constraint.length() > 1) return; 3615 3616 char ConstraintLetter = Constraint[0]; 3617 switch (ConstraintLetter) { 3618 default: break; // This will fall through to the generic implementation 3619 case 'I': // Signed 16 bit constant 3620 // If this fails, the parent routine will give an error 3621 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3622 EVT Type = Op.getValueType(); 3623 int64_t Val = C->getSExtValue(); 3624 if (isInt<16>(Val)) { 3625 Result = DAG.getTargetConstant(Val, Type); 3626 break; 3627 } 3628 } 3629 return; 3630 case 'J': // integer zero 3631 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3632 EVT Type = Op.getValueType(); 3633 int64_t Val = C->getZExtValue(); 3634 if (Val == 0) { 3635 Result = DAG.getTargetConstant(0, Type); 3636 break; 3637 } 3638 } 3639 return; 3640 case 'K': // unsigned 16 bit immediate 3641 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3642 EVT Type = Op.getValueType(); 3643 uint64_t Val = (uint64_t)C->getZExtValue(); 3644 if (isUInt<16>(Val)) { 3645 Result = DAG.getTargetConstant(Val, Type); 3646 break; 3647 } 3648 } 3649 return; 3650 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3651 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3652 EVT Type = Op.getValueType(); 3653 int64_t Val = C->getSExtValue(); 3654 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3655 Result = DAG.getTargetConstant(Val, Type); 3656 break; 3657 } 3658 } 3659 return; 3660 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3661 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3662 EVT Type = Op.getValueType(); 3663 int64_t Val = C->getSExtValue(); 3664 if ((Val >= -65535) && (Val <= -1)) { 3665 Result = DAG.getTargetConstant(Val, Type); 3666 break; 3667 } 3668 } 3669 return; 3670 case 'O': // signed 15 bit immediate 3671 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3672 EVT Type = Op.getValueType(); 3673 int64_t Val = C->getSExtValue(); 3674 if ((isInt<15>(Val))) { 3675 Result = DAG.getTargetConstant(Val, Type); 3676 break; 3677 } 3678 } 3679 return; 3680 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3681 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3682 EVT Type = Op.getValueType(); 3683 int64_t Val = C->getSExtValue(); 3684 if ((Val <= 65535) && (Val >= 1)) { 3685 Result = DAG.getTargetConstant(Val, Type); 3686 break; 3687 } 3688 } 3689 return; 3690 } 3691 3692 if (Result.getNode()) { 3693 Ops.push_back(Result); 3694 return; 3695 } 3696 3697 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3698} 3699 3700bool 3701MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const { 3702 // No global is ever allowed as a base. 3703 if (AM.BaseGV) 3704 return false; 3705 3706 switch (AM.Scale) { 3707 case 0: // "r+i" or just "i", depending on HasBaseReg. 3708 break; 3709 case 1: 3710 if (!AM.HasBaseReg) // allow "r+i". 3711 break; 3712 return false; // disallow "r+r" or "r+r+i". 3713 default: 3714 return false; 3715 } 3716 3717 return true; 3718} 3719 3720bool 3721MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3722 // The Mips target isn't yet aware of offsets. 3723 return false; 3724} 3725 3726EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3727 unsigned SrcAlign, 3728 bool IsMemset, bool ZeroMemset, 3729 bool MemcpyStrSrc, 3730 MachineFunction &MF) const { 3731 if (Subtarget->hasMips64()) 3732 return MVT::i64; 3733 3734 return MVT::i32; 3735} 3736 3737bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3738 if (VT != MVT::f32 && VT != MVT::f64) 3739 return false; 3740 if (Imm.isNegZero()) 3741 return false; 3742 return Imm.isZero(); 3743} 3744 3745unsigned MipsTargetLowering::getJumpTableEncoding() const { 3746 if (IsN64) 3747 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3748 3749 return TargetLowering::getJumpTableEncoding(); 3750} 3751 3752MipsTargetLowering::MipsCC::MipsCC(CallingConv::ID CallConv, bool IsVarArg, 3753 bool IsO32, CCState &Info) : CCInfo(Info) { 3754 UseRegsForByval = true; 3755 3756 if (IsO32) { 3757 RegSize = 4; 3758 NumIntArgRegs = array_lengthof(O32IntRegs); 3759 ReservedArgArea = 16; 3760 IntArgRegs = ShadowRegs = O32IntRegs; 3761 FixedFn = VarFn = CC_MipsO32; 3762 } else { 3763 RegSize = 8; 3764 NumIntArgRegs = array_lengthof(Mips64IntRegs); 3765 ReservedArgArea = 0; 3766 IntArgRegs = Mips64IntRegs; 3767 ShadowRegs = Mips64DPRegs; 3768 FixedFn = CC_MipsN; 3769 VarFn = CC_MipsN_VarArg; 3770 } 3771 3772 if (CallConv == CallingConv::Fast) { 3773 assert(!IsVarArg); 3774 UseRegsForByval = false; 3775 ReservedArgArea = 0; 3776 FixedFn = VarFn = CC_Mips_FastCC; 3777 } 3778 3779 // Pre-allocate reserved argument area. 3780 CCInfo.AllocateStack(ReservedArgArea, 1); 3781} 3782 3783void MipsTargetLowering::MipsCC:: 3784analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args) { 3785 unsigned NumOpnds = Args.size(); 3786 3787 for (unsigned I = 0; I != NumOpnds; ++I) { 3788 MVT ArgVT = Args[I].VT; 3789 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3790 bool R; 3791 3792 if (ArgFlags.isByVal()) { 3793 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3794 continue; 3795 } 3796 3797 if (Args[I].IsFixed) 3798 R = FixedFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 3799 else 3800 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 3801 3802 if (R) { 3803#ifndef NDEBUG 3804 dbgs() << "Call operand #" << I << " has unhandled type " 3805 << EVT(ArgVT).getEVTString(); 3806#endif 3807 llvm_unreachable(0); 3808 } 3809 } 3810} 3811 3812void MipsTargetLowering::MipsCC:: 3813analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args) { 3814 unsigned NumArgs = Args.size(); 3815 3816 for (unsigned I = 0; I != NumArgs; ++I) { 3817 MVT ArgVT = Args[I].VT; 3818 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3819 3820 if (ArgFlags.isByVal()) { 3821 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3822 continue; 3823 } 3824 3825 if (!FixedFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo)) 3826 continue; 3827 3828#ifndef NDEBUG 3829 dbgs() << "Formal Arg #" << I << " has unhandled type " 3830 << EVT(ArgVT).getEVTString(); 3831#endif 3832 llvm_unreachable(0); 3833 } 3834} 3835 3836void 3837MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT, 3838 MVT LocVT, 3839 CCValAssign::LocInfo LocInfo, 3840 ISD::ArgFlagsTy ArgFlags) { 3841 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0."); 3842 3843 struct ByValArgInfo ByVal; 3844 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize); 3845 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize), 3846 RegSize * 2); 3847 3848 if (UseRegsForByval) 3849 allocateRegs(ByVal, ByValSize, Align); 3850 3851 // Allocate space on caller's stack. 3852 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs, 3853 Align); 3854 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT, 3855 LocInfo)); 3856 ByValArgs.push_back(ByVal); 3857} 3858 3859void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal, 3860 unsigned ByValSize, 3861 unsigned Align) { 3862 assert(!(ByValSize % RegSize) && !(Align % RegSize) && 3863 "Byval argument's size and alignment should be a multiple of" 3864 "RegSize."); 3865 3866 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs); 3867 3868 // If Align > RegSize, the first arg register must be even. 3869 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) { 3870 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]); 3871 ++ByVal.FirstIdx; 3872 } 3873 3874 // Mark the registers allocated. 3875 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs); 3876 ByValSize -= RegSize, ++I, ++ByVal.NumRegs) 3877 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]); 3878} 3879 3880void MipsTargetLowering:: 3881copyByValRegs(SDValue Chain, DebugLoc DL, std::vector<SDValue> &OutChains, 3882 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 3883 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 3884 const MipsCC &CC, const ByValArgInfo &ByVal) const { 3885 MachineFunction &MF = DAG.getMachineFunction(); 3886 MachineFrameInfo *MFI = MF.getFrameInfo(); 3887 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize(); 3888 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3889 int FrameObjOffset; 3890 3891 if (RegAreaSize) 3892 FrameObjOffset = (int)CC.reservedArgArea() - 3893 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize()); 3894 else 3895 FrameObjOffset = ByVal.Address; 3896 3897 // Create frame object. 3898 EVT PtrTy = getPointerTy(); 3899 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3900 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3901 InVals.push_back(FIN); 3902 3903 if (!ByVal.NumRegs) 3904 return; 3905 3906 // Copy arg registers. 3907 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8); 3908 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3909 3910 for (unsigned I = 0; I < ByVal.NumRegs; ++I) { 3911 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I]; 3912 unsigned VReg = AddLiveIn(MF, ArgReg, RC); 3913 unsigned Offset = I * CC.regSize(); 3914 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3915 DAG.getConstant(Offset, PtrTy)); 3916 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3917 StorePtr, MachinePointerInfo(FuncArg, Offset), 3918 false, false, 0); 3919 OutChains.push_back(Store); 3920 } 3921} 3922 3923// Copy byVal arg to registers and stack. 3924void MipsTargetLowering:: 3925passByValArg(SDValue Chain, DebugLoc DL, 3926 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 3927 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, 3928 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 3929 const MipsCC &CC, const ByValArgInfo &ByVal, 3930 const ISD::ArgFlagsTy &Flags, bool isLittle) const { 3931 unsigned ByValSize = Flags.getByValSize(); 3932 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct. 3933 unsigned RegSize = CC.regSize(); 3934 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize); 3935 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8); 3936 3937 if (ByVal.NumRegs) { 3938 const uint16_t *ArgRegs = CC.intArgRegs(); 3939 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize); 3940 unsigned I = 0; 3941 3942 // Copy words to registers. 3943 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) { 3944 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3945 DAG.getConstant(Offset, PtrTy)); 3946 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3947 MachinePointerInfo(), false, false, false, 3948 Alignment); 3949 MemOpChains.push_back(LoadVal.getValue(1)); 3950 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3951 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3952 } 3953 3954 // Return if the struct has been fully copied. 3955 if (ByValSize == Offset) 3956 return; 3957 3958 // Copy the remainder of the byval argument with sub-word loads and shifts. 3959 if (LeftoverBytes) { 3960 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) && 3961 "Size of the remainder should be smaller than RegSize."); 3962 SDValue Val; 3963 3964 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0; 3965 Offset < ByValSize; LoadSize /= 2) { 3966 unsigned RemSize = ByValSize - Offset; 3967 3968 if (RemSize < LoadSize) 3969 continue; 3970 3971 // Load subword. 3972 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3973 DAG.getConstant(Offset, PtrTy)); 3974 SDValue LoadVal = 3975 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, 3976 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8), 3977 false, false, Alignment); 3978 MemOpChains.push_back(LoadVal.getValue(1)); 3979 3980 // Shift the loaded value. 3981 unsigned Shamt; 3982 3983 if (isLittle) 3984 Shamt = TotalSizeLoaded; 3985 else 3986 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8; 3987 3988 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 3989 DAG.getConstant(Shamt, MVT::i32)); 3990 3991 if (Val.getNode()) 3992 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3993 else 3994 Val = Shift; 3995 3996 Offset += LoadSize; 3997 TotalSizeLoaded += LoadSize; 3998 Alignment = std::min(Alignment, LoadSize); 3999 } 4000 4001 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 4002 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 4003 return; 4004 } 4005 } 4006 4007 // Copy remainder of byval arg to it with memcpy. 4008 unsigned MemCpySize = ByValSize - Offset; 4009 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4010 DAG.getConstant(Offset, PtrTy)); 4011 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 4012 DAG.getIntPtrConstant(ByVal.Address)); 4013 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 4014 DAG.getConstant(MemCpySize, PtrTy), Alignment, 4015 /*isVolatile=*/false, /*AlwaysInline=*/false, 4016 MachinePointerInfo(0), MachinePointerInfo(0)); 4017 MemOpChains.push_back(Chain); 4018} 4019 4020void 4021MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 4022 const MipsCC &CC, SDValue Chain, 4023 DebugLoc DL, SelectionDAG &DAG) const { 4024 unsigned NumRegs = CC.numIntArgRegs(); 4025 const uint16_t *ArgRegs = CC.intArgRegs(); 4026 const CCState &CCInfo = CC.getCCInfo(); 4027 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs); 4028 unsigned RegSize = CC.regSize(); 4029 MVT RegTy = MVT::getIntegerVT(RegSize * 8); 4030 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4031 MachineFunction &MF = DAG.getMachineFunction(); 4032 MachineFrameInfo *MFI = MF.getFrameInfo(); 4033 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 4034 4035 // Offset of the first variable argument from stack pointer. 4036 int VaArgOffset; 4037 4038 if (NumRegs == Idx) 4039 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize); 4040 else 4041 VaArgOffset = 4042 (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx)); 4043 4044 // Record the frame index of the first variable argument 4045 // which is a value necessary to VASTART. 4046 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 4047 MipsFI->setVarArgsFrameIndex(FI); 4048 4049 // Copy the integer registers that have not been used for argument passing 4050 // to the argument register save area. For O32, the save area is allocated 4051 // in the caller's stack frame, while for N32/64, it is allocated in the 4052 // callee's stack frame. 4053 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) { 4054 unsigned Reg = AddLiveIn(MF, ArgRegs[I], RC); 4055 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 4056 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 4057 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 4058 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, 4059 MachinePointerInfo(), false, false, 0); 4060 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0); 4061 OutChains.push_back(Store); 4062 } 4063} 4064