MipsISelLowering.cpp revision e2d529ac1111f153628a9c5c654f4a514e841b47
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-lower" 16#include "MipsISelLowering.h" 17#include "MipsMachineFunction.h" 18#include "MipsTargetMachine.h" 19#include "MipsTargetObjectFile.h" 20#include "MipsSubtarget.h" 21#include "InstPrinter/MipsInstPrinter.h" 22#include "MCTargetDesc/MipsBaseInfo.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/CallingConv.h" 28#include "llvm/CodeGen/CallingConvLower.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/SelectionDAGISel.h" 34#include "llvm/CodeGen/ValueTypes.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38 39using namespace llvm; 40 41// If I is a shifted mask, set the size (Size) and the first bit of the 42// mask (Pos), and return true. 43// For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 44static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 45 if (!isShiftedMask_64(I)) 46 return false; 47 48 Size = CountPopulation_64(I); 49 Pos = CountTrailingZeros_64(I); 50 return true; 51} 52 53static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) { 54 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 55 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 56} 57 58const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 59 switch (Opcode) { 60 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 61 case MipsISD::Hi: return "MipsISD::Hi"; 62 case MipsISD::Lo: return "MipsISD::Lo"; 63 case MipsISD::GPRel: return "MipsISD::GPRel"; 64 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 65 case MipsISD::Ret: return "MipsISD::Ret"; 66 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 67 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 68 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 69 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 70 case MipsISD::FPRound: return "MipsISD::FPRound"; 71 case MipsISD::MAdd: return "MipsISD::MAdd"; 72 case MipsISD::MAddu: return "MipsISD::MAddu"; 73 case MipsISD::MSub: return "MipsISD::MSub"; 74 case MipsISD::MSubu: return "MipsISD::MSubu"; 75 case MipsISD::DivRem: return "MipsISD::DivRem"; 76 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 77 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 78 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 79 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 80 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 81 case MipsISD::Sync: return "MipsISD::Sync"; 82 case MipsISD::Ext: return "MipsISD::Ext"; 83 case MipsISD::Ins: return "MipsISD::Ins"; 84 case MipsISD::LWL: return "MipsISD::LWL"; 85 case MipsISD::LWR: return "MipsISD::LWR"; 86 case MipsISD::SWL: return "MipsISD::SWL"; 87 case MipsISD::SWR: return "MipsISD::SWR"; 88 case MipsISD::LDL: return "MipsISD::LDL"; 89 case MipsISD::LDR: return "MipsISD::LDR"; 90 case MipsISD::SDL: return "MipsISD::SDL"; 91 case MipsISD::SDR: return "MipsISD::SDR"; 92 default: return NULL; 93 } 94} 95 96MipsTargetLowering:: 97MipsTargetLowering(MipsTargetMachine &TM) 98 : TargetLowering(TM, new MipsTargetObjectFile()), 99 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 100 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()), 101 IsO32(Subtarget->isABI_O32()) { 102 103 // Mips does not have i1 type, so use i32 for 104 // setcc operations results (slt, sgt, ...). 105 setBooleanContents(ZeroOrOneBooleanContent); 106 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 107 108 // Set up the register classes 109 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass); 110 111 if (HasMips64) 112 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass); 113 114 if (Subtarget->inMips16Mode()) { 115 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); 116 addRegisterClass(MVT::i32, &Mips::CPURARegRegClass); 117 } 118 119 if (!TM.Options.UseSoftFloat) { 120 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); 121 122 // When dealing with single precision only, use libcalls 123 if (!Subtarget->isSingleFloat()) { 124 if (HasMips64) 125 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); 126 else 127 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); 128 } 129 } 130 131 // Load extented operations for i1 types must be promoted 132 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 133 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 134 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 135 136 // MIPS doesn't have extending float->double load/store 137 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 138 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 139 140 // Used by legalize types to correctly generate the setcc result. 141 // Without this, every float setcc comes with a AND/OR with the result, 142 // we don't want this, since the fpcmp result goes to a flag register, 143 // which is used implicitly by brcond and select operations. 144 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 145 146 // Mips Custom Operations 147 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 148 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 149 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 150 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 151 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 152 setOperationAction(ISD::SELECT, MVT::f32, Custom); 153 setOperationAction(ISD::SELECT, MVT::f64, Custom); 154 setOperationAction(ISD::SELECT, MVT::i32, Custom); 155 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 156 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 157 setOperationAction(ISD::SETCC, MVT::f32, Custom); 158 setOperationAction(ISD::SETCC, MVT::f64, Custom); 159 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 160 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 161 setOperationAction(ISD::VASTART, MVT::Other, Custom); 162 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 163 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 164 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 165 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 166 setOperationAction(ISD::LOAD, MVT::i32, Custom); 167 setOperationAction(ISD::STORE, MVT::i32, Custom); 168 169 if (!TM.Options.NoNaNsFPMath) { 170 setOperationAction(ISD::FABS, MVT::f32, Custom); 171 setOperationAction(ISD::FABS, MVT::f64, Custom); 172 } 173 174 if (HasMips64) { 175 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 176 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 177 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 178 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 179 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 180 setOperationAction(ISD::SELECT, MVT::i64, Custom); 181 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); 182 setOperationAction(ISD::LOAD, MVT::i64, Custom); 183 setOperationAction(ISD::STORE, MVT::i64, Custom); 184 } 185 186 if (!HasMips64) { 187 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 188 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 189 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 190 } 191 192 setOperationAction(ISD::SDIV, MVT::i32, Expand); 193 setOperationAction(ISD::SREM, MVT::i32, Expand); 194 setOperationAction(ISD::UDIV, MVT::i32, Expand); 195 setOperationAction(ISD::UREM, MVT::i32, Expand); 196 setOperationAction(ISD::SDIV, MVT::i64, Expand); 197 setOperationAction(ISD::SREM, MVT::i64, Expand); 198 setOperationAction(ISD::UDIV, MVT::i64, Expand); 199 setOperationAction(ISD::UREM, MVT::i64, Expand); 200 201 // Operations not directly supported by Mips. 202 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 203 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 204 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 205 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 206 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 207 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 208 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 209 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 210 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 211 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 212 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 213 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 214 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 217 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 218 setOperationAction(ISD::ROTL, MVT::i32, Expand); 219 setOperationAction(ISD::ROTL, MVT::i64, Expand); 220 221 if (!Subtarget->hasMips32r2()) 222 setOperationAction(ISD::ROTR, MVT::i32, Expand); 223 224 if (!Subtarget->hasMips64r2()) 225 setOperationAction(ISD::ROTR, MVT::i64, Expand); 226 227 setOperationAction(ISD::FSIN, MVT::f32, Expand); 228 setOperationAction(ISD::FSIN, MVT::f64, Expand); 229 setOperationAction(ISD::FCOS, MVT::f32, Expand); 230 setOperationAction(ISD::FCOS, MVT::f64, Expand); 231 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 232 setOperationAction(ISD::FPOW, MVT::f32, Expand); 233 setOperationAction(ISD::FPOW, MVT::f64, Expand); 234 setOperationAction(ISD::FLOG, MVT::f32, Expand); 235 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 236 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 237 setOperationAction(ISD::FEXP, MVT::f32, Expand); 238 setOperationAction(ISD::FMA, MVT::f32, Expand); 239 setOperationAction(ISD::FMA, MVT::f64, Expand); 240 setOperationAction(ISD::FREM, MVT::f32, Expand); 241 setOperationAction(ISD::FREM, MVT::f64, Expand); 242 243 if (!TM.Options.NoNaNsFPMath) { 244 setOperationAction(ISD::FNEG, MVT::f32, Expand); 245 setOperationAction(ISD::FNEG, MVT::f64, Expand); 246 } 247 248 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 249 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 250 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 251 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 252 253 setOperationAction(ISD::VAARG, MVT::Other, Expand); 254 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 255 setOperationAction(ISD::VAEND, MVT::Other, Expand); 256 257 // Use the default for now 258 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 259 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 260 261 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 262 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 263 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 264 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 265 266 setInsertFencesForAtomic(true); 267 268 if (!Subtarget->hasSEInReg()) { 269 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 270 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 271 } 272 273 if (!Subtarget->hasBitCount()) { 274 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 275 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 276 } 277 278 if (!Subtarget->hasSwap()) { 279 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 280 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 281 } 282 283 if (HasMips64) { 284 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); 285 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom); 286 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom); 287 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 288 } 289 290 setTargetDAGCombine(ISD::ADDE); 291 setTargetDAGCombine(ISD::SUBE); 292 setTargetDAGCombine(ISD::SDIVREM); 293 setTargetDAGCombine(ISD::UDIVREM); 294 setTargetDAGCombine(ISD::SELECT); 295 setTargetDAGCombine(ISD::AND); 296 setTargetDAGCombine(ISD::OR); 297 setTargetDAGCombine(ISD::ADD); 298 299 setMinFunctionAlignment(HasMips64 ? 3 : 2); 300 301 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP); 302 computeRegisterProperties(); 303 304 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0); 305 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1); 306 307 maxStoresPerMemcpy = 16; 308} 309 310bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 311 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 312 313 switch (SVT) { 314 case MVT::i64: 315 case MVT::i32: 316 return true; 317 default: 318 return false; 319 } 320} 321 322EVT MipsTargetLowering::getSetCCResultType(EVT VT) const { 323 return MVT::i32; 324} 325 326// SelectMadd - 327// Transforms a subgraph in CurDAG if the following pattern is found: 328// (addc multLo, Lo0), (adde multHi, Hi0), 329// where, 330// multHi/Lo: product of multiplication 331// Lo0: initial value of Lo register 332// Hi0: initial value of Hi register 333// Return true if pattern matching was successful. 334static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) { 335 // ADDENode's second operand must be a flag output of an ADDC node in order 336 // for the matching to be successful. 337 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); 338 339 if (ADDCNode->getOpcode() != ISD::ADDC) 340 return false; 341 342 SDValue MultHi = ADDENode->getOperand(0); 343 SDValue MultLo = ADDCNode->getOperand(0); 344 SDNode *MultNode = MultHi.getNode(); 345 unsigned MultOpc = MultHi.getOpcode(); 346 347 // MultHi and MultLo must be generated by the same node, 348 if (MultLo.getNode() != MultNode) 349 return false; 350 351 // and it must be a multiplication. 352 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 353 return false; 354 355 // MultLo amd MultHi must be the first and second output of MultNode 356 // respectively. 357 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 358 return false; 359 360 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 361 // of the values of MultNode, in which case MultNode will be removed in later 362 // phases. 363 // If there exist users other than ADDENode or ADDCNode, this function returns 364 // here, which will result in MultNode being mapped to a single MULT 365 // instruction node rather than a pair of MULT and MADD instructions being 366 // produced. 367 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 368 return false; 369 370 SDValue Chain = CurDAG->getEntryNode(); 371 DebugLoc dl = ADDENode->getDebugLoc(); 372 373 // create MipsMAdd(u) node 374 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 375 376 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue, 377 MultNode->getOperand(0),// Factor 0 378 MultNode->getOperand(1),// Factor 1 379 ADDCNode->getOperand(1),// Lo0 380 ADDENode->getOperand(1));// Hi0 381 382 // create CopyFromReg nodes 383 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 384 MAdd); 385 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 386 Mips::HI, MVT::i32, 387 CopyFromLo.getValue(2)); 388 389 // replace uses of adde and addc here 390 if (!SDValue(ADDCNode, 0).use_empty()) 391 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 392 393 if (!SDValue(ADDENode, 0).use_empty()) 394 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 395 396 return true; 397} 398 399// SelectMsub - 400// Transforms a subgraph in CurDAG if the following pattern is found: 401// (addc Lo0, multLo), (sube Hi0, multHi), 402// where, 403// multHi/Lo: product of multiplication 404// Lo0: initial value of Lo register 405// Hi0: initial value of Hi register 406// Return true if pattern matching was successful. 407static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) { 408 // SUBENode's second operand must be a flag output of an SUBC node in order 409 // for the matching to be successful. 410 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); 411 412 if (SUBCNode->getOpcode() != ISD::SUBC) 413 return false; 414 415 SDValue MultHi = SUBENode->getOperand(1); 416 SDValue MultLo = SUBCNode->getOperand(1); 417 SDNode *MultNode = MultHi.getNode(); 418 unsigned MultOpc = MultHi.getOpcode(); 419 420 // MultHi and MultLo must be generated by the same node, 421 if (MultLo.getNode() != MultNode) 422 return false; 423 424 // and it must be a multiplication. 425 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 426 return false; 427 428 // MultLo amd MultHi must be the first and second output of MultNode 429 // respectively. 430 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 431 return false; 432 433 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 434 // of the values of MultNode, in which case MultNode will be removed in later 435 // phases. 436 // If there exist users other than SUBENode or SUBCNode, this function returns 437 // here, which will result in MultNode being mapped to a single MULT 438 // instruction node rather than a pair of MULT and MSUB instructions being 439 // produced. 440 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 441 return false; 442 443 SDValue Chain = CurDAG->getEntryNode(); 444 DebugLoc dl = SUBENode->getDebugLoc(); 445 446 // create MipsSub(u) node 447 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 448 449 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue, 450 MultNode->getOperand(0),// Factor 0 451 MultNode->getOperand(1),// Factor 1 452 SUBCNode->getOperand(0),// Lo0 453 SUBENode->getOperand(0));// Hi0 454 455 // create CopyFromReg nodes 456 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 457 MSub); 458 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 459 Mips::HI, MVT::i32, 460 CopyFromLo.getValue(2)); 461 462 // replace uses of sube and subc here 463 if (!SDValue(SUBCNode, 0).use_empty()) 464 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 465 466 if (!SDValue(SUBENode, 0).use_empty()) 467 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 468 469 return true; 470} 471 472static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG, 473 TargetLowering::DAGCombinerInfo &DCI, 474 const MipsSubtarget *Subtarget) { 475 if (DCI.isBeforeLegalize()) 476 return SDValue(); 477 478 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 479 SelectMadd(N, &DAG)) 480 return SDValue(N, 0); 481 482 return SDValue(); 483} 484 485static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG, 486 TargetLowering::DAGCombinerInfo &DCI, 487 const MipsSubtarget *Subtarget) { 488 if (DCI.isBeforeLegalize()) 489 return SDValue(); 490 491 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 492 SelectMsub(N, &DAG)) 493 return SDValue(N, 0); 494 495 return SDValue(); 496} 497 498static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG, 499 TargetLowering::DAGCombinerInfo &DCI, 500 const MipsSubtarget *Subtarget) { 501 if (DCI.isBeforeLegalizeOps()) 502 return SDValue(); 503 504 EVT Ty = N->getValueType(0); 505 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64; 506 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64; 507 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 508 MipsISD::DivRemU; 509 DebugLoc dl = N->getDebugLoc(); 510 511 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 512 N->getOperand(0), N->getOperand(1)); 513 SDValue InChain = DAG.getEntryNode(); 514 SDValue InGlue = DivRem; 515 516 // insert MFLO 517 if (N->hasAnyUseOfValue(0)) { 518 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty, 519 InGlue); 520 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 521 InChain = CopyFromLo.getValue(1); 522 InGlue = CopyFromLo.getValue(2); 523 } 524 525 // insert MFHI 526 if (N->hasAnyUseOfValue(1)) { 527 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 528 HI, Ty, InGlue); 529 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 530 } 531 532 return SDValue(); 533} 534 535static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 536 switch (CC) { 537 default: llvm_unreachable("Unknown fp condition code!"); 538 case ISD::SETEQ: 539 case ISD::SETOEQ: return Mips::FCOND_OEQ; 540 case ISD::SETUNE: return Mips::FCOND_UNE; 541 case ISD::SETLT: 542 case ISD::SETOLT: return Mips::FCOND_OLT; 543 case ISD::SETGT: 544 case ISD::SETOGT: return Mips::FCOND_OGT; 545 case ISD::SETLE: 546 case ISD::SETOLE: return Mips::FCOND_OLE; 547 case ISD::SETGE: 548 case ISD::SETOGE: return Mips::FCOND_OGE; 549 case ISD::SETULT: return Mips::FCOND_ULT; 550 case ISD::SETULE: return Mips::FCOND_ULE; 551 case ISD::SETUGT: return Mips::FCOND_UGT; 552 case ISD::SETUGE: return Mips::FCOND_UGE; 553 case ISD::SETUO: return Mips::FCOND_UN; 554 case ISD::SETO: return Mips::FCOND_OR; 555 case ISD::SETNE: 556 case ISD::SETONE: return Mips::FCOND_ONE; 557 case ISD::SETUEQ: return Mips::FCOND_UEQ; 558 } 559} 560 561 562// Returns true if condition code has to be inverted. 563static bool InvertFPCondCode(Mips::CondCode CC) { 564 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 565 return false; 566 567 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 568 "Illegal Condition Code"); 569 570 return true; 571} 572 573// Creates and returns an FPCmp node from a setcc node. 574// Returns Op if setcc is not a floating point comparison. 575static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) { 576 // must be a SETCC node 577 if (Op.getOpcode() != ISD::SETCC) 578 return Op; 579 580 SDValue LHS = Op.getOperand(0); 581 582 if (!LHS.getValueType().isFloatingPoint()) 583 return Op; 584 585 SDValue RHS = Op.getOperand(1); 586 DebugLoc dl = Op.getDebugLoc(); 587 588 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 589 // node if necessary. 590 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 591 592 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 593 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 594} 595 596// Creates and returns a CMovFPT/F node. 597static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 598 SDValue False, DebugLoc DL) { 599 bool invert = InvertFPCondCode((Mips::CondCode) 600 cast<ConstantSDNode>(Cond.getOperand(2)) 601 ->getSExtValue()); 602 603 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 604 True.getValueType(), True, False, Cond); 605} 606 607static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 608 TargetLowering::DAGCombinerInfo &DCI, 609 const MipsSubtarget *Subtarget) { 610 if (DCI.isBeforeLegalizeOps()) 611 return SDValue(); 612 613 SDValue SetCC = N->getOperand(0); 614 615 if ((SetCC.getOpcode() != ISD::SETCC) || 616 !SetCC.getOperand(0).getValueType().isInteger()) 617 return SDValue(); 618 619 SDValue False = N->getOperand(2); 620 EVT FalseTy = False.getValueType(); 621 622 if (!FalseTy.isInteger()) 623 return SDValue(); 624 625 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False); 626 627 if (!CN || CN->getZExtValue()) 628 return SDValue(); 629 630 const DebugLoc DL = N->getDebugLoc(); 631 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 632 SDValue True = N->getOperand(1); 633 634 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 635 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 636 637 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 638} 639 640static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG, 641 TargetLowering::DAGCombinerInfo &DCI, 642 const MipsSubtarget *Subtarget) { 643 // Pattern match EXT. 644 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 645 // => ext $dst, $src, size, pos 646 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 647 return SDValue(); 648 649 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 650 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 651 652 // Op's first operand must be a shift right. 653 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 654 return SDValue(); 655 656 // The second operand of the shift must be an immediate. 657 ConstantSDNode *CN; 658 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 659 return SDValue(); 660 661 uint64_t Pos = CN->getZExtValue(); 662 uint64_t SMPos, SMSize; 663 664 // Op's second operand must be a shifted mask. 665 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 666 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 667 return SDValue(); 668 669 // Return if the shifted mask does not start at bit 0 or the sum of its size 670 // and Pos exceeds the word's size. 671 EVT ValTy = N->getValueType(0); 672 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 673 return SDValue(); 674 675 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy, 676 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), 677 DAG.getConstant(SMSize, MVT::i32)); 678} 679 680static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG, 681 TargetLowering::DAGCombinerInfo &DCI, 682 const MipsSubtarget *Subtarget) { 683 // Pattern match INS. 684 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 685 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 686 // => ins $dst, $src, size, pos, $src1 687 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 688 return SDValue(); 689 690 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 691 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 692 ConstantSDNode *CN; 693 694 // See if Op's first operand matches (and $src1 , mask0). 695 if (And0.getOpcode() != ISD::AND) 696 return SDValue(); 697 698 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 699 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 700 return SDValue(); 701 702 // See if Op's second operand matches (and (shl $src, pos), mask1). 703 if (And1.getOpcode() != ISD::AND) 704 return SDValue(); 705 706 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 707 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 708 return SDValue(); 709 710 // The shift masks must have the same position and size. 711 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 712 return SDValue(); 713 714 SDValue Shl = And1.getOperand(0); 715 if (Shl.getOpcode() != ISD::SHL) 716 return SDValue(); 717 718 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 719 return SDValue(); 720 721 unsigned Shamt = CN->getZExtValue(); 722 723 // Return if the shift amount and the first bit position of mask are not the 724 // same. 725 EVT ValTy = N->getValueType(0); 726 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 727 return SDValue(); 728 729 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0), 730 DAG.getConstant(SMPos0, MVT::i32), 731 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0)); 732} 733 734static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG, 735 TargetLowering::DAGCombinerInfo &DCI, 736 const MipsSubtarget *Subtarget) { 737 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 738 739 if (DCI.isBeforeLegalizeOps()) 740 return SDValue(); 741 742 SDValue Add = N->getOperand(1); 743 744 if (Add.getOpcode() != ISD::ADD) 745 return SDValue(); 746 747 SDValue Lo = Add.getOperand(1); 748 749 if ((Lo.getOpcode() != MipsISD::Lo) || 750 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 751 return SDValue(); 752 753 EVT ValTy = N->getValueType(0); 754 DebugLoc DL = N->getDebugLoc(); 755 756 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 757 Add.getOperand(0)); 758 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 759} 760 761SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 762 const { 763 SelectionDAG &DAG = DCI.DAG; 764 unsigned opc = N->getOpcode(); 765 766 switch (opc) { 767 default: break; 768 case ISD::ADDE: 769 return PerformADDECombine(N, DAG, DCI, Subtarget); 770 case ISD::SUBE: 771 return PerformSUBECombine(N, DAG, DCI, Subtarget); 772 case ISD::SDIVREM: 773 case ISD::UDIVREM: 774 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 775 case ISD::SELECT: 776 return PerformSELECTCombine(N, DAG, DCI, Subtarget); 777 case ISD::AND: 778 return PerformANDCombine(N, DAG, DCI, Subtarget); 779 case ISD::OR: 780 return PerformORCombine(N, DAG, DCI, Subtarget); 781 case ISD::ADD: 782 return PerformADDCombine(N, DAG, DCI, Subtarget); 783 } 784 785 return SDValue(); 786} 787 788SDValue MipsTargetLowering:: 789LowerOperation(SDValue Op, SelectionDAG &DAG) const 790{ 791 switch (Op.getOpcode()) 792 { 793 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 794 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 795 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 796 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 797 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 798 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 799 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 800 case ISD::SELECT: return LowerSELECT(Op, DAG); 801 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 802 case ISD::SETCC: return LowerSETCC(Op, DAG); 803 case ISD::VASTART: return LowerVASTART(Op, DAG); 804 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 805 case ISD::FABS: return LowerFABS(Op, DAG); 806 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 807 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 808 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); 809 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 810 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); 811 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG, true); 812 case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false); 813 case ISD::LOAD: return LowerLOAD(Op, DAG); 814 case ISD::STORE: return LowerSTORE(Op, DAG); 815 } 816 return SDValue(); 817} 818 819//===----------------------------------------------------------------------===// 820// Lower helper functions 821//===----------------------------------------------------------------------===// 822 823// AddLiveIn - This helper function adds the specified physical register to the 824// MachineFunction as a live in value. It also creates a corresponding 825// virtual register for it. 826static unsigned 827AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 828{ 829 assert(RC->contains(PReg) && "Not the correct regclass!"); 830 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 831 MF.getRegInfo().addLiveIn(PReg, VReg); 832 return VReg; 833} 834 835// Get fp branch code (not opcode) from condition code. 836static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 837 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 838 return Mips::BRANCH_T; 839 840 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 841 "Invalid CondCode."); 842 843 return Mips::BRANCH_F; 844} 845 846/* 847static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, 848 DebugLoc dl, 849 const MipsSubtarget *Subtarget, 850 const TargetInstrInfo *TII, 851 bool isFPCmp, unsigned Opc) { 852 // There is no need to expand CMov instructions if target has 853 // conditional moves. 854 if (Subtarget->hasCondMov()) 855 return BB; 856 857 // To "insert" a SELECT_CC instruction, we actually have to insert the 858 // diamond control-flow pattern. The incoming instruction knows the 859 // destination vreg to set, the condition code register to branch on, the 860 // true/false values to select between, and a branch opcode to use. 861 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 862 MachineFunction::iterator It = BB; 863 ++It; 864 865 // thisMBB: 866 // ... 867 // TrueVal = ... 868 // setcc r1, r2, r3 869 // bNE r1, r0, copy1MBB 870 // fallthrough --> copy0MBB 871 MachineBasicBlock *thisMBB = BB; 872 MachineFunction *F = BB->getParent(); 873 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 874 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 875 F->insert(It, copy0MBB); 876 F->insert(It, sinkMBB); 877 878 // Transfer the remainder of BB and its successor edges to sinkMBB. 879 sinkMBB->splice(sinkMBB->begin(), BB, 880 llvm::next(MachineBasicBlock::iterator(MI)), 881 BB->end()); 882 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 883 884 // Next, add the true and fallthrough blocks as its successors. 885 BB->addSuccessor(copy0MBB); 886 BB->addSuccessor(sinkMBB); 887 888 // Emit the right instruction according to the type of the operands compared 889 if (isFPCmp) 890 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 891 else 892 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 893 .addReg(Mips::ZERO).addMBB(sinkMBB); 894 895 // copy0MBB: 896 // %FalseValue = ... 897 // # fallthrough to sinkMBB 898 BB = copy0MBB; 899 900 // Update machine-CFG edges 901 BB->addSuccessor(sinkMBB); 902 903 // sinkMBB: 904 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 905 // ... 906 BB = sinkMBB; 907 908 if (isFPCmp) 909 BuildMI(*BB, BB->begin(), dl, 910 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 911 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 912 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 913 else 914 BuildMI(*BB, BB->begin(), dl, 915 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 916 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 917 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 918 919 MI->eraseFromParent(); // The pseudo instruction is gone now. 920 return BB; 921} 922*/ 923MachineBasicBlock * 924MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 925 MachineBasicBlock *BB) const { 926 switch (MI->getOpcode()) { 927 default: llvm_unreachable("Unexpected instr type to insert"); 928 case Mips::ATOMIC_LOAD_ADD_I8: 929 case Mips::ATOMIC_LOAD_ADD_I8_P8: 930 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 931 case Mips::ATOMIC_LOAD_ADD_I16: 932 case Mips::ATOMIC_LOAD_ADD_I16_P8: 933 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 934 case Mips::ATOMIC_LOAD_ADD_I32: 935 case Mips::ATOMIC_LOAD_ADD_I32_P8: 936 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); 937 case Mips::ATOMIC_LOAD_ADD_I64: 938 case Mips::ATOMIC_LOAD_ADD_I64_P8: 939 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu); 940 941 case Mips::ATOMIC_LOAD_AND_I8: 942 case Mips::ATOMIC_LOAD_AND_I8_P8: 943 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 944 case Mips::ATOMIC_LOAD_AND_I16: 945 case Mips::ATOMIC_LOAD_AND_I16_P8: 946 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 947 case Mips::ATOMIC_LOAD_AND_I32: 948 case Mips::ATOMIC_LOAD_AND_I32_P8: 949 return EmitAtomicBinary(MI, BB, 4, Mips::AND); 950 case Mips::ATOMIC_LOAD_AND_I64: 951 case Mips::ATOMIC_LOAD_AND_I64_P8: 952 return EmitAtomicBinary(MI, BB, 8, Mips::AND64); 953 954 case Mips::ATOMIC_LOAD_OR_I8: 955 case Mips::ATOMIC_LOAD_OR_I8_P8: 956 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 957 case Mips::ATOMIC_LOAD_OR_I16: 958 case Mips::ATOMIC_LOAD_OR_I16_P8: 959 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 960 case Mips::ATOMIC_LOAD_OR_I32: 961 case Mips::ATOMIC_LOAD_OR_I32_P8: 962 return EmitAtomicBinary(MI, BB, 4, Mips::OR); 963 case Mips::ATOMIC_LOAD_OR_I64: 964 case Mips::ATOMIC_LOAD_OR_I64_P8: 965 return EmitAtomicBinary(MI, BB, 8, Mips::OR64); 966 967 case Mips::ATOMIC_LOAD_XOR_I8: 968 case Mips::ATOMIC_LOAD_XOR_I8_P8: 969 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 970 case Mips::ATOMIC_LOAD_XOR_I16: 971 case Mips::ATOMIC_LOAD_XOR_I16_P8: 972 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 973 case Mips::ATOMIC_LOAD_XOR_I32: 974 case Mips::ATOMIC_LOAD_XOR_I32_P8: 975 return EmitAtomicBinary(MI, BB, 4, Mips::XOR); 976 case Mips::ATOMIC_LOAD_XOR_I64: 977 case Mips::ATOMIC_LOAD_XOR_I64_P8: 978 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64); 979 980 case Mips::ATOMIC_LOAD_NAND_I8: 981 case Mips::ATOMIC_LOAD_NAND_I8_P8: 982 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); 983 case Mips::ATOMIC_LOAD_NAND_I16: 984 case Mips::ATOMIC_LOAD_NAND_I16_P8: 985 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); 986 case Mips::ATOMIC_LOAD_NAND_I32: 987 case Mips::ATOMIC_LOAD_NAND_I32_P8: 988 return EmitAtomicBinary(MI, BB, 4, 0, true); 989 case Mips::ATOMIC_LOAD_NAND_I64: 990 case Mips::ATOMIC_LOAD_NAND_I64_P8: 991 return EmitAtomicBinary(MI, BB, 8, 0, true); 992 993 case Mips::ATOMIC_LOAD_SUB_I8: 994 case Mips::ATOMIC_LOAD_SUB_I8_P8: 995 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 996 case Mips::ATOMIC_LOAD_SUB_I16: 997 case Mips::ATOMIC_LOAD_SUB_I16_P8: 998 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 999 case Mips::ATOMIC_LOAD_SUB_I32: 1000 case Mips::ATOMIC_LOAD_SUB_I32_P8: 1001 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); 1002 case Mips::ATOMIC_LOAD_SUB_I64: 1003 case Mips::ATOMIC_LOAD_SUB_I64_P8: 1004 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu); 1005 1006 case Mips::ATOMIC_SWAP_I8: 1007 case Mips::ATOMIC_SWAP_I8_P8: 1008 return EmitAtomicBinaryPartword(MI, BB, 1, 0); 1009 case Mips::ATOMIC_SWAP_I16: 1010 case Mips::ATOMIC_SWAP_I16_P8: 1011 return EmitAtomicBinaryPartword(MI, BB, 2, 0); 1012 case Mips::ATOMIC_SWAP_I32: 1013 case Mips::ATOMIC_SWAP_I32_P8: 1014 return EmitAtomicBinary(MI, BB, 4, 0); 1015 case Mips::ATOMIC_SWAP_I64: 1016 case Mips::ATOMIC_SWAP_I64_P8: 1017 return EmitAtomicBinary(MI, BB, 8, 0); 1018 1019 case Mips::ATOMIC_CMP_SWAP_I8: 1020 case Mips::ATOMIC_CMP_SWAP_I8_P8: 1021 return EmitAtomicCmpSwapPartword(MI, BB, 1); 1022 case Mips::ATOMIC_CMP_SWAP_I16: 1023 case Mips::ATOMIC_CMP_SWAP_I16_P8: 1024 return EmitAtomicCmpSwapPartword(MI, BB, 2); 1025 case Mips::ATOMIC_CMP_SWAP_I32: 1026 case Mips::ATOMIC_CMP_SWAP_I32_P8: 1027 return EmitAtomicCmpSwap(MI, BB, 4); 1028 case Mips::ATOMIC_CMP_SWAP_I64: 1029 case Mips::ATOMIC_CMP_SWAP_I64_P8: 1030 return EmitAtomicCmpSwap(MI, BB, 8); 1031 } 1032} 1033 1034// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1035// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1036MachineBasicBlock * 1037MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 1038 unsigned Size, unsigned BinOpcode, 1039 bool Nand) const { 1040 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 1041 1042 MachineFunction *MF = BB->getParent(); 1043 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1044 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1045 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1046 DebugLoc dl = MI->getDebugLoc(); 1047 unsigned LL, SC, AND, NOR, ZERO, BEQ; 1048 1049 if (Size == 4) { 1050 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1051 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1052 AND = Mips::AND; 1053 NOR = Mips::NOR; 1054 ZERO = Mips::ZERO; 1055 BEQ = Mips::BEQ; 1056 } 1057 else { 1058 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 1059 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 1060 AND = Mips::AND64; 1061 NOR = Mips::NOR64; 1062 ZERO = Mips::ZERO_64; 1063 BEQ = Mips::BEQ64; 1064 } 1065 1066 unsigned OldVal = MI->getOperand(0).getReg(); 1067 unsigned Ptr = MI->getOperand(1).getReg(); 1068 unsigned Incr = MI->getOperand(2).getReg(); 1069 1070 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1071 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1072 unsigned Success = RegInfo.createVirtualRegister(RC); 1073 1074 // insert new blocks after the current block 1075 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1076 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1077 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1078 MachineFunction::iterator It = BB; 1079 ++It; 1080 MF->insert(It, loopMBB); 1081 MF->insert(It, exitMBB); 1082 1083 // Transfer the remainder of BB and its successor edges to exitMBB. 1084 exitMBB->splice(exitMBB->begin(), BB, 1085 llvm::next(MachineBasicBlock::iterator(MI)), 1086 BB->end()); 1087 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1088 1089 // thisMBB: 1090 // ... 1091 // fallthrough --> loopMBB 1092 BB->addSuccessor(loopMBB); 1093 loopMBB->addSuccessor(loopMBB); 1094 loopMBB->addSuccessor(exitMBB); 1095 1096 // loopMBB: 1097 // ll oldval, 0(ptr) 1098 // <binop> storeval, oldval, incr 1099 // sc success, storeval, 0(ptr) 1100 // beq success, $0, loopMBB 1101 BB = loopMBB; 1102 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1103 if (Nand) { 1104 // and andres, oldval, incr 1105 // nor storeval, $0, andres 1106 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1107 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1108 } else if (BinOpcode) { 1109 // <binop> storeval, oldval, incr 1110 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1111 } else { 1112 StoreVal = Incr; 1113 } 1114 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1115 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1116 1117 MI->eraseFromParent(); // The instruction is gone now. 1118 1119 return exitMBB; 1120} 1121 1122MachineBasicBlock * 1123MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, 1124 MachineBasicBlock *BB, 1125 unsigned Size, unsigned BinOpcode, 1126 bool Nand) const { 1127 assert((Size == 1 || Size == 2) && 1128 "Unsupported size for EmitAtomicBinaryPartial."); 1129 1130 MachineFunction *MF = BB->getParent(); 1131 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1132 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1133 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1134 DebugLoc dl = MI->getDebugLoc(); 1135 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1136 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1137 1138 unsigned Dest = MI->getOperand(0).getReg(); 1139 unsigned Ptr = MI->getOperand(1).getReg(); 1140 unsigned Incr = MI->getOperand(2).getReg(); 1141 1142 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1143 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1144 unsigned Mask = RegInfo.createVirtualRegister(RC); 1145 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1146 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1147 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1148 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1149 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1150 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1151 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1152 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1153 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1154 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1155 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1156 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1157 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1158 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1159 unsigned Success = RegInfo.createVirtualRegister(RC); 1160 1161 // insert new blocks after the current block 1162 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1163 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1164 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1165 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1166 MachineFunction::iterator It = BB; 1167 ++It; 1168 MF->insert(It, loopMBB); 1169 MF->insert(It, sinkMBB); 1170 MF->insert(It, exitMBB); 1171 1172 // Transfer the remainder of BB and its successor edges to exitMBB. 1173 exitMBB->splice(exitMBB->begin(), BB, 1174 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1175 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1176 1177 BB->addSuccessor(loopMBB); 1178 loopMBB->addSuccessor(loopMBB); 1179 loopMBB->addSuccessor(sinkMBB); 1180 sinkMBB->addSuccessor(exitMBB); 1181 1182 // thisMBB: 1183 // addiu masklsb2,$0,-4 # 0xfffffffc 1184 // and alignedaddr,ptr,masklsb2 1185 // andi ptrlsb2,ptr,3 1186 // sll shiftamt,ptrlsb2,3 1187 // ori maskupper,$0,255 # 0xff 1188 // sll mask,maskupper,shiftamt 1189 // nor mask2,$0,mask 1190 // sll incr2,incr,shiftamt 1191 1192 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1193 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1194 .addReg(Mips::ZERO).addImm(-4); 1195 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1196 .addReg(Ptr).addReg(MaskLSB2); 1197 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1198 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1199 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1200 .addReg(Mips::ZERO).addImm(MaskImm); 1201 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1202 .addReg(ShiftAmt).addReg(MaskUpper); 1203 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1204 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); 1205 1206 // atomic.load.binop 1207 // loopMBB: 1208 // ll oldval,0(alignedaddr) 1209 // binop binopres,oldval,incr2 1210 // and newval,binopres,mask 1211 // and maskedoldval0,oldval,mask2 1212 // or storeval,maskedoldval0,newval 1213 // sc success,storeval,0(alignedaddr) 1214 // beq success,$0,loopMBB 1215 1216 // atomic.swap 1217 // loopMBB: 1218 // ll oldval,0(alignedaddr) 1219 // and newval,incr2,mask 1220 // and maskedoldval0,oldval,mask2 1221 // or storeval,maskedoldval0,newval 1222 // sc success,storeval,0(alignedaddr) 1223 // beq success,$0,loopMBB 1224 1225 BB = loopMBB; 1226 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1227 if (Nand) { 1228 // and andres, oldval, incr2 1229 // nor binopres, $0, andres 1230 // and newval, binopres, mask 1231 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1232 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes) 1233 .addReg(Mips::ZERO).addReg(AndRes); 1234 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1235 } else if (BinOpcode) { 1236 // <binop> binopres, oldval, incr2 1237 // and newval, binopres, mask 1238 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1239 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1240 } else {// atomic.swap 1241 // and newval, incr2, mask 1242 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1243 } 1244 1245 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1246 .addReg(OldVal).addReg(Mask2); 1247 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1248 .addReg(MaskedOldVal0).addReg(NewVal); 1249 BuildMI(BB, dl, TII->get(SC), Success) 1250 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1251 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1252 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1253 1254 // sinkMBB: 1255 // and maskedoldval1,oldval,mask 1256 // srl srlres,maskedoldval1,shiftamt 1257 // sll sllres,srlres,24 1258 // sra dest,sllres,24 1259 BB = sinkMBB; 1260 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1261 1262 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1263 .addReg(OldVal).addReg(Mask); 1264 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1265 .addReg(ShiftAmt).addReg(MaskedOldVal1); 1266 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1267 .addReg(SrlRes).addImm(ShiftImm); 1268 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1269 .addReg(SllRes).addImm(ShiftImm); 1270 1271 MI->eraseFromParent(); // The instruction is gone now. 1272 1273 return exitMBB; 1274} 1275 1276MachineBasicBlock * 1277MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 1278 MachineBasicBlock *BB, 1279 unsigned Size) const { 1280 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1281 1282 MachineFunction *MF = BB->getParent(); 1283 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1284 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1285 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1286 DebugLoc dl = MI->getDebugLoc(); 1287 unsigned LL, SC, ZERO, BNE, BEQ; 1288 1289 if (Size == 4) { 1290 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1291 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1292 ZERO = Mips::ZERO; 1293 BNE = Mips::BNE; 1294 BEQ = Mips::BEQ; 1295 } 1296 else { 1297 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 1298 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 1299 ZERO = Mips::ZERO_64; 1300 BNE = Mips::BNE64; 1301 BEQ = Mips::BEQ64; 1302 } 1303 1304 unsigned Dest = MI->getOperand(0).getReg(); 1305 unsigned Ptr = MI->getOperand(1).getReg(); 1306 unsigned OldVal = MI->getOperand(2).getReg(); 1307 unsigned NewVal = MI->getOperand(3).getReg(); 1308 1309 unsigned Success = RegInfo.createVirtualRegister(RC); 1310 1311 // insert new blocks after the current block 1312 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1313 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1314 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1315 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1316 MachineFunction::iterator It = BB; 1317 ++It; 1318 MF->insert(It, loop1MBB); 1319 MF->insert(It, loop2MBB); 1320 MF->insert(It, exitMBB); 1321 1322 // Transfer the remainder of BB and its successor edges to exitMBB. 1323 exitMBB->splice(exitMBB->begin(), BB, 1324 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1325 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1326 1327 // thisMBB: 1328 // ... 1329 // fallthrough --> loop1MBB 1330 BB->addSuccessor(loop1MBB); 1331 loop1MBB->addSuccessor(exitMBB); 1332 loop1MBB->addSuccessor(loop2MBB); 1333 loop2MBB->addSuccessor(loop1MBB); 1334 loop2MBB->addSuccessor(exitMBB); 1335 1336 // loop1MBB: 1337 // ll dest, 0(ptr) 1338 // bne dest, oldval, exitMBB 1339 BB = loop1MBB; 1340 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1341 BuildMI(BB, dl, TII->get(BNE)) 1342 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1343 1344 // loop2MBB: 1345 // sc success, newval, 0(ptr) 1346 // beq success, $0, loop1MBB 1347 BB = loop2MBB; 1348 BuildMI(BB, dl, TII->get(SC), Success) 1349 .addReg(NewVal).addReg(Ptr).addImm(0); 1350 BuildMI(BB, dl, TII->get(BEQ)) 1351 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1352 1353 MI->eraseFromParent(); // The instruction is gone now. 1354 1355 return exitMBB; 1356} 1357 1358MachineBasicBlock * 1359MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, 1360 MachineBasicBlock *BB, 1361 unsigned Size) const { 1362 assert((Size == 1 || Size == 2) && 1363 "Unsupported size for EmitAtomicCmpSwapPartial."); 1364 1365 MachineFunction *MF = BB->getParent(); 1366 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1367 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1368 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1369 DebugLoc dl = MI->getDebugLoc(); 1370 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1371 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1372 1373 unsigned Dest = MI->getOperand(0).getReg(); 1374 unsigned Ptr = MI->getOperand(1).getReg(); 1375 unsigned CmpVal = MI->getOperand(2).getReg(); 1376 unsigned NewVal = MI->getOperand(3).getReg(); 1377 1378 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1379 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1380 unsigned Mask = RegInfo.createVirtualRegister(RC); 1381 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1382 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1383 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1384 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1385 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1386 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1387 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1388 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1389 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1390 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1391 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1392 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1393 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1394 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1395 unsigned Success = RegInfo.createVirtualRegister(RC); 1396 1397 // insert new blocks after the current block 1398 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1399 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1400 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1401 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1402 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1403 MachineFunction::iterator It = BB; 1404 ++It; 1405 MF->insert(It, loop1MBB); 1406 MF->insert(It, loop2MBB); 1407 MF->insert(It, sinkMBB); 1408 MF->insert(It, exitMBB); 1409 1410 // Transfer the remainder of BB and its successor edges to exitMBB. 1411 exitMBB->splice(exitMBB->begin(), BB, 1412 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1413 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1414 1415 BB->addSuccessor(loop1MBB); 1416 loop1MBB->addSuccessor(sinkMBB); 1417 loop1MBB->addSuccessor(loop2MBB); 1418 loop2MBB->addSuccessor(loop1MBB); 1419 loop2MBB->addSuccessor(sinkMBB); 1420 sinkMBB->addSuccessor(exitMBB); 1421 1422 // FIXME: computation of newval2 can be moved to loop2MBB. 1423 // thisMBB: 1424 // addiu masklsb2,$0,-4 # 0xfffffffc 1425 // and alignedaddr,ptr,masklsb2 1426 // andi ptrlsb2,ptr,3 1427 // sll shiftamt,ptrlsb2,3 1428 // ori maskupper,$0,255 # 0xff 1429 // sll mask,maskupper,shiftamt 1430 // nor mask2,$0,mask 1431 // andi maskedcmpval,cmpval,255 1432 // sll shiftedcmpval,maskedcmpval,shiftamt 1433 // andi maskednewval,newval,255 1434 // sll shiftednewval,maskednewval,shiftamt 1435 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1436 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1437 .addReg(Mips::ZERO).addImm(-4); 1438 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1439 .addReg(Ptr).addReg(MaskLSB2); 1440 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1441 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1442 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1443 .addReg(Mips::ZERO).addImm(MaskImm); 1444 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1445 .addReg(ShiftAmt).addReg(MaskUpper); 1446 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1447 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) 1448 .addReg(CmpVal).addImm(MaskImm); 1449 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) 1450 .addReg(ShiftAmt).addReg(MaskedCmpVal); 1451 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) 1452 .addReg(NewVal).addImm(MaskImm); 1453 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) 1454 .addReg(ShiftAmt).addReg(MaskedNewVal); 1455 1456 // loop1MBB: 1457 // ll oldval,0(alginedaddr) 1458 // and maskedoldval0,oldval,mask 1459 // bne maskedoldval0,shiftedcmpval,sinkMBB 1460 BB = loop1MBB; 1461 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1462 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1463 .addReg(OldVal).addReg(Mask); 1464 BuildMI(BB, dl, TII->get(Mips::BNE)) 1465 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1466 1467 // loop2MBB: 1468 // and maskedoldval1,oldval,mask2 1469 // or storeval,maskedoldval1,shiftednewval 1470 // sc success,storeval,0(alignedaddr) 1471 // beq success,$0,loop1MBB 1472 BB = loop2MBB; 1473 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1474 .addReg(OldVal).addReg(Mask2); 1475 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1476 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1477 BuildMI(BB, dl, TII->get(SC), Success) 1478 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1479 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1480 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1481 1482 // sinkMBB: 1483 // srl srlres,maskedoldval0,shiftamt 1484 // sll sllres,srlres,24 1485 // sra dest,sllres,24 1486 BB = sinkMBB; 1487 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1488 1489 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1490 .addReg(ShiftAmt).addReg(MaskedOldVal0); 1491 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1492 .addReg(SrlRes).addImm(ShiftImm); 1493 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1494 .addReg(SllRes).addImm(ShiftImm); 1495 1496 MI->eraseFromParent(); // The instruction is gone now. 1497 1498 return exitMBB; 1499} 1500 1501//===----------------------------------------------------------------------===// 1502// Misc Lower Operation implementation 1503//===----------------------------------------------------------------------===// 1504SDValue MipsTargetLowering:: 1505LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const 1506{ 1507 MachineFunction &MF = DAG.getMachineFunction(); 1508 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1509 unsigned SP = IsN64 ? Mips::SP_64 : Mips::SP; 1510 1511 assert(getTargetMachine().getFrameLowering()->getStackAlignment() >= 1512 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() && 1513 "Cannot lower if the alignment of the allocated space is larger than \ 1514 that of the stack."); 1515 1516 SDValue Chain = Op.getOperand(0); 1517 SDValue Size = Op.getOperand(1); 1518 DebugLoc dl = Op.getDebugLoc(); 1519 1520 // Get a reference from Mips stack pointer 1521 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SP, getPointerTy()); 1522 1523 // Subtract the dynamic size from the actual stack size to 1524 // obtain the new stack size. 1525 SDValue Sub = DAG.getNode(ISD::SUB, dl, getPointerTy(), StackPointer, Size); 1526 1527 // The Sub result contains the new stack start address, so it 1528 // must be placed in the stack pointer register. 1529 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, SP, Sub, SDValue()); 1530 1531 // This node always has two return values: a new stack pointer 1532 // value and a chain 1533 SDVTList VTLs = DAG.getVTList(getPointerTy(), MVT::Other); 1534 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy()); 1535 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) }; 1536 1537 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3); 1538} 1539 1540SDValue MipsTargetLowering:: 1541LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1542{ 1543 // The first operand is the chain, the second is the condition, the third is 1544 // the block to branch to if the condition is true. 1545 SDValue Chain = Op.getOperand(0); 1546 SDValue Dest = Op.getOperand(2); 1547 DebugLoc dl = Op.getDebugLoc(); 1548 1549 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 1550 1551 // Return if flag is not set by a floating point comparison. 1552 if (CondRes.getOpcode() != MipsISD::FPCmp) 1553 return Op; 1554 1555 SDValue CCNode = CondRes.getOperand(2); 1556 Mips::CondCode CC = 1557 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1558 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 1559 1560 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 1561 Dest, CondRes); 1562} 1563 1564SDValue MipsTargetLowering:: 1565LowerSELECT(SDValue Op, SelectionDAG &DAG) const 1566{ 1567 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 1568 1569 // Return if flag is not set by a floating point comparison. 1570 if (Cond.getOpcode() != MipsISD::FPCmp) 1571 return Op; 1572 1573 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1574 Op.getDebugLoc()); 1575} 1576 1577SDValue MipsTargetLowering:: 1578LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 1579{ 1580 DebugLoc DL = Op.getDebugLoc(); 1581 EVT Ty = Op.getOperand(0).getValueType(); 1582 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty), 1583 Op.getOperand(0), Op.getOperand(1), 1584 Op.getOperand(4)); 1585 1586 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2), 1587 Op.getOperand(3)); 1588} 1589 1590SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1591 SDValue Cond = CreateFPCmp(DAG, Op); 1592 1593 assert(Cond.getOpcode() == MipsISD::FPCmp && 1594 "Floating point operand expected."); 1595 1596 SDValue True = DAG.getConstant(1, MVT::i32); 1597 SDValue False = DAG.getConstant(0, MVT::i32); 1598 1599 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc()); 1600} 1601 1602SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 1603 SelectionDAG &DAG) const { 1604 // FIXME there isn't actually debug info here 1605 DebugLoc dl = Op.getDebugLoc(); 1606 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1607 1608 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1609 SDVTList VTs = DAG.getVTList(MVT::i32); 1610 1611 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering(); 1612 1613 // %gp_rel relocation 1614 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1615 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1616 MipsII::MO_GPREL); 1617 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1); 1618 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1619 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); 1620 } 1621 // %hi/%lo relocation 1622 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1623 MipsII::MO_ABS_HI); 1624 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1625 MipsII::MO_ABS_LO); 1626 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1); 1627 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 1628 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1629 } 1630 1631 EVT ValTy = Op.getValueType(); 1632 bool HasGotOfst = (GV->hasInternalLinkage() || 1633 (GV->hasLocalLinkage() && !isa<Function>(GV))); 1634 unsigned GotFlag = HasMips64 ? 1635 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) : 1636 (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16); 1637 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag); 1638 GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), GA); 1639 SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA, 1640 MachinePointerInfo(), false, false, false, 0); 1641 // On functions and global targets not internal linked only 1642 // a load from got/GP is necessary for PIC to work. 1643 if (!HasGotOfst) 1644 return ResNode; 1645 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, 1646 HasMips64 ? MipsII::MO_GOT_OFST : 1647 MipsII::MO_ABS_LO); 1648 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo); 1649 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo); 1650} 1651 1652SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 1653 SelectionDAG &DAG) const { 1654 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1655 // FIXME there isn't actually debug info here 1656 DebugLoc dl = Op.getDebugLoc(); 1657 1658 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1659 // %hi/%lo relocation 1660 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_HI); 1661 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_LO); 1662 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi); 1663 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo); 1664 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1665 } 1666 1667 EVT ValTy = Op.getValueType(); 1668 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1669 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1670 SDValue BAGOTOffset = DAG.getBlockAddress(BA, ValTy, true, GOTFlag); 1671 BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy, 1672 GetGlobalReg(DAG, ValTy), BAGOTOffset); 1673 SDValue BALOOffset = DAG.getBlockAddress(BA, ValTy, true, OFSTFlag); 1674 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset, 1675 MachinePointerInfo(), false, false, false, 0); 1676 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset); 1677 return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo); 1678} 1679 1680SDValue MipsTargetLowering:: 1681LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1682{ 1683 // If the relocation model is PIC, use the General Dynamic TLS Model or 1684 // Local Dynamic TLS model, otherwise use the Initial Exec or 1685 // Local Exec TLS Model. 1686 1687 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1688 DebugLoc dl = GA->getDebugLoc(); 1689 const GlobalValue *GV = GA->getGlobal(); 1690 EVT PtrVT = getPointerTy(); 1691 1692 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1693 1694 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1695 // General Dynamic and Local Dynamic TLS Model. 1696 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1697 : MipsII::MO_TLSGD; 1698 1699 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag); 1700 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, 1701 GetGlobalReg(DAG, PtrVT), TGA); 1702 unsigned PtrSize = PtrVT.getSizeInBits(); 1703 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1704 1705 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1706 1707 ArgListTy Args; 1708 ArgListEntry Entry; 1709 Entry.Node = Argument; 1710 Entry.Ty = PtrTy; 1711 Args.push_back(Entry); 1712 1713 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy, 1714 false, false, false, false, 0, CallingConv::C, 1715 /*isTailCall=*/false, /*doesNotRet=*/false, 1716 /*isReturnValueUsed=*/true, 1717 TlsGetAddr, Args, DAG, dl); 1718 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1719 1720 SDValue Ret = CallResult.first; 1721 1722 if (model != TLSModel::LocalDynamic) 1723 return Ret; 1724 1725 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1726 MipsII::MO_DTPREL_HI); 1727 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 1728 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1729 MipsII::MO_DTPREL_LO); 1730 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 1731 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret); 1732 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo); 1733 } 1734 1735 SDValue Offset; 1736 if (model == TLSModel::InitialExec) { 1737 // Initial Exec TLS Model 1738 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1739 MipsII::MO_GOTTPREL); 1740 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT), 1741 TGA); 1742 Offset = DAG.getLoad(PtrVT, dl, 1743 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1744 false, false, false, 0); 1745 } else { 1746 // Local Exec TLS Model 1747 assert(model == TLSModel::LocalExec); 1748 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1749 MipsII::MO_TPREL_HI); 1750 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1751 MipsII::MO_TPREL_LO); 1752 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 1753 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 1754 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1755 } 1756 1757 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT); 1758 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1759} 1760 1761SDValue MipsTargetLowering:: 1762LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1763{ 1764 SDValue HiPart, JTI, JTILo; 1765 // FIXME there isn't actually debug info here 1766 DebugLoc dl = Op.getDebugLoc(); 1767 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1768 EVT PtrVT = Op.getValueType(); 1769 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1770 1771 if (!IsPIC && !IsN64) { 1772 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_HI); 1773 HiPart = DAG.getNode(MipsISD::Hi, dl, PtrVT, JTI); 1774 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO); 1775 } else {// Emit Load from Global Pointer 1776 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1777 unsigned OfstFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1778 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, GOTFlag); 1779 JTI = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT), 1780 JTI); 1781 HiPart = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), JTI, 1782 MachinePointerInfo(), false, false, false, 0); 1783 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OfstFlag); 1784 } 1785 1786 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo); 1787 return DAG.getNode(ISD::ADD, dl, PtrVT, HiPart, Lo); 1788} 1789 1790SDValue MipsTargetLowering:: 1791LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1792{ 1793 SDValue ResNode; 1794 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1795 const Constant *C = N->getConstVal(); 1796 // FIXME there isn't actually debug info here 1797 DebugLoc dl = Op.getDebugLoc(); 1798 1799 // gp_rel relocation 1800 // FIXME: we should reference the constant pool using small data sections, 1801 // but the asm printer currently doesn't support this feature without 1802 // hacking it. This feature should come soon so we can uncomment the 1803 // stuff below. 1804 //if (IsInSmallSection(C->getType())) { 1805 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1806 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1807 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1808 1809 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1810 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1811 N->getOffset(), MipsII::MO_ABS_HI); 1812 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1813 N->getOffset(), MipsII::MO_ABS_LO); 1814 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi); 1815 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1816 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1817 } else { 1818 EVT ValTy = Op.getValueType(); 1819 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1820 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1821 SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(), 1822 N->getOffset(), GOTFlag); 1823 CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), CP); 1824 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP, 1825 MachinePointerInfo::getConstantPool(), false, 1826 false, false, 0); 1827 SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(), 1828 N->getOffset(), OFSTFlag); 1829 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo); 1830 ResNode = DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo); 1831 } 1832 1833 return ResNode; 1834} 1835 1836SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1837 MachineFunction &MF = DAG.getMachineFunction(); 1838 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1839 1840 DebugLoc dl = Op.getDebugLoc(); 1841 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1842 getPointerTy()); 1843 1844 // vastart just stores the address of the VarArgsFrameIndex slot into the 1845 // memory location argument. 1846 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1847 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 1848 MachinePointerInfo(SV), false, false, 0); 1849} 1850 1851static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1852 EVT TyX = Op.getOperand(0).getValueType(); 1853 EVT TyY = Op.getOperand(1).getValueType(); 1854 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1855 SDValue Const31 = DAG.getConstant(31, MVT::i32); 1856 DebugLoc DL = Op.getDebugLoc(); 1857 SDValue Res; 1858 1859 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1860 // to i32. 1861 SDValue X = (TyX == MVT::f32) ? 1862 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1863 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1864 Const1); 1865 SDValue Y = (TyY == MVT::f32) ? 1866 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 1867 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 1868 Const1); 1869 1870 if (HasR2) { 1871 // ext E, Y, 31, 1 ; extract bit31 of Y 1872 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 1873 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 1874 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 1875 } else { 1876 // sll SllX, X, 1 1877 // srl SrlX, SllX, 1 1878 // srl SrlY, Y, 31 1879 // sll SllY, SrlX, 31 1880 // or Or, SrlX, SllY 1881 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1882 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1883 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 1884 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 1885 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 1886 } 1887 1888 if (TyX == MVT::f32) 1889 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 1890 1891 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1892 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1893 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1894} 1895 1896static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1897 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 1898 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 1899 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 1900 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1901 DebugLoc DL = Op.getDebugLoc(); 1902 1903 // Bitcast to integer nodes. 1904 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 1905 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 1906 1907 if (HasR2) { 1908 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 1909 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 1910 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 1911 DAG.getConstant(WidthY - 1, MVT::i32), Const1); 1912 1913 if (WidthX > WidthY) 1914 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 1915 else if (WidthY > WidthX) 1916 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 1917 1918 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 1919 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X); 1920 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 1921 } 1922 1923 // (d)sll SllX, X, 1 1924 // (d)srl SrlX, SllX, 1 1925 // (d)srl SrlY, Y, width(Y)-1 1926 // (d)sll SllY, SrlX, width(Y)-1 1927 // or Or, SrlX, SllY 1928 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 1929 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 1930 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 1931 DAG.getConstant(WidthY - 1, MVT::i32)); 1932 1933 if (WidthX > WidthY) 1934 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 1935 else if (WidthY > WidthX) 1936 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 1937 1938 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 1939 DAG.getConstant(WidthX - 1, MVT::i32)); 1940 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 1941 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 1942} 1943 1944SDValue 1945MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 1946 if (Subtarget->hasMips64()) 1947 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2()); 1948 1949 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2()); 1950} 1951 1952static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1953 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1954 DebugLoc DL = Op.getDebugLoc(); 1955 1956 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1957 // to i32. 1958 SDValue X = (Op.getValueType() == MVT::f32) ? 1959 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1960 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1961 Const1); 1962 1963 // Clear MSB. 1964 if (HasR2) 1965 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 1966 DAG.getRegister(Mips::ZERO, MVT::i32), 1967 DAG.getConstant(31, MVT::i32), Const1, X); 1968 else { 1969 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1970 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1971 } 1972 1973 if (Op.getValueType() == MVT::f32) 1974 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 1975 1976 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1977 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1978 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1979} 1980 1981static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1982 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1983 DebugLoc DL = Op.getDebugLoc(); 1984 1985 // Bitcast to integer node. 1986 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 1987 1988 // Clear MSB. 1989 if (HasR2) 1990 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 1991 DAG.getRegister(Mips::ZERO_64, MVT::i64), 1992 DAG.getConstant(63, MVT::i32), Const1, X); 1993 else { 1994 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 1995 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 1996 } 1997 1998 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 1999} 2000 2001SDValue 2002MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const { 2003 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64)) 2004 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2()); 2005 2006 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2()); 2007} 2008 2009SDValue MipsTargetLowering:: 2010LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2011 // check the depth 2012 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2013 "Frame address can only be determined for current frame."); 2014 2015 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2016 MFI->setFrameAddressIsTaken(true); 2017 EVT VT = Op.getValueType(); 2018 DebugLoc dl = Op.getDebugLoc(); 2019 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 2020 IsN64 ? Mips::FP_64 : Mips::FP, VT); 2021 return FrameAddr; 2022} 2023 2024SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op, 2025 SelectionDAG &DAG) const { 2026 // check the depth 2027 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2028 "Return address can be determined only for current frame."); 2029 2030 MachineFunction &MF = DAG.getMachineFunction(); 2031 MachineFrameInfo *MFI = MF.getFrameInfo(); 2032 EVT VT = Op.getValueType(); 2033 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA; 2034 MFI->setReturnAddressIsTaken(true); 2035 2036 // Return RA, which contains the return address. Mark it an implicit live-in. 2037 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2038 return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT); 2039} 2040 2041// TODO: set SType according to the desired memory barrier behavior. 2042SDValue 2043MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const { 2044 unsigned SType = 0; 2045 DebugLoc dl = Op.getDebugLoc(); 2046 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 2047 DAG.getConstant(SType, MVT::i32)); 2048} 2049 2050SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op, 2051 SelectionDAG &DAG) const { 2052 // FIXME: Need pseudo-fence for 'singlethread' fences 2053 // FIXME: Set SType for weaker fences where supported/appropriate. 2054 unsigned SType = 0; 2055 DebugLoc dl = Op.getDebugLoc(); 2056 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 2057 DAG.getConstant(SType, MVT::i32)); 2058} 2059 2060SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op, 2061 SelectionDAG &DAG) const { 2062 DebugLoc DL = Op.getDebugLoc(); 2063 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2064 SDValue Shamt = Op.getOperand(2); 2065 2066 // if shamt < 32: 2067 // lo = (shl lo, shamt) 2068 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2069 // else: 2070 // lo = 0 2071 // hi = (shl lo, shamt[4:0]) 2072 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2073 DAG.getConstant(-1, MVT::i32)); 2074 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, 2075 DAG.getConstant(1, MVT::i32)); 2076 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, 2077 Not); 2078 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); 2079 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 2080 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); 2081 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2082 DAG.getConstant(0x20, MVT::i32)); 2083 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 2084 DAG.getConstant(0, MVT::i32), ShiftLeftLo); 2085 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or); 2086 2087 SDValue Ops[2] = {Lo, Hi}; 2088 return DAG.getMergeValues(Ops, 2, DL); 2089} 2090 2091SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2092 bool IsSRA) const { 2093 DebugLoc DL = Op.getDebugLoc(); 2094 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2095 SDValue Shamt = Op.getOperand(2); 2096 2097 // if shamt < 32: 2098 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2099 // if isSRA: 2100 // hi = (sra hi, shamt) 2101 // else: 2102 // hi = (srl hi, shamt) 2103 // else: 2104 // if isSRA: 2105 // lo = (sra hi, shamt[4:0]) 2106 // hi = (sra hi, 31) 2107 // else: 2108 // lo = (srl hi, shamt[4:0]) 2109 // hi = 0 2110 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2111 DAG.getConstant(-1, MVT::i32)); 2112 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, 2113 DAG.getConstant(1, MVT::i32)); 2114 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not); 2115 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); 2116 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 2117 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, 2118 Hi, Shamt); 2119 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2120 DAG.getConstant(0x20, MVT::i32)); 2121 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi, 2122 DAG.getConstant(31, MVT::i32)); 2123 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or); 2124 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 2125 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32), 2126 ShiftRightHi); 2127 2128 SDValue Ops[2] = {Lo, Hi}; 2129 return DAG.getMergeValues(Ops, 2, DL); 2130} 2131 2132static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2133 SDValue Chain, SDValue Src, unsigned Offset) { 2134 SDValue Ptr = LD->getBasePtr(); 2135 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2136 EVT BasePtrVT = Ptr.getValueType(); 2137 DebugLoc DL = LD->getDebugLoc(); 2138 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2139 2140 if (Offset) 2141 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2142 DAG.getConstant(Offset, BasePtrVT)); 2143 2144 SDValue Ops[] = { Chain, Ptr, Src }; 2145 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2146 LD->getMemOperand()); 2147} 2148 2149// Expand an unaligned 32 or 64-bit integer load node. 2150SDValue MipsTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2151 LoadSDNode *LD = cast<LoadSDNode>(Op); 2152 EVT MemVT = LD->getMemoryVT(); 2153 2154 // Return if load is aligned or if MemVT is neither i32 nor i64. 2155 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2156 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2157 return SDValue(); 2158 2159 bool IsLittle = Subtarget->isLittle(); 2160 EVT VT = Op.getValueType(); 2161 ISD::LoadExtType ExtType = LD->getExtensionType(); 2162 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2163 2164 assert((VT == MVT::i32) || (VT == MVT::i64)); 2165 2166 // Expand 2167 // (set dst, (i64 (load baseptr))) 2168 // to 2169 // (set tmp, (ldl (add baseptr, 7), undef)) 2170 // (set dst, (ldr baseptr, tmp)) 2171 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2172 SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2173 IsLittle ? 7 : 0); 2174 return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2175 IsLittle ? 0 : 7); 2176 } 2177 2178 SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2179 IsLittle ? 3 : 0); 2180 SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2181 IsLittle ? 0 : 3); 2182 2183 // Expand 2184 // (set dst, (i32 (load baseptr))) or 2185 // (set dst, (i64 (sextload baseptr))) or 2186 // (set dst, (i64 (extload baseptr))) 2187 // to 2188 // (set tmp, (lwl (add baseptr, 3), undef)) 2189 // (set dst, (lwr baseptr, tmp)) 2190 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2191 (ExtType == ISD::EXTLOAD)) 2192 return LWR; 2193 2194 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2195 2196 // Expand 2197 // (set dst, (i64 (zextload baseptr))) 2198 // to 2199 // (set tmp0, (lwl (add baseptr, 3), undef)) 2200 // (set tmp1, (lwr baseptr, tmp0)) 2201 // (set tmp2, (shl tmp1, 32)) 2202 // (set dst, (srl tmp2, 32)) 2203 DebugLoc DL = LD->getDebugLoc(); 2204 SDValue Const32 = DAG.getConstant(32, MVT::i32); 2205 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2206 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2207 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2208 return DAG.getMergeValues(Ops, 2, DL); 2209} 2210 2211static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2212 SDValue Chain, unsigned Offset) { 2213 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2214 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2215 DebugLoc DL = SD->getDebugLoc(); 2216 SDVTList VTList = DAG.getVTList(MVT::Other); 2217 2218 if (Offset) 2219 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2220 DAG.getConstant(Offset, BasePtrVT)); 2221 2222 SDValue Ops[] = { Chain, Value, Ptr }; 2223 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2224 SD->getMemOperand()); 2225} 2226 2227// Expand an unaligned 32 or 64-bit integer store node. 2228SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2229 StoreSDNode *SD = cast<StoreSDNode>(Op); 2230 EVT MemVT = SD->getMemoryVT(); 2231 2232 // Return if store is aligned or if MemVT is neither i32 nor i64. 2233 if ((SD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2234 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2235 return SDValue(); 2236 2237 bool IsLittle = Subtarget->isLittle(); 2238 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2239 EVT VT = Value.getValueType(); 2240 2241 // Expand 2242 // (store val, baseptr) or 2243 // (truncstore val, baseptr) 2244 // to 2245 // (swl val, (add baseptr, 3)) 2246 // (swr val, baseptr) 2247 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2248 SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain, 2249 IsLittle ? 3 : 0); 2250 return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2251 } 2252 2253 assert(VT == MVT::i64); 2254 2255 // Expand 2256 // (store val, baseptr) 2257 // to 2258 // (sdl val, (add baseptr, 7)) 2259 // (sdr val, baseptr) 2260 SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2261 return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2262} 2263 2264//===----------------------------------------------------------------------===// 2265// Calling Convention Implementation 2266//===----------------------------------------------------------------------===// 2267 2268//===----------------------------------------------------------------------===// 2269// TODO: Implement a generic logic using tblgen that can support this. 2270// Mips O32 ABI rules: 2271// --- 2272// i32 - Passed in A0, A1, A2, A3 and stack 2273// f32 - Only passed in f32 registers if no int reg has been used yet to hold 2274// an argument. Otherwise, passed in A1, A2, A3 and stack. 2275// f64 - Only passed in two aliased f32 registers if no int reg has been used 2276// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2277// not used, it must be shadowed. If only A3 is avaiable, shadow it and 2278// go to stack. 2279// 2280// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2281//===----------------------------------------------------------------------===// 2282 2283static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 2284 MVT LocVT, CCValAssign::LocInfo LocInfo, 2285 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2286 2287 static const unsigned IntRegsSize=4, FloatRegsSize=2; 2288 2289 static const uint16_t IntRegs[] = { 2290 Mips::A0, Mips::A1, Mips::A2, Mips::A3 2291 }; 2292 static const uint16_t F32Regs[] = { 2293 Mips::F12, Mips::F14 2294 }; 2295 static const uint16_t F64Regs[] = { 2296 Mips::D6, Mips::D7 2297 }; 2298 2299 // ByVal Args 2300 if (ArgFlags.isByVal()) { 2301 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 2302 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags); 2303 unsigned NextReg = (State.getNextStackOffset() + 3) / 4; 2304 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize); 2305 r < std::min(IntRegsSize, NextReg); ++r) 2306 State.AllocateReg(IntRegs[r]); 2307 return false; 2308 } 2309 2310 // Promote i8 and i16 2311 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2312 LocVT = MVT::i32; 2313 if (ArgFlags.isSExt()) 2314 LocInfo = CCValAssign::SExt; 2315 else if (ArgFlags.isZExt()) 2316 LocInfo = CCValAssign::ZExt; 2317 else 2318 LocInfo = CCValAssign::AExt; 2319 } 2320 2321 unsigned Reg; 2322 2323 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2324 // is true: function is vararg, argument is 3rd or higher, there is previous 2325 // argument which is not f32 or f64. 2326 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 2327 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 2328 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2329 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2330 2331 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2332 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2333 // If this is the first part of an i64 arg, 2334 // the allocated register must be either A0 or A2. 2335 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2336 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2337 LocVT = MVT::i32; 2338 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2339 // Allocate int register and shadow next int register. If first 2340 // available register is Mips::A1 or Mips::A3, shadow it too. 2341 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2342 if (Reg == Mips::A1 || Reg == Mips::A3) 2343 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2344 State.AllocateReg(IntRegs, IntRegsSize); 2345 LocVT = MVT::i32; 2346 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2347 // we are guaranteed to find an available float register 2348 if (ValVT == MVT::f32) { 2349 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 2350 // Shadow int register 2351 State.AllocateReg(IntRegs, IntRegsSize); 2352 } else { 2353 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 2354 // Shadow int registers 2355 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 2356 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2357 State.AllocateReg(IntRegs, IntRegsSize); 2358 State.AllocateReg(IntRegs, IntRegsSize); 2359 } 2360 } else 2361 llvm_unreachable("Cannot handle this ValVT."); 2362 2363 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; 2364 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign); 2365 2366 if (!Reg) 2367 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2368 else 2369 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2370 2371 return false; // CC must always match 2372} 2373 2374static const uint16_t Mips64IntRegs[8] = 2375 {Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, 2376 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64}; 2377static const uint16_t Mips64DPRegs[8] = 2378 {Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 2379 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64}; 2380 2381static bool CC_Mips64Byval(unsigned ValNo, MVT ValVT, MVT LocVT, 2382 CCValAssign::LocInfo LocInfo, 2383 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2384 unsigned Align = std::max(ArgFlags.getByValAlign(), (unsigned)8); 2385 unsigned Size = (ArgFlags.getByValSize() + 7) / 8 * 8; 2386 unsigned FirstIdx = State.getFirstUnallocated(Mips64IntRegs, 8); 2387 2388 assert(Align <= 16 && "Cannot handle alignments larger than 16."); 2389 2390 // If byval is 16-byte aligned, the first arg register must be even. 2391 if ((Align == 16) && (FirstIdx % 2)) { 2392 State.AllocateReg(Mips64IntRegs[FirstIdx], Mips64DPRegs[FirstIdx]); 2393 ++FirstIdx; 2394 } 2395 2396 // Mark the registers allocated. 2397 for (unsigned I = FirstIdx; Size && (I < 8); Size -= 8, ++I) 2398 State.AllocateReg(Mips64IntRegs[I], Mips64DPRegs[I]); 2399 2400 // Allocate space on caller's stack. 2401 unsigned Offset = State.AllocateStack(Size, Align); 2402 2403 if (FirstIdx < 8) 2404 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Mips64IntRegs[FirstIdx], 2405 LocVT, LocInfo)); 2406 else 2407 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2408 2409 return true; 2410} 2411 2412#include "MipsGenCallingConv.inc" 2413 2414static void 2415AnalyzeMips64CallOperands(CCState &CCInfo, 2416 const SmallVectorImpl<ISD::OutputArg> &Outs) { 2417 unsigned NumOps = Outs.size(); 2418 for (unsigned i = 0; i != NumOps; ++i) { 2419 MVT ArgVT = Outs[i].VT; 2420 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 2421 bool R; 2422 2423 if (Outs[i].IsFixed) 2424 R = CC_MipsN(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 2425 else 2426 R = CC_MipsN_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 2427 2428 if (R) { 2429#ifndef NDEBUG 2430 dbgs() << "Call operand #" << i << " has unhandled type " 2431 << EVT(ArgVT).getEVTString(); 2432#endif 2433 llvm_unreachable(0); 2434 } 2435 } 2436} 2437 2438//===----------------------------------------------------------------------===// 2439// Call Calling Convention Implementation 2440//===----------------------------------------------------------------------===// 2441 2442static const unsigned O32IntRegsSize = 4; 2443 2444static const uint16_t O32IntRegs[] = { 2445 Mips::A0, Mips::A1, Mips::A2, Mips::A3 2446}; 2447 2448// Return next O32 integer argument register. 2449static unsigned getNextIntArgReg(unsigned Reg) { 2450 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2451 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2452} 2453 2454// Write ByVal Arg to arg registers and stack. 2455static void 2456WriteByValArg(SDValue Chain, DebugLoc dl, 2457 SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass, 2458 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, 2459 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 2460 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, 2461 MVT PtrType, bool isLittle) { 2462 unsigned LocMemOffset = VA.getLocMemOffset(); 2463 unsigned Offset = 0; 2464 uint32_t RemainingSize = Flags.getByValSize(); 2465 unsigned ByValAlign = Flags.getByValAlign(); 2466 2467 // Copy the first 4 words of byval arg to registers A0 - A3. 2468 // FIXME: Use a stricter alignment if it enables better optimization in passes 2469 // run later. 2470 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4; 2471 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) { 2472 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2473 DAG.getConstant(Offset, MVT::i32)); 2474 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr, 2475 MachinePointerInfo(), false, false, false, 2476 std::min(ByValAlign, (unsigned )4)); 2477 MemOpChains.push_back(LoadVal.getValue(1)); 2478 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 2479 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 2480 } 2481 2482 if (RemainingSize == 0) 2483 return; 2484 2485 // If there still is a register available for argument passing, write the 2486 // remaining part of the structure to it using subword loads and shifts. 2487 if (LocMemOffset < 4 * 4) { 2488 assert(RemainingSize <= 3 && RemainingSize >= 1 && 2489 "There must be one to three bytes remaining."); 2490 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize); 2491 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2492 DAG.getConstant(Offset, MVT::i32)); 2493 unsigned Alignment = std::min(ByValAlign, (unsigned )4); 2494 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 2495 LoadPtr, MachinePointerInfo(), 2496 MVT::getIntegerVT(LoadSize * 8), false, 2497 false, Alignment); 2498 MemOpChains.push_back(LoadVal.getValue(1)); 2499 2500 // If target is big endian, shift it to the most significant half-word or 2501 // byte. 2502 if (!isLittle) 2503 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal, 2504 DAG.getConstant(32 - LoadSize * 8, MVT::i32)); 2505 2506 Offset += LoadSize; 2507 RemainingSize -= LoadSize; 2508 2509 // Read second subword if necessary. 2510 if (RemainingSize != 0) { 2511 assert(RemainingSize == 1 && "There must be one byte remaining."); 2512 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2513 DAG.getConstant(Offset, MVT::i32)); 2514 unsigned Alignment = std::min(ByValAlign, (unsigned )2); 2515 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 2516 LoadPtr, MachinePointerInfo(), 2517 MVT::i8, false, false, Alignment); 2518 MemOpChains.push_back(Subword.getValue(1)); 2519 // Insert the loaded byte to LoadVal. 2520 // FIXME: Use INS if supported by target. 2521 unsigned ShiftAmt = isLittle ? 16 : 8; 2522 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword, 2523 DAG.getConstant(ShiftAmt, MVT::i32)); 2524 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift); 2525 } 2526 2527 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 2528 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 2529 return; 2530 } 2531 2532 // Copy remaining part of byval arg using memcpy. 2533 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2534 DAG.getConstant(Offset, MVT::i32)); 2535 SDValue Dst = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, 2536 DAG.getIntPtrConstant(LocMemOffset)); 2537 Chain = DAG.getMemcpy(Chain, dl, Dst, Src, 2538 DAG.getConstant(RemainingSize, MVT::i32), 2539 std::min(ByValAlign, (unsigned)4), 2540 /*isVolatile=*/false, /*AlwaysInline=*/false, 2541 MachinePointerInfo(0), MachinePointerInfo(0)); 2542 MemOpChains.push_back(Chain); 2543} 2544 2545// Copy Mips64 byVal arg to registers and stack. 2546void static 2547PassByValArg64(SDValue Chain, DebugLoc dl, 2548 SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass, 2549 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, 2550 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 2551 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, 2552 EVT PtrTy, bool isLittle) { 2553 unsigned ByValSize = Flags.getByValSize(); 2554 unsigned Alignment = std::min(Flags.getByValAlign(), (unsigned)8); 2555 bool IsRegLoc = VA.isRegLoc(); 2556 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct. 2557 unsigned LocMemOffset = 0; 2558 unsigned MemCpySize = ByValSize; 2559 2560 if (!IsRegLoc) 2561 LocMemOffset = VA.getLocMemOffset(); 2562 else { 2563 const uint16_t *Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, 2564 VA.getLocReg()); 2565 const uint16_t *RegEnd = Mips64IntRegs + 8; 2566 2567 // Copy double words to registers. 2568 for (; (Reg != RegEnd) && (ByValSize >= Offset + 8); ++Reg, Offset += 8) { 2569 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg, 2570 DAG.getConstant(Offset, PtrTy)); 2571 SDValue LoadVal = DAG.getLoad(MVT::i64, dl, Chain, LoadPtr, 2572 MachinePointerInfo(), false, false, false, 2573 Alignment); 2574 MemOpChains.push_back(LoadVal.getValue(1)); 2575 RegsToPass.push_back(std::make_pair(*Reg, LoadVal)); 2576 } 2577 2578 // Return if the struct has been fully copied. 2579 if (!(MemCpySize = ByValSize - Offset)) 2580 return; 2581 2582 // If there is an argument register available, copy the remainder of the 2583 // byval argument with sub-doubleword loads and shifts. 2584 if (Reg != RegEnd) { 2585 assert((ByValSize < Offset + 8) && 2586 "Size of the remainder should be smaller than 8-byte."); 2587 SDValue Val; 2588 for (unsigned LoadSize = 4; Offset < ByValSize; LoadSize /= 2) { 2589 unsigned RemSize = ByValSize - Offset; 2590 2591 if (RemSize < LoadSize) 2592 continue; 2593 2594 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg, 2595 DAG.getConstant(Offset, PtrTy)); 2596 SDValue LoadVal = 2597 DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i64, Chain, LoadPtr, 2598 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8), 2599 false, false, Alignment); 2600 MemOpChains.push_back(LoadVal.getValue(1)); 2601 2602 // Offset in number of bits from double word boundary. 2603 unsigned OffsetDW = (Offset % 8) * 8; 2604 unsigned Shamt = isLittle ? OffsetDW : 64 - (OffsetDW + LoadSize * 8); 2605 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i64, LoadVal, 2606 DAG.getConstant(Shamt, MVT::i32)); 2607 2608 Val = Val.getNode() ? DAG.getNode(ISD::OR, dl, MVT::i64, Val, Shift) : 2609 Shift; 2610 Offset += LoadSize; 2611 Alignment = std::min(Alignment, LoadSize); 2612 } 2613 2614 RegsToPass.push_back(std::make_pair(*Reg, Val)); 2615 return; 2616 } 2617 } 2618 2619 assert(MemCpySize && "MemCpySize must not be zero."); 2620 2621 // Copy remainder of byval arg to it with memcpy. 2622 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrTy, Arg, 2623 DAG.getConstant(Offset, PtrTy)); 2624 SDValue Dst = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, 2625 DAG.getIntPtrConstant(LocMemOffset)); 2626 Chain = DAG.getMemcpy(Chain, dl, Dst, Src, 2627 DAG.getConstant(MemCpySize, PtrTy), Alignment, 2628 /*isVolatile=*/false, /*AlwaysInline=*/false, 2629 MachinePointerInfo(0), MachinePointerInfo(0)); 2630 MemOpChains.push_back(Chain); 2631} 2632 2633/// LowerCall - functions arguments are copied from virtual regs to 2634/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2635/// TODO: isTailCall. 2636SDValue 2637MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2638 SmallVectorImpl<SDValue> &InVals) const { 2639 SelectionDAG &DAG = CLI.DAG; 2640 DebugLoc &dl = CLI.DL; 2641 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 2642 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 2643 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 2644 SDValue Chain = CLI.Chain; 2645 SDValue Callee = CLI.Callee; 2646 bool &isTailCall = CLI.IsTailCall; 2647 CallingConv::ID CallConv = CLI.CallConv; 2648 bool isVarArg = CLI.IsVarArg; 2649 2650 // MIPs target does not yet support tail call optimization. 2651 isTailCall = false; 2652 2653 MachineFunction &MF = DAG.getMachineFunction(); 2654 MachineFrameInfo *MFI = MF.getFrameInfo(); 2655 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 2656 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2657 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2658 2659 // Analyze operands of the call, assigning locations to each operand. 2660 SmallVector<CCValAssign, 16> ArgLocs; 2661 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2662 getTargetMachine(), ArgLocs, *DAG.getContext()); 2663 2664 if (CallConv == CallingConv::Fast) 2665 CCInfo.AnalyzeCallOperands(Outs, CC_Mips_FastCC); 2666 else if (IsO32) 2667 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); 2668 else if (HasMips64) 2669 AnalyzeMips64CallOperands(CCInfo, Outs); 2670 else 2671 CCInfo.AnalyzeCallOperands(Outs, CC_Mips); 2672 2673 // Get a count of how many bytes are to be pushed on the stack. 2674 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2675 unsigned StackAlignment = TFL->getStackAlignment(); 2676 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment); 2677 2678 // Update size of the maximum argument space. 2679 // For O32, a minimum of four words (16 bytes) of argument space is 2680 // allocated. 2681 if (IsO32 && (CallConv != CallingConv::Fast)) 2682 NextStackOffset = std::max(NextStackOffset, (unsigned)16); 2683 2684 // Chain is the output chain of the last Load/Store or CopyToReg node. 2685 // ByValChain is the output chain of the last Memcpy node created for copying 2686 // byval arguments to the stack. 2687 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 2688 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal); 2689 2690 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, 2691 IsN64 ? Mips::SP_64 : Mips::SP, 2692 getPointerTy()); 2693 2694 // Get the frame index of the stack frame object that points to the location 2695 // of dynamically allocated area on the stack. 2696 int DynAllocFI = MipsFI->getDynAllocFI(); 2697 2698 if (MipsFI->getMaxCallFrameSize() < NextStackOffset) { 2699 MipsFI->setMaxCallFrameSize(NextStackOffset); 2700 2701 // Set the offsets relative to $sp of the $gp restore slot and dynamically 2702 // allocated stack space. These offsets must be aligned to a boundary 2703 // determined by the stack alignment of the ABI. 2704 MFI->setObjectOffset(DynAllocFI, NextStackOffset); 2705 } 2706 2707 // With EABI is it possible to have 16 args on registers. 2708 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 2709 SmallVector<SDValue, 8> MemOpChains; 2710 2711 // Walk the register/memloc assignments, inserting copies/loads. 2712 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2713 SDValue Arg = OutVals[i]; 2714 CCValAssign &VA = ArgLocs[i]; 2715 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2716 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2717 2718 // ByVal Arg. 2719 if (Flags.isByVal()) { 2720 assert(Flags.getByValSize() && 2721 "ByVal args of size 0 should have been ignored by front-end."); 2722 if (IsO32) 2723 WriteByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, 2724 MFI, DAG, Arg, VA, Flags, getPointerTy(), 2725 Subtarget->isLittle()); 2726 else 2727 PassByValArg64(Chain, dl, RegsToPass, MemOpChains, StackPtr, 2728 MFI, DAG, Arg, VA, Flags, getPointerTy(), 2729 Subtarget->isLittle()); 2730 continue; 2731 } 2732 2733 // Promote the value if needed. 2734 switch (VA.getLocInfo()) { 2735 default: llvm_unreachable("Unknown loc info!"); 2736 case CCValAssign::Full: 2737 if (VA.isRegLoc()) { 2738 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2739 (ValVT == MVT::f64 && LocVT == MVT::i64)) 2740 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg); 2741 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2742 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2743 Arg, DAG.getConstant(0, MVT::i32)); 2744 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2745 Arg, DAG.getConstant(1, MVT::i32)); 2746 if (!Subtarget->isLittle()) 2747 std::swap(Lo, Hi); 2748 unsigned LocRegLo = VA.getLocReg(); 2749 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2750 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2751 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2752 continue; 2753 } 2754 } 2755 break; 2756 case CCValAssign::SExt: 2757 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg); 2758 break; 2759 case CCValAssign::ZExt: 2760 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg); 2761 break; 2762 case CCValAssign::AExt: 2763 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg); 2764 break; 2765 } 2766 2767 // Arguments that can be passed on register must be kept at 2768 // RegsToPass vector 2769 if (VA.isRegLoc()) { 2770 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2771 continue; 2772 } 2773 2774 // Register can't get to this point... 2775 assert(VA.isMemLoc()); 2776 2777 // emit ISD::STORE whichs stores the 2778 // parameter value to a stack Location 2779 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, 2780 DAG.getIntPtrConstant(VA.getLocMemOffset())); 2781 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2782 MachinePointerInfo(), false, false, 0)); 2783 } 2784 2785 // Transform all store nodes into one single node because all store 2786 // nodes are independent of each other. 2787 if (!MemOpChains.empty()) 2788 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2789 &MemOpChains[0], MemOpChains.size()); 2790 2791 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2792 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2793 // node so that legalize doesn't hack it. 2794 unsigned char OpFlag; 2795 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25 2796 bool GlobalOrExternal = false; 2797 SDValue CalleeLo; 2798 2799 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2800 if (IsPICCall && G->getGlobal()->hasInternalLinkage()) { 2801 OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE; 2802 unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST; 2803 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0, 2804 OpFlag); 2805 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 2806 0, LoFlag); 2807 } else { 2808 OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG; 2809 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2810 getPointerTy(), 0, OpFlag); 2811 } 2812 2813 GlobalOrExternal = true; 2814 } 2815 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2816 if (IsN64 || (!IsO32 && IsPIC)) 2817 OpFlag = MipsII::MO_GOT_DISP; 2818 else if (!IsPIC) // !N64 && static 2819 OpFlag = MipsII::MO_NO_FLAG; 2820 else // O32 & PIC 2821 OpFlag = MipsII::MO_GOT_CALL; 2822 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2823 OpFlag); 2824 GlobalOrExternal = true; 2825 } 2826 2827 SDValue InFlag; 2828 2829 // Create nodes that load address of callee and copy it to T9 2830 if (IsPICCall) { 2831 if (GlobalOrExternal) { 2832 // Load callee address 2833 Callee = DAG.getNode(MipsISD::Wrapper, dl, getPointerTy(), 2834 GetGlobalReg(DAG, getPointerTy()), Callee); 2835 SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 2836 Callee, MachinePointerInfo::getGOT(), 2837 false, false, false, 0); 2838 2839 // Use GOT+LO if callee has internal linkage. 2840 if (CalleeLo.getNode()) { 2841 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo); 2842 Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo); 2843 } else 2844 Callee = LoadValue; 2845 } 2846 } 2847 2848 // T9 register operand. 2849 SDValue T9; 2850 2851 // T9 should contain the address of the callee function if 2852 // -reloction-model=pic or it is an indirect call. 2853 if (IsPICCall || !GlobalOrExternal) { 2854 // copy to T9 2855 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9; 2856 Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0)); 2857 InFlag = Chain.getValue(1); 2858 2859 if (Subtarget->inMips16Mode()) 2860 T9 = DAG.getRegister(T9Reg, getPointerTy()); 2861 else 2862 Callee = DAG.getRegister(T9Reg, getPointerTy()); 2863 } 2864 2865 // Insert node "GP copy globalreg" before call to function. 2866 // Lazy-binding stubs require GP to point to the GOT. 2867 if (IsPICCall) { 2868 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP; 2869 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 2870 RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty))); 2871 } 2872 2873 // Build a sequence of copy-to-reg nodes chained together with token 2874 // chain and flag operands which copy the outgoing args into registers. 2875 // The InFlag in necessary since all emitted instructions must be 2876 // stuck together. 2877 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2878 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2879 RegsToPass[i].second, InFlag); 2880 InFlag = Chain.getValue(1); 2881 } 2882 2883 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 2884 // = Chain, Callee, Reg#1, Reg#2, ... 2885 // 2886 // Returns a chain & a flag for retval copy to use. 2887 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2888 SmallVector<SDValue, 8> Ops; 2889 Ops.push_back(Chain); 2890 Ops.push_back(Callee); 2891 2892 // Add argument registers to the end of the list so that they are 2893 // known live into the call. 2894 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2895 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2896 RegsToPass[i].second.getValueType())); 2897 2898 // Add T9 register operand. 2899 if (T9.getNode()) 2900 Ops.push_back(T9); 2901 2902 // Add a register mask operand representing the call-preserved registers. 2903 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2904 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2905 assert(Mask && "Missing call preserved mask for calling convention"); 2906 Ops.push_back(DAG.getRegisterMask(Mask)); 2907 2908 if (InFlag.getNode()) 2909 Ops.push_back(InFlag); 2910 2911 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 2912 InFlag = Chain.getValue(1); 2913 2914 // Create the CALLSEQ_END node. 2915 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2916 DAG.getIntPtrConstant(0, true), InFlag); 2917 InFlag = Chain.getValue(1); 2918 2919 // Handle result values, copying them out of physregs into vregs that we 2920 // return. 2921 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2922 Ins, dl, DAG, InVals); 2923} 2924 2925/// LowerCallResult - Lower the result values of a call into the 2926/// appropriate copies out of appropriate physical registers. 2927SDValue 2928MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2929 CallingConv::ID CallConv, bool isVarArg, 2930 const SmallVectorImpl<ISD::InputArg> &Ins, 2931 DebugLoc dl, SelectionDAG &DAG, 2932 SmallVectorImpl<SDValue> &InVals) const { 2933 // Assign locations to each value returned by this call. 2934 SmallVector<CCValAssign, 16> RVLocs; 2935 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2936 getTargetMachine(), RVLocs, *DAG.getContext()); 2937 2938 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 2939 2940 // Copy all of the result registers out of their specified physreg. 2941 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2942 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 2943 RVLocs[i].getValVT(), InFlag).getValue(1); 2944 InFlag = Chain.getValue(2); 2945 InVals.push_back(Chain.getValue(0)); 2946 } 2947 2948 return Chain; 2949} 2950 2951//===----------------------------------------------------------------------===// 2952// Formal Arguments Calling Convention Implementation 2953//===----------------------------------------------------------------------===// 2954static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl, 2955 std::vector<SDValue> &OutChains, 2956 SelectionDAG &DAG, unsigned NumWords, SDValue FIN, 2957 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, 2958 const Argument *FuncArg) { 2959 unsigned LocMem = VA.getLocMemOffset(); 2960 unsigned FirstWord = LocMem / 4; 2961 2962 // copy register A0 - A3 to frame object 2963 for (unsigned i = 0; i < NumWords; ++i) { 2964 unsigned CurWord = FirstWord + i; 2965 if (CurWord >= O32IntRegsSize) 2966 break; 2967 2968 unsigned SrcReg = O32IntRegs[CurWord]; 2969 unsigned Reg = AddLiveIn(MF, SrcReg, &Mips::CPURegsRegClass); 2970 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN, 2971 DAG.getConstant(i * 4, MVT::i32)); 2972 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32), 2973 StorePtr, MachinePointerInfo(FuncArg, i * 4), 2974 false, false, 0); 2975 OutChains.push_back(Store); 2976 } 2977} 2978 2979// Create frame object on stack and copy registers used for byval passing to it. 2980static unsigned 2981CopyMips64ByValRegs(MachineFunction &MF, SDValue Chain, DebugLoc dl, 2982 std::vector<SDValue> &OutChains, SelectionDAG &DAG, 2983 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, 2984 MachineFrameInfo *MFI, bool IsRegLoc, 2985 SmallVectorImpl<SDValue> &InVals, MipsFunctionInfo *MipsFI, 2986 EVT PtrTy, const Argument *FuncArg) { 2987 const uint16_t *Reg = Mips64IntRegs + 8; 2988 int FOOffset; // Frame object offset from virtual frame pointer. 2989 2990 if (IsRegLoc) { 2991 Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, VA.getLocReg()); 2992 FOOffset = (Reg - Mips64IntRegs) * 8 - 8 * 8; 2993 } 2994 else 2995 FOOffset = VA.getLocMemOffset(); 2996 2997 // Create frame object. 2998 unsigned NumRegs = (Flags.getByValSize() + 7) / 8; 2999 unsigned LastFI = MFI->CreateFixedObject(NumRegs * 8, FOOffset, true); 3000 SDValue FIN = DAG.getFrameIndex(LastFI, PtrTy); 3001 InVals.push_back(FIN); 3002 3003 // Copy arg registers. 3004 for (unsigned I = 0; (Reg != Mips64IntRegs + 8) && (I < NumRegs); 3005 ++Reg, ++I) { 3006 unsigned VReg = AddLiveIn(MF, *Reg, &Mips::CPU64RegsRegClass); 3007 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, PtrTy, FIN, 3008 DAG.getConstant(I * 8, PtrTy)); 3009 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64), 3010 StorePtr, MachinePointerInfo(FuncArg, I * 8), 3011 false, false, 0); 3012 OutChains.push_back(Store); 3013 } 3014 3015 return LastFI; 3016} 3017 3018/// LowerFormalArguments - transform physical registers into virtual registers 3019/// and generate load operations for arguments places on the stack. 3020SDValue 3021MipsTargetLowering::LowerFormalArguments(SDValue Chain, 3022 CallingConv::ID CallConv, 3023 bool isVarArg, 3024 const SmallVectorImpl<ISD::InputArg> &Ins, 3025 DebugLoc dl, SelectionDAG &DAG, 3026 SmallVectorImpl<SDValue> &InVals) 3027 const { 3028 MachineFunction &MF = DAG.getMachineFunction(); 3029 MachineFrameInfo *MFI = MF.getFrameInfo(); 3030 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3031 3032 MipsFI->setVarArgsFrameIndex(0); 3033 3034 // Used with vargs to acumulate store chains. 3035 std::vector<SDValue> OutChains; 3036 3037 // Assign locations to all of the incoming arguments. 3038 SmallVector<CCValAssign, 16> ArgLocs; 3039 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3040 getTargetMachine(), ArgLocs, *DAG.getContext()); 3041 3042 if (CallConv == CallingConv::Fast) 3043 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FastCC); 3044 else if (IsO32) 3045 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32); 3046 else 3047 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips); 3048 3049 Function::const_arg_iterator FuncArg = 3050 DAG.getMachineFunction().getFunction()->arg_begin(); 3051 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function. 3052 3053 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++FuncArg) { 3054 CCValAssign &VA = ArgLocs[i]; 3055 EVT ValVT = VA.getValVT(); 3056 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3057 bool IsRegLoc = VA.isRegLoc(); 3058 3059 if (Flags.isByVal()) { 3060 assert(Flags.getByValSize() && 3061 "ByVal args of size 0 should have been ignored by front-end."); 3062 if (IsO32) { 3063 unsigned NumWords = (Flags.getByValSize() + 3) / 4; 3064 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(), 3065 true); 3066 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 3067 InVals.push_back(FIN); 3068 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags, 3069 &*FuncArg); 3070 } else // N32/64 3071 LastFI = CopyMips64ByValRegs(MF, Chain, dl, OutChains, DAG, VA, Flags, 3072 MFI, IsRegLoc, InVals, MipsFI, 3073 getPointerTy(), &*FuncArg); 3074 continue; 3075 } 3076 3077 // Arguments stored on registers 3078 if (IsRegLoc) { 3079 EVT RegVT = VA.getLocVT(); 3080 unsigned ArgReg = VA.getLocReg(); 3081 const TargetRegisterClass *RC; 3082 3083 if (RegVT == MVT::i32) 3084 RC = &Mips::CPURegsRegClass; 3085 else if (RegVT == MVT::i64) 3086 RC = &Mips::CPU64RegsRegClass; 3087 else if (RegVT == MVT::f32) 3088 RC = &Mips::FGR32RegClass; 3089 else if (RegVT == MVT::f64) 3090 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; 3091 else 3092 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 3093 3094 // Transform the arguments stored on 3095 // physical registers into virtual ones 3096 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3097 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 3098 3099 // If this is an 8 or 16-bit value, it has been passed promoted 3100 // to 32 bits. Insert an assert[sz]ext to capture this, then 3101 // truncate to the right size. 3102 if (VA.getLocInfo() != CCValAssign::Full) { 3103 unsigned Opcode = 0; 3104 if (VA.getLocInfo() == CCValAssign::SExt) 3105 Opcode = ISD::AssertSext; 3106 else if (VA.getLocInfo() == CCValAssign::ZExt) 3107 Opcode = ISD::AssertZext; 3108 if (Opcode) 3109 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 3110 DAG.getValueType(ValVT)); 3111 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue); 3112 } 3113 3114 // Handle floating point arguments passed in integer registers. 3115 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3116 (RegVT == MVT::i64 && ValVT == MVT::f64)) 3117 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue); 3118 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) { 3119 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 3120 getNextIntArgReg(ArgReg), RC); 3121 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 3122 if (!Subtarget->isLittle()) 3123 std::swap(ArgValue, ArgValue2); 3124 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 3125 ArgValue, ArgValue2); 3126 } 3127 3128 InVals.push_back(ArgValue); 3129 } else { // VA.isRegLoc() 3130 3131 // sanity check 3132 assert(VA.isMemLoc()); 3133 3134 // The stack pointer offset is relative to the caller stack frame. 3135 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 3136 VA.getLocMemOffset(), true); 3137 3138 // Create load nodes to retrieve arguments from the stack 3139 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 3140 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN, 3141 MachinePointerInfo::getFixedStack(LastFI), 3142 false, false, false, 0)); 3143 } 3144 } 3145 3146 // The mips ABIs for returning structs by value requires that we copy 3147 // the sret argument into $v0 for the return. Save the argument into 3148 // a virtual register so that we can access it from the return points. 3149 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 3150 unsigned Reg = MipsFI->getSRetReturnReg(); 3151 if (!Reg) { 3152 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); 3153 MipsFI->setSRetReturnReg(Reg); 3154 } 3155 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 3156 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 3157 } 3158 3159 if (isVarArg) { 3160 unsigned NumOfRegs = IsO32 ? 4 : 8; 3161 const uint16_t *ArgRegs = IsO32 ? O32IntRegs : Mips64IntRegs; 3162 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumOfRegs); 3163 int FirstRegSlotOffset = IsO32 ? 0 : -64 ; // offset of $a0's slot. 3164 const TargetRegisterClass *RC = IsO32 ? 3165 (const TargetRegisterClass*)&Mips::CPURegsRegClass : 3166 (const TargetRegisterClass*)&Mips::CPU64RegsRegClass; 3167 unsigned RegSize = RC->getSize(); 3168 int RegSlotOffset = FirstRegSlotOffset + Idx * RegSize; 3169 3170 // Offset of the first variable argument from stack pointer. 3171 int FirstVaArgOffset; 3172 3173 if (IsO32 || (Idx == NumOfRegs)) { 3174 FirstVaArgOffset = 3175 (CCInfo.getNextStackOffset() + RegSize - 1) / RegSize * RegSize; 3176 } else 3177 FirstVaArgOffset = RegSlotOffset; 3178 3179 // Record the frame index of the first variable argument 3180 // which is a value necessary to VASTART. 3181 LastFI = MFI->CreateFixedObject(RegSize, FirstVaArgOffset, true); 3182 MipsFI->setVarArgsFrameIndex(LastFI); 3183 3184 // Copy the integer registers that have not been used for argument passing 3185 // to the argument register save area. For O32, the save area is allocated 3186 // in the caller's stack frame, while for N32/64, it is allocated in the 3187 // callee's stack frame. 3188 for (int StackOffset = RegSlotOffset; 3189 Idx < NumOfRegs; ++Idx, StackOffset += RegSize) { 3190 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegs[Idx], RC); 3191 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, 3192 MVT::getIntegerVT(RegSize * 8)); 3193 LastFI = MFI->CreateFixedObject(RegSize, StackOffset, true); 3194 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 3195 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, 3196 MachinePointerInfo(), false, false, 0)); 3197 } 3198 } 3199 3200 MipsFI->setLastInArgFI(LastFI); 3201 3202 // All stores are grouped in one node to allow the matching between 3203 // the size of Ins and InVals. This only happens when on varg functions 3204 if (!OutChains.empty()) { 3205 OutChains.push_back(Chain); 3206 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3207 &OutChains[0], OutChains.size()); 3208 } 3209 3210 return Chain; 3211} 3212 3213//===----------------------------------------------------------------------===// 3214// Return Value Calling Convention Implementation 3215//===----------------------------------------------------------------------===// 3216 3217SDValue 3218MipsTargetLowering::LowerReturn(SDValue Chain, 3219 CallingConv::ID CallConv, bool isVarArg, 3220 const SmallVectorImpl<ISD::OutputArg> &Outs, 3221 const SmallVectorImpl<SDValue> &OutVals, 3222 DebugLoc dl, SelectionDAG &DAG) const { 3223 3224 // CCValAssign - represent the assignment of 3225 // the return value to a location 3226 SmallVector<CCValAssign, 16> RVLocs; 3227 3228 // CCState - Info about the registers and stack slot. 3229 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3230 getTargetMachine(), RVLocs, *DAG.getContext()); 3231 3232 // Analize return values. 3233 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3234 3235 // If this is the first return lowered for this function, add 3236 // the regs to the liveout set for the function. 3237 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 3238 for (unsigned i = 0; i != RVLocs.size(); ++i) 3239 if (RVLocs[i].isRegLoc()) 3240 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 3241 } 3242 3243 SDValue Flag; 3244 3245 // Copy the result values into the output registers. 3246 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3247 CCValAssign &VA = RVLocs[i]; 3248 assert(VA.isRegLoc() && "Can only return in registers!"); 3249 3250 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 3251 3252 // guarantee that all emitted copies are 3253 // stuck together, avoiding something bad 3254 Flag = Chain.getValue(1); 3255 } 3256 3257 // The mips ABIs for returning structs by value requires that we copy 3258 // the sret argument into $v0 for the return. We saved the argument into 3259 // a virtual register in the entry block, so now we copy the value out 3260 // and into $v0. 3261 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 3262 MachineFunction &MF = DAG.getMachineFunction(); 3263 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3264 unsigned Reg = MipsFI->getSRetReturnReg(); 3265 3266 if (!Reg) 3267 llvm_unreachable("sret virtual register not created in the entry block"); 3268 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 3269 3270 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); 3271 Flag = Chain.getValue(1); 3272 } 3273 3274 // Return on Mips is always a "jr $ra" 3275 if (Flag.getNode()) 3276 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain, Flag); 3277 3278 // Return Void 3279 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain); 3280} 3281 3282//===----------------------------------------------------------------------===// 3283// Mips Inline Assembly Support 3284//===----------------------------------------------------------------------===// 3285 3286/// getConstraintType - Given a constraint letter, return the type of 3287/// constraint it is for this target. 3288MipsTargetLowering::ConstraintType MipsTargetLowering:: 3289getConstraintType(const std::string &Constraint) const 3290{ 3291 // Mips specific constrainy 3292 // GCC config/mips/constraints.md 3293 // 3294 // 'd' : An address register. Equivalent to r 3295 // unless generating MIPS16 code. 3296 // 'y' : Equivalent to r; retained for 3297 // backwards compatibility. 3298 // 'c' : A register suitable for use in an indirect 3299 // jump. This will always be $25 for -mabicalls. 3300 // 'l' : The lo register. 1 word storage. 3301 // 'x' : The hilo register pair. Double word storage. 3302 if (Constraint.size() == 1) { 3303 switch (Constraint[0]) { 3304 default : break; 3305 case 'd': 3306 case 'y': 3307 case 'f': 3308 case 'c': 3309 case 'l': 3310 case 'x': 3311 return C_RegisterClass; 3312 } 3313 } 3314 return TargetLowering::getConstraintType(Constraint); 3315} 3316 3317/// Examine constraint type and operand type and determine a weight value. 3318/// This object must already have been set up with the operand type 3319/// and the current alternative constraint selected. 3320TargetLowering::ConstraintWeight 3321MipsTargetLowering::getSingleConstraintMatchWeight( 3322 AsmOperandInfo &info, const char *constraint) const { 3323 ConstraintWeight weight = CW_Invalid; 3324 Value *CallOperandVal = info.CallOperandVal; 3325 // If we don't have a value, we can't do a match, 3326 // but allow it at the lowest weight. 3327 if (CallOperandVal == NULL) 3328 return CW_Default; 3329 Type *type = CallOperandVal->getType(); 3330 // Look at the constraint type. 3331 switch (*constraint) { 3332 default: 3333 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3334 break; 3335 case 'd': 3336 case 'y': 3337 if (type->isIntegerTy()) 3338 weight = CW_Register; 3339 break; 3340 case 'f': 3341 if (type->isFloatTy()) 3342 weight = CW_Register; 3343 break; 3344 case 'c': // $25 for indirect jumps 3345 case 'l': // lo register 3346 case 'x': // hilo register pair 3347 if (type->isIntegerTy()) 3348 weight = CW_SpecificReg; 3349 break; 3350 case 'I': // signed 16 bit immediate 3351 case 'J': // integer zero 3352 case 'K': // unsigned 16 bit immediate 3353 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3354 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3355 case 'O': // signed 15 bit immediate (+- 16383) 3356 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3357 if (isa<ConstantInt>(CallOperandVal)) 3358 weight = CW_Constant; 3359 break; 3360 } 3361 return weight; 3362} 3363 3364/// Given a register class constraint, like 'r', if this corresponds directly 3365/// to an LLVM register class, return a register of 0 and the register class 3366/// pointer. 3367std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 3368getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 3369{ 3370 if (Constraint.size() == 1) { 3371 switch (Constraint[0]) { 3372 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3373 case 'y': // Same as 'r'. Exists for compatibility. 3374 case 'r': 3375 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) 3376 return std::make_pair(0U, &Mips::CPURegsRegClass); 3377 if (VT == MVT::i64 && !HasMips64) 3378 return std::make_pair(0U, &Mips::CPURegsRegClass); 3379 if (VT == MVT::i64 && HasMips64) 3380 return std::make_pair(0U, &Mips::CPU64RegsRegClass); 3381 // This will generate an error message 3382 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 3383 case 'f': 3384 if (VT == MVT::f32) 3385 return std::make_pair(0U, &Mips::FGR32RegClass); 3386 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { 3387 if (Subtarget->isFP64bit()) 3388 return std::make_pair(0U, &Mips::FGR64RegClass); 3389 return std::make_pair(0U, &Mips::AFGR64RegClass); 3390 } 3391 break; 3392 case 'c': // register suitable for indirect jump 3393 if (VT == MVT::i32) 3394 return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass); 3395 assert(VT == MVT::i64 && "Unexpected type."); 3396 return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass); 3397 case 'l': // register suitable for indirect jump 3398 if (VT == MVT::i32) 3399 return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass); 3400 return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass); 3401 case 'x': // register suitable for indirect jump 3402 // Fixme: Not triggering the use of both hi and low 3403 // This will generate an error message 3404 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 3405 } 3406 } 3407 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3408} 3409 3410/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3411/// vector. If it is invalid, don't add anything to Ops. 3412void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3413 std::string &Constraint, 3414 std::vector<SDValue>&Ops, 3415 SelectionDAG &DAG) const { 3416 SDValue Result(0, 0); 3417 3418 // Only support length 1 constraints for now. 3419 if (Constraint.length() > 1) return; 3420 3421 char ConstraintLetter = Constraint[0]; 3422 switch (ConstraintLetter) { 3423 default: break; // This will fall through to the generic implementation 3424 case 'I': // Signed 16 bit constant 3425 // If this fails, the parent routine will give an error 3426 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3427 EVT Type = Op.getValueType(); 3428 int64_t Val = C->getSExtValue(); 3429 if (isInt<16>(Val)) { 3430 Result = DAG.getTargetConstant(Val, Type); 3431 break; 3432 } 3433 } 3434 return; 3435 case 'J': // integer zero 3436 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3437 EVT Type = Op.getValueType(); 3438 int64_t Val = C->getZExtValue(); 3439 if (Val == 0) { 3440 Result = DAG.getTargetConstant(0, Type); 3441 break; 3442 } 3443 } 3444 return; 3445 case 'K': // unsigned 16 bit immediate 3446 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3447 EVT Type = Op.getValueType(); 3448 uint64_t Val = (uint64_t)C->getZExtValue(); 3449 if (isUInt<16>(Val)) { 3450 Result = DAG.getTargetConstant(Val, Type); 3451 break; 3452 } 3453 } 3454 return; 3455 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3456 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3457 EVT Type = Op.getValueType(); 3458 int64_t Val = C->getSExtValue(); 3459 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3460 Result = DAG.getTargetConstant(Val, Type); 3461 break; 3462 } 3463 } 3464 return; 3465 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3466 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3467 EVT Type = Op.getValueType(); 3468 int64_t Val = C->getSExtValue(); 3469 if ((Val >= -65535) && (Val <= -1)) { 3470 Result = DAG.getTargetConstant(Val, Type); 3471 break; 3472 } 3473 } 3474 return; 3475 case 'O': // signed 15 bit immediate 3476 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3477 EVT Type = Op.getValueType(); 3478 int64_t Val = C->getSExtValue(); 3479 if ((isInt<15>(Val))) { 3480 Result = DAG.getTargetConstant(Val, Type); 3481 break; 3482 } 3483 } 3484 return; 3485 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3486 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3487 EVT Type = Op.getValueType(); 3488 int64_t Val = C->getSExtValue(); 3489 if ((Val <= 65535) && (Val >= 1)) { 3490 Result = DAG.getTargetConstant(Val, Type); 3491 break; 3492 } 3493 } 3494 return; 3495 } 3496 3497 if (Result.getNode()) { 3498 Ops.push_back(Result); 3499 return; 3500 } 3501 3502 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3503} 3504 3505bool 3506MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3507 // The Mips target isn't yet aware of offsets. 3508 return false; 3509} 3510 3511EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3512 unsigned SrcAlign, bool IsZeroVal, 3513 bool MemcpyStrSrc, 3514 MachineFunction &MF) const { 3515 if (Subtarget->hasMips64()) 3516 return MVT::i64; 3517 3518 return MVT::i32; 3519} 3520 3521bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3522 if (VT != MVT::f32 && VT != MVT::f64) 3523 return false; 3524 if (Imm.isNegZero()) 3525 return false; 3526 return Imm.isZero(); 3527} 3528 3529unsigned MipsTargetLowering::getJumpTableEncoding() const { 3530 if (IsN64) 3531 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3532 3533 return TargetLowering::getJumpTableEncoding(); 3534} 3535