MipsInstrFormats.td revision 5c5402564515ad87425af9881619545c096b84b9 
1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11//  Describe MIPS instructions format
12//
13//  CPU INSTRUCTION FORMATS
14//
15//  opcode  - operation code.
16//  rs      - src reg.
17//  rt      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18//  rd      - dst reg, only used on 3 regs instr.
19//  shamt   - only used on shift instructions, contains the shift amount.
20//  funct   - combined with opcode field give us an operation code.
21//
22//===----------------------------------------------------------------------===//
23
24// Format specifies the encoding used by the instruction.  This is part of the
25// ad-hoc solution used to emit machine instruction encodings by our machine
26// code emitter.
27class Format<bits<4> val> {
28  bits<4> Value = val;
29}
30
31def Pseudo    : Format<0>;
32def FrmR      : Format<1>;
33def FrmI      : Format<2>;
34def FrmJ      : Format<3>;
35def FrmFR     : Format<4>;
36def FrmFI     : Format<5>;
37def FrmOther  : Format<6>; // Instruction w/ a custom format
38
39// Generic Mips Format
40class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
41               InstrItinClass itin, Format f>: Instruction
42{
43  field bits<32> Inst;
44  Format Form = f;
45
46  let Namespace = "Mips";
47
48  let Size = 4;
49
50  bits<6> Opcode = 0;
51
52  // Top 6 bits are the 'opcode' field
53  let Inst{31-26} = Opcode;
54
55  let OutOperandList = outs;
56  let InOperandList  = ins;
57
58  let AsmString   = asmstr;
59  let Pattern     = pattern;
60  let Itinerary   = itin;
61
62  //
63  // Attributes specific to Mips instructions...
64  //
65  bits<4> FormBits = Form.Value;
66
67  // TSFlags layout should be kept in sync with MipsInstrInfo.h.
68  let TSFlags{3-0}   = FormBits;
69
70  let DecoderNamespace = "Mips";
71
72  field bits<32> SoftFail = 0;
73}
74
75// Mips32/64 Instruction Format
76class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
77             InstrItinClass itin, Format f>:
78  MipsInst<outs, ins, asmstr, pattern, itin, f> {
79  let Predicates = [HasStdEnc];
80}
81
82// Mips Pseudo Instructions Format
83class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
84  MipsInst<outs, ins, asmstr, pattern, IIPseudo, Pseudo> {
85  let isCodeGenOnly = 1;
86  let isPseudo = 1;
87}
88
89// Mips32/64 Pseudo Instruction Format
90class PseudoSE<dag outs, dag ins, string asmstr, list<dag> pattern>:
91  MipsPseudo<outs, ins, asmstr, pattern> {
92  let Predicates = [HasStdEnc];
93}
94
95// Pseudo-instructions for alternate assembly syntax (never used by codegen).
96// These are aliases that require C++ handling to convert to the target
97// instruction, while InstAliases can be handled directly by tblgen.
98class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
99  MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
100  let isPseudo = 1;
101  let Pattern = [];
102}
103//===----------------------------------------------------------------------===//
104// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
105//===----------------------------------------------------------------------===//
106
107class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
108         list<dag> pattern, InstrItinClass itin>:
109  InstSE<outs, ins, asmstr, pattern, itin, FrmR>
110{
111  bits<5>  rd;
112  bits<5>  rs;
113  bits<5>  rt;
114  bits<5>  shamt;
115  bits<6>  funct;
116
117  let Opcode = op;
118  let funct  = _funct;
119
120  let Inst{25-21} = rs;
121  let Inst{20-16} = rt;
122  let Inst{15-11} = rd;
123  let Inst{10-6}  = shamt;
124  let Inst{5-0}   = funct;
125}
126
127//===----------------------------------------------------------------------===//
128// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
129//===----------------------------------------------------------------------===//
130
131class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
132         InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
133{
134  bits<5>  rt;
135  bits<5>  rs;
136  bits<16> imm16;
137
138  let Opcode = op;
139
140  let Inst{25-21} = rs;
141  let Inst{20-16} = rt;
142  let Inst{15-0}  = imm16;
143}
144
145class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
146                  list<dag> pattern, InstrItinClass itin>:
147  InstSE<outs, ins, asmstr, pattern, itin, FrmI>
148{
149  bits<5>  rs;
150  bits<5>  rt;
151  bits<16> imm16;
152
153  let Opcode = op;
154
155  let Inst{25-21} = rs;
156  let Inst{20-16} = rt;
157  let Inst{15-0}  = imm16;
158}
159
160//===----------------------------------------------------------------------===//
161// Format J instruction class in Mips : <|opcode|address|>
162//===----------------------------------------------------------------------===//
163
164class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
165         InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmJ>
166{
167  bits<26> addr;
168
169  let Opcode = op;
170
171  let Inst{25-0} = addr;
172}
173
174 //===----------------------------------------------------------------------===//
175// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
176//===----------------------------------------------------------------------===//
177class MFC3OP<bits<6> op, bits<5> _mfmt, dag outs, dag ins, string asmstr>:
178  InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>
179{
180  bits<5> mfmt;
181  bits<5> rt;
182  bits<5> rd;
183  bits<3> sel;
184
185  let Opcode = op;
186  let mfmt = _mfmt;
187
188  let Inst{25-21} = mfmt;
189  let Inst{20-16} = rt;
190  let Inst{15-11} = rd;
191  let Inst{10-3}  = 0;
192  let Inst{2-0}   = sel;
193}
194
195class ADD_FM<bits<6> op, bits<6> funct> {
196  bits<5> rd;
197  bits<5> rs;
198  bits<5> rt;
199
200  bits<32> Inst;
201
202  let Inst{31-26} = op;
203  let Inst{25-21} = rs;
204  let Inst{20-16} = rt;
205  let Inst{15-11} = rd;
206  let Inst{10-6}  = 0;
207  let Inst{5-0}   = funct;
208}
209
210class ADDI_FM<bits<6> op> {
211  bits<5>  rs;
212  bits<5>  rt;
213  bits<16> imm16;
214
215  bits<32> Inst;
216
217  let Inst{31-26} = op;
218  let Inst{25-21} = rs;
219  let Inst{20-16} = rt;
220  let Inst{15-0}  = imm16;
221}
222
223class SRA_FM<bits<6> funct, bit rotate> {
224  bits<5> rd;
225  bits<5> rt;
226  bits<5> shamt;
227
228  bits<32> Inst;
229
230  let Inst{31-26} = 0;
231  let Inst{25-22} = 0;
232  let Inst{21}    = rotate;
233  let Inst{20-16} = rt;
234  let Inst{15-11} = rd;
235  let Inst{10-6}  = shamt;
236  let Inst{5-0}   = funct;
237}
238
239class SRLV_FM<bits<6> funct, bit rotate> {
240  bits<5> rd;
241  bits<5> rt;
242  bits<5> rs;
243
244  bits<32> Inst;
245
246  let Inst{31-26} = 0;
247  let Inst{25-21} = rs;
248  let Inst{20-16} = rt;
249  let Inst{15-11} = rd;
250  let Inst{10-7}  = 0;
251  let Inst{6}     = rotate;
252  let Inst{5-0}   = funct;
253}
254
255class BEQ_FM<bits<6> op> {
256  bits<5>  rs;
257  bits<5>  rt;
258  bits<16> offset;
259
260  bits<32> Inst;
261
262  let Inst{31-26} = op;
263  let Inst{25-21} = rs;
264  let Inst{20-16} = rt;
265  let Inst{15-0}  = offset;
266}
267
268class BGEZ_FM<bits<6> op, bits<5> funct> {
269  bits<5>  rs;
270  bits<16> offset;
271
272  bits<32> Inst;
273
274  let Inst{31-26} = op;
275  let Inst{25-21} = rs;
276  let Inst{20-16} = funct;
277  let Inst{15-0}  = offset;
278}
279
280//===----------------------------------------------------------------------===//
281//
282//  FLOATING POINT INSTRUCTION FORMATS
283//
284//  opcode  - operation code.
285//  fs      - src reg.
286//  ft      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
287//  fd      - dst reg, only used on 3 regs instr.
288//  fmt     - double or single precision.
289//  funct   - combined with opcode field give us an operation code.
290//
291//===----------------------------------------------------------------------===//
292
293//===----------------------------------------------------------------------===//
294// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
295//===----------------------------------------------------------------------===//
296
297class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
298  InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
299{
300  bits<5>  ft;
301  bits<5>  base;
302  bits<16> imm16;
303
304  let Opcode = op;
305
306  let Inst{25-21} = base;
307  let Inst{20-16} = ft;
308  let Inst{15-0}  = imm16;
309}
310
311class ADDS_FM<bits<6> funct, bits<5> fmt> {
312  bits<5> fd;
313  bits<5> fs;
314  bits<5> ft;
315
316  bits<32> Inst;
317
318  let Inst{31-26} = 0x11;
319  let Inst{25-21} = fmt;
320  let Inst{20-16} = ft;
321  let Inst{15-11} = fs;
322  let Inst{10-6}  = fd;
323  let Inst{5-0}   = funct;
324}
325
326class ABSS_FM<bits<6> funct, bits<5> fmt> {
327  bits<5> fd;
328  bits<5> fs;
329
330  bits<32> Inst;
331
332  let Inst{31-26} = 0x11;
333  let Inst{25-21} = fmt;
334  let Inst{20-16} = 0;
335  let Inst{15-11} = fs;
336  let Inst{10-6}  = fd;
337  let Inst{5-0}   = funct;
338}
339
340class MFC1_FM<bits<5> funct> {
341  bits<5> rt;
342  bits<5> fs;
343
344  bits<32> Inst;
345
346  let Inst{31-26} = 0x11;
347  let Inst{25-21} = funct;
348  let Inst{20-16} = rt;
349  let Inst{15-11} = fs;
350  let Inst{10-0}  = 0;
351}
352
353class LW_FM<bits<6> op> {
354  bits<5> rt;
355  bits<21> addr;
356
357  bits<32> Inst;
358
359  let Inst{31-26} = op;
360  let Inst{25-21} = addr{20-16};
361  let Inst{20-16} = rt;
362  let Inst{15-0}  = addr{15-0};
363}
364
365class MADDS_FM<bits<3> funct, bits<3> fmt> {
366  bits<5> fd;
367  bits<5> fr;
368  bits<5> fs;
369  bits<5> ft;
370
371  bits<32> Inst;
372
373  let Inst{31-26} = 0x13;
374  let Inst{25-21} = fr;
375  let Inst{20-16} = ft;
376  let Inst{15-11} = fs;
377  let Inst{10-6}  = fd;
378  let Inst{5-3}   = funct;
379  let Inst{2-0}   = fmt;
380}
381
382class LWXC1_FM<bits<6> funct> {
383  bits<5> fd;
384  bits<5> base;
385  bits<5> index;
386
387  bits<32> Inst;
388
389  let Inst{31-26} = 0x13;
390  let Inst{25-21} = base;
391  let Inst{20-16} = index;
392  let Inst{15-11} = 0;
393  let Inst{10-6}  = fd;
394  let Inst{5-0}   = funct;
395}
396
397class SWXC1_FM<bits<6> funct> {
398  bits<5> fs;
399  bits<5> base;
400  bits<5> index;
401
402  bits<32> Inst;
403
404  let Inst{31-26} = 0x13;
405  let Inst{25-21} = base;
406  let Inst{20-16} = index;
407  let Inst{15-11} = fs;
408  let Inst{10-6}  = 0;
409  let Inst{5-0}   = funct;
410}
411
412class BC1F_FM<bit nd, bit tf> {
413  bits<16> offset;
414
415  bits<32> Inst;
416
417  let Inst{31-26} = 0x11;
418  let Inst{25-21} = 0x8;
419  let Inst{20-18} = 0; // cc
420  let Inst{17} = nd;
421  let Inst{16} = tf;
422  let Inst{15-0} = offset;
423}
424
425class CEQS_FM<bits<5> fmt> {
426  bits<5> fs;
427  bits<5> ft;
428  bits<4> cond;
429
430  bits<32> Inst;
431
432  let Inst{31-26} = 0x11;
433  let Inst{25-21} = fmt;
434  let Inst{20-16} = ft;
435  let Inst{15-11} = fs;
436  let Inst{10-8} = 0; // cc
437  let Inst{7-4} = 0x3;
438  let Inst{3-0} = cond;
439}
440
441class CMov_I_F_FM<bits<6> funct, bits<5> fmt> {
442  bits<5> fd;
443  bits<5> fs;
444  bits<5> rt;
445
446  bits<32> Inst;
447
448  let Inst{31-26} = 0x11;
449  let Inst{25-21} = fmt;
450  let Inst{20-16} = rt;
451  let Inst{15-11} = fs;
452  let Inst{10-6} = fd;
453  let Inst{5-0} = funct;
454}
455
456class CMov_F_I_FM<bit tf> {
457  bits<5> rd;
458  bits<5> rs;
459
460  bits<32> Inst;
461
462  let Inst{31-26} = 0;
463  let Inst{25-21} = rs;
464  let Inst{20-18} = 0; // cc
465  let Inst{17} = 0;
466  let Inst{16} = tf;
467  let Inst{15-11} = rd;
468  let Inst{10-6} = 0;
469  let Inst{5-0} = 1;
470}
471
472class CMov_F_F_FM<bits<5> fmt, bit tf> {
473  bits<5> fd;
474  bits<5> fs;
475
476  bits<32> Inst;
477
478  let Inst{31-26} = 0x11;
479  let Inst{25-21} = fmt;
480  let Inst{20-18} = 0; // cc
481  let Inst{17} = 0;
482  let Inst{16} = tf;
483  let Inst{15-11} = fs;
484  let Inst{10-6} = fd;
485  let Inst{5-0} = 0x11;
486}
487