| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 1206f1968b0886ab41739aebe113dd4813f3fc46 |
|
13-Nov-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for microMIPS trap instruction with immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194569 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 9f471750fa6f34120d4758d5d14f54f899e34a54 |
|
07-Nov-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for microMIPS trap instructions 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194205 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 5c042162beb3c2dd556e00aab84c4278a69cd5b1 |
|
04-Nov-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for microMIPS branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193992 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 1aaf43c2a2ec0fd4c8dbfe56558237219c5f8af7 |
|
29-Oct-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for microMIPS jump instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| dcc425c6301c088b4c0598696de50c01fbca5733 |
|
14-Sep-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Fixed bug when generating Load Upper Immediate microMIPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 47b33528d1b4298bf8cc5dcca8b531dfd0e704bb |
|
14-Sep-2013 |
Zoran Jovanovic <zoran.jovanovic@imgtec.com> |
Support for misc microMIPS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190744 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 1d04ca7987ef0abb5be07b11e3bb9c9e756a1fce |
|
07-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, which is
equivalent to "beq $zero, $zero, offset".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190220 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| dadd1fba3280295936f556acbdc3fbb68b496bad |
|
06-Sep-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| bf7f7b5e0eae40bb47a410c90f9f0885c0f38b2c |
|
06-Sep-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190148 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| e4bf77a1282bfdacb61bae192fdf79a696be780a |
|
26-Aug-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch implements trap instructions for mips. The test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189213 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 809313970fc98bba6f36a332adfa3e5fef4110b3 |
|
12-Aug-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch implements ei and di instructions for mips. Test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188176 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 588f408b95c83e9b59c0777925d2ae70ac445fae |
|
01-Aug-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Moving definition of MnemonicContainsDot field from class Instruction to class AsmParser as suggested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187569 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 80bec28b6645676a7cd9408d780b4c805774ef42 |
|
30-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete instruction format for "bal".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187443 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 407883b69b3bc10ebf053f5922d877b2e786d124 |
|
26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix FP conditional move instructions to have explicit FP condition code
register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187242 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 83d8ef133b121b7e752e7468cb1e0e5e3b636aee |
|
26-Jul-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix FP branch instructions to have explicit FP condition code register
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 16f385f90f481195bfcf6b139ced4cee033bb887 |
|
17-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Implement eret and deret(return from exception) instructions for Mips. Test examples are given.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186507 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 088483627720acb58c96951b7b634f67312c7272 |
|
16-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| dd51a0c1e0b3cce8093244533b3505668d16f218 |
|
12-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Add support for Mips break and syscall insructions. The corresponding test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186151 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 296c1534b4ad835c6d9280145b63ca2b25831228 |
|
10-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Reverting commit r185999 due to buildboot failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186000 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 2ec5933eae2e889225d33bd2f93a35926e958c95 |
|
10-Jul-2013 |
Vladimir Medic <Vladimir.Medic@imgtec.com> |
Add support for Mips break and syscall insructions. The corresponding test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185999 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| f894199a14fff1399f6ee9d78c6a601d86649155 |
|
20-May-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Trap on integer division by zero.
By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182306 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 089741479be03b625f5a8cc52e750b4e532338c6 |
|
25-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add definitions of micromips load and store instructions.
Patch by Zoran Jovanovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 385de773033080503491919dc50be7203552247b |
|
25-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add definitions of micromips shift instructions.
Patch by Zoran Jovanovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| f530aff9de2738db0e3471b259ff0b577a6603e6 |
|
19-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] First patch which adds support for micromips.
This patch adds support for recoded (meaning assembly-language compatible to
standard mips32) arithmetic 32-bit instructions.
Patch by Zoran Jovanovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 0c66403efdf88ff4f247b6a9f45339bb3a893235 |
|
07-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add definition of JALR instruction which has two register operands. Change the
original JALR instruction with one register operand to be a pseudo-instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 6c59c9f57c8428e477ed592ee3537323d287d96f |
|
06-Feb-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Make NOP a pseudo instruction and expand it to "sll $zero, $zero, 0".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174546 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 1ebe5fce8ed51ab7e3908458bc5e2f0f24e0b21b |
|
04-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171515 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 5f560bb2ebd9b489750fafd0c2d7c5136d18c622 |
|
04-Jan-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor instructions which move data from or to coprocessors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| dbf51ee4596791d8cf38538b80805b2c3a577836 |
|
22-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170956 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| e8bc10b902f15eb4a12b810d5ab06a2755e7f990 |
|
22-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor SYNC and multiply/divide instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170955 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| aa7c9cd1814ad080c7f8e5c2c4434c206e0ea66d |
|
22-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor BAL instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 6a8309e62afd88fbea4f1c39121de6dc4dc0d899 |
|
22-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor jump, jump register, jump-and-link and nop instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170952 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 8e719fac46c3c79dedfde86bf439819444223537 |
|
21-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor LUI instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 35242e27c578da3915451079b5bdd7b9a89ed77c |
|
21-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor count leading zero or one instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 8aaed99a99fcb879be2ed9bbc25a68c2e8558960 |
|
21-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor sign-extension-in-register instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 7de001b97e1087b393efc90f7b10ffedd4f66fed |
|
21-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor instructions which copy from and to HI/LO registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 9bf571fe2c24305aee6a930ed3b2561f6d4ff237 |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor SLT (set on less than) instructions. Separate encoding
information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| c23061547de868c5971e1f7a12bc54a37a59a53f |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor unconditional branch instruction. Separate encoding information
from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 1e7739f6140da773b6e998525d7900fa82670f00 |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass
parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170661 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 5c5402564515ad87425af9881619545c096b84b9 |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor conditional branch instructions with one register operand.
Separate encoding information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| c4889013553a4e407e110d1f76d9b6cf1396e702 |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor conditional branch instructions with two register operands.
Separate encoding information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| cdc0c59d1ed5ac6c616b8899222d1e102ccd9f8d |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor shift instructions with register operands. Separate encoding
information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170650 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 0dad34a9bf850132e9ec84397f13604143c3aeff |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor shift immediate instructions. Separate encoding information
from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170649 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| ab48c503e231c9a3c9ccccbb57c0a3a7a4302a75 |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor arithmetic and logic instructions with immediate operands.
Separate encoding information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170648 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 23a3da0113600a2c3204f766cbc51d68a8ed4d94 |
|
20-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Refactor arithmetic and logic instructions. Separate encoding
information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170647 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| c567b1cd0d6bf973a21df4b5c8cae37e5e7518f8 |
|
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Delete all floating point instruction classes that are no longer used.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170084 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 5c3739927900af1bf5f5cdcbb3ebead2d89cd943 |
|
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Modify definitions of floating point conditional move instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| b573539c6b47d020ade2e41c0ff3afcd00f294f4 |
|
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Modify definitions of floating point comparison instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170077 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 89828a6a563426edda0e30384997b2b24be6bb12 |
|
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Modify definitions of floating point branch instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170076 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 2b1a50cfdb2db28605fc9834310890160c29be4f |
|
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Modify definitions of floating point indexed load and store instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170075 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| b2c68ddaaba55c417679d3ed466ebd403d991cec |
|
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Modify definitions of floating point multiply-add/sub instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 6f94eb3512ebc7b279451d26427153d9300a6a14 |
|
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Modify definitions of floating point load and store instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170072 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| be9f72d2d8ab4a785cf788c5d9c5092b0fc02bfc |
|
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Modify definitions of move from/to coprocessor instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170071 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 4b921416b4a702705a83a4288d217017512a7634 |
|
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Modify definitions of two register operand floating point instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170069 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 82fdad75f7efa9d15261068e1bb3691f10fb3d36 |
|
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Modify definitions of three register operand floating point instructions
and separate encoding information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 10bd7264598a806aced15d0b7a3a5fc6803112a1 |
|
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Move classes that do not belong in MipsInstrFormats.td into
MipsInstrFPU.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170061 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 625cb5ac72f1e23e1dfbb9600a5183a9a072c74a |
|
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove single-precision floating point instruction from multiclass
FFR2P_M.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 6085780a91c722839b3f9f2dca33b974a083df82 |
|
13-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Remove single-precision floating point instructions from multiclasses
FFR1_W_M and FFR1P_M. The new instruction definitions have one-to-one
correspondence with the instructions in the ISA manual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 249330eadb9d1d4835d6b55146147840492e5d13 |
|
07-Dec-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Shorten predicate name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| de3322746280b957d552cc5e69e121b38c07406c |
|
06-Oct-2012 |
Jack Carter <jcarter@mips.com> |
Adding support for instructions mfc0, mfc2, mtc0, mtc2
move from and to coprocessors 0 and 2.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165351 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 9d577c861414c28967d77c2a1edf64b68efdeaee |
|
04-Oct-2012 |
Jack Carter <jcarter@mips.com> |
Implement methods that enable expansion of load immediate
macro instruction (li) in the assembler.
We have identified three possible expansions depending on
the size of immediate operand:
1) for 0 ≤ j ≤ 65535.
li d,j =>
ori d,$zero,j
2) for −32768 ≤ j < 0.
li d,j =>
addiu d,$zero,j
3) for any other value of j that is representable as a 32-bit integer.
li d,j =>
lui d,hi16(j)
ori d,d,lo16(j)
All of the above have been implemented in ths patch.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 603f69dc2c69ac3f4040e125febd3925dec2bcb2 |
|
31-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Define ADJCALLSTACKDOWN/UP nodes. These nodes are emitted regardless of whether
or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and
PseudoSE (mips32/64 pseudo) classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161071 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| c4388d41994dc7e4492392f0c57c7b281ff165e6 |
|
31-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Change name of class MipsInst to InstSE to distinguish it from mips16's
instruction class. SE stands for standard encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161069 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 18f3c7809292fe6ebdce47d551f23d6ee216023f |
|
22-May-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
This patch adds a predicate to existing mips32 and mips64 so that those
instruction encodings can be excluded during mips16 processing.
This revision fixes the issue raised by Jim Grosbach.
bool hasStandardEncoding() const { return !inMips16Mode(); }
When micromips is added it will be
bool StandardEncoding() const { return !inMips16Mode()&& !inMicroMipsMode(); }
No additional testing is needed other than to assure that there is no regression
from this patch.
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157234 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| ecdc9d5bb26936a68060f1238abc6c1d6b3c2a01 |
|
17-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add disassembler to MIPS.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 02365945a62f368c18547da57a4ef3382beb89d0 |
|
03-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Revert r153924. There were buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 885020a7a7299c0cfc12f691bc298e0f41d02190 |
|
03-Apr-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
MIPS disassembler support.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153924 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| dfa27aea12ae1d69a7e94ed5e6df6be1cc90d9e3 |
|
01-Mar-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix bugs which were introduced when support for base+index floating point loads
and stores was added.
- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| bb481f882093fb738d2bb15610c79364bada5496 |
|
28-Feb-2012 |
Jia Liu <proljc@gmail.com> |
remove blanks, and some code format
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 44b6c715ac87505f98066fa3bf6e3e99a26b886a |
|
28-Feb-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add support for floating point base register + offset register addressing mode
load and store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| e4ea2418531379de98ceb60301caf2be14cbe701 |
|
25-Feb-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of floating point multiply add/sub and negative multiply
add/sub instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| ff452f53498229668af8e7476efc151c5a227be5 |
|
06-Dec-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145912 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| c3f16b316a7a15ee3bd32b4eb5753595cdce2757 |
|
18-Oct-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Final patch that completes old JIT support for Mips:
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.
Patch by Sasa Stankovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142378 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 8f3af87e99b9556224480f1aa18d340fb343bbf6 |
|
17-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Move class and instruction definitions for conditional moves to a seperate file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142220 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 3e3427a5c3fe8303723129207ce1864bee8fa481 |
|
11-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add support for conditional branch instructions with 64-bit register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141694 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| c9289f6a71017171c7d7c686379a4767903b3c3a |
|
08-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Define classes and multiclasses for FP binary instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141475 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| a8de1c1be01fd32b16f018e3e9f55c90edc9d862 |
|
08-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Define classes for FP unary instructions and multiclasses for FP-to-fixed point
conversion instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141473 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 854222fa47de9b8ba7bdb74669f1d827e9782a9f |
|
27-Sep-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Mark MipsPseudo isPseudo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140598 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 667645f814523a65cb4c775b06b97234a7b002d7 |
|
18-Aug-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Changed definition of EXT and INS per Bruno's comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137892 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| bb15e117d328bd991b0723dd1b586c8437d9dced |
|
17-Aug-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Add support for ext and ins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137804 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 49ac3d7da9cb058557ba1c9076d1aab33d8645ba |
|
09-May-2011 |
Eric Christopher <echristo@apple.com> |
Fix td file comments for Mips.
Patch by Liu <proljc@gmail.com>!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131086 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 4552c9a3b34ad9b2085635266348d0d9b95514a6 |
|
15-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129612 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 0bf3dfbef60e36827df9c7e12b62503f1e345cd0 |
|
15-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 1d6b38d9d37d5de471f5954b23b46dac58136fec |
|
31-Mar-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128650 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 81092dc20abe5253a5b4d48a75997baa84dde196 |
|
04-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127003 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 23e70ebf352ff4938210711464c68b5a6e46e61c |
|
17-Aug-2010 |
Chris Lattner <sabre@nondot.org> |
fix emacs language spec's, patch by Edmund Grimley-Evans!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 7b76da145be2b3b7518ca42b43a903eabd52e1b7 |
|
09-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fixe typos and 80 column size problems
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 225ca9cdd70de3d12641b0aba7daf6cb568a7ebd |
|
05-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| e90ea5e81fb09663f8589b638998ef3a3cb16953 |
|
08-Jun-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added FP instruction formats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52086 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 07cec75913b74d04df40ff7fecf51f87175076c1 |
|
06-Jun-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added custom SELECT_CC lowering
Added special isel for ADDE,SUBE and new patterns to match SUBC,ADDC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52031 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| e78080c4dc1942fe8e2a1f28a280903868282e48 |
|
09-Oct-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Position Independent Code (PIC) support [1]
- Modified instruction format to handle pseudo instructions
- Added LoadAddr SDNode to load symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42778 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| edeede2bb5fa002116a840453bf748cec1c107c7 |
|
21-Aug-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Instruction Itinerary attribution fixed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| e88c36819e7bece82f38176eb464678ab6099794 |
|
18-Aug-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added InstrItinClass support for instruction formats
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41156 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 64d80e3387f328d21cd9cc06464b5de7861e3f27 |
|
19-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|
| 972f5896e417d8e81cf400083fab15a37b6d4277 |
|
06-Jun-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Initial Mips support, here we go! =)
- Modifications from the last patch included
(issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrFormats.td
|