MipsInstrFormats.td revision 8e719fac46c3c79dedfde86bf439819444223537 
1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11//  Describe MIPS instructions format
12//
13//  CPU INSTRUCTION FORMATS
14//
15//  opcode  - operation code.
16//  rs      - src reg.
17//  rt      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18//  rd      - dst reg, only used on 3 regs instr.
19//  shamt   - only used on shift instructions, contains the shift amount.
20//  funct   - combined with opcode field give us an operation code.
21//
22//===----------------------------------------------------------------------===//
23
24// Format specifies the encoding used by the instruction.  This is part of the
25// ad-hoc solution used to emit machine instruction encodings by our machine
26// code emitter.
27class Format<bits<4> val> {
28  bits<4> Value = val;
29}
30
31def Pseudo    : Format<0>;
32def FrmR      : Format<1>;
33def FrmI      : Format<2>;
34def FrmJ      : Format<3>;
35def FrmFR     : Format<4>;
36def FrmFI     : Format<5>;
37def FrmOther  : Format<6>; // Instruction w/ a custom format
38
39// Generic Mips Format
40class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
41               InstrItinClass itin, Format f>: Instruction
42{
43  field bits<32> Inst;
44  Format Form = f;
45
46  let Namespace = "Mips";
47
48  let Size = 4;
49
50  bits<6> Opcode = 0;
51
52  // Top 6 bits are the 'opcode' field
53  let Inst{31-26} = Opcode;
54
55  let OutOperandList = outs;
56  let InOperandList  = ins;
57
58  let AsmString   = asmstr;
59  let Pattern     = pattern;
60  let Itinerary   = itin;
61
62  //
63  // Attributes specific to Mips instructions...
64  //
65  bits<4> FormBits = Form.Value;
66
67  // TSFlags layout should be kept in sync with MipsInstrInfo.h.
68  let TSFlags{3-0}   = FormBits;
69
70  let DecoderNamespace = "Mips";
71
72  field bits<32> SoftFail = 0;
73}
74
75// Mips32/64 Instruction Format
76class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
77             InstrItinClass itin, Format f>:
78  MipsInst<outs, ins, asmstr, pattern, itin, f> {
79  let Predicates = [HasStdEnc];
80}
81
82// Mips Pseudo Instructions Format
83class MipsPseudo<dag outs, dag ins, list<dag> pattern,
84                 InstrItinClass itin = IIPseudo> :
85  MipsInst<outs, ins, "", pattern, itin, Pseudo> {
86  let isCodeGenOnly = 1;
87  let isPseudo = 1;
88}
89
90// Mips32/64 Pseudo Instruction Format
91class PseudoSE<dag outs, dag ins, list<dag> pattern,
92               InstrItinClass itin = IIPseudo>:
93  MipsPseudo<outs, ins, pattern, itin> {
94  let Predicates = [HasStdEnc];
95}
96
97// Pseudo-instructions for alternate assembly syntax (never used by codegen).
98// These are aliases that require C++ handling to convert to the target
99// instruction, while InstAliases can be handled directly by tblgen.
100class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
101  MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
102  let isPseudo = 1;
103  let Pattern = [];
104}
105//===----------------------------------------------------------------------===//
106// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
107//===----------------------------------------------------------------------===//
108
109class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
110         list<dag> pattern, InstrItinClass itin>:
111  InstSE<outs, ins, asmstr, pattern, itin, FrmR>
112{
113  bits<5>  rd;
114  bits<5>  rs;
115  bits<5>  rt;
116  bits<5>  shamt;
117  bits<6>  funct;
118
119  let Opcode = op;
120  let funct  = _funct;
121
122  let Inst{25-21} = rs;
123  let Inst{20-16} = rt;
124  let Inst{15-11} = rd;
125  let Inst{10-6}  = shamt;
126  let Inst{5-0}   = funct;
127}
128
129//===----------------------------------------------------------------------===//
130// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
131//===----------------------------------------------------------------------===//
132
133class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
134         InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
135{
136  bits<5>  rt;
137  bits<5>  rs;
138  bits<16> imm16;
139
140  let Opcode = op;
141
142  let Inst{25-21} = rs;
143  let Inst{20-16} = rt;
144  let Inst{15-0}  = imm16;
145}
146
147class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
148                  list<dag> pattern, InstrItinClass itin>:
149  InstSE<outs, ins, asmstr, pattern, itin, FrmI>
150{
151  bits<5>  rs;
152  bits<5>  rt;
153  bits<16> imm16;
154
155  let Opcode = op;
156
157  let Inst{25-21} = rs;
158  let Inst{20-16} = rt;
159  let Inst{15-0}  = imm16;
160}
161
162//===----------------------------------------------------------------------===//
163// Format J instruction class in Mips : <|opcode|address|>
164//===----------------------------------------------------------------------===//
165
166class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
167         InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmJ>
168{
169  bits<26> addr;
170
171  let Opcode = op;
172
173  let Inst{25-0} = addr;
174}
175
176 //===----------------------------------------------------------------------===//
177// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
178//===----------------------------------------------------------------------===//
179class MFC3OP<bits<6> op, bits<5> _mfmt, dag outs, dag ins, string asmstr>:
180  InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>
181{
182  bits<5> mfmt;
183  bits<5> rt;
184  bits<5> rd;
185  bits<3> sel;
186
187  let Opcode = op;
188  let mfmt = _mfmt;
189
190  let Inst{25-21} = mfmt;
191  let Inst{20-16} = rt;
192  let Inst{15-11} = rd;
193  let Inst{10-3}  = 0;
194  let Inst{2-0}   = sel;
195}
196
197class ADD_FM<bits<6> op, bits<6> funct> {
198  bits<5> rd;
199  bits<5> rs;
200  bits<5> rt;
201
202  bits<32> Inst;
203
204  let Inst{31-26} = op;
205  let Inst{25-21} = rs;
206  let Inst{20-16} = rt;
207  let Inst{15-11} = rd;
208  let Inst{10-6}  = 0;
209  let Inst{5-0}   = funct;
210}
211
212class ADDI_FM<bits<6> op> {
213  bits<5>  rs;
214  bits<5>  rt;
215  bits<16> imm16;
216
217  bits<32> Inst;
218
219  let Inst{31-26} = op;
220  let Inst{25-21} = rs;
221  let Inst{20-16} = rt;
222  let Inst{15-0}  = imm16;
223}
224
225class SRA_FM<bits<6> funct, bit rotate> {
226  bits<5> rd;
227  bits<5> rt;
228  bits<5> shamt;
229
230  bits<32> Inst;
231
232  let Inst{31-26} = 0;
233  let Inst{25-22} = 0;
234  let Inst{21}    = rotate;
235  let Inst{20-16} = rt;
236  let Inst{15-11} = rd;
237  let Inst{10-6}  = shamt;
238  let Inst{5-0}   = funct;
239}
240
241class SRLV_FM<bits<6> funct, bit rotate> {
242  bits<5> rd;
243  bits<5> rt;
244  bits<5> rs;
245
246  bits<32> Inst;
247
248  let Inst{31-26} = 0;
249  let Inst{25-21} = rs;
250  let Inst{20-16} = rt;
251  let Inst{15-11} = rd;
252  let Inst{10-7}  = 0;
253  let Inst{6}     = rotate;
254  let Inst{5-0}   = funct;
255}
256
257class BEQ_FM<bits<6> op> {
258  bits<5>  rs;
259  bits<5>  rt;
260  bits<16> offset;
261
262  bits<32> Inst;
263
264  let Inst{31-26} = op;
265  let Inst{25-21} = rs;
266  let Inst{20-16} = rt;
267  let Inst{15-0}  = offset;
268}
269
270class BGEZ_FM<bits<6> op, bits<5> funct> {
271  bits<5>  rs;
272  bits<16> offset;
273
274  bits<32> Inst;
275
276  let Inst{31-26} = op;
277  let Inst{25-21} = rs;
278  let Inst{20-16} = funct;
279  let Inst{15-0}  = offset;
280}
281
282class B_FM {
283  bits<16> offset;
284
285  bits<32> Inst;
286
287  let Inst{31-26} = 4;
288  let Inst{25-21} = 0;
289  let Inst{20-16} = 0;
290  let Inst{15-0}  = offset;
291}
292
293class SLTI_FM<bits<6> op> {
294  bits<5> rt;
295  bits<5> rs;
296  bits<16> imm16;
297
298  bits<32> Inst;
299
300  let Inst{31-26} = op;
301  let Inst{25-21} = rs;
302  let Inst{20-16} = rt;
303  let Inst{15-0}  = imm16;
304}
305
306class MFLO_FM<bits<6> funct> {
307  bits<5> rd;
308
309  bits<32> Inst;
310
311  let Inst{31-26} = 0;
312  let Inst{25-16} = 0;
313  let Inst{15-11} = rd;
314  let Inst{10-6}  = 0;
315  let Inst{5-0}   = funct;
316}
317
318class MTLO_FM<bits<6> funct> {
319  bits<5> rs;
320
321  bits<32> Inst;
322
323  let Inst{31-26} = 0;
324  let Inst{25-21} = rs;
325  let Inst{20-6}  = 0;
326  let Inst{5-0}   = funct;
327}
328
329class SEB_FM<bits<5> funct> {
330  bits<5> rd;
331  bits<5> rt;
332
333  bits<32> Inst;
334
335  let Inst{31-26} = 0x1f;
336  let Inst{25-21} = 0;
337  let Inst{20-16} = rt;
338  let Inst{15-11} = rd;
339  let Inst{10-6}  = funct;
340  let Inst{5-0}   = 0x20;
341}
342
343class CLO_FM<bits<6> funct> {
344  bits<5> rd;
345  bits<5> rs;
346  bits<5> rt;
347
348  bits<32> Inst;
349
350  let Inst{31-26} = 0x1c;
351  let Inst{25-21} = rs;
352  let Inst{20-16} = rt;
353  let Inst{15-11} = rd;
354  let Inst{10-6}  = 0;
355  let Inst{5-0}   = funct;
356  let rt = rd;
357}
358
359class LUI_FM {
360  bits<5> rt;
361  bits<16> imm16;
362
363  bits<32> Inst;
364
365  let Inst{31-26} = 0xf;
366  let Inst{25-21} = 0;
367  let Inst{20-16} = rt;
368  let Inst{15-0}  = imm16;
369}
370
371//===----------------------------------------------------------------------===//
372//
373//  FLOATING POINT INSTRUCTION FORMATS
374//
375//  opcode  - operation code.
376//  fs      - src reg.
377//  ft      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
378//  fd      - dst reg, only used on 3 regs instr.
379//  fmt     - double or single precision.
380//  funct   - combined with opcode field give us an operation code.
381//
382//===----------------------------------------------------------------------===//
383
384//===----------------------------------------------------------------------===//
385// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
386//===----------------------------------------------------------------------===//
387
388class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
389  InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
390{
391  bits<5>  ft;
392  bits<5>  base;
393  bits<16> imm16;
394
395  let Opcode = op;
396
397  let Inst{25-21} = base;
398  let Inst{20-16} = ft;
399  let Inst{15-0}  = imm16;
400}
401
402class ADDS_FM<bits<6> funct, bits<5> fmt> {
403  bits<5> fd;
404  bits<5> fs;
405  bits<5> ft;
406
407  bits<32> Inst;
408
409  let Inst{31-26} = 0x11;
410  let Inst{25-21} = fmt;
411  let Inst{20-16} = ft;
412  let Inst{15-11} = fs;
413  let Inst{10-6}  = fd;
414  let Inst{5-0}   = funct;
415}
416
417class ABSS_FM<bits<6> funct, bits<5> fmt> {
418  bits<5> fd;
419  bits<5> fs;
420
421  bits<32> Inst;
422
423  let Inst{31-26} = 0x11;
424  let Inst{25-21} = fmt;
425  let Inst{20-16} = 0;
426  let Inst{15-11} = fs;
427  let Inst{10-6}  = fd;
428  let Inst{5-0}   = funct;
429}
430
431class MFC1_FM<bits<5> funct> {
432  bits<5> rt;
433  bits<5> fs;
434
435  bits<32> Inst;
436
437  let Inst{31-26} = 0x11;
438  let Inst{25-21} = funct;
439  let Inst{20-16} = rt;
440  let Inst{15-11} = fs;
441  let Inst{10-0}  = 0;
442}
443
444class LW_FM<bits<6> op> {
445  bits<5> rt;
446  bits<21> addr;
447
448  bits<32> Inst;
449
450  let Inst{31-26} = op;
451  let Inst{25-21} = addr{20-16};
452  let Inst{20-16} = rt;
453  let Inst{15-0}  = addr{15-0};
454}
455
456class MADDS_FM<bits<3> funct, bits<3> fmt> {
457  bits<5> fd;
458  bits<5> fr;
459  bits<5> fs;
460  bits<5> ft;
461
462  bits<32> Inst;
463
464  let Inst{31-26} = 0x13;
465  let Inst{25-21} = fr;
466  let Inst{20-16} = ft;
467  let Inst{15-11} = fs;
468  let Inst{10-6}  = fd;
469  let Inst{5-3}   = funct;
470  let Inst{2-0}   = fmt;
471}
472
473class LWXC1_FM<bits<6> funct> {
474  bits<5> fd;
475  bits<5> base;
476  bits<5> index;
477
478  bits<32> Inst;
479
480  let Inst{31-26} = 0x13;
481  let Inst{25-21} = base;
482  let Inst{20-16} = index;
483  let Inst{15-11} = 0;
484  let Inst{10-6}  = fd;
485  let Inst{5-0}   = funct;
486}
487
488class SWXC1_FM<bits<6> funct> {
489  bits<5> fs;
490  bits<5> base;
491  bits<5> index;
492
493  bits<32> Inst;
494
495  let Inst{31-26} = 0x13;
496  let Inst{25-21} = base;
497  let Inst{20-16} = index;
498  let Inst{15-11} = fs;
499  let Inst{10-6}  = 0;
500  let Inst{5-0}   = funct;
501}
502
503class BC1F_FM<bit nd, bit tf> {
504  bits<16> offset;
505
506  bits<32> Inst;
507
508  let Inst{31-26} = 0x11;
509  let Inst{25-21} = 0x8;
510  let Inst{20-18} = 0; // cc
511  let Inst{17} = nd;
512  let Inst{16} = tf;
513  let Inst{15-0} = offset;
514}
515
516class CEQS_FM<bits<5> fmt> {
517  bits<5> fs;
518  bits<5> ft;
519  bits<4> cond;
520
521  bits<32> Inst;
522
523  let Inst{31-26} = 0x11;
524  let Inst{25-21} = fmt;
525  let Inst{20-16} = ft;
526  let Inst{15-11} = fs;
527  let Inst{10-8} = 0; // cc
528  let Inst{7-4} = 0x3;
529  let Inst{3-0} = cond;
530}
531
532class CMov_I_F_FM<bits<6> funct, bits<5> fmt> {
533  bits<5> fd;
534  bits<5> fs;
535  bits<5> rt;
536
537  bits<32> Inst;
538
539  let Inst{31-26} = 0x11;
540  let Inst{25-21} = fmt;
541  let Inst{20-16} = rt;
542  let Inst{15-11} = fs;
543  let Inst{10-6} = fd;
544  let Inst{5-0} = funct;
545}
546
547class CMov_F_I_FM<bit tf> {
548  bits<5> rd;
549  bits<5> rs;
550
551  bits<32> Inst;
552
553  let Inst{31-26} = 0;
554  let Inst{25-21} = rs;
555  let Inst{20-18} = 0; // cc
556  let Inst{17} = 0;
557  let Inst{16} = tf;
558  let Inst{15-11} = rd;
559  let Inst{10-6} = 0;
560  let Inst{5-0} = 1;
561}
562
563class CMov_F_F_FM<bits<5> fmt, bit tf> {
564  bits<5> fd;
565  bits<5> fs;
566
567  bits<32> Inst;
568
569  let Inst{31-26} = 0x11;
570  let Inst{25-21} = fmt;
571  let Inst{20-18} = 0; // cc
572  let Inst{17} = 0;
573  let Inst{16} = tf;
574  let Inst{15-11} = fs;
575  let Inst{10-6} = fd;
576  let Inst{5-0} = 0x11;
577}
578