MipsInstrFormats.td revision a8de1c1be01fd32b16f018e3e9f55c90edc9d862 
1//===- MipsInstrFormats.td - Mips Instruction Formats ------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11//  Describe MIPS instructions format
12//
13//  CPU INSTRUCTION FORMATS
14//
15//  opcode  - operation code.
16//  rs      - src reg.
17//  rt      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18//  rd      - dst reg, only used on 3 regs instr.
19//  shamt   - only used on shift instructions, contains the shift amount.
20//  funct   - combined with opcode field give us an operation code.
21//
22//===----------------------------------------------------------------------===//
23
24// Generic Mips Format
25class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
26               InstrItinClass itin>: Instruction
27{
28  field bits<32> Inst;
29
30  let Namespace = "Mips";
31
32  bits<6> opcode;
33
34  // Top 5 bits are the 'opcode' field
35  let Inst{31-26} = opcode;
36
37  dag OutOperandList = outs;
38  dag InOperandList  = ins;
39
40  let AsmString   = asmstr;
41  let Pattern     = pattern;
42  let Itinerary   = itin;
43}
44
45// Mips Pseudo Instructions Format
46class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
47      MipsInst<outs, ins, asmstr, pattern, IIPseudo> {
48  let isPseudo = 1;
49}
50
51//===----------------------------------------------------------------------===//
52// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
53//===----------------------------------------------------------------------===//
54
55class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
56         list<dag> pattern, InstrItinClass itin>:
57      MipsInst<outs, ins, asmstr, pattern, itin>
58{
59  bits<5>  rd;
60  bits<5>  rs;
61  bits<5>  rt;
62  bits<5>  shamt;
63  bits<6>  funct;
64
65  let opcode = op;
66  let funct  = _funct;
67
68  let Inst{25-21} = rs;
69  let Inst{20-16} = rt;
70  let Inst{15-11} = rd;
71  let Inst{10-6}  = shamt;
72  let Inst{5-0}   = funct;
73}
74
75//===----------------------------------------------------------------------===//
76// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
77//===----------------------------------------------------------------------===//
78
79class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
80         InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin>
81{
82  bits<5>  rt;
83  bits<5>  rs;
84  bits<16> imm16;
85
86  let opcode = op;
87
88  let Inst{25-21} = rs;
89  let Inst{20-16} = rt;
90  let Inst{15-0}  = imm16;
91}
92
93//===----------------------------------------------------------------------===//
94// Format J instruction class in Mips : <|opcode|address|>
95//===----------------------------------------------------------------------===//
96
97class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
98         InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin>
99{
100  bits<26> addr;
101
102  let opcode = op;
103
104  let Inst{25-0} = addr;
105}
106
107//===----------------------------------------------------------------------===//
108//
109//  FLOATING POINT INSTRUCTION FORMATS
110//
111//  opcode  - operation code.
112//  fs      - src reg.
113//  ft      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
114//  fd      - dst reg, only used on 3 regs instr.
115//  fmt     - double or single precision.
116//  funct   - combined with opcode field give us an operation code.
117//
118//===----------------------------------------------------------------------===//
119
120//===----------------------------------------------------------------------===//
121// Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|>
122//===----------------------------------------------------------------------===//
123
124class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
125          string asmstr, list<dag> pattern> :
126          MipsInst<outs, ins, asmstr, pattern, NoItinerary>
127{
128  bits<5>  fd;
129  bits<5>  fs;
130  bits<5>  ft;
131  bits<5>  fmt;
132  bits<6>  funct;
133
134  let opcode = op;
135  let funct  = _funct;
136  let fmt    = _fmt;
137
138  let Inst{25-21} = fmt;
139  let Inst{20-16} = ft;
140  let Inst{15-11} = fs;
141  let Inst{10-6}  = fd;
142  let Inst{5-0}   = funct;
143}
144
145//===----------------------------------------------------------------------===//
146// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
147//===----------------------------------------------------------------------===//
148
149class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
150          MipsInst<outs, ins, asmstr, pattern, NoItinerary>
151{
152  bits<5>  ft;
153  bits<5>  base;
154  bits<16> imm16;
155
156  let opcode = op;
157
158  let Inst{25-21} = base;
159  let Inst{20-16} = ft;
160  let Inst{15-0}  = imm16;
161}
162
163//===----------------------------------------------------------------------===//
164// Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|>
165//===----------------------------------------------------------------------===//
166
167class FCC<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern> :
168          MipsInst<outs, ins, asmstr, pattern, NoItinerary>
169{
170  bits<5>  fs;
171  bits<5>  ft;
172  bits<4>  cc;
173  bits<5>  fmt;
174
175  let opcode = 0x11;
176  let fmt    = _fmt;
177
178  let Inst{25-21} = fmt;
179  let Inst{20-16} = ft;
180  let Inst{15-11} = fs;
181  let Inst{10-6}  = 0;
182  let Inst{5-4}   = 0b11;
183  let Inst{3-0}   = cc;
184}
185
186
187class FCMOV<bits<1> _tf, dag outs, dag ins, string asmstr,
188            list<dag> pattern> :
189  MipsInst<outs, ins, asmstr, pattern, NoItinerary>
190{
191  bits<5>  rd;
192  bits<5>  rs;
193  bits<3>  N;
194  bits<1>  tf;
195
196  let opcode = 0;
197  let tf = _tf;
198
199  let Inst{25-21} = rs;
200  let Inst{20-18} = N;
201  let Inst{17} = 0;
202  let Inst{16} = tf;
203  let Inst{15-11} = rd;
204  let Inst{10-6}  = 0;
205  let Inst{5-0}   = 1;
206}
207
208class FFCMOV<bits<5> _fmt, bits<1> _tf, dag outs, dag ins, string asmstr,
209             list<dag> pattern> :
210  MipsInst<outs, ins, asmstr, pattern, NoItinerary>
211{
212  bits<5>  fd;
213  bits<5>  fs;
214  bits<3>  N;
215  bits<5>  fmt;
216  bits<1>  tf;
217
218  let opcode = 17;
219  let fmt = _fmt;
220  let tf = _tf;
221
222  let Inst{25-21} = fmt;
223  let Inst{20-18} = N;
224  let Inst{17} = 0;
225  let Inst{16} = tf;
226  let Inst{15-11} = fs;
227  let Inst{10-6}  = fd;
228  let Inst{5-0}   = 17;
229}
230
231// FP unary instructions without patterns.
232class FFR1<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
233           RegisterClass DstRC, RegisterClass SrcRC> :
234  FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
235      !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), []> {
236  let ft = 0;
237}
238
239// FP unary instructions with patterns.
240class FFR1P<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
241            RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> :
242  FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
243      !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"),
244      [(set DstRC:$fd, (OpNode SrcRC:$fs))]> {
245  let ft = 0;
246}
247
248