MipsInstrFormats.td revision 80bec28b6645676a7cd9408d780b4c805774ef42 
1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11//  Describe MIPS instructions format
12//
13//  CPU INSTRUCTION FORMATS
14//
15//  opcode  - operation code.
16//  rs      - src reg.
17//  rt      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18//  rd      - dst reg, only used on 3 regs instr.
19//  shamt   - only used on shift instructions, contains the shift amount.
20//  funct   - combined with opcode field give us an operation code.
21//
22//===----------------------------------------------------------------------===//
23
24// Format specifies the encoding used by the instruction.  This is part of the
25// ad-hoc solution used to emit machine instruction encodings by our machine
26// code emitter.
27class Format<bits<4> val> {
28  bits<4> Value = val;
29}
30
31def Pseudo    : Format<0>;
32def FrmR      : Format<1>;
33def FrmI      : Format<2>;
34def FrmJ      : Format<3>;
35def FrmFR     : Format<4>;
36def FrmFI     : Format<5>;
37def FrmOther  : Format<6>; // Instruction w/ a custom format
38
39class MMRel;
40
41def Std2MicroMips : InstrMapping {
42  let FilterClass = "MMRel";
43  // Instructions with the same BaseOpcode and isNVStore values form a row.
44  let RowFields = ["BaseOpcode"];
45  // Instructions with the same predicate sense form a column.
46  let ColFields = ["Arch"];
47  // The key column is the unpredicated instructions.
48  let KeyCol = ["se"];
49  // Value columns are PredSense=true and PredSense=false
50  let ValueCols = [["se"], ["micromips"]];
51}
52
53class StdArch {
54  string Arch = "se";
55}
56
57// Generic Mips Format
58class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
59               InstrItinClass itin, Format f>: Instruction
60{
61  field bits<32> Inst;
62  Format Form = f;
63
64  let Namespace = "Mips";
65
66  let Size = 4;
67
68  bits<6> Opcode = 0;
69
70  // Top 6 bits are the 'opcode' field
71  let Inst{31-26} = Opcode;
72
73  let OutOperandList = outs;
74  let InOperandList  = ins;
75
76  let AsmString   = asmstr;
77  let Pattern     = pattern;
78  let Itinerary   = itin;
79
80  //
81  // Attributes specific to Mips instructions...
82  //
83  bits<4> FormBits = Form.Value;
84
85  // TSFlags layout should be kept in sync with MipsInstrInfo.h.
86  let TSFlags{3-0}   = FormBits;
87
88  let DecoderNamespace = "Mips";
89
90  field bits<32> SoftFail = 0;
91}
92
93// Mips32/64 Instruction Format
94class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
95             InstrItinClass itin, Format f, string opstr = ""> :
96  MipsInst<outs, ins, asmstr, pattern, itin, f> {
97  let Predicates = [HasStdEnc];
98  string BaseOpcode = opstr;
99  string Arch;
100  let MnemonicContainsDot = 1;
101}
102
103// Mips Pseudo Instructions Format
104class MipsPseudo<dag outs, dag ins, list<dag> pattern,
105                 InstrItinClass itin = IIPseudo> :
106  MipsInst<outs, ins, "", pattern, itin, Pseudo> {
107  let isCodeGenOnly = 1;
108  let isPseudo = 1;
109}
110
111// Mips32/64 Pseudo Instruction Format
112class PseudoSE<dag outs, dag ins, list<dag> pattern,
113               InstrItinClass itin = IIPseudo>:
114  MipsPseudo<outs, ins, pattern, itin> {
115  let Predicates = [HasStdEnc];
116}
117
118// Pseudo-instructions for alternate assembly syntax (never used by codegen).
119// These are aliases that require C++ handling to convert to the target
120// instruction, while InstAliases can be handled directly by tblgen.
121class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
122  MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
123  let isPseudo = 1;
124  let Pattern = [];
125}
126//===----------------------------------------------------------------------===//
127// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
128//===----------------------------------------------------------------------===//
129
130class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
131         list<dag> pattern, InstrItinClass itin>:
132  InstSE<outs, ins, asmstr, pattern, itin, FrmR>
133{
134  bits<5>  rd;
135  bits<5>  rs;
136  bits<5>  rt;
137  bits<5>  shamt;
138  bits<6>  funct;
139
140  let Opcode = op;
141  let funct  = _funct;
142
143  let Inst{25-21} = rs;
144  let Inst{20-16} = rt;
145  let Inst{15-11} = rd;
146  let Inst{10-6}  = shamt;
147  let Inst{5-0}   = funct;
148}
149
150//===----------------------------------------------------------------------===//
151// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
152//===----------------------------------------------------------------------===//
153
154class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
155         InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
156{
157  bits<5>  rt;
158  bits<5>  rs;
159  bits<16> imm16;
160
161  let Opcode = op;
162
163  let Inst{25-21} = rs;
164  let Inst{20-16} = rt;
165  let Inst{15-0}  = imm16;
166}
167
168class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
169                  list<dag> pattern, InstrItinClass itin>:
170  InstSE<outs, ins, asmstr, pattern, itin, FrmI>
171{
172  bits<5>  rs;
173  bits<5>  rt;
174  bits<16> imm16;
175
176  let Opcode = op;
177
178  let Inst{25-21} = rs;
179  let Inst{20-16} = rt;
180  let Inst{15-0}  = imm16;
181}
182
183//===----------------------------------------------------------------------===//
184// Format J instruction class in Mips : <|opcode|address|>
185//===----------------------------------------------------------------------===//
186
187class FJ<bits<6> op>
188{
189  bits<26> target;
190
191  bits<32> Inst;
192
193  let Inst{31-26} = op;
194  let Inst{25-0}  = target;
195}
196
197//===----------------------------------------------------------------------===//
198// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
199//===----------------------------------------------------------------------===//
200class MFC3OP_FM<bits<6> op, bits<5> mfmt>
201{
202  bits<5> rt;
203  bits<5> rd;
204  bits<3> sel;
205
206  bits<32> Inst;
207
208  let Inst{31-26} = op;
209  let Inst{25-21} = mfmt;
210  let Inst{20-16} = rt;
211  let Inst{15-11} = rd;
212  let Inst{10-3}  = 0;
213  let Inst{2-0}   = sel;
214}
215
216class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
217  bits<5> rd;
218  bits<5> rs;
219  bits<5> rt;
220
221  bits<32> Inst;
222
223  let Inst{31-26} = op;
224  let Inst{25-21} = rs;
225  let Inst{20-16} = rt;
226  let Inst{15-11} = rd;
227  let Inst{10-6}  = 0;
228  let Inst{5-0}   = funct;
229}
230
231class ADDI_FM<bits<6> op> : StdArch {
232  bits<5>  rs;
233  bits<5>  rt;
234  bits<16> imm16;
235
236  bits<32> Inst;
237
238  let Inst{31-26} = op;
239  let Inst{25-21} = rs;
240  let Inst{20-16} = rt;
241  let Inst{15-0}  = imm16;
242}
243
244class SRA_FM<bits<6> funct, bit rotate> : StdArch {
245  bits<5> rd;
246  bits<5> rt;
247  bits<5> shamt;
248
249  bits<32> Inst;
250
251  let Inst{31-26} = 0;
252  let Inst{25-22} = 0;
253  let Inst{21}    = rotate;
254  let Inst{20-16} = rt;
255  let Inst{15-11} = rd;
256  let Inst{10-6}  = shamt;
257  let Inst{5-0}   = funct;
258}
259
260class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
261  bits<5> rd;
262  bits<5> rt;
263  bits<5> rs;
264
265  bits<32> Inst;
266
267  let Inst{31-26} = 0;
268  let Inst{25-21} = rs;
269  let Inst{20-16} = rt;
270  let Inst{15-11} = rd;
271  let Inst{10-7}  = 0;
272  let Inst{6}     = rotate;
273  let Inst{5-0}   = funct;
274}
275
276class BEQ_FM<bits<6> op> {
277  bits<5>  rs;
278  bits<5>  rt;
279  bits<16> offset;
280
281  bits<32> Inst;
282
283  let Inst{31-26} = op;
284  let Inst{25-21} = rs;
285  let Inst{20-16} = rt;
286  let Inst{15-0}  = offset;
287}
288
289class BGEZ_FM<bits<6> op, bits<5> funct> {
290  bits<5>  rs;
291  bits<16> offset;
292
293  bits<32> Inst;
294
295  let Inst{31-26} = op;
296  let Inst{25-21} = rs;
297  let Inst{20-16} = funct;
298  let Inst{15-0}  = offset;
299}
300
301class B_FM {
302  bits<16> offset;
303
304  bits<32> Inst;
305
306  let Inst{31-26} = 4;
307  let Inst{25-21} = 0;
308  let Inst{20-16} = 0;
309  let Inst{15-0}  = offset;
310}
311
312class SLTI_FM<bits<6> op> : StdArch {
313  bits<5> rt;
314  bits<5> rs;
315  bits<16> imm16;
316
317  bits<32> Inst;
318
319  let Inst{31-26} = op;
320  let Inst{25-21} = rs;
321  let Inst{20-16} = rt;
322  let Inst{15-0}  = imm16;
323}
324
325class MFLO_FM<bits<6> funct> {
326  bits<5> rd;
327
328  bits<32> Inst;
329
330  let Inst{31-26} = 0;
331  let Inst{25-16} = 0;
332  let Inst{15-11} = rd;
333  let Inst{10-6}  = 0;
334  let Inst{5-0}   = funct;
335}
336
337class MTLO_FM<bits<6> funct> {
338  bits<5> rs;
339
340  bits<32> Inst;
341
342  let Inst{31-26} = 0;
343  let Inst{25-21} = rs;
344  let Inst{20-6}  = 0;
345  let Inst{5-0}   = funct;
346}
347
348class SEB_FM<bits<5> funct, bits<6> funct2> {
349  bits<5> rd;
350  bits<5> rt;
351
352  bits<32> Inst;
353
354  let Inst{31-26} = 0x1f;
355  let Inst{25-21} = 0;
356  let Inst{20-16} = rt;
357  let Inst{15-11} = rd;
358  let Inst{10-6}  = funct;
359  let Inst{5-0}   = funct2;
360}
361
362class CLO_FM<bits<6> funct> {
363  bits<5> rd;
364  bits<5> rs;
365  bits<5> rt;
366
367  bits<32> Inst;
368
369  let Inst{31-26} = 0x1c;
370  let Inst{25-21} = rs;
371  let Inst{20-16} = rt;
372  let Inst{15-11} = rd;
373  let Inst{10-6}  = 0;
374  let Inst{5-0}   = funct;
375  let rt = rd;
376}
377
378class LUI_FM {
379  bits<5> rt;
380  bits<16> imm16;
381
382  bits<32> Inst;
383
384  let Inst{31-26} = 0xf;
385  let Inst{25-21} = 0;
386  let Inst{20-16} = rt;
387  let Inst{15-0}  = imm16;
388}
389
390class JALR_FM {
391  bits<5> rd;
392  bits<5> rs;
393
394  bits<32> Inst;
395
396  let Inst{31-26} = 0;
397  let Inst{25-21} = rs;
398  let Inst{20-16} = 0;
399  let Inst{15-11} = rd;
400  let Inst{10-6}  = 0;
401  let Inst{5-0}   = 9;
402}
403
404class BGEZAL_FM<bits<5> funct> {
405  bits<5>  rs;
406  bits<16> offset;
407
408  bits<32> Inst;
409
410  let Inst{31-26} = 1;
411  let Inst{25-21} = rs;
412  let Inst{20-16} = funct;
413  let Inst{15-0}  = offset;
414}
415
416class SYNC_FM {
417  bits<5> stype;
418
419  bits<32> Inst;
420
421  let Inst{31-26} = 0;
422  let Inst{10-6}  = stype;
423  let Inst{5-0}   = 0xf;
424}
425
426class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
427  bits<5>  rs;
428  bits<5>  rt;
429
430  bits<32> Inst;
431
432  let Inst{31-26} = op;
433  let Inst{25-21} = rs;
434  let Inst{20-16} = rt;
435  let Inst{15-6}  = 0;
436  let Inst{5-0}   = funct;
437}
438
439class EXT_FM<bits<6> funct> {
440  bits<5> rt;
441  bits<5> rs;
442  bits<5> pos;
443  bits<5> size;
444
445  bits<32> Inst;
446
447  let Inst{31-26} = 0x1f;
448  let Inst{25-21} = rs;
449  let Inst{20-16} = rt;
450  let Inst{15-11} = size;
451  let Inst{10-6}  = pos;
452  let Inst{5-0}   = funct;
453}
454
455class RDHWR_FM {
456  bits<5> rt;
457  bits<5> rd;
458
459  bits<32> Inst;
460
461  let Inst{31-26} = 0x1f;
462  let Inst{25-21} = 0;
463  let Inst{20-16} = rt;
464  let Inst{15-11} = rd;
465  let Inst{10-6}  = 0;
466  let Inst{5-0}   = 0x3b;
467}
468
469class TEQ_FM<bits<6> funct> {
470  bits<5> rs;
471  bits<5> rt;
472  bits<10> code_;
473
474  bits<32> Inst;
475
476  let Inst{31-26} = 0;
477  let Inst{25-21} = rs;
478  let Inst{20-16} = rt;
479  let Inst{15-6}  = code_;
480  let Inst{5-0}   = funct;
481}
482
483//===----------------------------------------------------------------------===//
484//  System calls format <op|code_|funct>
485//===----------------------------------------------------------------------===//
486
487class SYS_FM<bits<6> funct>
488{
489  bits<20> code_;
490  bits<32> Inst;
491  let Inst{31-26} = 0x0;
492  let Inst{25-6} = code_;
493  let Inst{5-0}  = funct;
494}
495
496//===----------------------------------------------------------------------===//
497//  Break instruction format <op|code_1|funct>
498//===----------------------------------------------------------------------===//
499
500class BRK_FM<bits<6> funct>
501{
502  bits<10> code_1;
503  bits<10> code_2;
504  bits<32> Inst;
505  let Inst{31-26} = 0x0;
506  let Inst{25-16} = code_1;
507  let Inst{15-6}  = code_2;
508  let Inst{5-0}   = funct;
509}
510
511//===----------------------------------------------------------------------===//
512//  Exception return format <Cop0|1|0|funct>
513//===----------------------------------------------------------------------===//
514
515class ER_FM<bits<6> funct>
516{
517  bits<32> Inst;
518  let Inst{31-26} = 0x10;
519  let Inst{25}    = 1;
520  let Inst{24-6}  = 0;
521  let Inst{5-0}   = funct;
522}
523
524//===----------------------------------------------------------------------===//
525//
526//  FLOATING POINT INSTRUCTION FORMATS
527//
528//  opcode  - operation code.
529//  fs      - src reg.
530//  ft      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
531//  fd      - dst reg, only used on 3 regs instr.
532//  fmt     - double or single precision.
533//  funct   - combined with opcode field give us an operation code.
534//
535//===----------------------------------------------------------------------===//
536
537//===----------------------------------------------------------------------===//
538// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
539//===----------------------------------------------------------------------===//
540
541class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
542  InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
543{
544  bits<5>  ft;
545  bits<5>  base;
546  bits<16> imm16;
547
548  let Opcode = op;
549
550  let Inst{25-21} = base;
551  let Inst{20-16} = ft;
552  let Inst{15-0}  = imm16;
553}
554
555class ADDS_FM<bits<6> funct, bits<5> fmt> {
556  bits<5> fd;
557  bits<5> fs;
558  bits<5> ft;
559
560  bits<32> Inst;
561
562  let Inst{31-26} = 0x11;
563  let Inst{25-21} = fmt;
564  let Inst{20-16} = ft;
565  let Inst{15-11} = fs;
566  let Inst{10-6}  = fd;
567  let Inst{5-0}   = funct;
568}
569
570class ABSS_FM<bits<6> funct, bits<5> fmt> {
571  bits<5> fd;
572  bits<5> fs;
573
574  bits<32> Inst;
575
576  let Inst{31-26} = 0x11;
577  let Inst{25-21} = fmt;
578  let Inst{20-16} = 0;
579  let Inst{15-11} = fs;
580  let Inst{10-6}  = fd;
581  let Inst{5-0}   = funct;
582}
583
584class MFC1_FM<bits<5> funct> {
585  bits<5> rt;
586  bits<5> fs;
587
588  bits<32> Inst;
589
590  let Inst{31-26} = 0x11;
591  let Inst{25-21} = funct;
592  let Inst{20-16} = rt;
593  let Inst{15-11} = fs;
594  let Inst{10-0}  = 0;
595}
596
597class LW_FM<bits<6> op> : StdArch {
598  bits<5> rt;
599  bits<21> addr;
600
601  bits<32> Inst;
602
603  let Inst{31-26} = op;
604  let Inst{25-21} = addr{20-16};
605  let Inst{20-16} = rt;
606  let Inst{15-0}  = addr{15-0};
607}
608
609class MADDS_FM<bits<3> funct, bits<3> fmt> {
610  bits<5> fd;
611  bits<5> fr;
612  bits<5> fs;
613  bits<5> ft;
614
615  bits<32> Inst;
616
617  let Inst{31-26} = 0x13;
618  let Inst{25-21} = fr;
619  let Inst{20-16} = ft;
620  let Inst{15-11} = fs;
621  let Inst{10-6}  = fd;
622  let Inst{5-3}   = funct;
623  let Inst{2-0}   = fmt;
624}
625
626class LWXC1_FM<bits<6> funct> {
627  bits<5> fd;
628  bits<5> base;
629  bits<5> index;
630
631  bits<32> Inst;
632
633  let Inst{31-26} = 0x13;
634  let Inst{25-21} = base;
635  let Inst{20-16} = index;
636  let Inst{15-11} = 0;
637  let Inst{10-6}  = fd;
638  let Inst{5-0}   = funct;
639}
640
641class SWXC1_FM<bits<6> funct> {
642  bits<5> fs;
643  bits<5> base;
644  bits<5> index;
645
646  bits<32> Inst;
647
648  let Inst{31-26} = 0x13;
649  let Inst{25-21} = base;
650  let Inst{20-16} = index;
651  let Inst{15-11} = fs;
652  let Inst{10-6}  = 0;
653  let Inst{5-0}   = funct;
654}
655
656class BC1F_FM<bit nd, bit tf> {
657  bits<3>  fcc;
658  bits<16> offset;
659
660  bits<32> Inst;
661
662  let Inst{31-26} = 0x11;
663  let Inst{25-21} = 0x8;
664  let Inst{20-18} = fcc;
665  let Inst{17} = nd;
666  let Inst{16} = tf;
667  let Inst{15-0} = offset;
668}
669
670class CEQS_FM<bits<5> fmt> {
671  bits<5> fs;
672  bits<5> ft;
673  bits<4> cond;
674
675  bits<32> Inst;
676
677  let Inst{31-26} = 0x11;
678  let Inst{25-21} = fmt;
679  let Inst{20-16} = ft;
680  let Inst{15-11} = fs;
681  let Inst{10-8} = 0; // cc
682  let Inst{7-4} = 0x3;
683  let Inst{3-0} = cond;
684}
685
686class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
687  let cond = c;
688}
689
690class CMov_I_F_FM<bits<6> funct, bits<5> fmt> {
691  bits<5> fd;
692  bits<5> fs;
693  bits<5> rt;
694
695  bits<32> Inst;
696
697  let Inst{31-26} = 0x11;
698  let Inst{25-21} = fmt;
699  let Inst{20-16} = rt;
700  let Inst{15-11} = fs;
701  let Inst{10-6} = fd;
702  let Inst{5-0} = funct;
703}
704
705class CMov_F_I_FM<bit tf> {
706  bits<5> rd;
707  bits<5> rs;
708  bits<3> fcc;
709
710  bits<32> Inst;
711
712  let Inst{31-26} = 0;
713  let Inst{25-21} = rs;
714  let Inst{20-18} = fcc;
715  let Inst{17} = 0;
716  let Inst{16} = tf;
717  let Inst{15-11} = rd;
718  let Inst{10-6} = 0;
719  let Inst{5-0} = 1;
720}
721
722class CMov_F_F_FM<bits<5> fmt, bit tf> {
723  bits<5> fd;
724  bits<5> fs;
725  bits<3> fcc;
726
727  bits<32> Inst;
728
729  let Inst{31-26} = 0x11;
730  let Inst{25-21} = fmt;
731  let Inst{20-18} = fcc;
732  let Inst{17} = 0;
733  let Inst{16} = tf;
734  let Inst{15-11} = fs;
735  let Inst{10-6} = fd;
736  let Inst{5-0} = 0x11;
737}
738