MipsInstrFormats.td revision b573539c6b47d020ade2e41c0ff3afcd00f294f4
1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Describe MIPS instructions format 12// 13// CPU INSTRUCTION FORMATS 14// 15// opcode - operation code. 16// rs - src reg. 17// rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 18// rd - dst reg, only used on 3 regs instr. 19// shamt - only used on shift instructions, contains the shift amount. 20// funct - combined with opcode field give us an operation code. 21// 22//===----------------------------------------------------------------------===// 23 24// Format specifies the encoding used by the instruction. This is part of the 25// ad-hoc solution used to emit machine instruction encodings by our machine 26// code emitter. 27class Format<bits<4> val> { 28 bits<4> Value = val; 29} 30 31def Pseudo : Format<0>; 32def FrmR : Format<1>; 33def FrmI : Format<2>; 34def FrmJ : Format<3>; 35def FrmFR : Format<4>; 36def FrmFI : Format<5>; 37def FrmOther : Format<6>; // Instruction w/ a custom format 38 39// Generic Mips Format 40class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern, 41 InstrItinClass itin, Format f>: Instruction 42{ 43 field bits<32> Inst; 44 Format Form = f; 45 46 let Namespace = "Mips"; 47 48 let Size = 4; 49 50 bits<6> Opcode = 0; 51 52 // Top 6 bits are the 'opcode' field 53 let Inst{31-26} = Opcode; 54 55 let OutOperandList = outs; 56 let InOperandList = ins; 57 58 let AsmString = asmstr; 59 let Pattern = pattern; 60 let Itinerary = itin; 61 62 // 63 // Attributes specific to Mips instructions... 64 // 65 bits<4> FormBits = Form.Value; 66 67 // TSFlags layout should be kept in sync with MipsInstrInfo.h. 68 let TSFlags{3-0} = FormBits; 69 70 let DecoderNamespace = "Mips"; 71 72 field bits<32> SoftFail = 0; 73} 74 75// Mips32/64 Instruction Format 76class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern, 77 InstrItinClass itin, Format f>: 78 MipsInst<outs, ins, asmstr, pattern, itin, f> { 79 let Predicates = [HasStdEnc]; 80} 81 82// Mips Pseudo Instructions Format 83class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>: 84 MipsInst<outs, ins, asmstr, pattern, IIPseudo, Pseudo> { 85 let isCodeGenOnly = 1; 86 let isPseudo = 1; 87} 88 89// Mips32/64 Pseudo Instruction Format 90class PseudoSE<dag outs, dag ins, string asmstr, list<dag> pattern>: 91 MipsPseudo<outs, ins, asmstr, pattern> { 92 let Predicates = [HasStdEnc]; 93} 94 95// Pseudo-instructions for alternate assembly syntax (never used by codegen). 96// These are aliases that require C++ handling to convert to the target 97// instruction, while InstAliases can be handled directly by tblgen. 98class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>: 99 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> { 100 let isPseudo = 1; 101 let Pattern = []; 102} 103//===----------------------------------------------------------------------===// 104// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> 105//===----------------------------------------------------------------------===// 106 107class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, 108 list<dag> pattern, InstrItinClass itin>: 109 InstSE<outs, ins, asmstr, pattern, itin, FrmR> 110{ 111 bits<5> rd; 112 bits<5> rs; 113 bits<5> rt; 114 bits<5> shamt; 115 bits<6> funct; 116 117 let Opcode = op; 118 let funct = _funct; 119 120 let Inst{25-21} = rs; 121 let Inst{20-16} = rt; 122 let Inst{15-11} = rd; 123 let Inst{10-6} = shamt; 124 let Inst{5-0} = funct; 125} 126 127//===----------------------------------------------------------------------===// 128// Format I instruction class in Mips : <|opcode|rs|rt|immediate|> 129//===----------------------------------------------------------------------===// 130 131class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 132 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI> 133{ 134 bits<5> rt; 135 bits<5> rs; 136 bits<16> imm16; 137 138 let Opcode = op; 139 140 let Inst{25-21} = rs; 141 let Inst{20-16} = rt; 142 let Inst{15-0} = imm16; 143} 144 145class BranchBase<bits<6> op, dag outs, dag ins, string asmstr, 146 list<dag> pattern, InstrItinClass itin>: 147 InstSE<outs, ins, asmstr, pattern, itin, FrmI> 148{ 149 bits<5> rs; 150 bits<5> rt; 151 bits<16> imm16; 152 153 let Opcode = op; 154 155 let Inst{25-21} = rs; 156 let Inst{20-16} = rt; 157 let Inst{15-0} = imm16; 158} 159 160//===----------------------------------------------------------------------===// 161// Format J instruction class in Mips : <|opcode|address|> 162//===----------------------------------------------------------------------===// 163 164class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 165 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmJ> 166{ 167 bits<26> addr; 168 169 let Opcode = op; 170 171 let Inst{25-0} = addr; 172} 173 174 //===----------------------------------------------------------------------===// 175// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|> 176//===----------------------------------------------------------------------===// 177class MFC3OP<bits<6> op, bits<5> _mfmt, dag outs, dag ins, string asmstr>: 178 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR> 179{ 180 bits<5> mfmt; 181 bits<5> rt; 182 bits<5> rd; 183 bits<3> sel; 184 185 let Opcode = op; 186 let mfmt = _mfmt; 187 188 let Inst{25-21} = mfmt; 189 let Inst{20-16} = rt; 190 let Inst{15-11} = rd; 191 let Inst{10-3} = 0; 192 let Inst{2-0} = sel; 193} 194 195//===----------------------------------------------------------------------===// 196// 197// FLOATING POINT INSTRUCTION FORMATS 198// 199// opcode - operation code. 200// fs - src reg. 201// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 202// fd - dst reg, only used on 3 regs instr. 203// fmt - double or single precision. 204// funct - combined with opcode field give us an operation code. 205// 206//===----------------------------------------------------------------------===// 207 208//===----------------------------------------------------------------------===// 209// Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|> 210//===----------------------------------------------------------------------===// 211 212class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins, 213 string asmstr, list<dag> pattern> : 214 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFR> 215{ 216 bits<5> fd; 217 bits<5> fs; 218 bits<5> ft; 219 bits<5> fmt; 220 bits<6> funct; 221 222 let Opcode = op; 223 let funct = _funct; 224 let fmt = _fmt; 225 226 let Inst{25-21} = fmt; 227 let Inst{20-16} = ft; 228 let Inst{15-11} = fs; 229 let Inst{10-6} = fd; 230 let Inst{5-0} = funct; 231} 232 233//===----------------------------------------------------------------------===// 234// Format FI instruction class in Mips : <|opcode|base|ft|immediate|> 235//===----------------------------------------------------------------------===// 236 237class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>: 238 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI> 239{ 240 bits<5> ft; 241 bits<5> base; 242 bits<16> imm16; 243 244 let Opcode = op; 245 246 let Inst{25-21} = base; 247 let Inst{20-16} = ft; 248 let Inst{15-0} = imm16; 249} 250 251//===----------------------------------------------------------------------===// 252// Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|> 253//===----------------------------------------------------------------------===// 254 255class FCC<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern> : 256 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther> 257{ 258 bits<5> fs; 259 bits<5> ft; 260 bits<4> cc; 261 bits<5> fmt; 262 263 let Opcode = 0x11; 264 let fmt = _fmt; 265 266 let Inst{25-21} = fmt; 267 let Inst{20-16} = ft; 268 let Inst{15-11} = fs; 269 let Inst{10-6} = 0; 270 let Inst{5-4} = 0b11; 271 let Inst{3-0} = cc; 272} 273 274 275class FCMOV<bits<1> _tf, dag outs, dag ins, string asmstr, 276 list<dag> pattern> : 277 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther> 278{ 279 bits<5> rd; 280 bits<5> rs; 281 bits<3> cc; 282 bits<1> tf; 283 284 let Opcode = 0; 285 let tf = _tf; 286 287 let Inst{25-21} = rs; 288 let Inst{20-18} = cc; 289 let Inst{17} = 0; 290 let Inst{16} = tf; 291 let Inst{15-11} = rd; 292 let Inst{10-6} = 0; 293 let Inst{5-0} = 1; 294} 295 296class FFCMOV<bits<5> _fmt, bits<1> _tf, dag outs, dag ins, string asmstr, 297 list<dag> pattern> : 298 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther> 299{ 300 bits<5> fd; 301 bits<5> fs; 302 bits<3> cc; 303 bits<5> fmt; 304 bits<1> tf; 305 306 let Opcode = 17; 307 let fmt = _fmt; 308 let tf = _tf; 309 310 let Inst{25-21} = fmt; 311 let Inst{20-18} = cc; 312 let Inst{17} = 0; 313 let Inst{16} = tf; 314 let Inst{15-11} = fs; 315 let Inst{10-6} = fd; 316 let Inst{5-0} = 17; 317} 318 319// Floating point madd/msub/nmadd/nmsub. 320class FFMADDSUB<bits<3> funct, bits<3> fmt, dag outs, dag ins, string asmstr, 321 list<dag> pattern> 322 : InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther> { 323 bits<5> fd; 324 bits<5> fr; 325 bits<5> fs; 326 bits<5> ft; 327 328 let Opcode = 0x13; 329 let Inst{25-21} = fr; 330 let Inst{20-16} = ft; 331 let Inst{15-11} = fs; 332 let Inst{10-6} = fd; 333 let Inst{5-3} = funct; 334 let Inst{2-0} = fmt; 335} 336 337// FP indexed load/store instructions. 338class FFMemIdx<bits<6> funct, dag outs, dag ins, string asmstr, 339 list<dag> pattern> : 340 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther> 341{ 342 bits<5> base; 343 bits<5> index; 344 bits<5> fs; 345 bits<5> fd; 346 347 let Opcode = 0x13; 348 349 let Inst{25-21} = base; 350 let Inst{20-16} = index; 351 let Inst{15-11} = fs; 352 let Inst{10-6} = fd; 353 let Inst{5-0} = funct; 354} 355 356class ADDS_FM<bits<6> funct, bits<5> fmt> { 357 bits<5> fd; 358 bits<5> fs; 359 bits<5> ft; 360 361 bits<32> Inst; 362 363 let Inst{31-26} = 0x11; 364 let Inst{25-21} = fmt; 365 let Inst{20-16} = ft; 366 let Inst{15-11} = fs; 367 let Inst{10-6} = fd; 368 let Inst{5-0} = funct; 369} 370 371class ABSS_FM<bits<6> funct, bits<5> fmt> { 372 bits<5> fd; 373 bits<5> fs; 374 375 bits<32> Inst; 376 377 let Inst{31-26} = 0x11; 378 let Inst{25-21} = fmt; 379 let Inst{20-16} = 0; 380 let Inst{15-11} = fs; 381 let Inst{10-6} = fd; 382 let Inst{5-0} = funct; 383} 384 385class MFC1_FM<bits<5> funct> { 386 bits<5> rt; 387 bits<5> fs; 388 389 bits<32> Inst; 390 391 let Inst{31-26} = 0x11; 392 let Inst{25-21} = funct; 393 let Inst{20-16} = rt; 394 let Inst{15-11} = fs; 395 let Inst{10-0} = 0; 396} 397 398class LW_FM<bits<6> op> { 399 bits<5> rt; 400 bits<21> addr; 401 402 bits<32> Inst; 403 404 let Inst{31-26} = op; 405 let Inst{25-21} = addr{20-16}; 406 let Inst{20-16} = rt; 407 let Inst{15-0} = addr{15-0}; 408} 409 410class MADDS_FM<bits<3> funct, bits<3> fmt> { 411 bits<5> fd; 412 bits<5> fr; 413 bits<5> fs; 414 bits<5> ft; 415 416 bits<32> Inst; 417 418 let Inst{31-26} = 0x13; 419 let Inst{25-21} = fr; 420 let Inst{20-16} = ft; 421 let Inst{15-11} = fs; 422 let Inst{10-6} = fd; 423 let Inst{5-3} = funct; 424 let Inst{2-0} = fmt; 425} 426 427class LWXC1_FM<bits<6> funct> { 428 bits<5> fd; 429 bits<5> base; 430 bits<5> index; 431 432 bits<32> Inst; 433 434 let Inst{31-26} = 0x13; 435 let Inst{25-21} = base; 436 let Inst{20-16} = index; 437 let Inst{15-11} = 0; 438 let Inst{10-6} = fd; 439 let Inst{5-0} = funct; 440} 441 442class SWXC1_FM<bits<6> funct> { 443 bits<5> fs; 444 bits<5> base; 445 bits<5> index; 446 447 bits<32> Inst; 448 449 let Inst{31-26} = 0x13; 450 let Inst{25-21} = base; 451 let Inst{20-16} = index; 452 let Inst{15-11} = fs; 453 let Inst{10-6} = 0; 454 let Inst{5-0} = funct; 455} 456 457class BC1F_FM<bit nd, bit tf> { 458 bits<16> offset; 459 460 bits<32> Inst; 461 462 let Inst{31-26} = 0x11; 463 let Inst{25-21} = 0x8; 464 let Inst{20-18} = 0; // cc 465 let Inst{17} = nd; 466 let Inst{16} = tf; 467 let Inst{15-0} = offset; 468} 469 470class CEQS_FM<bits<5> fmt> { 471 bits<5> fs; 472 bits<5> ft; 473 bits<4> cond; 474 475 bits<32> Inst; 476 477 let Inst{31-26} = 0x11; 478 let Inst{25-21} = fmt; 479 let Inst{20-16} = ft; 480 let Inst{15-11} = fs; 481 let Inst{10-8} = 0; // cc 482 let Inst{7-4} = 0x3; 483 let Inst{3-0} = cond; 484} 485