MipsInstrInfo.td revision 16164657d88c50be59a3fbff035ded786a98cf7f
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 37 38def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 40def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 42 SDTCisSameAs<0, 4>]>; 43 44def SDTMipsLoadLR : SDTypeProfile<1, 2, 45 [SDTCisInt<0>, SDTCisPtrTy<1>, 46 SDTCisSameAs<0, 2>]>; 47 48// Call 49def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 51 SDNPVariadic]>; 52 53// Tail call 54def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 56 57// Hi and Lo nodes are used to handle global addresses. Used on 58// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 59// static model. (nothing to do with Mips Registers Hi and Lo) 60def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 61def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 62def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 63 64// TlsGd node is used to handle General Dynamic TLS 65def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 66 67// TprelHi and TprelLo nodes are used to handle Local Exec TLS 68def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 69def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 70 71// Thread pointer 72def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 73 74// Return 75def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; 76 77// These are target-independent nodes, but have target-specific formats. 78def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 79 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 80def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 81 [SDNPHasChain, SDNPSideEffect, 82 SDNPOptInGlue, SDNPOutGlue]>; 83 84// MAdd*/MSub* nodes 85def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 86 [SDNPOptInGlue, SDNPOutGlue]>; 87def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 88 [SDNPOptInGlue, SDNPOutGlue]>; 89def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 90 [SDNPOptInGlue, SDNPOutGlue]>; 91def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 92 [SDNPOptInGlue, SDNPOutGlue]>; 93 94// DivRem(u) nodes 95def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 96 [SDNPOutGlue]>; 97def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 98 [SDNPOutGlue]>; 99 100// Target constant nodes that are not part of any isel patterns and remain 101// unchanged can cause instructions with illegal operands to be emitted. 102// Wrapper node patterns give the instruction selector a chance to replace 103// target constant nodes that would otherwise remain unchanged with ADDiu 104// nodes. Without these wrapper node patterns, the following conditional move 105// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 106// compiled: 107// movn %got(d)($gp), %got(c)($gp), $4 108// This instruction is illegal since movn can take only register operands. 109 110def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 111 112def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 113 114def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 115def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 116 117def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 118 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 119def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 121def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 122 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 123def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 125def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 127def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 129def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 131def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 133 134//===----------------------------------------------------------------------===// 135// Mips Instruction Predicate Definitions. 136//===----------------------------------------------------------------------===// 137def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 138 AssemblerPredicate<"FeatureSEInReg">; 139def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 140 AssemblerPredicate<"FeatureBitCount">; 141def HasSwap : Predicate<"Subtarget.hasSwap()">, 142 AssemblerPredicate<"FeatureSwap">; 143def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 144 AssemblerPredicate<"FeatureCondMov">; 145def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 146 AssemblerPredicate<"FeatureFPIdx">; 147def HasMips32 : Predicate<"Subtarget.hasMips32()">, 148 AssemblerPredicate<"FeatureMips32">; 149def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 150 AssemblerPredicate<"FeatureMips32r2">; 151def HasMips64 : Predicate<"Subtarget.hasMips64()">, 152 AssemblerPredicate<"FeatureMips64">; 153def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 154 AssemblerPredicate<"!FeatureMips64">; 155def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 156 AssemblerPredicate<"FeatureMips64r2">; 157def IsN64 : Predicate<"Subtarget.isABI_N64()">, 158 AssemblerPredicate<"FeatureN64">; 159def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 160 AssemblerPredicate<"!FeatureN64">; 161def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 162 AssemblerPredicate<"FeatureMips16">; 163def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 164 AssemblerPredicate<"FeatureMips32">; 165def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 166 AssemblerPredicate<"FeatureMips32">; 167def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 168 AssemblerPredicate<"FeatureMips32">; 169def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 170 AssemblerPredicate<"!FeatureMips16">; 171 172class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 173 let Predicates = [HasStdEnc]; 174} 175 176class IsCommutable { 177 bit isCommutable = 1; 178} 179 180class IsBranch { 181 bit isBranch = 1; 182} 183 184class IsReturn { 185 bit isReturn = 1; 186} 187 188class IsCall { 189 bit isCall = 1; 190} 191 192class IsTailCall { 193 bit isCall = 1; 194 bit isTerminator = 1; 195 bit isReturn = 1; 196 bit isBarrier = 1; 197 bit hasExtraSrcRegAllocReq = 1; 198 bit isCodeGenOnly = 1; 199} 200 201class IsAsCheapAsAMove { 202 bit isAsCheapAsAMove = 1; 203} 204 205class NeverHasSideEffects { 206 bit neverHasSideEffects = 1; 207} 208 209//===----------------------------------------------------------------------===// 210// Instruction format superclass 211//===----------------------------------------------------------------------===// 212 213include "MipsInstrFormats.td" 214 215//===----------------------------------------------------------------------===// 216// Mips Operand, Complex Patterns and Transformations Definitions. 217//===----------------------------------------------------------------------===// 218 219// Instruction operand types 220def jmptarget : Operand<OtherVT> { 221 let EncoderMethod = "getJumpTargetOpValue"; 222} 223def brtarget : Operand<OtherVT> { 224 let EncoderMethod = "getBranchTargetOpValue"; 225 let OperandType = "OPERAND_PCREL"; 226 let DecoderMethod = "DecodeBranchTarget"; 227} 228def calltarget : Operand<iPTR> { 229 let EncoderMethod = "getJumpTargetOpValue"; 230} 231def calltarget64: Operand<i64>; 232def simm16 : Operand<i32> { 233 let DecoderMethod= "DecodeSimm16"; 234} 235def simm16_64 : Operand<i64>; 236def shamt : Operand<i32>; 237 238// Unsigned Operand 239def uimm16 : Operand<i32> { 240 let PrintMethod = "printUnsignedImm"; 241} 242 243def MipsMemAsmOperand : AsmOperandClass { 244 let Name = "Mem"; 245 let ParserMethod = "parseMemOperand"; 246} 247 248// Address operand 249def mem : Operand<i32> { 250 let PrintMethod = "printMemOperand"; 251 let MIOperandInfo = (ops CPURegs, simm16); 252 let EncoderMethod = "getMemEncoding"; 253 let ParserMatchClass = MipsMemAsmOperand; 254} 255 256def mem64 : Operand<i64> { 257 let PrintMethod = "printMemOperand"; 258 let MIOperandInfo = (ops CPU64Regs, simm16_64); 259 let EncoderMethod = "getMemEncoding"; 260 let ParserMatchClass = MipsMemAsmOperand; 261} 262 263def mem_ea : Operand<i32> { 264 let PrintMethod = "printMemOperandEA"; 265 let MIOperandInfo = (ops CPURegs, simm16); 266 let EncoderMethod = "getMemEncoding"; 267} 268 269def mem_ea_64 : Operand<i64> { 270 let PrintMethod = "printMemOperandEA"; 271 let MIOperandInfo = (ops CPU64Regs, simm16_64); 272 let EncoderMethod = "getMemEncoding"; 273} 274 275// size operand of ext instruction 276def size_ext : Operand<i32> { 277 let EncoderMethod = "getSizeExtEncoding"; 278 let DecoderMethod = "DecodeExtSize"; 279} 280 281// size operand of ins instruction 282def size_ins : Operand<i32> { 283 let EncoderMethod = "getSizeInsEncoding"; 284 let DecoderMethod = "DecodeInsSize"; 285} 286 287// Transformation Function - get the lower 16 bits. 288def LO16 : SDNodeXForm<imm, [{ 289 return getImm(N, N->getZExtValue() & 0xFFFF); 290}]>; 291 292// Transformation Function - get the higher 16 bits. 293def HI16 : SDNodeXForm<imm, [{ 294 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 295}]>; 296 297// Node immediate fits as 16-bit sign extended on target immediate. 298// e.g. addi, andi 299def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 300 301// Node immediate fits as 15-bit sign extended on target immediate. 302// e.g. addi, andi 303def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 304 305// Node immediate fits as 16-bit zero extended on target immediate. 306// The LO16 param means that only the lower 16 bits of the node 307// immediate are caught. 308// e.g. addiu, sltiu 309def immZExt16 : PatLeaf<(imm), [{ 310 if (N->getValueType(0) == MVT::i32) 311 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 312 else 313 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 314}], LO16>; 315 316// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 317def immLow16Zero : PatLeaf<(imm), [{ 318 int64_t Val = N->getSExtValue(); 319 return isInt<32>(Val) && !(Val & 0xffff); 320}]>; 321 322// shamt field must fit in 5 bits. 323def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 324 325// Mips Address Mode! SDNode frameindex could possibily be a match 326// since load and store instructions from stack used it. 327def addr : 328 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; 329 330//===----------------------------------------------------------------------===// 331// Instructions specific format 332//===----------------------------------------------------------------------===// 333 334// Arithmetic and logical instructions with 3 register operands. 335class ArithLogicR<string opstr, RegisterClass RC, bit isComm = 0, 336 InstrItinClass Itin = NoItinerary, 337 SDPatternOperator OpNode = null_frag>: 338 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 339 !strconcat(opstr, "\t$rd, $rs, $rt"), 340 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], Itin, FrmR> { 341 let isCommutable = isComm; 342 let isReMaterializable = 1; 343} 344 345// Arithmetic and logical instructions with 2 register operands. 346class ArithLogicI<string opstr, Operand Od, RegisterClass RC, 347 SDPatternOperator imm_type = null_frag, 348 SDPatternOperator OpNode = null_frag> : 349 InstSE<(outs RC:$rt), (ins RC:$rs, Od:$imm16), 350 !strconcat(opstr, "\t$rt, $rs, $imm16"), 351 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu, FrmI> { 352 let isReMaterializable = 1; 353} 354 355// Arithmetic Multiply ADD/SUB 356let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in 357class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> : 358 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt), 359 !strconcat(instr_asm, "\t$rs, $rt"), 360 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> { 361 let rd = 0; 362 let shamt = 0; 363 let isCommutable = isComm; 364} 365 366// Logical 367class LogicNOR<string opstr, RegisterClass RC>: 368 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 369 !strconcat(opstr, "\t$rd, $rs, $rt"), 370 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> { 371 let isCommutable = 1; 372} 373 374// Shifts 375class shift_rotate_imm<string opstr, PatFrag PF, Operand ImmOpnd, 376 RegisterClass RC, SDPatternOperator OpNode> : 377 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 378 !strconcat(opstr, "\t$rd, $rt, $shamt"), 379 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>; 380 381// 32-bit shift instructions. 382class shift_rotate_imm32<string opstr, SDPatternOperator OpNode = null_frag> : 383 shift_rotate_imm<opstr, immZExt5, shamt, CPURegs, OpNode>; 384 385class shift_rotate_reg<string opstr, SDNode OpNode, RegisterClass RC>: 386 InstSE<(outs RC:$rd), (ins CPURegs:$rs, RC:$rt), 387 !strconcat(opstr, "\t$rd, $rt, $rs"), 388 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu, FrmR>; 389 390// Load Upper Imediate 391class LoadUpper<string opstr, RegisterClass RC, Operand Imm>: 392 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 393 [], IIAlu, FrmI>, IsAsCheapAsAMove { 394 let neverHasSideEffects = 1; 395 let isReMaterializable = 1; 396} 397 398class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 399 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 400 bits<21> addr; 401 let Inst{25-21} = addr{20-16}; 402 let Inst{15-0} = addr{15-0}; 403 let DecoderMethod = "DecodeMem"; 404} 405 406// Memory Load/Store 407class Load<string opstr, PatFrag OpNode, RegisterClass RC, Operand MemOpnd> : 408 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 409 [(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> { 410 let DecoderMethod = "DecodeMem"; 411 let canFoldAsLoad = 1; 412} 413 414class Store<string opstr, PatFrag OpNode, RegisterClass RC, Operand MemOpnd> : 415 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 416 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 417 let DecoderMethod = "DecodeMem"; 418} 419 420multiclass LoadM<string opstr, PatFrag OpNode, RegisterClass RC> { 421 def #NAME# : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 422 def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 423 let DecoderNamespace = "Mips64"; 424 let isCodeGenOnly = 1; 425 } 426} 427 428multiclass StoreM<string opstr, PatFrag OpNode, RegisterClass RC> { 429 def #NAME# : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 430 def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 431 let DecoderNamespace = "Mips64"; 432 let isCodeGenOnly = 1; 433 } 434} 435 436// Load/Store Left/Right 437let canFoldAsLoad = 1 in 438class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 439 RegisterClass RC, Operand MemOpnd> : 440 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 441 !strconcat(instr_asm, "\t$rt, $addr"), 442 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> { 443 string Constraints = "$src = $rt"; 444} 445 446class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 447 RegisterClass RC, Operand MemOpnd>: 448 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 449 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)], 450 IIStore>; 451 452// 32-bit load left/right. 453multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 454 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 455 Requires<[NotN64, HasStdEnc]>; 456 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 457 Requires<[IsN64, HasStdEnc]> { 458 let DecoderNamespace = "Mips64"; 459 let isCodeGenOnly = 1; 460 } 461} 462 463// 64-bit load left/right. 464multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 465 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 466 Requires<[NotN64, HasStdEnc]>; 467 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 468 Requires<[IsN64, HasStdEnc]> { 469 let DecoderNamespace = "Mips64"; 470 let isCodeGenOnly = 1; 471 } 472} 473 474// 32-bit store left/right. 475multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 476 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 477 Requires<[NotN64, HasStdEnc]>; 478 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 479 Requires<[IsN64, HasStdEnc]> { 480 let DecoderNamespace = "Mips64"; 481 let isCodeGenOnly = 1; 482 } 483} 484 485// 64-bit store left/right. 486multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 487 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 488 Requires<[NotN64, HasStdEnc]>; 489 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 490 Requires<[IsN64, HasStdEnc]> { 491 let DecoderNamespace = "Mips64"; 492 let isCodeGenOnly = 1; 493 } 494} 495 496// Conditional Branch 497class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> : 498 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 499 !strconcat(opstr, "\t$rs, $rt, $offset"), 500 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 501 FrmI> { 502 let isBranch = 1; 503 let isTerminator = 1; 504 let hasDelaySlot = 1; 505 let Defs = [AT]; 506} 507 508class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> : 509 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 510 !strconcat(opstr, "\t$rs, $offset"), 511 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 512 let isBranch = 1; 513 let isTerminator = 1; 514 let hasDelaySlot = 1; 515 let Defs = [AT]; 516} 517 518// SetCC 519class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : 520 InstSE<(outs CPURegs:$rd), (ins RC:$rs, RC:$rt), 521 !strconcat(opstr, "\t$rd, $rs, $rt"), 522 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>; 523 524class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 525 RegisterClass RC>: 526 InstSE<(outs CPURegs:$rt), (ins RC:$rs, Od:$imm16), 527 !strconcat(opstr, "\t$rt, $rs, $imm16"), 528 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], IIAlu, FrmI>; 529 530// Jump 531class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm, 532 SDPatternOperator operator, SDPatternOperator targetoperator>: 533 FJ<op, (outs), (ins opnd:$target), !strconcat(instr_asm, "\t$target"), 534 [(operator targetoperator:$target)], IIBranch> { 535 let isTerminator=1; 536 let isBarrier=1; 537 let hasDelaySlot = 1; 538 let DecoderMethod = "DecodeJumpTarget"; 539 let Defs = [AT]; 540} 541 542// Unconditional branch 543class UncondBranch<string opstr> : 544 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 545 [(br bb:$offset)], IIBranch, FrmI> { 546 let isBranch = 1; 547 let isTerminator = 1; 548 let isBarrier = 1; 549 let hasDelaySlot = 1; 550 let Predicates = [RelocPIC, HasStdEnc]; 551 let Defs = [AT]; 552} 553 554// Base class for indirect branch and return instruction classes. 555let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 556class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 557 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch> { 558 let rt = 0; 559 let rd = 0; 560 let shamt = 0; 561} 562 563// Indirect branch 564class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 565 let isBranch = 1; 566 let isIndirectBranch = 1; 567} 568 569// Return instruction 570class RetBase<RegisterClass RC>: JumpFR<RC> { 571 let isReturn = 1; 572 let isCodeGenOnly = 1; 573 let hasCtrlDep = 1; 574 let hasExtraSrcRegAllocReq = 1; 575} 576 577// Jump and Link (Call) 578let isCall=1, hasDelaySlot=1, Defs = [RA] in { 579 class JumpLink<bits<6> op, string instr_asm>: 580 FJ<op, (outs), (ins calltarget:$target), 581 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)], 582 IIBranch> { 583 let DecoderMethod = "DecodeJumpTarget"; 584 } 585 586 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm, 587 RegisterClass RC>: 588 FR<op, func, (outs), (ins RC:$rs), 589 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> { 590 let rt = 0; 591 let rd = 31; 592 let shamt = 0; 593 } 594 595 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>: 596 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16), 597 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> { 598 let rt = _rt; 599 } 600} 601 602// Mul, Div 603class Mult<bits<6> func, string instr_asm, InstrItinClass itin, 604 RegisterClass RC, list<Register> DefRegs>: 605 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 606 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> { 607 let rd = 0; 608 let shamt = 0; 609 let isCommutable = 1; 610 let Defs = DefRegs; 611 let neverHasSideEffects = 1; 612} 613 614class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>: 615 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>; 616 617class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin, 618 RegisterClass RC, list<Register> DefRegs>: 619 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 620 !strconcat(instr_asm, "\t$$zero, $rs, $rt"), 621 [(op RC:$rs, RC:$rt)], itin> { 622 let rd = 0; 623 let shamt = 0; 624 let Defs = DefRegs; 625} 626 627class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 628 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>; 629 630// Move from Hi/Lo 631class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>: 632 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 633 let Uses = UseRegs; 634 let neverHasSideEffects = 1; 635} 636 637class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>: 638 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 639 let Defs = DefRegs; 640 let neverHasSideEffects = 1; 641} 642 643class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> : 644 FMem<opc, (outs RC:$rt), (ins Mem:$addr), 645 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> { 646 let isCodeGenOnly = 1; 647} 648 649// Count Leading Ones/Zeros in Word 650class CountLeading0<string opstr, RegisterClass RC>: 651 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 652 [(set RC:$rd, (ctlz RC:$rs))], IIAlu, FrmR>, 653 Requires<[HasBitCount, HasStdEnc]>; 654 655class CountLeading1<string opstr, RegisterClass RC>: 656 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 657 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu, FrmR>, 658 Requires<[HasBitCount, HasStdEnc]>; 659 660 661// Sign Extend in Register. 662class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : 663 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), 664 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> { 665 let Predicates = [HasSEInReg, HasStdEnc]; 666} 667 668// Subword Swap 669class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>: 670 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt), 671 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> { 672 let rs = 0; 673 let shamt = sa; 674 let Predicates = [HasSwap, HasStdEnc]; 675 let neverHasSideEffects = 1; 676} 677 678// Read Hardware 679class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass> 680 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd), 681 "rdhwr\t$rt, $rd", [], IIAlu> { 682 let rs = 0; 683 let shamt = 0; 684} 685 686// Ext and Ins 687class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 688 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz), 689 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 690 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> { 691 bits<5> pos; 692 bits<5> sz; 693 let rd = sz; 694 let shamt = pos; 695 let Predicates = [HasMips32r2, HasStdEnc]; 696} 697 698class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 699 FR<0x1f, _funct, (outs RC:$rt), 700 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src), 701 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 702 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))], 703 NoItinerary> { 704 bits<5> pos; 705 bits<5> sz; 706 let rd = sz; 707 let shamt = pos; 708 let Predicates = [HasMips32r2, HasStdEnc]; 709 let Constraints = "$src = $rt"; 710} 711 712// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 713class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 714 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 715 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 716 717multiclass Atomic2Ops32<PatFrag Op> { 718 def #NAME# : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 719 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 720 Requires<[IsN64, HasStdEnc]> { 721 let DecoderNamespace = "Mips64"; 722 } 723} 724 725// Atomic Compare & Swap. 726class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 727 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 728 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 729 730multiclass AtomicCmpSwap32<PatFrag Op> { 731 def #NAME# : AtomicCmpSwap<Op, CPURegs, CPURegs>, 732 Requires<[NotN64, HasStdEnc]>; 733 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 734 Requires<[IsN64, HasStdEnc]> { 735 let DecoderNamespace = "Mips64"; 736 } 737} 738 739class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 740 FMem<Opc, (outs RC:$rt), (ins Mem:$addr), 741 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> { 742 let mayLoad = 1; 743} 744 745class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 746 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr), 747 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> { 748 let mayStore = 1; 749 let Constraints = "$rt = $dst"; 750} 751 752//===----------------------------------------------------------------------===// 753// Pseudo instructions 754//===----------------------------------------------------------------------===// 755 756// Return RA. 757let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 758def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 759 760let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 761def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 762 [(callseq_start timm:$amt)]>; 763def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 764 [(callseq_end timm:$amt1, timm:$amt2)]>; 765} 766 767let usesCustomInserter = 1 in { 768 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 769 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 770 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 771 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 772 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 773 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 774 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 775 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 776 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 777 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 778 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 779 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 780 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 781 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 782 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 783 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 784 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 785 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 786 787 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 788 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 789 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 790 791 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 792 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 793 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 794} 795 796//===----------------------------------------------------------------------===// 797// Instruction definition 798//===----------------------------------------------------------------------===// 799//===----------------------------------------------------------------------===// 800// MipsI Instructions 801//===----------------------------------------------------------------------===// 802 803/// Arithmetic Instructions (ALU Immediate) 804def ADDiu : ArithLogicI<"addiu", simm16, CPURegs, immSExt16, add>, 805 ADDI_FM<0x9>, IsAsCheapAsAMove; 806def ADDi : ArithLogicI<"addi", simm16, CPURegs>, ADDI_FM<0x8>; 807def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>; 808def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>; 809def ANDi : ArithLogicI<"andi", uimm16, CPURegs, immZExt16, and>, ADDI_FM<0xc>; 810def ORi : ArithLogicI<"ori", uimm16, CPURegs, immZExt16, or>, ADDI_FM<0xd>; 811def XORi : ArithLogicI<"xori", uimm16, CPURegs, immZExt16, xor>, ADDI_FM<0xe>; 812def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; 813 814/// Arithmetic Instructions (3-Operand, R-Type) 815def ADDu : ArithLogicR<"addu", CPURegs, 1, IIAlu, add>, ADD_FM<0, 0x21>; 816def SUBu : ArithLogicR<"subu", CPURegs, 0, IIAlu, sub>, ADD_FM<0, 0x23>; 817def MUL : ArithLogicR<"mul", CPURegs, 1, IIImul, mul>, ADD_FM<0x1c, 2>; 818def ADD : ArithLogicR<"add", CPURegs>, ADD_FM<0, 0x20>; 819def SUB : ArithLogicR<"sub", CPURegs>, ADD_FM<0, 0x22>; 820def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; 821def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; 822def AND : ArithLogicR<"and", CPURegs, 1, IIAlu, and>, ADD_FM<0, 0x24>; 823def OR : ArithLogicR<"or", CPURegs, 1, IIAlu, or>, ADD_FM<0, 0x25>; 824def XOR : ArithLogicR<"xor", CPURegs, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 825def NOR : LogicNOR<"nor", CPURegs>, ADD_FM<0, 0x27>; 826 827/// Shift Instructions 828def SLL : shift_rotate_imm32<"sll", shl>, SRA_FM<0, 0>; 829def SRL : shift_rotate_imm32<"srl", srl>, SRA_FM<2, 0>; 830def SRA : shift_rotate_imm32<"sra", sra>, SRA_FM<3, 0>; 831def SLLV : shift_rotate_reg<"sllv", shl, CPURegs>, SRLV_FM<4, 0>; 832def SRLV : shift_rotate_reg<"srlv", srl, CPURegs>, SRLV_FM<6, 0>; 833def SRAV : shift_rotate_reg<"srav", sra, CPURegs>, SRLV_FM<7, 0>; 834 835// Rotate Instructions 836let Predicates = [HasMips32r2, HasStdEnc] in { 837 def ROTR : shift_rotate_imm32<"rotr", rotr>, SRA_FM<2, 1>; 838 def ROTRV : shift_rotate_reg<"rotrv", rotr, CPURegs>, SRLV_FM<6, 1>; 839} 840 841/// Load and Store Instructions 842/// aligned 843defm LB : LoadM<"lb", sextloadi8, CPURegs>, LW_FM<0x20>; 844defm LBu : LoadM<"lbu", zextloadi8, CPURegs>, LW_FM<0x24>; 845defm LH : LoadM<"lh", sextloadi16, CPURegs>, LW_FM<0x21>; 846defm LHu : LoadM<"lhu", zextloadi16, CPURegs>, LW_FM<0x25>; 847defm LW : LoadM<"lw", load, CPURegs>, LW_FM<0x23>; 848defm SB : StoreM<"sb", truncstorei8, CPURegs>, LW_FM<0x28>; 849defm SH : StoreM<"sh", truncstorei16, CPURegs>, LW_FM<0x29>; 850defm SW : StoreM<"sw", store, CPURegs>, LW_FM<0x2b>; 851 852/// load/store left/right 853defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>; 854defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>; 855defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>; 856defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>; 857 858let hasSideEffects = 1 in 859def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype", 860 [(MipsSync imm:$stype)], NoItinerary, FrmOther> 861{ 862 bits<5> stype; 863 let Opcode = 0; 864 let Inst{25-11} = 0; 865 let Inst{10-6} = stype; 866 let Inst{5-0} = 15; 867} 868 869/// Load-linked, Store-conditional 870def LL : LLBase<0x30, "ll", CPURegs, mem>, 871 Requires<[NotN64, HasStdEnc]>; 872def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, 873 Requires<[IsN64, HasStdEnc]> { 874 let DecoderNamespace = "Mips64"; 875} 876 877def SC : SCBase<0x38, "sc", CPURegs, mem>, 878 Requires<[NotN64, HasStdEnc]>; 879def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, 880 Requires<[IsN64, HasStdEnc]> { 881 let DecoderNamespace = "Mips64"; 882} 883 884/// Jump and Branch Instructions 885def J : JumpFJ<0x02, jmptarget, "j", br, bb>, 886 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 887def JR : IndirectBranch<CPURegs>; 888def B : UncondBranch<"b">, B_FM; 889def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>; 890def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>; 891def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>; 892def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>; 893def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>; 894def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>; 895 896let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1, 897 hasDelaySlot = 1, Defs = [RA] in 898def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>; 899 900def JAL : JumpLink<0x03, "jal">; 901def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>; 902def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>; 903def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>; 904def TAILCALL : JumpFJ<0x02, calltarget, "j", MipsTailCall, imm>, IsTailCall; 905def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, IsTailCall; 906 907def RET : RetBase<CPURegs>; 908 909/// Multiply and Divide Instructions. 910def MULT : Mult32<0x18, "mult", IIImul>; 911def MULTu : Mult32<0x19, "multu", IIImul>; 912def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>; 913def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>; 914 915def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; 916def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; 917def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; 918def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; 919 920/// Sign Ext In Register Instructions. 921def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10>; 922def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18>; 923 924/// Count Leading 925def CLZ : CountLeading0<"clz", CPURegs>, CLO_FM<0x20>; 926def CLO : CountLeading1<"clo", CPURegs>, CLO_FM<0x21>; 927 928/// Word Swap Bytes Within Halfwords 929def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>; 930 931/// No operation 932let addr=0 in 933 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>; 934 935// FrameIndexes are legalized when they are operands from load/store 936// instructions. The same not happens for stack address copies, so an 937// add op with mem ComplexPattern is used and the stack address copy 938// can be matched. It's similar to Sparc LEA_ADDRi 939def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>; 940 941// MADD*/MSUB* 942def MADD : MArithR<0, "madd", MipsMAdd, 1>; 943def MADDU : MArithR<1, "maddu", MipsMAddu, 1>; 944def MSUB : MArithR<4, "msub", MipsMSub>; 945def MSUBU : MArithR<5, "msubu", MipsMSubu>; 946 947def RDHWR : ReadHardware<CPURegs, HWRegs>; 948 949def EXT : ExtBase<0, "ext", CPURegs>; 950def INS : InsBase<4, "ins", CPURegs>; 951 952/// Move Control Registers From/To CPU Registers 953def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt), 954 (ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">; 955def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 956 957def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel), 958 (ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">; 959def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 960 961def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt), 962 (ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">; 963def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 964 965def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel), 966 (ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">; 967def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 968 969//===----------------------------------------------------------------------===// 970// Instruction aliases 971//===----------------------------------------------------------------------===// 972def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>; 973def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>; 974def : InstAlias<"addu $rs,$rt,$imm", 975 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 976def : InstAlias<"add $rs,$rt,$imm", 977 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 978def : InstAlias<"and $rs,$rt,$imm", 979 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 980def : InstAlias<"j $rs", (JR CPURegs:$rs)>; 981def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>; 982def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>; 983def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>; 984def : InstAlias<"slt $rs,$rt,$imm", 985 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 986def : InstAlias<"xor $rs,$rt,$imm", 987 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 988 989//===----------------------------------------------------------------------===// 990// Assembler Pseudo Instructions 991//===----------------------------------------------------------------------===// 992 993class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> : 994 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 995 !strconcat(instr_asm, "\t$rt, $imm32")> ; 996def LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>; 997 998class LoadAddress<string instr_asm, Operand MemOpnd, RegisterClass RC> : 999 MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr), 1000 !strconcat(instr_asm, "\t$rt, $addr")> ; 1001def LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>; 1002 1003class LoadAddressImm<string instr_asm, Operand Od, RegisterClass RC> : 1004 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 1005 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1006def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>; 1007 1008 1009 1010//===----------------------------------------------------------------------===// 1011// Arbitrary patterns that map to one or more instructions 1012//===----------------------------------------------------------------------===// 1013 1014// Small immediates 1015def : MipsPat<(i32 immSExt16:$in), 1016 (ADDiu ZERO, imm:$in)>; 1017def : MipsPat<(i32 immZExt16:$in), 1018 (ORi ZERO, imm:$in)>; 1019def : MipsPat<(i32 immLow16Zero:$in), 1020 (LUi (HI16 imm:$in))>; 1021 1022// Arbitrary immediates 1023def : MipsPat<(i32 imm:$imm), 1024 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1025 1026// Carry MipsPatterns 1027def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1028 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1029def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1030 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1031def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1032 (ADDiu CPURegs:$src, imm:$imm)>; 1033 1034// Call 1035def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1036 (JAL tglobaladdr:$dst)>; 1037def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1038 (JAL texternalsym:$dst)>; 1039//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1040// (JALR CPURegs:$dst)>; 1041 1042// Tail call 1043def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1044 (TAILCALL tglobaladdr:$dst)>; 1045def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1046 (TAILCALL texternalsym:$dst)>; 1047// hi/lo relocs 1048def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1049def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1050def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1051def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1052def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1053def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1054 1055def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1056def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1057def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1058def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1059def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1060def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1061 1062def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1063 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1064def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1065 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1066def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1067 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1068def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1069 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1070def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1071 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1072 1073// gp_rel relocs 1074def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1075 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1076def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1077 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1078 1079// wrapper_pic 1080class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1081 MipsPat<(MipsWrapper RC:$gp, node:$in), 1082 (ADDiuOp RC:$gp, node:$in)>; 1083 1084def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1085def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1086def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1087def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1088def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1089def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1090 1091// Mips does not have "not", so we expand our way 1092def : MipsPat<(not CPURegs:$in), 1093 (NOR CPURegs:$in, ZERO)>; 1094 1095// extended loads 1096let Predicates = [NotN64, HasStdEnc] in { 1097 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1098 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1099 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1100} 1101let Predicates = [IsN64, HasStdEnc] in { 1102 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1103 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1104 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1105} 1106 1107// peepholes 1108let Predicates = [NotN64, HasStdEnc] in { 1109 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1110} 1111let Predicates = [IsN64, HasStdEnc] in { 1112 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1113} 1114 1115// brcond patterns 1116multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1117 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1118 Instruction SLTiuOp, Register ZEROReg> { 1119def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1120 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1121def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1122 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1123 1124def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1125 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1126def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1127 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1128def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1129 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1130def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1131 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1132 1133def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1134 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1135def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1136 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1137 1138def : MipsPat<(brcond RC:$cond, bb:$dst), 1139 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1140} 1141 1142defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1143 1144// setcc patterns 1145multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1146 Instruction SLTuOp, Register ZEROReg> { 1147 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1148 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1149 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1150 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1151} 1152 1153multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1154 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1155 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1156 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1157 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1158} 1159 1160multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1161 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1162 (SLTOp RC:$rhs, RC:$lhs)>; 1163 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1164 (SLTuOp RC:$rhs, RC:$lhs)>; 1165} 1166 1167multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1168 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1169 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1170 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1171 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1172} 1173 1174multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1175 Instruction SLTiuOp> { 1176 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1177 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1178 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1179 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1180} 1181 1182defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1183defm : SetlePats<CPURegs, SLT, SLTu>; 1184defm : SetgtPats<CPURegs, SLT, SLTu>; 1185defm : SetgePats<CPURegs, SLT, SLTu>; 1186defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1187 1188// bswap pattern 1189def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1190 1191//===----------------------------------------------------------------------===// 1192// Floating Point Support 1193//===----------------------------------------------------------------------===// 1194 1195include "MipsInstrFPU.td" 1196include "Mips64InstrInfo.td" 1197include "MipsCondMov.td" 1198 1199// 1200// Mips16 1201 1202include "Mips16InstrFormats.td" 1203include "Mips16InstrInfo.td" 1204 1205// DSP 1206include "MipsDSPInstrFormats.td" 1207include "MipsDSPInstrInfo.td" 1208 1209