MipsInstrInfo.td revision 16f385f90f481195bfcf6b139ced4cee033bb887
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>, 27 SDTCisVT<2, i32>]>; 28def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 29 SDTCisVT<1, i32>, 30 SDTCisSameAs<1, 2>]>; 31def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 32 SDTCisSameAs<1, 2>]>; 33def SDT_MipsMAddMSub : SDTypeProfile<1, 3, 34 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 35 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 36def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 37 38def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 39 40def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 41 42def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 44def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 45 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 46 SDTCisSameAs<0, 4>]>; 47 48def SDTMipsLoadLR : SDTypeProfile<1, 2, 49 [SDTCisInt<0>, SDTCisPtrTy<1>, 50 SDTCisSameAs<0, 2>]>; 51 52// Call 53def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 55 SDNPVariadic]>; 56 57// Tail call 58def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 59 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 60 61// Hi and Lo nodes are used to handle global addresses. Used on 62// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 63// static model. (nothing to do with Mips Registers Hi and Lo) 64def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 65def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 66def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 67 68// TlsGd node is used to handle General Dynamic TLS 69def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 70 71// TprelHi and TprelLo nodes are used to handle Local Exec TLS 72def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 73def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 74 75// Thread pointer 76def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 77 78// Return 79def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 80 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 81 82// These are target-independent nodes, but have target-specific formats. 83def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 84 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 85def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 86 [SDNPHasChain, SDNPSideEffect, 87 SDNPOptInGlue, SDNPOutGlue]>; 88 89// Node used to extract integer from LO/HI register. 90def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>; 91 92// Node used to insert 32-bit integers to LOHI register pair. 93def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>; 94 95// Mult nodes. 96def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 97def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 98 99// MAdd*/MSub* nodes 100def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 101def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 102def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 103def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 104 105// DivRem(u) nodes 106def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 107def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 108def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, 109 [SDNPOutGlue]>; 110def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 111 [SDNPOutGlue]>; 112 113// Target constant nodes that are not part of any isel patterns and remain 114// unchanged can cause instructions with illegal operands to be emitted. 115// Wrapper node patterns give the instruction selector a chance to replace 116// target constant nodes that would otherwise remain unchanged with ADDiu 117// nodes. Without these wrapper node patterns, the following conditional move 118// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 119// compiled: 120// movn %got(d)($gp), %got(c)($gp), $4 121// This instruction is illegal since movn can take only register operands. 122 123def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 124 125def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 126 127def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 128def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 129 130def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 132def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 134def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 136def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 138def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 140def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 142def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 144def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 146 147//===----------------------------------------------------------------------===// 148// Mips Instruction Predicate Definitions. 149//===----------------------------------------------------------------------===// 150def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 151 AssemblerPredicate<"FeatureSEInReg">; 152def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 153 AssemblerPredicate<"FeatureBitCount">; 154def HasSwap : Predicate<"Subtarget.hasSwap()">, 155 AssemblerPredicate<"FeatureSwap">; 156def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 157 AssemblerPredicate<"FeatureCondMov">; 158def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 159 AssemblerPredicate<"FeatureFPIdx">; 160def HasMips32 : Predicate<"Subtarget.hasMips32()">, 161 AssemblerPredicate<"FeatureMips32">; 162def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 163 AssemblerPredicate<"FeatureMips32r2">; 164def HasMips64 : Predicate<"Subtarget.hasMips64()">, 165 AssemblerPredicate<"FeatureMips64">; 166def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 167 AssemblerPredicate<"!FeatureMips64">; 168def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 169 AssemblerPredicate<"FeatureMips64r2">; 170def IsN64 : Predicate<"Subtarget.isABI_N64()">, 171 AssemblerPredicate<"FeatureN64">; 172def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 173 AssemblerPredicate<"!FeatureN64">; 174def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 175 AssemblerPredicate<"FeatureMips16">; 176def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 177 AssemblerPredicate<"FeatureMips32">; 178def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 179 AssemblerPredicate<"FeatureMips32">; 180def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 181 AssemblerPredicate<"FeatureMips32">; 182def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 183 AssemblerPredicate<"!FeatureMips16">; 184def NotDSP : Predicate<"!Subtarget.hasDSP()">; 185 186class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 187 let Predicates = [HasStdEnc]; 188} 189 190class IsCommutable { 191 bit isCommutable = 1; 192} 193 194class IsBranch { 195 bit isBranch = 1; 196} 197 198class IsReturn { 199 bit isReturn = 1; 200} 201 202class IsCall { 203 bit isCall = 1; 204} 205 206class IsTailCall { 207 bit isCall = 1; 208 bit isTerminator = 1; 209 bit isReturn = 1; 210 bit isBarrier = 1; 211 bit hasExtraSrcRegAllocReq = 1; 212 bit isCodeGenOnly = 1; 213} 214 215class IsAsCheapAsAMove { 216 bit isAsCheapAsAMove = 1; 217} 218 219class NeverHasSideEffects { 220 bit neverHasSideEffects = 1; 221} 222 223//===----------------------------------------------------------------------===// 224// Instruction format superclass 225//===----------------------------------------------------------------------===// 226 227include "MipsInstrFormats.td" 228 229//===----------------------------------------------------------------------===// 230// Mips Operand, Complex Patterns and Transformations Definitions. 231//===----------------------------------------------------------------------===// 232 233// Instruction operand types 234def jmptarget : Operand<OtherVT> { 235 let EncoderMethod = "getJumpTargetOpValue"; 236} 237def brtarget : Operand<OtherVT> { 238 let EncoderMethod = "getBranchTargetOpValue"; 239 let OperandType = "OPERAND_PCREL"; 240 let DecoderMethod = "DecodeBranchTarget"; 241} 242def calltarget : Operand<iPTR> { 243 let EncoderMethod = "getJumpTargetOpValue"; 244} 245def calltarget64: Operand<i64>; 246def simm16 : Operand<i32> { 247 let DecoderMethod= "DecodeSimm16"; 248} 249 250def simm20 : Operand<i32> { 251} 252 253def uimm20 : Operand<i32> { 254} 255 256def uimm10 : Operand<i32> { 257} 258 259def simm16_64 : Operand<i64>; 260def shamt : Operand<i32>; 261 262// Unsigned Operand 263def uimm16 : Operand<i32> { 264 let PrintMethod = "printUnsignedImm"; 265} 266 267def MipsMemAsmOperand : AsmOperandClass { 268 let Name = "Mem"; 269 let ParserMethod = "parseMemOperand"; 270} 271 272// Address operand 273def mem : Operand<i32> { 274 let PrintMethod = "printMemOperand"; 275 let MIOperandInfo = (ops CPURegs, simm16); 276 let EncoderMethod = "getMemEncoding"; 277 let ParserMatchClass = MipsMemAsmOperand; 278 let OperandType = "OPERAND_MEMORY"; 279} 280 281def mem64 : Operand<i64> { 282 let PrintMethod = "printMemOperand"; 283 let MIOperandInfo = (ops CPU64Regs, simm16_64); 284 let EncoderMethod = "getMemEncoding"; 285 let ParserMatchClass = MipsMemAsmOperand; 286 let OperandType = "OPERAND_MEMORY"; 287} 288 289def mem_ea : Operand<i32> { 290 let PrintMethod = "printMemOperandEA"; 291 let MIOperandInfo = (ops CPURegs, simm16); 292 let EncoderMethod = "getMemEncoding"; 293 let OperandType = "OPERAND_MEMORY"; 294} 295 296def mem_ea_64 : Operand<i64> { 297 let PrintMethod = "printMemOperandEA"; 298 let MIOperandInfo = (ops CPU64Regs, simm16_64); 299 let EncoderMethod = "getMemEncoding"; 300 let OperandType = "OPERAND_MEMORY"; 301} 302 303// size operand of ext instruction 304def size_ext : Operand<i32> { 305 let EncoderMethod = "getSizeExtEncoding"; 306 let DecoderMethod = "DecodeExtSize"; 307} 308 309// size operand of ins instruction 310def size_ins : Operand<i32> { 311 let EncoderMethod = "getSizeInsEncoding"; 312 let DecoderMethod = "DecodeInsSize"; 313} 314 315// Transformation Function - get the lower 16 bits. 316def LO16 : SDNodeXForm<imm, [{ 317 return getImm(N, N->getZExtValue() & 0xFFFF); 318}]>; 319 320// Transformation Function - get the higher 16 bits. 321def HI16 : SDNodeXForm<imm, [{ 322 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 323}]>; 324 325// Plus 1. 326def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 327 328// Node immediate fits as 16-bit sign extended on target immediate. 329// e.g. addi, andi 330def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 331 332// Node immediate fits as 16-bit sign extended on target immediate. 333// e.g. addi, andi 334def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 335 336// Node immediate fits as 15-bit sign extended on target immediate. 337// e.g. addi, andi 338def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 339 340// Node immediate fits as 16-bit zero extended on target immediate. 341// The LO16 param means that only the lower 16 bits of the node 342// immediate are caught. 343// e.g. addiu, sltiu 344def immZExt16 : PatLeaf<(imm), [{ 345 if (N->getValueType(0) == MVT::i32) 346 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 347 else 348 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 349}], LO16>; 350 351// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 352def immLow16Zero : PatLeaf<(imm), [{ 353 int64_t Val = N->getSExtValue(); 354 return isInt<32>(Val) && !(Val & 0xffff); 355}]>; 356 357// shamt field must fit in 5 bits. 358def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 359 360// True if (N + 1) fits in 16-bit field. 361def immSExt16Plus1 : PatLeaf<(imm), [{ 362 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 363}]>; 364 365// Mips Address Mode! SDNode frameindex could possibily be a match 366// since load and store instructions from stack used it. 367def addr : 368 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 369 370def addrRegImm : 371 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 372 373def addrDefault : 374 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 375 376//===----------------------------------------------------------------------===// 377// Instructions specific format 378//===----------------------------------------------------------------------===// 379 380// Arithmetic and logical instructions with 3 register operands. 381class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 382 InstrItinClass Itin = NoItinerary, 383 SDPatternOperator OpNode = null_frag>: 384 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 385 !strconcat(opstr, "\t$rd, $rs, $rt"), 386 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { 387 let isCommutable = isComm; 388 let isReMaterializable = 1; 389} 390 391// Arithmetic and logical instructions with 2 register operands. 392class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 393 SDPatternOperator imm_type = null_frag, 394 SDPatternOperator OpNode = null_frag> : 395 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 396 !strconcat(opstr, "\t$rt, $rs, $imm16"), 397 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], 398 IIAlu, FrmI, opstr> { 399 let isReMaterializable = 1; 400 let TwoOperandAliasConstraint = "$rs = $rt"; 401} 402 403// Arithmetic Multiply ADD/SUB 404class MArithR<string opstr, bit isComm = 0> : 405 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt), 406 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR> { 407 let Defs = [HI, LO]; 408 let Uses = [HI, LO]; 409 let isCommutable = isComm; 410} 411 412// Logical 413class LogicNOR<string opstr, RegisterOperand RC>: 414 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 415 !strconcat(opstr, "\t$rd, $rs, $rt"), 416 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR, opstr> { 417 let isCommutable = 1; 418} 419 420// Shifts 421class shift_rotate_imm<string opstr, Operand ImmOpnd, 422 RegisterOperand RC, SDPatternOperator OpNode = null_frag, 423 SDPatternOperator PF = null_frag> : 424 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 425 !strconcat(opstr, "\t$rd, $rt, $shamt"), 426 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR, opstr>; 427 428class shift_rotate_reg<string opstr, RegisterOperand RC, 429 SDPatternOperator OpNode = null_frag>: 430 InstSE<(outs RC:$rd), (ins RC:$rt, CPURegsOpnd:$rs), 431 !strconcat(opstr, "\t$rd, $rt, $rs"), 432 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR, opstr>; 433 434// Load Upper Imediate 435class LoadUpper<string opstr, RegisterClass RC, Operand Imm>: 436 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 437 [], IIAlu, FrmI>, IsAsCheapAsAMove { 438 let neverHasSideEffects = 1; 439 let isReMaterializable = 1; 440} 441 442class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 443 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 444 bits<21> addr; 445 let Inst{25-21} = addr{20-16}; 446 let Inst{15-0} = addr{15-0}; 447 let DecoderMethod = "DecodeMem"; 448} 449 450// Memory Load/Store 451class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC, 452 InstrItinClass Itin, Operand MemOpnd, ComplexPattern Addr, 453 string ofsuffix> : 454 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 455 [(set RC:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI, 456 !strconcat(opstr, ofsuffix)> { 457 let DecoderMethod = "DecodeMem"; 458 let canFoldAsLoad = 1; 459 let mayLoad = 1; 460} 461 462class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC, 463 InstrItinClass Itin, Operand MemOpnd, ComplexPattern Addr, 464 string ofsuffix> : 465 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 466 [(OpNode RC:$rt, Addr:$addr)], NoItinerary, FrmI, 467 !strconcat(opstr, ofsuffix)> { 468 let DecoderMethod = "DecodeMem"; 469 let mayStore = 1; 470} 471 472multiclass LoadM<string opstr, RegisterClass RC, 473 SDPatternOperator OpNode = null_frag, 474 InstrItinClass Itin = NoItinerary, 475 ComplexPattern Addr = addr> { 476 def NAME : Load<opstr, OpNode, RC, Itin, mem, Addr, "">, 477 Requires<[NotN64, HasStdEnc]>; 478 def _P8 : Load<opstr, OpNode, RC, Itin, mem64, Addr, "_p8">, 479 Requires<[IsN64, HasStdEnc]> { 480 let DecoderNamespace = "Mips64"; 481 let isCodeGenOnly = 1; 482 } 483} 484 485multiclass StoreM<string opstr, RegisterClass RC, 486 SDPatternOperator OpNode = null_frag, 487 InstrItinClass Itin = NoItinerary, 488 ComplexPattern Addr = addr> { 489 def NAME : Store<opstr, OpNode, RC, Itin, mem, Addr, "">, 490 Requires<[NotN64, HasStdEnc]>; 491 def _P8 : Store<opstr, OpNode, RC, Itin, mem64, Addr, "_p8">, 492 Requires<[IsN64, HasStdEnc]> { 493 let DecoderNamespace = "Mips64"; 494 let isCodeGenOnly = 1; 495 } 496} 497 498// Load/Store Left/Right 499let canFoldAsLoad = 1 in 500class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 501 Operand MemOpnd> : 502 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 503 !strconcat(opstr, "\t$rt, $addr"), 504 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> { 505 let DecoderMethod = "DecodeMem"; 506 string Constraints = "$src = $rt"; 507} 508 509class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 510 Operand MemOpnd>: 511 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 512 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 513 let DecoderMethod = "DecodeMem"; 514} 515 516multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 517 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>, 518 Requires<[NotN64, HasStdEnc]>; 519 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>, 520 Requires<[IsN64, HasStdEnc]> { 521 let DecoderNamespace = "Mips64"; 522 let isCodeGenOnly = 1; 523 } 524} 525 526multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 527 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>, 528 Requires<[NotN64, HasStdEnc]>; 529 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>, 530 Requires<[IsN64, HasStdEnc]> { 531 let DecoderNamespace = "Mips64"; 532 let isCodeGenOnly = 1; 533 } 534} 535 536// Conditional Branch 537class CBranch<string opstr, PatFrag cond_op, RegisterOperand RC> : 538 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 539 !strconcat(opstr, "\t$rs, $rt, $offset"), 540 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 541 FrmI> { 542 let isBranch = 1; 543 let isTerminator = 1; 544 let hasDelaySlot = 1; 545 let Defs = [AT]; 546} 547 548class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RC> : 549 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 550 !strconcat(opstr, "\t$rs, $offset"), 551 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 552 let isBranch = 1; 553 let isTerminator = 1; 554 let hasDelaySlot = 1; 555 let Defs = [AT]; 556} 557 558// SetCC 559class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : 560 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt), 561 !strconcat(opstr, "\t$rd, $rs, $rt"), 562 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))], 563 IIslt, FrmR, opstr>; 564 565class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 566 RegisterClass RC>: 567 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16), 568 !strconcat(opstr, "\t$rt, $rs, $imm16"), 569 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))], 570 IIslt, FrmI, opstr>; 571 572// Jump 573class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 574 SDPatternOperator targetoperator> : 575 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 576 [(operator targetoperator:$target)], IIBranch, FrmJ> { 577 let isTerminator=1; 578 let isBarrier=1; 579 let hasDelaySlot = 1; 580 let DecoderMethod = "DecodeJumpTarget"; 581 let Defs = [AT]; 582} 583 584// Unconditional branch 585class UncondBranch<string opstr> : 586 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 587 [(br bb:$offset)], IIBranch, FrmI> { 588 let isBranch = 1; 589 let isTerminator = 1; 590 let isBarrier = 1; 591 let hasDelaySlot = 1; 592 let Predicates = [RelocPIC, HasStdEnc]; 593 let Defs = [AT]; 594} 595 596// Base class for indirect branch and return instruction classes. 597let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 598class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 599 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>; 600 601// Indirect branch 602class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 603 let isBranch = 1; 604 let isIndirectBranch = 1; 605} 606 607// Return instruction 608class RetBase<RegisterClass RC>: JumpFR<RC> { 609 let isReturn = 1; 610 let isCodeGenOnly = 1; 611 let hasCtrlDep = 1; 612 let hasExtraSrcRegAllocReq = 1; 613} 614 615// Jump and Link (Call) 616let isCall=1, hasDelaySlot=1, Defs = [RA] in { 617 class JumpLink<string opstr> : 618 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 619 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 620 let DecoderMethod = "DecodeJumpTarget"; 621 } 622 623 class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst, 624 Register RetReg>: 625 PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>, 626 PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>; 627 628 class JumpLinkReg<string opstr, RegisterClass RC>: 629 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 630 [], IIBranch, FrmR>; 631 632 class BGEZAL_FT<string opstr, RegisterOperand RO> : 633 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 634 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 635 636} 637 638class BAL_FT : 639 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> { 640 let isBranch = 1; 641 let isTerminator = 1; 642 let isBarrier = 1; 643 let hasDelaySlot = 1; 644 let Defs = [RA]; 645} 646// Syscall 647class SYS_FT<string opstr> : 648 InstSE<(outs), (ins uimm20:$code_), 649 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>; 650// Break 651class BRK_FT<string opstr> : 652 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2), 653 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>; 654 655// (D)Eret 656class ER_FT<string opstr> : 657 InstSE<(outs), (ins), 658 opstr, [], NoItinerary, FrmOther>; 659 660// Sync 661let hasSideEffects = 1 in 662class SYNC_FT : 663 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 664 NoItinerary, FrmOther>; 665 666let hasSideEffects = 1 in 667class TEQ_FT<string opstr, RegisterOperand RO> : 668 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_), 669 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>; 670 671// Mul, Div 672class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 673 list<Register> DefRegs> : 674 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 675 itin, FrmR, opstr> { 676 let isCommutable = 1; 677 let Defs = DefRegs; 678 let neverHasSideEffects = 1; 679} 680 681// Pseudo multiply/divide instruction with explicit accumulator register 682// operands. 683class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 684 SDPatternOperator OpNode, InstrItinClass Itin, 685 bit IsComm = 1, bit HasSideEffects = 0, 686 bit UsesCustomInserter = 0> : 687 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 688 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 689 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 690 let isCommutable = IsComm; 691 let hasSideEffects = HasSideEffects; 692 let usesCustomInserter = UsesCustomInserter; 693} 694 695// Pseudo multiply add/sub instruction with explicit accumulator register 696// operands. 697class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode> 698 : PseudoSE<(outs ACRegs:$ac), 699 (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin), 700 [(set ACRegs:$ac, 701 (OpNode CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin))], 702 IIImult>, 703 PseudoInstExpansion<(RealInst CPURegsOpnd:$rs, CPURegsOpnd:$rt)> { 704 string Constraints = "$acin = $ac"; 705} 706 707class Div<string opstr, InstrItinClass itin, RegisterOperand RO, 708 list<Register> DefRegs> : 709 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 710 [], itin, FrmR> { 711 let Defs = DefRegs; 712} 713 714// Move from Hi/Lo 715class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>: 716 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 717 let Uses = UseRegs; 718 let neverHasSideEffects = 1; 719} 720 721class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>: 722 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 723 let Defs = DefRegs; 724 let neverHasSideEffects = 1; 725} 726 727class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> : 728 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 729 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> { 730 let isCodeGenOnly = 1; 731 let DecoderMethod = "DecodeMem"; 732} 733 734// Count Leading Ones/Zeros in Word 735class CountLeading0<string opstr, RegisterOperand RO>: 736 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 737 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>, 738 Requires<[HasBitCount, HasStdEnc]>; 739 740class CountLeading1<string opstr, RegisterOperand RO>: 741 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 742 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>, 743 Requires<[HasBitCount, HasStdEnc]>; 744 745 746// Sign Extend in Register. 747class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : 748 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), 749 [(set RC:$rd, (sext_inreg RC:$rt, vt))], IIseb, FrmR> { 750 let Predicates = [HasSEInReg, HasStdEnc]; 751} 752 753// Subword Swap 754class SubwordSwap<string opstr, RegisterOperand RO>: 755 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 756 NoItinerary, FrmR> { 757 let Predicates = [HasSwap, HasStdEnc]; 758 let neverHasSideEffects = 1; 759} 760 761// Read Hardware 762class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> : 763 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 764 IIAlu, FrmR>; 765 766// Ext and Ins 767class ExtBase<string opstr, RegisterOperand RO>: 768 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size), 769 !strconcat(opstr, " $rt, $rs, $pos, $size"), 770 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary, 771 FrmR> { 772 let Predicates = [HasMips32r2, HasStdEnc]; 773} 774 775class InsBase<string opstr, RegisterOperand RO>: 776 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src), 777 !strconcat(opstr, " $rt, $rs, $pos, $size"), 778 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))], 779 NoItinerary, FrmR> { 780 let Predicates = [HasMips32r2, HasStdEnc]; 781 let Constraints = "$src = $rt"; 782} 783 784// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 785class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 786 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 787 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 788 789multiclass Atomic2Ops32<PatFrag Op> { 790 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 791 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 792 Requires<[IsN64, HasStdEnc]> { 793 let DecoderNamespace = "Mips64"; 794 } 795} 796 797// Atomic Compare & Swap. 798class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 799 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 800 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 801 802multiclass AtomicCmpSwap32<PatFrag Op> { 803 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>, 804 Requires<[NotN64, HasStdEnc]>; 805 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 806 Requires<[IsN64, HasStdEnc]> { 807 let DecoderNamespace = "Mips64"; 808 } 809} 810 811class LLBase<string opstr, RegisterOperand RO, Operand Mem> : 812 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 813 [], NoItinerary, FrmI> { 814 let DecoderMethod = "DecodeMem"; 815 let mayLoad = 1; 816} 817 818class SCBase<string opstr, RegisterOperand RO, Operand Mem> : 819 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr), 820 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 821 let DecoderMethod = "DecodeMem"; 822 let mayStore = 1; 823 let Constraints = "$rt = $dst"; 824} 825 826class MFC3OP<dag outs, dag ins, string asmstr> : 827 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>; 828 829//===----------------------------------------------------------------------===// 830// Pseudo instructions 831//===----------------------------------------------------------------------===// 832 833// Return RA. 834let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 835def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 836 837let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 838def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 839 [(callseq_start timm:$amt)]>; 840def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 841 [(callseq_end timm:$amt1, timm:$amt2)]>; 842} 843 844let usesCustomInserter = 1 in { 845 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 846 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 847 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 848 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 849 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 850 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 851 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 852 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 853 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 854 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 855 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 856 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 857 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 858 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 859 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 860 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 861 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 862 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 863 864 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 865 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 866 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 867 868 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 869 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 870 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 871} 872 873/// Pseudo instructions for loading and storing accumulator registers. 874let isPseudo = 1 in { 875 defm LOAD_AC64 : LoadM<"load_ac64", ACRegs>; 876 defm STORE_AC64 : StoreM<"store_ac64", ACRegs>; 877} 878 879//===----------------------------------------------------------------------===// 880// Instruction definition 881//===----------------------------------------------------------------------===// 882//===----------------------------------------------------------------------===// 883// MipsI Instructions 884//===----------------------------------------------------------------------===// 885 886/// Arithmetic Instructions (ALU Immediate) 887def ADDiu : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>, 888 ADDI_FM<0x9>, IsAsCheapAsAMove; 889def ADDi : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>; 890def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, 891 SLTI_FM<0xa>; 892def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, 893 SLTI_FM<0xb>; 894def ANDi : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>, 895 ADDI_FM<0xc>; 896def ORi : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>, 897 ADDI_FM<0xd>; 898def XORi : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>, 899 ADDI_FM<0xe>; 900def LUi : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; 901 902/// Arithmetic Instructions (3-Operand, R-Type) 903def ADDu : MMRel, ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>, 904 ADD_FM<0, 0x21>; 905def SUBu : MMRel, ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>, 906 ADD_FM<0, 0x23>; 907def MUL : MMRel, ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>, 908 ADD_FM<0x1c, 2>; 909def ADD : MMRel, ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>; 910def SUB : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>; 911def SLT : MMRel, SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; 912def SLTu : MMRel, SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; 913def AND : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, 914 ADD_FM<0, 0x24>; 915def OR : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, 916 ADD_FM<0, 0x25>; 917def XOR : MMRel, ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, 918 ADD_FM<0, 0x26>; 919def NOR : MMRel, LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>; 920 921/// Shift Instructions 922def SLL : MMRel, shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>, 923 SRA_FM<0, 0>; 924def SRL : MMRel, shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>, 925 SRA_FM<2, 0>; 926def SRA : MMRel, shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>, 927 SRA_FM<3, 0>; 928def SLLV : MMRel, shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>; 929def SRLV : MMRel, shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>; 930def SRAV : MMRel, shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>; 931 932// Rotate Instructions 933let Predicates = [HasMips32r2, HasStdEnc] in { 934 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr, 935 immZExt5>, 936 SRA_FM<2, 1>; 937 def ROTRV : MMRel, shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>, 938 SRLV_FM<6, 1>; 939} 940 941/// Load and Store Instructions 942/// aligned 943defm LB : LoadM<"lb", CPURegs, sextloadi8, IILoad>, MMRel, LW_FM<0x20>; 944defm LBu : LoadM<"lbu", CPURegs, zextloadi8, IILoad, addrDefault>, MMRel, 945 LW_FM<0x24>; 946defm LH : LoadM<"lh", CPURegs, sextloadi16, IILoad, addrDefault>, MMRel, 947 LW_FM<0x21>; 948defm LHu : LoadM<"lhu", CPURegs, zextloadi16, IILoad>, MMRel, LW_FM<0x25>; 949defm LW : LoadM<"lw", CPURegs, load, IILoad, addrDefault>, MMRel, LW_FM<0x23>; 950defm SB : StoreM<"sb", CPURegs, truncstorei8, IIStore>, MMRel, LW_FM<0x28>; 951defm SH : StoreM<"sh", CPURegs, truncstorei16, IIStore>, MMRel, LW_FM<0x29>; 952defm SW : StoreM<"sw", CPURegs, store, IIStore>, MMRel, LW_FM<0x2b>; 953 954/// load/store left/right 955defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>; 956defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>; 957defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>; 958defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; 959 960def SYNC : SYNC_FT, SYNC_FM; 961def TEQ : TEQ_FT<"teq", CPURegsOpnd>, TEQ_FM<0x34>; 962 963def BREAK : BRK_FT<"break">, BRK_FM<0xd>; 964def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>; 965 966def ERET : ER_FT<"eret">, ER_FM<0x18>; 967def DERET : ER_FT<"deret">, ER_FM<0x1f>; 968 969/// Load-linked, Store-conditional 970let Predicates = [NotN64, HasStdEnc] in { 971 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>; 972 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>; 973} 974 975let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 976 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>; 977 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>; 978} 979 980/// Jump and Branch Instructions 981def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 982 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 983def JR : IndirectBranch<CPURegs>, MTLO_FM<8>; 984def B : UncondBranch<"b">, B_FM; 985def BEQ : CBranch<"beq", seteq, CPURegsOpnd>, BEQ_FM<4>; 986def BNE : CBranch<"bne", setne, CPURegsOpnd>, BEQ_FM<5>; 987def BGEZ : CBranchZero<"bgez", setge, CPURegsOpnd>, BGEZ_FM<1, 1>; 988def BGTZ : CBranchZero<"bgtz", setgt, CPURegsOpnd>, BGEZ_FM<7, 0>; 989def BLEZ : CBranchZero<"blez", setle, CPURegsOpnd>, BGEZ_FM<6, 0>; 990def BLTZ : CBranchZero<"bltz", setlt, CPURegsOpnd>, BGEZ_FM<1, 0>; 991 992def BAL_BR: BAL_FT, BAL_FM; 993 994def JAL : JumpLink<"jal">, FJ<3>; 995def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM; 996def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>; 997def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>; 998def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>; 999def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 1000def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 1001 1002def RET : RetBase<CPURegs>, MTLO_FM<8>; 1003 1004// Exception handling related node and instructions. 1005// The conversion sequence is: 1006// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 1007// MIPSeh_return -> (stack change + indirect branch) 1008// 1009// MIPSeh_return takes the place of regular return instruction 1010// but takes two arguments (V1, V0) which are used for storing 1011// the offset and return address respectively. 1012def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 1013 1014def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 1015 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 1016 1017let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 1018 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst), 1019 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>; 1020 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff, 1021 CPU64Regs:$dst), 1022 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>; 1023} 1024 1025/// Multiply and Divide Instructions. 1026def MULT : MMRel, Mult<"mult", IIImult, CPURegsOpnd, [HI, LO]>, 1027 MULT_FM<0, 0x18>; 1028def MULTu : MMRel, Mult<"multu", IIImult, CPURegsOpnd, [HI, LO]>, 1029 MULT_FM<0, 0x19>; 1030def PseudoMULT : MultDivPseudo<MULT, ACRegs, CPURegsOpnd, MipsMult, IIImult>; 1031def PseudoMULTu : MultDivPseudo<MULTu, ACRegs, CPURegsOpnd, MipsMultu, IIImult>; 1032def SDIV : Div<"div", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1a>; 1033def UDIV : Div<"divu", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1b>; 1034def PseudoSDIV : MultDivPseudo<SDIV, ACRegs, CPURegsOpnd, MipsDivRem, IIIdiv, 1035 0, 1, 1>; 1036def PseudoUDIV : MultDivPseudo<UDIV, ACRegs, CPURegsOpnd, MipsDivRemU, IIIdiv, 1037 0, 1, 1>; 1038 1039def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; 1040def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; 1041def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; 1042def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; 1043 1044/// Sign Ext In Register Instructions. 1045def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>; 1046def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>; 1047 1048/// Count Leading 1049def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>; 1050def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>; 1051 1052/// Word Swap Bytes Within Halfwords 1053def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>; 1054 1055/// No operation. 1056def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 1057 1058// FrameIndexes are legalized when they are operands from load/store 1059// instructions. The same not happens for stack address copies, so an 1060// add op with mem ComplexPattern is used and the stack address copy 1061// can be matched. It's similar to Sparc LEA_ADDRi 1062def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>; 1063 1064// MADD*/MSUB* 1065def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>; 1066def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>; 1067def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>; 1068def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>; 1069def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>; 1070def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>; 1071def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>; 1072def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>; 1073 1074def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM; 1075 1076def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>; 1077def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>; 1078 1079/// Move Control Registers From/To CPU Registers 1080def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 1081 (ins CPURegsOpnd:$rd, uimm16:$sel), 1082 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>; 1083 1084def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 1085 (ins CPURegsOpnd:$rt), 1086 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>; 1087 1088def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 1089 (ins CPURegsOpnd:$rd, uimm16:$sel), 1090 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>; 1091 1092def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 1093 (ins CPURegsOpnd:$rt), 1094 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>; 1095 1096//===----------------------------------------------------------------------===// 1097// Instruction aliases 1098//===----------------------------------------------------------------------===// 1099def : InstAlias<"move $dst, $src", 1100 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 1101 Requires<[NotMips64]>; 1102def : InstAlias<"move $dst, $src", 1103 (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 1104 Requires<[NotMips64]>; 1105def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>; 1106def : InstAlias<"addu $rs, $rt, $imm", 1107 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1108def : InstAlias<"add $rs, $rt, $imm", 1109 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1110def : InstAlias<"and $rs, $rt, $imm", 1111 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1112def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>, 1113 Requires<[NotMips64]>; 1114def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>; 1115def : InstAlias<"jal $rs", (JALR RA, CPURegs:$rs), 0>, Requires<[NotMips64]>; 1116def : InstAlias<"jal $rd,$rs", (JALR CPURegs:$rd, CPURegs:$rs), 0>, 1117 Requires<[NotMips64]>; 1118def : InstAlias<"not $rt, $rs", 1119 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>; 1120def : InstAlias<"neg $rt, $rs", 1121 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 1122def : InstAlias<"negu $rt, $rs", 1123 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 1124def : InstAlias<"slt $rs, $rt, $imm", 1125 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>; 1126def : InstAlias<"xor $rs, $rt, $imm", 1127 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>, 1128 Requires<[NotMips64]>; 1129def : InstAlias<"or $rs, $rt, $imm", 1130 (ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>, 1131 Requires<[NotMips64]>; 1132def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1133def : InstAlias<"mfc0 $rt, $rd", 1134 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1135def : InstAlias<"mtc0 $rt, $rd", 1136 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1137def : InstAlias<"mfc2 $rt, $rd", 1138 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1139def : InstAlias<"mtc2 $rt, $rd", 1140 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1141def : InstAlias<"bnez $rs,$offset", 1142 (BNE CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>, 1143 Requires<[NotMips64]>; 1144def : InstAlias<"beqz $rs,$offset", 1145 (BEQ CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>, 1146 Requires<[NotMips64]>; 1147def : InstAlias<"syscall", (SYSCALL 0), 1>; 1148 1149def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; 1150def : InstAlias<"break", (BREAK 0, 0), 1>; 1151//===----------------------------------------------------------------------===// 1152// Assembler Pseudo Instructions 1153//===----------------------------------------------------------------------===// 1154 1155class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1156 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1157 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1158def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>; 1159 1160class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1161 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1162 !strconcat(instr_asm, "\t$rt, $addr")> ; 1163def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>; 1164 1165class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1166 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1167 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1168def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>; 1169 1170 1171 1172//===----------------------------------------------------------------------===// 1173// Arbitrary patterns that map to one or more instructions 1174//===----------------------------------------------------------------------===// 1175 1176// Load/store pattern templates. 1177class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 1178 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 1179 1180class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 1181 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 1182 1183// Small immediates 1184def : MipsPat<(i32 immSExt16:$in), 1185 (ADDiu ZERO, imm:$in)>; 1186def : MipsPat<(i32 immZExt16:$in), 1187 (ORi ZERO, imm:$in)>; 1188def : MipsPat<(i32 immLow16Zero:$in), 1189 (LUi (HI16 imm:$in))>; 1190 1191// Arbitrary immediates 1192def : MipsPat<(i32 imm:$imm), 1193 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1194 1195// Carry MipsPatterns 1196def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1197 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1198let Predicates = [HasStdEnc, NotDSP] in { 1199 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1200 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1201 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1202 (ADDiu CPURegs:$src, imm:$imm)>; 1203} 1204 1205// Call 1206def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1207 (JAL tglobaladdr:$dst)>; 1208def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1209 (JAL texternalsym:$dst)>; 1210//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1211// (JALR CPURegs:$dst)>; 1212 1213// Tail call 1214def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1215 (TAILCALL tglobaladdr:$dst)>; 1216def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1217 (TAILCALL texternalsym:$dst)>; 1218// hi/lo relocs 1219def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1220def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1221def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1222def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1223def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1224def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1225 1226def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1227def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1228def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1229def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1230def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1231def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1232 1233def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1234 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1235def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1236 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1237def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1238 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1239def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1240 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1241def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1242 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1243 1244// gp_rel relocs 1245def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1246 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1247def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1248 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1249 1250// wrapper_pic 1251class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1252 MipsPat<(MipsWrapper RC:$gp, node:$in), 1253 (ADDiuOp RC:$gp, node:$in)>; 1254 1255def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1256def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1257def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1258def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1259def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1260def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1261 1262// Mips does not have "not", so we expand our way 1263def : MipsPat<(not CPURegs:$in), 1264 (NOR CPURegsOpnd:$in, ZERO)>; 1265 1266// extended loads 1267let Predicates = [NotN64, HasStdEnc] in { 1268 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1269 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1270 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1271} 1272let Predicates = [IsN64, HasStdEnc] in { 1273 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1274 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1275 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1276} 1277 1278// peepholes 1279let Predicates = [NotN64, HasStdEnc] in { 1280 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1281} 1282let Predicates = [IsN64, HasStdEnc] in { 1283 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1284} 1285 1286// brcond patterns 1287multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1288 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1289 Instruction SLTiuOp, Register ZEROReg> { 1290def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1291 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1292def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1293 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1294 1295def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1296 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1297def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1298 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1299def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1300 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1301def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1302 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1303def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1304 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1305def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1306 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1307 1308def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1309 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1310def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1311 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1312 1313def : MipsPat<(brcond RC:$cond, bb:$dst), 1314 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1315} 1316 1317defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1318 1319def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), 1320 (BLEZ i32:$lhs, bb:$dst)>; 1321def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), 1322 (BGEZ i32:$lhs, bb:$dst)>; 1323 1324// setcc patterns 1325multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1326 Instruction SLTuOp, Register ZEROReg> { 1327 def : MipsPat<(seteq RC:$lhs, 0), 1328 (SLTiuOp RC:$lhs, 1)>; 1329 def : MipsPat<(setne RC:$lhs, 0), 1330 (SLTuOp ZEROReg, RC:$lhs)>; 1331 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1332 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1333 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1334 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1335} 1336 1337multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1338 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1339 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1340 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1341 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1342} 1343 1344multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1345 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1346 (SLTOp RC:$rhs, RC:$lhs)>; 1347 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1348 (SLTuOp RC:$rhs, RC:$lhs)>; 1349} 1350 1351multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1352 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1353 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1354 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1355 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1356} 1357 1358multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1359 Instruction SLTiuOp> { 1360 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1361 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1362 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1363 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1364} 1365 1366defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1367defm : SetlePats<CPURegs, SLT, SLTu>; 1368defm : SetgtPats<CPURegs, SLT, SLTu>; 1369defm : SetgePats<CPURegs, SLT, SLTu>; 1370defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1371 1372// bswap pattern 1373def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1374 1375// mflo/hi patterns. 1376def : MipsPat<(i32 (ExtractLOHI ACRegs:$ac, imm:$lohi_idx)), 1377 (EXTRACT_SUBREG ACRegs:$ac, imm:$lohi_idx)>; 1378 1379// Load halfword/word patterns. 1380let AddedComplexity = 40 in { 1381 let Predicates = [NotN64, HasStdEnc] in { 1382 def : LoadRegImmPat<LBu, i32, zextloadi8>; 1383 def : LoadRegImmPat<LH, i32, sextloadi16>; 1384 def : LoadRegImmPat<LW, i32, load>; 1385 } 1386 let Predicates = [IsN64, HasStdEnc] in { 1387 def : LoadRegImmPat<LBu_P8, i32, zextloadi8>; 1388 def : LoadRegImmPat<LH_P8, i32, sextloadi16>; 1389 def : LoadRegImmPat<LW_P8, i32, load>; 1390 } 1391} 1392 1393//===----------------------------------------------------------------------===// 1394// Floating Point Support 1395//===----------------------------------------------------------------------===// 1396 1397include "MipsInstrFPU.td" 1398include "Mips64InstrInfo.td" 1399include "MipsCondMov.td" 1400 1401// 1402// Mips16 1403 1404include "Mips16InstrFormats.td" 1405include "Mips16InstrInfo.td" 1406 1407// DSP 1408include "MipsDSPInstrFormats.td" 1409include "MipsDSPInstrInfo.td" 1410 1411// Micromips 1412include "MicroMipsInstrFormats.td" 1413include "MicroMipsInstrInfo.td" 1414