MipsInstrInfo.td revision 1d04ca7987ef0abb5be07b11e3bb9c9e756a1fce
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>, 27 SDTCisVT<2, i32>]>; 28def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 29 SDTCisVT<1, i32>, 30 SDTCisSameAs<1, 2>]>; 31def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 32 SDTCisSameAs<1, 2>]>; 33def SDT_MipsMAddMSub : SDTypeProfile<1, 3, 34 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 35 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 36def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 37 38def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 39 40def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 41 42def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 44def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 45 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 46 SDTCisSameAs<0, 4>]>; 47 48def SDTMipsLoadLR : SDTypeProfile<1, 2, 49 [SDTCisInt<0>, SDTCisPtrTy<1>, 50 SDTCisSameAs<0, 2>]>; 51 52// Call 53def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 55 SDNPVariadic]>; 56 57// Tail call 58def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 59 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 60 61// Hi and Lo nodes are used to handle global addresses. Used on 62// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 63// static model. (nothing to do with Mips Registers Hi and Lo) 64def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 65def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 66def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 67 68// TlsGd node is used to handle General Dynamic TLS 69def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 70 71// TprelHi and TprelLo nodes are used to handle Local Exec TLS 72def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 73def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 74 75// Thread pointer 76def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 77 78// Return 79def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 80 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 81 82// These are target-independent nodes, but have target-specific formats. 83def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 84 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 85def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 86 [SDNPHasChain, SDNPSideEffect, 87 SDNPOptInGlue, SDNPOutGlue]>; 88 89// Node used to extract integer from LO/HI register. 90def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>; 91 92// Node used to insert 32-bit integers to LOHI register pair. 93def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>; 94 95// Mult nodes. 96def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 97def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 98 99// MAdd*/MSub* nodes 100def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 101def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 102def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 103def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 104 105// DivRem(u) nodes 106def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 107def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 108def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, 109 [SDNPOutGlue]>; 110def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 111 [SDNPOutGlue]>; 112 113// Target constant nodes that are not part of any isel patterns and remain 114// unchanged can cause instructions with illegal operands to be emitted. 115// Wrapper node patterns give the instruction selector a chance to replace 116// target constant nodes that would otherwise remain unchanged with ADDiu 117// nodes. Without these wrapper node patterns, the following conditional move 118// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 119// compiled: 120// movn %got(d)($gp), %got(c)($gp), $4 121// This instruction is illegal since movn can take only register operands. 122 123def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 124 125def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 126 127def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 128def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 129 130def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 132def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 134def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 136def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 138def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 140def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 142def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 144def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 146 147//===----------------------------------------------------------------------===// 148// Mips Instruction Predicate Definitions. 149//===----------------------------------------------------------------------===// 150def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 151 AssemblerPredicate<"FeatureSEInReg">; 152def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 153 AssemblerPredicate<"FeatureBitCount">; 154def HasSwap : Predicate<"Subtarget.hasSwap()">, 155 AssemblerPredicate<"FeatureSwap">; 156def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 157 AssemblerPredicate<"FeatureCondMov">; 158def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 159 AssemblerPredicate<"FeatureFPIdx">; 160def HasMips32 : Predicate<"Subtarget.hasMips32()">, 161 AssemblerPredicate<"FeatureMips32">; 162def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 163 AssemblerPredicate<"FeatureMips32r2">; 164def HasMips64 : Predicate<"Subtarget.hasMips64()">, 165 AssemblerPredicate<"FeatureMips64">; 166def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 167 AssemblerPredicate<"!FeatureMips64">; 168def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 169 AssemblerPredicate<"FeatureMips64r2">; 170def IsN64 : Predicate<"Subtarget.isABI_N64()">, 171 AssemblerPredicate<"FeatureN64">; 172def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 173 AssemblerPredicate<"!FeatureN64">; 174def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 175 AssemblerPredicate<"FeatureMips16">; 176def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 177 AssemblerPredicate<"FeatureMips32">; 178def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 179 AssemblerPredicate<"FeatureMips32">; 180def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 181 AssemblerPredicate<"FeatureMips32">; 182def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 183 AssemblerPredicate<"!FeatureMips16,!FeatureMicroMips">; 184def NotDSP : Predicate<"!Subtarget.hasDSP()">; 185def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">, 186 AssemblerPredicate<"FeatureMicroMips">; 187def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">, 188 AssemblerPredicate<"!FeatureMicroMips">; 189def IsLE : Predicate<"Subtarget.isLittle()">; 190def IsBE : Predicate<"!Subtarget.isLittle()">; 191 192class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 193 let Predicates = [HasStdEnc]; 194} 195 196class IsCommutable { 197 bit isCommutable = 1; 198} 199 200class IsBranch { 201 bit isBranch = 1; 202} 203 204class IsReturn { 205 bit isReturn = 1; 206} 207 208class IsCall { 209 bit isCall = 1; 210} 211 212class IsTailCall { 213 bit isCall = 1; 214 bit isTerminator = 1; 215 bit isReturn = 1; 216 bit isBarrier = 1; 217 bit hasExtraSrcRegAllocReq = 1; 218 bit isCodeGenOnly = 1; 219} 220 221class IsAsCheapAsAMove { 222 bit isAsCheapAsAMove = 1; 223} 224 225class NeverHasSideEffects { 226 bit neverHasSideEffects = 1; 227} 228 229//===----------------------------------------------------------------------===// 230// Instruction format superclass 231//===----------------------------------------------------------------------===// 232 233include "MipsInstrFormats.td" 234 235//===----------------------------------------------------------------------===// 236// Mips Operand, Complex Patterns and Transformations Definitions. 237//===----------------------------------------------------------------------===// 238 239// Instruction operand types 240def jmptarget : Operand<OtherVT> { 241 let EncoderMethod = "getJumpTargetOpValue"; 242} 243def brtarget : Operand<OtherVT> { 244 let EncoderMethod = "getBranchTargetOpValue"; 245 let OperandType = "OPERAND_PCREL"; 246 let DecoderMethod = "DecodeBranchTarget"; 247} 248def calltarget : Operand<iPTR> { 249 let EncoderMethod = "getJumpTargetOpValue"; 250} 251def calltarget64: Operand<i64>; 252def simm16 : Operand<i32> { 253 let DecoderMethod= "DecodeSimm16"; 254} 255 256def simm20 : Operand<i32> { 257} 258 259def uimm20 : Operand<i32> { 260} 261 262def uimm10 : Operand<i32> { 263} 264 265def simm16_64 : Operand<i64>; 266def shamt : Operand<i32>; 267 268// Unsigned Operand 269def uimm5 : Operand<i32> { 270 let PrintMethod = "printUnsignedImm"; 271} 272 273def uimm16 : Operand<i32> { 274 let PrintMethod = "printUnsignedImm"; 275} 276 277def MipsMemAsmOperand : AsmOperandClass { 278 let Name = "Mem"; 279 let ParserMethod = "parseMemOperand"; 280} 281 282def PtrRegAsmOperand : AsmOperandClass { 283 let Name = "PtrReg"; 284 let ParserMethod = "parsePtrReg"; 285} 286 287// Address operand 288def mem : Operand<iPTR> { 289 let PrintMethod = "printMemOperand"; 290 let MIOperandInfo = (ops ptr_rc, simm16); 291 let EncoderMethod = "getMemEncoding"; 292 let ParserMatchClass = MipsMemAsmOperand; 293 let OperandType = "OPERAND_MEMORY"; 294} 295 296def mem_ea : Operand<iPTR> { 297 let PrintMethod = "printMemOperandEA"; 298 let MIOperandInfo = (ops ptr_rc, simm16); 299 let EncoderMethod = "getMemEncoding"; 300 let OperandType = "OPERAND_MEMORY"; 301} 302 303def PtrRC : Operand<iPTR> { 304 let MIOperandInfo = (ops ptr_rc); 305 let DecoderMethod = "DecodePtrRegisterClass"; 306 let ParserMatchClass = PtrRegAsmOperand; 307} 308 309// size operand of ext instruction 310def size_ext : Operand<i32> { 311 let EncoderMethod = "getSizeExtEncoding"; 312 let DecoderMethod = "DecodeExtSize"; 313} 314 315// size operand of ins instruction 316def size_ins : Operand<i32> { 317 let EncoderMethod = "getSizeInsEncoding"; 318 let DecoderMethod = "DecodeInsSize"; 319} 320 321// Transformation Function - get the lower 16 bits. 322def LO16 : SDNodeXForm<imm, [{ 323 return getImm(N, N->getZExtValue() & 0xFFFF); 324}]>; 325 326// Transformation Function - get the higher 16 bits. 327def HI16 : SDNodeXForm<imm, [{ 328 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 329}]>; 330 331// Plus 1. 332def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 333 334// Node immediate fits as 16-bit sign extended on target immediate. 335// e.g. addi, andi 336def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 337 338// Node immediate fits as 16-bit sign extended on target immediate. 339// e.g. addi, andi 340def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 341 342// Node immediate fits as 15-bit sign extended on target immediate. 343// e.g. addi, andi 344def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 345 346// Node immediate fits as 16-bit zero extended on target immediate. 347// The LO16 param means that only the lower 16 bits of the node 348// immediate are caught. 349// e.g. addiu, sltiu 350def immZExt16 : PatLeaf<(imm), [{ 351 if (N->getValueType(0) == MVT::i32) 352 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 353 else 354 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 355}], LO16>; 356 357// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 358def immLow16Zero : PatLeaf<(imm), [{ 359 int64_t Val = N->getSExtValue(); 360 return isInt<32>(Val) && !(Val & 0xffff); 361}]>; 362 363// shamt field must fit in 5 bits. 364def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 365 366// True if (N + 1) fits in 16-bit field. 367def immSExt16Plus1 : PatLeaf<(imm), [{ 368 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 369}]>; 370 371// Mips Address Mode! SDNode frameindex could possibily be a match 372// since load and store instructions from stack used it. 373def addr : 374 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 375 376def addrRegImm : 377 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 378 379def addrRegReg : 380 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>; 381 382def addrDefault : 383 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 384 385//===----------------------------------------------------------------------===// 386// Instructions specific format 387//===----------------------------------------------------------------------===// 388 389// Arithmetic and logical instructions with 3 register operands. 390class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 391 InstrItinClass Itin = NoItinerary, 392 SDPatternOperator OpNode = null_frag>: 393 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 394 !strconcat(opstr, "\t$rd, $rs, $rt"), 395 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { 396 let isCommutable = isComm; 397 let isReMaterializable = 1; 398} 399 400// Arithmetic and logical instructions with 2 register operands. 401class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 402 InstrItinClass Itin = NoItinerary, 403 SDPatternOperator imm_type = null_frag, 404 SDPatternOperator OpNode = null_frag> : 405 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 406 !strconcat(opstr, "\t$rt, $rs, $imm16"), 407 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], 408 Itin, FrmI, opstr> { 409 let isReMaterializable = 1; 410 let TwoOperandAliasConstraint = "$rs = $rt"; 411} 412 413// Arithmetic Multiply ADD/SUB 414class MArithR<string opstr, bit isComm = 0> : 415 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 416 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR, opstr> { 417 let Defs = [HI0, LO0]; 418 let Uses = [HI0, LO0]; 419 let isCommutable = isComm; 420} 421 422// Logical 423class LogicNOR<string opstr, RegisterOperand RO>: 424 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 425 !strconcat(opstr, "\t$rd, $rs, $rt"), 426 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> { 427 let isCommutable = 1; 428} 429 430// Shifts 431class shift_rotate_imm<string opstr, Operand ImmOpnd, 432 RegisterOperand RO, SDPatternOperator OpNode = null_frag, 433 SDPatternOperator PF = null_frag> : 434 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), 435 !strconcat(opstr, "\t$rd, $rt, $shamt"), 436 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>; 437 438class shift_rotate_reg<string opstr, RegisterOperand RO, 439 SDPatternOperator OpNode = null_frag>: 440 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs), 441 !strconcat(opstr, "\t$rd, $rt, $rs"), 442 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>; 443 444// Load Upper Imediate 445class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>: 446 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 447 [], IIArith, FrmI>, IsAsCheapAsAMove { 448 let neverHasSideEffects = 1; 449 let isReMaterializable = 1; 450} 451 452class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 453 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 454 bits<21> addr; 455 let Inst{25-21} = addr{20-16}; 456 let Inst{15-0} = addr{15-0}; 457 let DecoderMethod = "DecodeMem"; 458} 459 460// Memory Load/Store 461class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 462 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 463 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 464 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> { 465 let DecoderMethod = "DecodeMem"; 466 let canFoldAsLoad = 1; 467 let mayLoad = 1; 468} 469 470class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 471 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 472 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 473 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> { 474 let DecoderMethod = "DecodeMem"; 475 let mayStore = 1; 476} 477 478// Load/Store Left/Right 479let canFoldAsLoad = 1 in 480class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 481 InstrItinClass Itin> : 482 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src), 483 !strconcat(opstr, "\t$rt, $addr"), 484 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> { 485 let DecoderMethod = "DecodeMem"; 486 string Constraints = "$src = $rt"; 487} 488 489class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 490 InstrItinClass Itin> : 491 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 492 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> { 493 let DecoderMethod = "DecodeMem"; 494} 495 496// Conditional Branch 497class CBranch<string opstr, PatFrag cond_op, RegisterOperand RO> : 498 InstSE<(outs), (ins RO:$rs, RO:$rt, brtarget:$offset), 499 !strconcat(opstr, "\t$rs, $rt, $offset"), 500 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch, 501 FrmI> { 502 let isBranch = 1; 503 let isTerminator = 1; 504 let hasDelaySlot = 1; 505 let Defs = [AT]; 506} 507 508class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RO> : 509 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 510 !strconcat(opstr, "\t$rs, $offset"), 511 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 512 let isBranch = 1; 513 let isTerminator = 1; 514 let hasDelaySlot = 1; 515 let Defs = [AT]; 516} 517 518// SetCC 519class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> : 520 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt), 521 !strconcat(opstr, "\t$rd, $rs, $rt"), 522 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))], 523 IIslt, FrmR, opstr>; 524 525class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 526 RegisterOperand RO>: 527 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16), 528 !strconcat(opstr, "\t$rt, $rs, $imm16"), 529 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))], 530 IIslt, FrmI, opstr>; 531 532// Jump 533class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 534 SDPatternOperator targetoperator> : 535 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 536 [(operator targetoperator:$target)], IIBranch, FrmJ> { 537 let isTerminator=1; 538 let isBarrier=1; 539 let hasDelaySlot = 1; 540 let DecoderMethod = "DecodeJumpTarget"; 541 let Defs = [AT]; 542} 543 544// Unconditional branch 545class UncondBranch<Instruction BEQInst> : 546 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>, 547 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> { 548 let isBranch = 1; 549 let isTerminator = 1; 550 let isBarrier = 1; 551 let hasDelaySlot = 1; 552 let Predicates = [RelocPIC, HasStdEnc]; 553 let Defs = [AT]; 554} 555 556// Base class for indirect branch and return instruction classes. 557let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 558class JumpFR<RegisterOperand RO, SDPatternOperator operator = null_frag>: 559 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, FrmR>; 560 561// Indirect branch 562class IndirectBranch<RegisterOperand RO>: JumpFR<RO, brind> { 563 let isBranch = 1; 564 let isIndirectBranch = 1; 565} 566 567// Return instruction 568class RetBase<RegisterOperand RO>: JumpFR<RO> { 569 let isReturn = 1; 570 let isCodeGenOnly = 1; 571 let hasCtrlDep = 1; 572 let hasExtraSrcRegAllocReq = 1; 573} 574 575// Jump and Link (Call) 576let isCall=1, hasDelaySlot=1, Defs = [RA] in { 577 class JumpLink<string opstr> : 578 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 579 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 580 let DecoderMethod = "DecodeJumpTarget"; 581 } 582 583 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst, 584 Register RetReg, RegisterOperand ResRO = RO>: 585 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>, 586 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>; 587 588 class JumpLinkReg<string opstr, RegisterOperand RO>: 589 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 590 [], IIBranch, FrmR>; 591 592 class BGEZAL_FT<string opstr, RegisterOperand RO> : 593 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 594 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 595 596} 597 598class BAL_BR_Pseudo<Instruction RealInst> : 599 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>, 600 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> { 601 let isBranch = 1; 602 let isTerminator = 1; 603 let isBarrier = 1; 604 let hasDelaySlot = 1; 605 let Defs = [RA]; 606} 607 608// Syscall 609class SYS_FT<string opstr> : 610 InstSE<(outs), (ins uimm20:$code_), 611 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>; 612// Break 613class BRK_FT<string opstr> : 614 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2), 615 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>; 616 617// (D)Eret 618class ER_FT<string opstr> : 619 InstSE<(outs), (ins), 620 opstr, [], NoItinerary, FrmOther>; 621 622// Interrupts 623class DEI_FT<string opstr, RegisterOperand RO> : 624 InstSE<(outs RO:$rt), (ins), 625 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>; 626 627// Wait 628class WAIT_FT<string opstr> : 629 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther> { 630 let Inst{31-26} = 0x10; 631 let Inst{25} = 1; 632 let Inst{24-6} = 0; 633 let Inst{5-0} = 0x20; 634} 635 636// Sync 637let hasSideEffects = 1 in 638class SYNC_FT : 639 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 640 NoItinerary, FrmOther>; 641 642let hasSideEffects = 1 in 643class TEQ_FT<string opstr, RegisterOperand RO> : 644 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_), 645 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>; 646 647class TEQI_FT<string opstr, RegisterOperand RO> : 648 InstSE<(outs), (ins RO:$rs, uimm16:$imm16), 649 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther>; 650// Mul, Div 651class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 652 list<Register> DefRegs> : 653 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 654 itin, FrmR, opstr> { 655 let isCommutable = 1; 656 let Defs = DefRegs; 657 let neverHasSideEffects = 1; 658} 659 660// Pseudo multiply/divide instruction with explicit accumulator register 661// operands. 662class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 663 SDPatternOperator OpNode, InstrItinClass Itin, 664 bit IsComm = 1, bit HasSideEffects = 0, 665 bit UsesCustomInserter = 0> : 666 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 667 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 668 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 669 let isCommutable = IsComm; 670 let hasSideEffects = HasSideEffects; 671 let usesCustomInserter = UsesCustomInserter; 672} 673 674// Pseudo multiply add/sub instruction with explicit accumulator register 675// operands. 676class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode> 677 : PseudoSE<(outs ACC64:$ac), 678 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin), 679 [(set ACC64:$ac, 680 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))], 681 IIImult>, 682 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> { 683 string Constraints = "$acin = $ac"; 684} 685 686class Div<string opstr, InstrItinClass itin, RegisterOperand RO, 687 list<Register> DefRegs> : 688 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 689 [], itin, FrmR> { 690 let Defs = DefRegs; 691} 692 693// Move from Hi/Lo 694class MoveFromLOHI<string opstr, RegisterOperand RO, list<Register> UseRegs>: 695 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, 696 FrmR, opstr> { 697 let Uses = UseRegs; 698 let neverHasSideEffects = 1; 699} 700 701class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>: 702 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, 703 FrmR, opstr> { 704 let Defs = DefRegs; 705 let neverHasSideEffects = 1; 706} 707 708class EffectiveAddress<string opstr, RegisterOperand RO> : 709 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"), 710 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> { 711 let isCodeGenOnly = 1; 712 let DecoderMethod = "DecodeMem"; 713} 714 715// Count Leading Ones/Zeros in Word 716class CountLeading0<string opstr, RegisterOperand RO>: 717 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 718 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR>, 719 Requires<[HasBitCount, HasStdEnc]>; 720 721class CountLeading1<string opstr, RegisterOperand RO>: 722 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 723 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR>, 724 Requires<[HasBitCount, HasStdEnc]>; 725 726 727// Sign Extend in Register. 728class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> : 729 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), 730 [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR> { 731 let Predicates = [HasSEInReg, HasStdEnc]; 732} 733 734// Subword Swap 735class SubwordSwap<string opstr, RegisterOperand RO>: 736 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 737 NoItinerary, FrmR> { 738 let Predicates = [HasSwap, HasStdEnc]; 739 let neverHasSideEffects = 1; 740} 741 742// Read Hardware 743class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> : 744 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 745 IIArith, FrmR>; 746 747// Ext and Ins 748class ExtBase<string opstr, RegisterOperand RO>: 749 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size), 750 !strconcat(opstr, " $rt, $rs, $pos, $size"), 751 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary, 752 FrmR> { 753 let Predicates = [HasMips32r2, HasStdEnc]; 754} 755 756class InsBase<string opstr, RegisterOperand RO>: 757 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src), 758 !strconcat(opstr, " $rt, $rs, $pos, $size"), 759 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))], 760 NoItinerary, FrmR> { 761 let Predicates = [HasMips32r2, HasStdEnc]; 762 let Constraints = "$src = $rt"; 763} 764 765// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 766class Atomic2Ops<PatFrag Op, RegisterClass DRC> : 767 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr), 768 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>; 769 770// Atomic Compare & Swap. 771class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> : 772 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap), 773 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>; 774 775class LLBase<string opstr, RegisterOperand RO> : 776 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 777 [], NoItinerary, FrmI> { 778 let DecoderMethod = "DecodeMem"; 779 let mayLoad = 1; 780} 781 782class SCBase<string opstr, RegisterOperand RO> : 783 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr), 784 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 785 let DecoderMethod = "DecodeMem"; 786 let mayStore = 1; 787 let Constraints = "$rt = $dst"; 788} 789 790class MFC3OP<string asmstr, RegisterOperand RO> : 791 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins), 792 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>; 793 794let isBarrier = 1, isTerminator = 1, isCodeGenOnly = 1 in 795def TRAP : InstSE<(outs), (ins), "break", [(trap)], NoItinerary, FrmOther> { 796 let Inst = 0x0000000d; 797} 798 799//===----------------------------------------------------------------------===// 800// Pseudo instructions 801//===----------------------------------------------------------------------===// 802 803// Return RA. 804let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 805def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 806 807let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 808def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 809 [(callseq_start timm:$amt)]>; 810def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 811 [(callseq_end timm:$amt1, timm:$amt2)]>; 812} 813 814let usesCustomInserter = 1 in { 815 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>; 816 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>; 817 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>; 818 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>; 819 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>; 820 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>; 821 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>; 822 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>; 823 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>; 824 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>; 825 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>; 826 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>; 827 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>; 828 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>; 829 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>; 830 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>; 831 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>; 832 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>; 833 834 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>; 835 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>; 836 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>; 837 838 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>; 839 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>; 840 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>; 841} 842 843/// Pseudo instructions for loading and storing accumulator registers. 844let isPseudo = 1, isCodeGenOnly = 1 in { 845 def LOAD_ACC64 : Load<"", ACC64>; 846 def STORE_ACC64 : Store<"", ACC64>; 847} 848 849//===----------------------------------------------------------------------===// 850// Instruction definition 851//===----------------------------------------------------------------------===// 852//===----------------------------------------------------------------------===// 853// MipsI Instructions 854//===----------------------------------------------------------------------===// 855 856/// Arithmetic Instructions (ALU Immediate) 857def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16, 858 add>, 859 ADDI_FM<0x9>, IsAsCheapAsAMove; 860def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>; 861def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, 862 SLTI_FM<0xa>; 863def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, 864 SLTI_FM<0xb>; 865def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16, 866 and>, 867 ADDI_FM<0xc>; 868def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16, 869 or>, 870 ADDI_FM<0xd>; 871def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16, 872 xor>, 873 ADDI_FM<0xe>; 874def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM; 875 876/// Arithmetic Instructions (3-Operand, R-Type) 877def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>, 878 ADD_FM<0, 0x21>; 879def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>, 880 ADD_FM<0, 0x23>; 881def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>, 882 ADD_FM<0x1c, 2>; 883def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>; 884def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>; 885def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; 886def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; 887def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>, 888 ADD_FM<0, 0x24>; 889def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>, 890 ADD_FM<0, 0x25>; 891def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>, 892 ADD_FM<0, 0x26>; 893def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; 894 895/// Shift Instructions 896def SLL : MMRel, shift_rotate_imm<"sll", shamt, GPR32Opnd, shl, immZExt5>, 897 SRA_FM<0, 0>; 898def SRL : MMRel, shift_rotate_imm<"srl", shamt, GPR32Opnd, srl, immZExt5>, 899 SRA_FM<2, 0>; 900def SRA : MMRel, shift_rotate_imm<"sra", shamt, GPR32Opnd, sra, immZExt5>, 901 SRA_FM<3, 0>; 902def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>; 903def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>; 904def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>; 905 906// Rotate Instructions 907let Predicates = [HasMips32r2, HasStdEnc] in { 908 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, GPR32Opnd, rotr, 909 immZExt5>, 910 SRA_FM<2, 1>; 911 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>, 912 SRLV_FM<6, 1>; 913} 914 915/// Load and Store Instructions 916/// aligned 917def LB : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>; 918def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel, 919 LW_FM<0x24>; 920def LH : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel, 921 LW_FM<0x21>; 922def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>; 923def LW : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel, 924 LW_FM<0x23>; 925def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>; 926def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>; 927def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>; 928 929/// load/store left/right 930def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, IILoad>, LW_FM<0x22>; 931def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, IILoad>, LW_FM<0x26>; 932def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>; 933def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>; 934 935def SYNC : SYNC_FT, SYNC_FM; 936def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>; 937def TGE : TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>; 938def TGEU : TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>; 939def TLT : TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>; 940def TLTU : TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>; 941def TNE : TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>; 942 943def TEQI : TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>; 944def TGEI : TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>; 945def TGEIU : TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>; 946def TLTI : TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>; 947def TTLTIU : TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>; 948def TNEI : TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>; 949 950def BREAK : BRK_FT<"break">, BRK_FM<0xd>; 951def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>; 952 953def ERET : ER_FT<"eret">, ER_FM<0x18>; 954def DERET : ER_FT<"deret">, ER_FM<0x1f>; 955 956def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>; 957def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>; 958 959def WAIT : WAIT_FT<"wait">; 960 961/// Load-linked, Store-conditional 962def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>; 963def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>; 964 965/// Jump and Branch Instructions 966def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 967 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 968def JR : IndirectBranch<GPR32Opnd>, MTLO_FM<8>; 969def BEQ : CBranch<"beq", seteq, GPR32Opnd>, BEQ_FM<4>; 970def BNE : CBranch<"bne", setne, GPR32Opnd>, BEQ_FM<5>; 971def BGEZ : CBranchZero<"bgez", setge, GPR32Opnd>, BGEZ_FM<1, 1>; 972def BGTZ : CBranchZero<"bgtz", setgt, GPR32Opnd>, BGEZ_FM<7, 0>; 973def BLEZ : CBranchZero<"blez", setle, GPR32Opnd>, BGEZ_FM<6, 0>; 974def BLTZ : CBranchZero<"bltz", setlt, GPR32Opnd>, BGEZ_FM<1, 0>; 975def B : UncondBranch<BEQ>; 976 977def JAL : JumpLink<"jal">, FJ<3>; 978def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM; 979def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>; 980def BGEZAL : BGEZAL_FT<"bgezal", GPR32Opnd>, BGEZAL_FM<0x11>; 981def BLTZAL : BGEZAL_FT<"bltzal", GPR32Opnd>, BGEZAL_FM<0x10>; 982def BAL_BR : BAL_BR_Pseudo<BGEZAL>; 983def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 984def TAILCALL_R : JumpFR<GPR32Opnd, MipsTailCall>, MTLO_FM<8>, IsTailCall; 985 986def RET : RetBase<GPR32Opnd>, MTLO_FM<8>; 987 988// Exception handling related node and instructions. 989// The conversion sequence is: 990// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 991// MIPSeh_return -> (stack change + indirect branch) 992// 993// MIPSeh_return takes the place of regular return instruction 994// but takes two arguments (V1, V0) which are used for storing 995// the offset and return address respectively. 996def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 997 998def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 999 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 1000 1001let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 1002 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst), 1003 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>; 1004 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff, 1005 GPR64:$dst), 1006 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>; 1007} 1008 1009/// Multiply and Divide Instructions. 1010def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>, 1011 MULT_FM<0, 0x18>; 1012def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>, 1013 MULT_FM<0, 0x19>; 1014def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>; 1015def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>; 1016def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1a>; 1017def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1b>; 1018def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv, 1019 0, 1, 1>; 1020def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv, 1021 0, 1, 1>; 1022 1023def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>; 1024def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>; 1025def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, [HI0]>, MFLO_FM<0x10>; 1026def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, [LO0]>, MFLO_FM<0x12>; 1027 1028/// Sign Ext In Register Instructions. 1029def SEB : SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>; 1030def SEH : SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>; 1031 1032/// Count Leading 1033def CLZ : CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>; 1034def CLO : CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>; 1035 1036/// Word Swap Bytes Within Halfwords 1037def WSBH : SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>; 1038 1039/// No operation. 1040def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 1041 1042// FrameIndexes are legalized when they are operands from load/store 1043// instructions. The same not happens for stack address copies, so an 1044// add op with mem ComplexPattern is used and the stack address copy 1045// can be matched. It's similar to Sparc LEA_ADDRi 1046def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>; 1047 1048// MADD*/MSUB* 1049def MADD : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>; 1050def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>; 1051def MSUB : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>; 1052def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>; 1053def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>; 1054def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>; 1055def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>; 1056def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>; 1057 1058def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM; 1059 1060def EXT : ExtBase<"ext", GPR32Opnd>, EXT_FM<0>; 1061def INS : InsBase<"ins", GPR32Opnd>, EXT_FM<4>; 1062 1063/// Move Control Registers From/To CPU Registers 1064def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>; 1065def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>; 1066def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>; 1067def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>; 1068 1069//===----------------------------------------------------------------------===// 1070// Instruction aliases 1071//===----------------------------------------------------------------------===// 1072def : InstAlias<"move $dst, $src", 1073 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>, 1074 Requires<[NotMips64]>; 1075def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>; 1076def : InstAlias<"addu $rs, $rt, $imm", 1077 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1078def : InstAlias<"add $rs, $rt, $imm", 1079 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1080def : InstAlias<"and $rs, $rt, $imm", 1081 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1082def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>; 1083def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1084def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1085def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>; 1086def : InstAlias<"not $rt, $rs", 1087 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; 1088def : InstAlias<"neg $rt, $rs", 1089 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1090def : InstAlias<"negu $rt, $rs", 1091 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1092def : InstAlias<"slt $rs, $rt, $imm", 1093 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1094def : InstAlias<"xor $rs, $rt, $imm", 1095 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1096def : InstAlias<"or $rs, $rt, $imm", 1097 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1098def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1099def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1100def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1101def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1102def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1103def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>; 1104def : InstAlias<"bnez $rs,$offset", 1105 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1106def : InstAlias<"beqz $rs,$offset", 1107 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1108def : InstAlias<"syscall", (SYSCALL 0), 1>; 1109 1110def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; 1111def : InstAlias<"break", (BREAK 0, 0), 1>; 1112def : InstAlias<"ei", (EI ZERO), 1>; 1113def : InstAlias<"di", (DI ZERO), 1>; 1114 1115def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1116def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1117def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1118def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1119def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1120def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1121//===----------------------------------------------------------------------===// 1122// Assembler Pseudo Instructions 1123//===----------------------------------------------------------------------===// 1124 1125class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1126 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1127 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1128def LoadImm32Reg : LoadImm32<"li", shamt,GPR32Opnd>; 1129 1130class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1131 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1132 !strconcat(instr_asm, "\t$rt, $addr")> ; 1133def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>; 1134 1135class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1136 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1137 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1138def LoadAddr32Imm : LoadAddressImm<"la", shamt,GPR32Opnd>; 1139 1140 1141 1142//===----------------------------------------------------------------------===// 1143// Arbitrary patterns that map to one or more instructions 1144//===----------------------------------------------------------------------===// 1145 1146// Load/store pattern templates. 1147class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 1148 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 1149 1150class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 1151 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 1152 1153// Small immediates 1154def : MipsPat<(i32 immSExt16:$in), 1155 (ADDiu ZERO, imm:$in)>; 1156def : MipsPat<(i32 immZExt16:$in), 1157 (ORi ZERO, imm:$in)>; 1158def : MipsPat<(i32 immLow16Zero:$in), 1159 (LUi (HI16 imm:$in))>; 1160 1161// Arbitrary immediates 1162def : MipsPat<(i32 imm:$imm), 1163 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1164 1165// Carry MipsPatterns 1166def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), 1167 (SUBu GPR32:$lhs, GPR32:$rhs)>; 1168let Predicates = [HasStdEnc, NotDSP] in { 1169 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs), 1170 (ADDu GPR32:$lhs, GPR32:$rhs)>; 1171 def : MipsPat<(addc GPR32:$src, immSExt16:$imm), 1172 (ADDiu GPR32:$src, imm:$imm)>; 1173} 1174 1175// Call 1176def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1177 (JAL tglobaladdr:$dst)>; 1178def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1179 (JAL texternalsym:$dst)>; 1180//def : MipsPat<(MipsJmpLink GPR32:$dst), 1181// (JALR GPR32:$dst)>; 1182 1183// Tail call 1184def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1185 (TAILCALL tglobaladdr:$dst)>; 1186def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1187 (TAILCALL texternalsym:$dst)>; 1188// hi/lo relocs 1189def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1190def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1191def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1192def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1193def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1194def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1195 1196def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1197def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1198def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1199def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1200def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1201def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1202 1203def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)), 1204 (ADDiu GPR32:$hi, tglobaladdr:$lo)>; 1205def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)), 1206 (ADDiu GPR32:$hi, tblockaddress:$lo)>; 1207def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)), 1208 (ADDiu GPR32:$hi, tjumptable:$lo)>; 1209def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)), 1210 (ADDiu GPR32:$hi, tconstpool:$lo)>; 1211def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)), 1212 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>; 1213 1214// gp_rel relocs 1215def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)), 1216 (ADDiu GPR32:$gp, tglobaladdr:$in)>; 1217def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)), 1218 (ADDiu GPR32:$gp, tconstpool:$in)>; 1219 1220// wrapper_pic 1221class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1222 MipsPat<(MipsWrapper RC:$gp, node:$in), 1223 (ADDiuOp RC:$gp, node:$in)>; 1224 1225def : WrapperPat<tglobaladdr, ADDiu, GPR32>; 1226def : WrapperPat<tconstpool, ADDiu, GPR32>; 1227def : WrapperPat<texternalsym, ADDiu, GPR32>; 1228def : WrapperPat<tblockaddress, ADDiu, GPR32>; 1229def : WrapperPat<tjumptable, ADDiu, GPR32>; 1230def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>; 1231 1232// Mips does not have "not", so we expand our way 1233def : MipsPat<(not GPR32:$in), 1234 (NOR GPR32Opnd:$in, ZERO)>; 1235 1236// extended loads 1237let Predicates = [HasStdEnc] in { 1238 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1239 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1240 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1241} 1242 1243// peepholes 1244let Predicates = [HasStdEnc] in 1245def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1246 1247// brcond patterns 1248multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1249 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1250 Instruction SLTiuOp, Register ZEROReg> { 1251def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1252 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1253def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1254 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1255 1256def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1257 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1258def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1259 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1260def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1261 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1262def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1263 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1264def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1265 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1266def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1267 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1268 1269def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1270 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1271def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1272 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1273 1274def : MipsPat<(brcond RC:$cond, bb:$dst), 1275 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1276} 1277 1278defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1279 1280def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), 1281 (BLEZ i32:$lhs, bb:$dst)>; 1282def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), 1283 (BGEZ i32:$lhs, bb:$dst)>; 1284 1285// setcc patterns 1286multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1287 Instruction SLTuOp, Register ZEROReg> { 1288 def : MipsPat<(seteq RC:$lhs, 0), 1289 (SLTiuOp RC:$lhs, 1)>; 1290 def : MipsPat<(setne RC:$lhs, 0), 1291 (SLTuOp ZEROReg, RC:$lhs)>; 1292 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1293 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1294 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1295 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1296} 1297 1298multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1299 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1300 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1301 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1302 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1303} 1304 1305multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1306 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1307 (SLTOp RC:$rhs, RC:$lhs)>; 1308 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1309 (SLTuOp RC:$rhs, RC:$lhs)>; 1310} 1311 1312multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1313 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1314 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1315 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1316 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1317} 1318 1319multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1320 Instruction SLTiuOp> { 1321 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1322 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1323 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1324 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1325} 1326 1327defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>; 1328defm : SetlePats<GPR32, SLT, SLTu>; 1329defm : SetgtPats<GPR32, SLT, SLTu>; 1330defm : SetgePats<GPR32, SLT, SLTu>; 1331defm : SetgeImmPats<GPR32, SLTi, SLTiu>; 1332 1333// bswap pattern 1334def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>; 1335 1336// mflo/hi patterns. 1337def : MipsPat<(i32 (ExtractLOHI ACC64:$ac, imm:$lohi_idx)), 1338 (EXTRACT_SUBREG ACC64:$ac, imm:$lohi_idx)>; 1339 1340// Load halfword/word patterns. 1341let AddedComplexity = 40 in { 1342 let Predicates = [HasStdEnc] in { 1343 def : LoadRegImmPat<LBu, i32, zextloadi8>; 1344 def : LoadRegImmPat<LH, i32, sextloadi16>; 1345 def : LoadRegImmPat<LW, i32, load>; 1346 } 1347} 1348 1349//===----------------------------------------------------------------------===// 1350// Floating Point Support 1351//===----------------------------------------------------------------------===// 1352 1353include "MipsInstrFPU.td" 1354include "Mips64InstrInfo.td" 1355include "MipsCondMov.td" 1356 1357// 1358// Mips16 1359 1360include "Mips16InstrFormats.td" 1361include "Mips16InstrInfo.td" 1362 1363// DSP 1364include "MipsDSPInstrFormats.td" 1365include "MipsDSPInstrInfo.td" 1366 1367// MSA 1368include "MipsMSAInstrFormats.td" 1369include "MipsMSAInstrInfo.td" 1370 1371// Micromips 1372include "MicroMipsInstrFormats.td" 1373include "MicroMipsInstrInfo.td" 1374