MipsInstrInfo.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>; 27def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>; 29def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 30 SDTCisSameAs<1, 2>]>; 31def SDT_MipsMAddMSub : SDTypeProfile<1, 3, 32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 34def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 35 36def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 37 38def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 39 40def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 42def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 44 SDTCisSameAs<0, 4>]>; 45 46def SDTMipsLoadLR : SDTypeProfile<1, 2, 47 [SDTCisInt<0>, SDTCisPtrTy<1>, 48 SDTCisSameAs<0, 2>]>; 49 50// Call 51def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 53 SDNPVariadic]>; 54 55// Tail call 56def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 58 59// Hi and Lo nodes are used to handle global addresses. Used on 60// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 61// static model. (nothing to do with Mips Registers Hi and Lo) 62def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 63def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 64def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 65 66// TlsGd node is used to handle General Dynamic TLS 67def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 68 69// TprelHi and TprelLo nodes are used to handle Local Exec TLS 70def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 71def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 72 73// Thread pointer 74def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 75 76// Return 77def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 79 80// These are target-independent nodes, but have target-specific formats. 81def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 83def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 84 [SDNPHasChain, SDNPSideEffect, 85 SDNPOptInGlue, SDNPOutGlue]>; 86 87// Nodes used to extract LO/HI registers. 88def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>; 89def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>; 90 91// Node used to insert 32-bit integers to LOHI register pair. 92def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>; 93 94// Mult nodes. 95def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 96def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 97 98// MAdd*/MSub* nodes 99def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 100def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 101def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 102def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 103 104// DivRem(u) nodes 105def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 106def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 107def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, 108 [SDNPOutGlue]>; 109def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 110 [SDNPOutGlue]>; 111 112// Target constant nodes that are not part of any isel patterns and remain 113// unchanged can cause instructions with illegal operands to be emitted. 114// Wrapper node patterns give the instruction selector a chance to replace 115// target constant nodes that would otherwise remain unchanged with ADDiu 116// nodes. Without these wrapper node patterns, the following conditional move 117// instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 118// compiled: 119// movn %got(d)($gp), %got(c)($gp), $4 120// This instruction is illegal since movn can take only register operands. 121 122def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 123 124def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 125 126def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 127def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 128 129def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 131def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 133def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 135def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 137def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 139def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 141def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 143def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 145 146//===----------------------------------------------------------------------===// 147// Mips Instruction Predicate Definitions. 148//===----------------------------------------------------------------------===// 149def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 150 AssemblerPredicate<"FeatureSEInReg">; 151def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 152 AssemblerPredicate<"FeatureBitCount">; 153def HasSwap : Predicate<"Subtarget.hasSwap()">, 154 AssemblerPredicate<"FeatureSwap">; 155def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 156 AssemblerPredicate<"FeatureCondMov">; 157def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 158 AssemblerPredicate<"FeatureFPIdx">; 159def HasMips32 : Predicate<"Subtarget.hasMips32()">, 160 AssemblerPredicate<"FeatureMips32">; 161def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 162 AssemblerPredicate<"FeatureMips32r2">; 163def HasMips64 : Predicate<"Subtarget.hasMips64()">, 164 AssemblerPredicate<"FeatureMips64">; 165def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 166 AssemblerPredicate<"!FeatureMips64">; 167def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 168 AssemblerPredicate<"FeatureMips64r2">; 169def IsN64 : Predicate<"Subtarget.isABI_N64()">, 170 AssemblerPredicate<"FeatureN64">; 171def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 172 AssemblerPredicate<"FeatureMips16">; 173def HasCnMips : Predicate<"Subtarget.hasCnMips()">, 174 AssemblerPredicate<"FeatureCnMips">; 175def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 176 AssemblerPredicate<"FeatureMips32">; 177def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 178 AssemblerPredicate<"FeatureMips32">; 179def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 180 AssemblerPredicate<"FeatureMips32">; 181def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 182 AssemblerPredicate<"!FeatureMips16">; 183def NotDSP : Predicate<"!Subtarget.hasDSP()">; 184def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">, 185 AssemblerPredicate<"FeatureMicroMips">; 186def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">, 187 AssemblerPredicate<"!FeatureMicroMips">; 188def IsLE : Predicate<"Subtarget.isLittle()">; 189def IsBE : Predicate<"!Subtarget.isLittle()">; 190def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">; 191 192class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 193 let Predicates = [HasStdEnc]; 194} 195 196class IsCommutable { 197 bit isCommutable = 1; 198} 199 200class IsBranch { 201 bit isBranch = 1; 202} 203 204class IsReturn { 205 bit isReturn = 1; 206} 207 208class IsCall { 209 bit isCall = 1; 210} 211 212class IsTailCall { 213 bit isCall = 1; 214 bit isTerminator = 1; 215 bit isReturn = 1; 216 bit isBarrier = 1; 217 bit hasExtraSrcRegAllocReq = 1; 218 bit isCodeGenOnly = 1; 219} 220 221class IsAsCheapAsAMove { 222 bit isAsCheapAsAMove = 1; 223} 224 225class NeverHasSideEffects { 226 bit neverHasSideEffects = 1; 227} 228 229//===----------------------------------------------------------------------===// 230// Instruction format superclass 231//===----------------------------------------------------------------------===// 232 233include "MipsInstrFormats.td" 234 235//===----------------------------------------------------------------------===// 236// Mips Operand, Complex Patterns and Transformations Definitions. 237//===----------------------------------------------------------------------===// 238 239def MipsJumpTargetAsmOperand : AsmOperandClass { 240 let Name = "JumpTarget"; 241 let ParserMethod = "ParseJumpTarget"; 242 let PredicateMethod = "isImm"; 243 let RenderMethod = "addImmOperands"; 244} 245 246// Instruction operand types 247def jmptarget : Operand<OtherVT> { 248 let EncoderMethod = "getJumpTargetOpValue"; 249 let ParserMatchClass = MipsJumpTargetAsmOperand; 250} 251def brtarget : Operand<OtherVT> { 252 let EncoderMethod = "getBranchTargetOpValue"; 253 let OperandType = "OPERAND_PCREL"; 254 let DecoderMethod = "DecodeBranchTarget"; 255 let ParserMatchClass = MipsJumpTargetAsmOperand; 256} 257def calltarget : Operand<iPTR> { 258 let EncoderMethod = "getJumpTargetOpValue"; 259 let ParserMatchClass = MipsJumpTargetAsmOperand; 260} 261 262def simm10 : Operand<i32>; 263 264def simm16 : Operand<i32> { 265 let DecoderMethod= "DecodeSimm16"; 266} 267 268def simm20 : Operand<i32> { 269} 270 271def uimm20 : Operand<i32> { 272} 273 274def uimm10 : Operand<i32> { 275} 276 277def simm16_64 : Operand<i64> { 278 let DecoderMethod = "DecodeSimm16"; 279} 280 281// Zero 282def uimmz : Operand<i32> { 283 let PrintMethod = "printUnsignedImm"; 284} 285 286// Unsigned Operand 287def uimm5 : Operand<i32> { 288 let PrintMethod = "printUnsignedImm"; 289} 290 291def uimm6 : Operand<i32> { 292 let PrintMethod = "printUnsignedImm"; 293} 294 295def uimm16 : Operand<i32> { 296 let PrintMethod = "printUnsignedImm"; 297} 298 299def pcrel16 : Operand<i32> { 300} 301 302def MipsMemAsmOperand : AsmOperandClass { 303 let Name = "Mem"; 304 let ParserMethod = "parseMemOperand"; 305} 306 307def MipsInvertedImmoperand : AsmOperandClass { 308 let Name = "InvNum"; 309 let RenderMethod = "addImmOperands"; 310 let ParserMethod = "parseInvNum"; 311} 312 313def InvertedImOperand : Operand<i32> { 314 let ParserMatchClass = MipsInvertedImmoperand; 315} 316 317class mem_generic : Operand<iPTR> { 318 let PrintMethod = "printMemOperand"; 319 let MIOperandInfo = (ops ptr_rc, simm16); 320 let EncoderMethod = "getMemEncoding"; 321 let ParserMatchClass = MipsMemAsmOperand; 322 let OperandType = "OPERAND_MEMORY"; 323} 324 325// Address operand 326def mem : mem_generic; 327 328// MSA specific address operand 329def mem_msa : mem_generic { 330 let MIOperandInfo = (ops ptr_rc, simm10); 331 let EncoderMethod = "getMSAMemEncoding"; 332} 333 334def mem_ea : Operand<iPTR> { 335 let PrintMethod = "printMemOperandEA"; 336 let MIOperandInfo = (ops ptr_rc, simm16); 337 let EncoderMethod = "getMemEncoding"; 338 let OperandType = "OPERAND_MEMORY"; 339} 340 341def PtrRC : Operand<iPTR> { 342 let MIOperandInfo = (ops ptr_rc); 343 let DecoderMethod = "DecodePtrRegisterClass"; 344 let ParserMatchClass = GPR32AsmOperand; 345} 346 347// size operand of ext instruction 348def size_ext : Operand<i32> { 349 let EncoderMethod = "getSizeExtEncoding"; 350 let DecoderMethod = "DecodeExtSize"; 351} 352 353// size operand of ins instruction 354def size_ins : Operand<i32> { 355 let EncoderMethod = "getSizeInsEncoding"; 356 let DecoderMethod = "DecodeInsSize"; 357} 358 359// Transformation Function - get the lower 16 bits. 360def LO16 : SDNodeXForm<imm, [{ 361 return getImm(N, N->getZExtValue() & 0xFFFF); 362}]>; 363 364// Transformation Function - get the higher 16 bits. 365def HI16 : SDNodeXForm<imm, [{ 366 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 367}]>; 368 369// Plus 1. 370def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 371 372// Node immediate is zero (e.g. insve.d) 373def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>; 374 375// Node immediate fits as 16-bit sign extended on target immediate. 376// e.g. addi, andi 377def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 378 379// Node immediate fits as 16-bit sign extended on target immediate. 380// e.g. addi, andi 381def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 382 383// Node immediate fits as 15-bit sign extended on target immediate. 384// e.g. addi, andi 385def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 386 387// Node immediate fits as 16-bit zero extended on target immediate. 388// The LO16 param means that only the lower 16 bits of the node 389// immediate are caught. 390// e.g. addiu, sltiu 391def immZExt16 : PatLeaf<(imm), [{ 392 if (N->getValueType(0) == MVT::i32) 393 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 394 else 395 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 396}], LO16>; 397 398// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 399def immLow16Zero : PatLeaf<(imm), [{ 400 int64_t Val = N->getSExtValue(); 401 return isInt<32>(Val) && !(Val & 0xffff); 402}]>; 403 404// shamt field must fit in 5 bits. 405def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 406 407// True if (N + 1) fits in 16-bit field. 408def immSExt16Plus1 : PatLeaf<(imm), [{ 409 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 410}]>; 411 412// Mips Address Mode! SDNode frameindex could possibily be a match 413// since load and store instructions from stack used it. 414def addr : 415 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 416 417def addrRegImm : 418 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 419 420def addrRegReg : 421 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>; 422 423def addrDefault : 424 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 425 426def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>; 427 428//===----------------------------------------------------------------------===// 429// Instructions specific format 430//===----------------------------------------------------------------------===// 431 432// Arithmetic and logical instructions with 3 register operands. 433class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 434 InstrItinClass Itin = NoItinerary, 435 SDPatternOperator OpNode = null_frag>: 436 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 437 !strconcat(opstr, "\t$rd, $rs, $rt"), 438 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { 439 let isCommutable = isComm; 440 let isReMaterializable = 1; 441 let TwoOperandAliasConstraint = "$rd = $rs"; 442} 443 444// Arithmetic and logical instructions with 2 register operands. 445class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 446 InstrItinClass Itin = NoItinerary, 447 SDPatternOperator imm_type = null_frag, 448 SDPatternOperator OpNode = null_frag> : 449 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 450 !strconcat(opstr, "\t$rt, $rs, $imm16"), 451 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], 452 Itin, FrmI, opstr> { 453 let isReMaterializable = 1; 454 let TwoOperandAliasConstraint = "$rs = $rt"; 455} 456 457// Arithmetic Multiply ADD/SUB 458class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> : 459 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), 460 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> { 461 let Defs = [HI0, LO0]; 462 let Uses = [HI0, LO0]; 463 let isCommutable = isComm; 464} 465 466// Logical 467class LogicNOR<string opstr, RegisterOperand RO>: 468 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 469 !strconcat(opstr, "\t$rd, $rs, $rt"), 470 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> { 471 let isCommutable = 1; 472} 473 474// Shifts 475class shift_rotate_imm<string opstr, Operand ImmOpnd, 476 RegisterOperand RO, InstrItinClass itin, 477 SDPatternOperator OpNode = null_frag, 478 SDPatternOperator PF = null_frag> : 479 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), 480 !strconcat(opstr, "\t$rd, $rt, $shamt"), 481 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr>; 482 483class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin, 484 SDPatternOperator OpNode = null_frag>: 485 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs), 486 !strconcat(opstr, "\t$rd, $rt, $rs"), 487 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR, 488 opstr>; 489 490// Load Upper Imediate 491class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>: 492 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 493 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove { 494 let neverHasSideEffects = 1; 495 let isReMaterializable = 1; 496} 497 498// Memory Load/Store 499class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 500 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 501 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 502 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> { 503 let DecoderMethod = "DecodeMem"; 504 let canFoldAsLoad = 1; 505 let mayLoad = 1; 506} 507 508class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, 509 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : 510 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 511 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> { 512 let DecoderMethod = "DecodeMem"; 513 let mayStore = 1; 514} 515 516// Load/Store Left/Right 517let canFoldAsLoad = 1 in 518class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 519 InstrItinClass Itin> : 520 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src), 521 !strconcat(opstr, "\t$rt, $addr"), 522 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> { 523 let DecoderMethod = "DecodeMem"; 524 string Constraints = "$src = $rt"; 525} 526 527class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, 528 InstrItinClass Itin> : 529 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 530 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> { 531 let DecoderMethod = "DecodeMem"; 532} 533 534// Conditional Branch 535class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op, 536 RegisterOperand RO> : 537 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset), 538 !strconcat(opstr, "\t$rs, $rt, $offset"), 539 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch, 540 FrmI, opstr> { 541 let isBranch = 1; 542 let isTerminator = 1; 543 let hasDelaySlot = 1; 544 let Defs = [AT]; 545} 546 547class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op, 548 RegisterOperand RO> : 549 InstSE<(outs), (ins RO:$rs, opnd:$offset), 550 !strconcat(opstr, "\t$rs, $offset"), 551 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, 552 FrmI, opstr> { 553 let isBranch = 1; 554 let isTerminator = 1; 555 let hasDelaySlot = 1; 556 let Defs = [AT]; 557} 558 559// SetCC 560class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> : 561 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt), 562 !strconcat(opstr, "\t$rd, $rs, $rt"), 563 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))], 564 II_SLT_SLTU, FrmR, opstr>; 565 566class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 567 RegisterOperand RO>: 568 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16), 569 !strconcat(opstr, "\t$rt, $rs, $imm16"), 570 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))], 571 II_SLTI_SLTIU, FrmI, opstr>; 572 573// Jump 574class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 575 SDPatternOperator targetoperator, string bopstr> : 576 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 577 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> { 578 let isTerminator=1; 579 let isBarrier=1; 580 let hasDelaySlot = 1; 581 let DecoderMethod = "DecodeJumpTarget"; 582 let Defs = [AT]; 583} 584 585// Unconditional branch 586class UncondBranch<Instruction BEQInst> : 587 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>, 588 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> { 589 let isBranch = 1; 590 let isTerminator = 1; 591 let isBarrier = 1; 592 let hasDelaySlot = 1; 593 let Predicates = [RelocPIC, HasStdEnc]; 594 let Defs = [AT]; 595} 596 597// Base class for indirect branch and return instruction classes. 598let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 599class JumpFR<string opstr, RegisterOperand RO, 600 SDPatternOperator operator = null_frag>: 601 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, 602 FrmR, opstr>; 603 604// Indirect branch 605class IndirectBranch<string opstr, RegisterOperand RO> : 606 JumpFR<opstr, RO, brind> { 607 let isBranch = 1; 608 let isIndirectBranch = 1; 609} 610 611// Return instruction 612class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> { 613 let isReturn = 1; 614 let isCodeGenOnly = 1; 615 let hasCtrlDep = 1; 616 let hasExtraSrcRegAllocReq = 1; 617} 618 619// Jump and Link (Call) 620let isCall=1, hasDelaySlot=1, Defs = [RA] in { 621 class JumpLink<string opstr, DAGOperand opnd> : 622 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 623 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> { 624 let DecoderMethod = "DecodeJumpTarget"; 625 } 626 627 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst, 628 Register RetReg, RegisterOperand ResRO = RO>: 629 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>, 630 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>; 631 632 class JumpLinkReg<string opstr, RegisterOperand RO>: 633 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 634 [], IIBranch, FrmR>; 635 636 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> : 637 InstSE<(outs), (ins RO:$rs, opnd:$offset), 638 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>; 639 640} 641 642let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1, 643 hasExtraSrcRegAllocReq = 1, Defs = [AT] in { 644 class TailCall<Instruction JumpInst> : 645 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>, 646 PseudoInstExpansion<(JumpInst jmptarget:$target)>; 647 648 class TailCallReg<RegisterOperand RO, Instruction JRInst, 649 RegisterOperand ResRO = RO> : 650 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>, 651 PseudoInstExpansion<(JRInst ResRO:$rs)>; 652} 653 654class BAL_BR_Pseudo<Instruction RealInst> : 655 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>, 656 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> { 657 let isBranch = 1; 658 let isTerminator = 1; 659 let isBarrier = 1; 660 let hasDelaySlot = 1; 661 let Defs = [RA]; 662} 663 664// Syscall 665class SYS_FT<string opstr> : 666 InstSE<(outs), (ins uimm20:$code_), 667 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>; 668// Break 669class BRK_FT<string opstr> : 670 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2), 671 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, 672 FrmOther, opstr>; 673 674// (D)Eret 675class ER_FT<string opstr> : 676 InstSE<(outs), (ins), 677 opstr, [], NoItinerary, FrmOther, opstr>; 678 679// Interrupts 680class DEI_FT<string opstr, RegisterOperand RO> : 681 InstSE<(outs RO:$rt), (ins), 682 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>; 683 684// Wait 685class WAIT_FT<string opstr> : 686 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>; 687 688// Sync 689let hasSideEffects = 1 in 690class SYNC_FT<string opstr> : 691 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 692 NoItinerary, FrmOther, opstr>; 693 694let hasSideEffects = 1 in 695class TEQ_FT<string opstr, RegisterOperand RO> : 696 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_), 697 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, 698 FrmI, opstr>; 699 700class TEQI_FT<string opstr, RegisterOperand RO> : 701 InstSE<(outs), (ins RO:$rs, uimm16:$imm16), 702 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>; 703// Mul, Div 704class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 705 list<Register> DefRegs> : 706 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 707 itin, FrmR, opstr> { 708 let isCommutable = 1; 709 let Defs = DefRegs; 710 let neverHasSideEffects = 1; 711} 712 713// Pseudo multiply/divide instruction with explicit accumulator register 714// operands. 715class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 716 SDPatternOperator OpNode, InstrItinClass Itin, 717 bit IsComm = 1, bit HasSideEffects = 0, 718 bit UsesCustomInserter = 0> : 719 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 720 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 721 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 722 let isCommutable = IsComm; 723 let hasSideEffects = HasSideEffects; 724 let usesCustomInserter = UsesCustomInserter; 725} 726 727// Pseudo multiply add/sub instruction with explicit accumulator register 728// operands. 729class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode, 730 InstrItinClass itin> 731 : PseudoSE<(outs ACC64:$ac), 732 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin), 733 [(set ACC64:$ac, 734 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))], 735 itin>, 736 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> { 737 string Constraints = "$acin = $ac"; 738} 739 740class Div<string opstr, InstrItinClass itin, RegisterOperand RO, 741 list<Register> DefRegs> : 742 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 743 [], itin, FrmR, opstr> { 744 let Defs = DefRegs; 745} 746 747// Move from Hi/Lo 748class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> 749 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo), 750 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>; 751 752class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>: 753 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO, 754 FrmR, opstr> { 755 let Uses = [UseReg]; 756 let neverHasSideEffects = 1; 757} 758 759class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC> 760 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi), 761 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))], 762 II_MTHI_MTLO>; 763 764class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>: 765 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO, 766 FrmR, opstr> { 767 let Defs = DefRegs; 768 let neverHasSideEffects = 1; 769} 770 771class EffectiveAddress<string opstr, RegisterOperand RO> : 772 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"), 773 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI, 774 !strconcat(opstr, "_lea")> { 775 let isCodeGenOnly = 1; 776 let DecoderMethod = "DecodeMem"; 777} 778 779// Count Leading Ones/Zeros in Word 780class CountLeading0<string opstr, RegisterOperand RO>: 781 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 782 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>, 783 Requires<[HasBitCount, HasStdEnc]>; 784 785class CountLeading1<string opstr, RegisterOperand RO>: 786 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 787 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>, 788 Requires<[HasBitCount, HasStdEnc]>; 789 790// Sign Extend in Register. 791class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO, 792 InstrItinClass itin> : 793 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), 794 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr> { 795 let Predicates = [HasSEInReg, HasStdEnc]; 796} 797 798// Subword Swap 799class SubwordSwap<string opstr, RegisterOperand RO>: 800 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 801 NoItinerary, FrmR, opstr> { 802 let Predicates = [HasSwap, HasStdEnc]; 803 let neverHasSideEffects = 1; 804} 805 806// Read Hardware 807class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> : 808 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 809 II_RDHWR, FrmR>; 810 811// Ext and Ins 812class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd, 813 SDPatternOperator Op = null_frag>: 814 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size), 815 !strconcat(opstr, " $rt, $rs, $pos, $size"), 816 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary, 817 FrmR, opstr> { 818 let Predicates = [HasMips32r2, HasStdEnc]; 819} 820 821class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd, 822 SDPatternOperator Op = null_frag>: 823 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src), 824 !strconcat(opstr, " $rt, $rs, $pos, $size"), 825 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))], 826 NoItinerary, FrmR, opstr> { 827 let Predicates = [HasMips32r2, HasStdEnc]; 828 let Constraints = "$src = $rt"; 829} 830 831// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 832class Atomic2Ops<PatFrag Op, RegisterClass DRC> : 833 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr), 834 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>; 835 836// Atomic Compare & Swap. 837class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> : 838 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap), 839 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>; 840 841class LLBase<string opstr, RegisterOperand RO> : 842 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 843 [], NoItinerary, FrmI> { 844 let DecoderMethod = "DecodeMem"; 845 let mayLoad = 1; 846} 847 848class SCBase<string opstr, RegisterOperand RO> : 849 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr), 850 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 851 let DecoderMethod = "DecodeMem"; 852 let mayStore = 1; 853 let Constraints = "$rt = $dst"; 854} 855 856class MFC3OP<string asmstr, RegisterOperand RO> : 857 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins), 858 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>; 859 860class TrapBase<Instruction RealInst> 861 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>, 862 PseudoInstExpansion<(RealInst 0, 0)> { 863 let isBarrier = 1; 864 let isTerminator = 1; 865 let isCodeGenOnly = 1; 866} 867 868//===----------------------------------------------------------------------===// 869// Pseudo instructions 870//===----------------------------------------------------------------------===// 871 872// Return RA. 873let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 874def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 875 876let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 877def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 878 [(callseq_start timm:$amt)]>; 879def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 880 [(callseq_end timm:$amt1, timm:$amt2)]>; 881} 882 883let usesCustomInserter = 1 in { 884 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>; 885 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>; 886 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>; 887 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>; 888 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>; 889 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>; 890 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>; 891 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>; 892 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>; 893 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>; 894 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>; 895 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>; 896 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>; 897 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>; 898 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>; 899 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>; 900 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>; 901 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>; 902 903 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>; 904 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>; 905 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>; 906 907 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>; 908 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>; 909 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>; 910} 911 912/// Pseudo instructions for loading and storing accumulator registers. 913let isPseudo = 1, isCodeGenOnly = 1 in { 914 def LOAD_ACC64 : Load<"", ACC64>; 915 def STORE_ACC64 : Store<"", ACC64>; 916} 917 918//===----------------------------------------------------------------------===// 919// Instruction definition 920//===----------------------------------------------------------------------===// 921//===----------------------------------------------------------------------===// 922// MipsI Instructions 923//===----------------------------------------------------------------------===// 924 925/// Arithmetic Instructions (ALU Immediate) 926def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, 927 add>, 928 ADDI_FM<0x9>, IsAsCheapAsAMove; 929def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>; 930def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, 931 SLTI_FM<0xa>; 932def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, 933 SLTI_FM<0xb>; 934def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, 935 and>, 936 ADDI_FM<0xc>; 937def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, 938 or>, 939 ADDI_FM<0xd>; 940def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, 941 xor>, 942 ADDI_FM<0xe>; 943def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM; 944 945/// Arithmetic Instructions (3-Operand, R-Type) 946def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, 947 ADD_FM<0, 0x21>; 948def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, 949 ADD_FM<0, 0x23>; 950let Defs = [HI0, LO0] in 951def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>, 952 ADD_FM<0x1c, 2>; 953def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>; 954def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>; 955def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; 956def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; 957def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, 958 ADD_FM<0, 0x24>; 959def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, 960 ADD_FM<0, 0x25>; 961def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, 962 ADD_FM<0, 0x26>; 963def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; 964 965/// Shift Instructions 966def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl, 967 immZExt5>, SRA_FM<0, 0>; 968def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl, 969 immZExt5>, SRA_FM<2, 0>; 970def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra, 971 immZExt5>, SRA_FM<3, 0>; 972def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>, 973 SRLV_FM<4, 0>; 974def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>, 975 SRLV_FM<6, 0>; 976def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>, 977 SRLV_FM<7, 0>; 978 979// Rotate Instructions 980let Predicates = [HasMips32r2, HasStdEnc] in { 981 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, 982 immZExt5>, SRA_FM<2, 1>; 983 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, 984 SRLV_FM<6, 1>; 985} 986 987/// Load and Store Instructions 988/// aligned 989def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>; 990def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel, 991 LW_FM<0x24>; 992def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel, 993 LW_FM<0x21>; 994def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>; 995def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, 996 LW_FM<0x23>; 997def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>; 998def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>; 999def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>; 1000 1001/// load/store left/right 1002let Predicates = [NotInMicroMips] in { 1003def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>; 1004def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>; 1005def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>; 1006def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>; 1007} 1008 1009def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM; 1010def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>; 1011def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>; 1012def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>; 1013def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>; 1014def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>; 1015def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>; 1016 1017def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>; 1018def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>; 1019def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>; 1020def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>; 1021def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>; 1022def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>; 1023 1024def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>; 1025def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>; 1026def TRAP : TrapBase<BREAK>; 1027 1028def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>; 1029def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>; 1030 1031def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>; 1032def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>; 1033 1034let Predicates = [NotInMicroMips] in { 1035def WAIT : WAIT_FT<"wait">, WAIT_FM; 1036 1037/// Load-linked, Store-conditional 1038def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>; 1039def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>; 1040} 1041 1042/// Jump and Branch Instructions 1043def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>, 1044 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 1045def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>; 1046def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>; 1047def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>; 1048def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>, 1049 BGEZ_FM<1, 1>; 1050def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>, 1051 BGEZ_FM<7, 0>; 1052def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>, 1053 BGEZ_FM<6, 0>; 1054def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>, 1055 BGEZ_FM<1, 0>; 1056def B : UncondBranch<BEQ>; 1057 1058def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>; 1059let Predicates = [NotInMicroMips, HasStdEnc] in { 1060def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM; 1061def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>; 1062} 1063def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>; 1064def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>; 1065def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>; 1066def BAL_BR : BAL_BR_Pseudo<BGEZAL>; 1067def TAILCALL : TailCall<J>; 1068def TAILCALL_R : TailCallReg<GPR32Opnd, JR>; 1069 1070def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>; 1071 1072// Exception handling related node and instructions. 1073// The conversion sequence is: 1074// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 1075// MIPSeh_return -> (stack change + indirect branch) 1076// 1077// MIPSeh_return takes the place of regular return instruction 1078// but takes two arguments (V1, V0) which are used for storing 1079// the offset and return address respectively. 1080def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 1081 1082def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 1083 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 1084 1085let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 1086 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst), 1087 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>; 1088 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff, 1089 GPR64:$dst), 1090 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>; 1091} 1092 1093/// Multiply and Divide Instructions. 1094def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>, 1095 MULT_FM<0, 0x18>; 1096def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>, 1097 MULT_FM<0, 0x19>; 1098def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>, 1099 MULT_FM<0, 0x1a>; 1100def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>, 1101 MULT_FM<0, 0x1b>; 1102 1103def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>; 1104def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>; 1105let Predicates = [NotInMicroMips] in { 1106def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>; 1107def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>; 1108} 1109 1110/// Sign Ext In Register Instructions. 1111def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>; 1112def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>; 1113 1114/// Count Leading 1115def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>; 1116def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>; 1117 1118/// Word Swap Bytes Within Halfwords 1119def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>; 1120 1121/// No operation. 1122def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 1123 1124// FrameIndexes are legalized when they are operands from load/store 1125// instructions. The same not happens for stack address copies, so an 1126// add op with mem ComplexPattern is used and the stack address copy 1127// can be matched. It's similar to Sparc LEA_ADDRi 1128def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>; 1129 1130// MADD*/MSUB* 1131def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>; 1132def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>; 1133def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>; 1134def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>; 1135 1136let Predicates = [HasStdEnc, NotDSP] in { 1137def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>; 1138def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>; 1139def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>; 1140def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>; 1141def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>; 1142def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>; 1143def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>; 1144def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>; 1145def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>; 1146} 1147 1148def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV, 1149 0, 1, 1>; 1150def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU, 1151 0, 1, 1>; 1152 1153def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM; 1154 1155def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>; 1156def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>; 1157 1158/// Move Control Registers From/To CPU Registers 1159def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>; 1160def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>; 1161def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>; 1162def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>; 1163 1164class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary, 1165 FrmOther>; 1166def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>; 1167def EHB : Barrier<"ehb">, BARRIER_FM<3>; 1168def PAUSE : Barrier<"pause">, BARRIER_FM<5>, Requires<[HasMips32r2]>; 1169 1170//===----------------------------------------------------------------------===// 1171// Instruction aliases 1172//===----------------------------------------------------------------------===// 1173def : InstAlias<"move $dst, $src", 1174 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>, 1175 Requires<[NotMips64, NotInMicroMips]>; 1176def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>; 1177def : InstAlias<"addu $rs, $rt, $imm", 1178 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1179def : InstAlias<"add $rs, $rt, $imm", 1180 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1181def : InstAlias<"and $rs, $rt, $imm", 1182 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1183def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>; 1184let Predicates = [NotInMicroMips] in { 1185def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1186} 1187def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>; 1188def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>; 1189def : InstAlias<"not $rt, $rs", 1190 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; 1191def : InstAlias<"neg $rt, $rs", 1192 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1193def : InstAlias<"negu $rt, $rs", 1194 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; 1195def : InstAlias<"slt $rs, $rt, $imm", 1196 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; 1197def : InstAlias<"xor $rs, $rt, $imm", 1198 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1199def : InstAlias<"or $rs, $rt, $imm", 1200 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; 1201def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1202def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1203def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1204def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1205def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; 1206def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>; 1207def : InstAlias<"bnez $rs,$offset", 1208 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1209def : InstAlias<"beqz $rs,$offset", 1210 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; 1211def : InstAlias<"syscall", (SYSCALL 0), 1>; 1212 1213def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; 1214def : InstAlias<"break", (BREAK 0, 0), 1>; 1215def : InstAlias<"ei", (EI ZERO), 1>; 1216def : InstAlias<"di", (DI ZERO), 1>; 1217 1218def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1219def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1220def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1221def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1222def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1223def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; 1224def : InstAlias<"sub, $rd, $rs, $imm", 1225 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>; 1226def : InstAlias<"subu, $rd, $rs, $imm", 1227 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>; 1228 1229//===----------------------------------------------------------------------===// 1230// Assembler Pseudo Instructions 1231//===----------------------------------------------------------------------===// 1232 1233class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1234 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1235 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1236def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>; 1237 1238class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1239 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1240 !strconcat(instr_asm, "\t$rt, $addr")> ; 1241def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>; 1242 1243class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1244 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1245 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1246def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>; 1247 1248//===----------------------------------------------------------------------===// 1249// Arbitrary patterns that map to one or more instructions 1250//===----------------------------------------------------------------------===// 1251 1252// Load/store pattern templates. 1253class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 1254 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 1255 1256class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 1257 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 1258 1259// Small immediates 1260def : MipsPat<(i32 immSExt16:$in), 1261 (ADDiu ZERO, imm:$in)>; 1262def : MipsPat<(i32 immZExt16:$in), 1263 (ORi ZERO, imm:$in)>; 1264def : MipsPat<(i32 immLow16Zero:$in), 1265 (LUi (HI16 imm:$in))>; 1266 1267// Arbitrary immediates 1268def : MipsPat<(i32 imm:$imm), 1269 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1270 1271// Carry MipsPatterns 1272def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), 1273 (SUBu GPR32:$lhs, GPR32:$rhs)>; 1274let Predicates = [HasStdEnc, NotDSP] in { 1275 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs), 1276 (ADDu GPR32:$lhs, GPR32:$rhs)>; 1277 def : MipsPat<(addc GPR32:$src, immSExt16:$imm), 1278 (ADDiu GPR32:$src, imm:$imm)>; 1279} 1280 1281// Call 1282def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1283 (JAL tglobaladdr:$dst)>; 1284def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1285 (JAL texternalsym:$dst)>; 1286//def : MipsPat<(MipsJmpLink GPR32:$dst), 1287// (JALR GPR32:$dst)>; 1288 1289// Tail call 1290def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1291 (TAILCALL tglobaladdr:$dst)>; 1292def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1293 (TAILCALL texternalsym:$dst)>; 1294// hi/lo relocs 1295def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1296def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1297def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1298def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1299def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1300def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1301 1302def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1303def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1304def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1305def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1306def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1307def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1308 1309def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)), 1310 (ADDiu GPR32:$hi, tglobaladdr:$lo)>; 1311def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)), 1312 (ADDiu GPR32:$hi, tblockaddress:$lo)>; 1313def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)), 1314 (ADDiu GPR32:$hi, tjumptable:$lo)>; 1315def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)), 1316 (ADDiu GPR32:$hi, tconstpool:$lo)>; 1317def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)), 1318 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>; 1319 1320// gp_rel relocs 1321def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)), 1322 (ADDiu GPR32:$gp, tglobaladdr:$in)>; 1323def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)), 1324 (ADDiu GPR32:$gp, tconstpool:$in)>; 1325 1326// wrapper_pic 1327class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1328 MipsPat<(MipsWrapper RC:$gp, node:$in), 1329 (ADDiuOp RC:$gp, node:$in)>; 1330 1331def : WrapperPat<tglobaladdr, ADDiu, GPR32>; 1332def : WrapperPat<tconstpool, ADDiu, GPR32>; 1333def : WrapperPat<texternalsym, ADDiu, GPR32>; 1334def : WrapperPat<tblockaddress, ADDiu, GPR32>; 1335def : WrapperPat<tjumptable, ADDiu, GPR32>; 1336def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>; 1337 1338// Mips does not have "not", so we expand our way 1339def : MipsPat<(not GPR32:$in), 1340 (NOR GPR32Opnd:$in, ZERO)>; 1341 1342// extended loads 1343let Predicates = [HasStdEnc] in { 1344 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1345 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1346 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1347} 1348 1349// peepholes 1350let Predicates = [HasStdEnc] in 1351def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1352 1353// brcond patterns 1354multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1355 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1356 Instruction SLTiuOp, Register ZEROReg> { 1357def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1358 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1359def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1360 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1361 1362def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1363 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1364def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1365 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1366def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1367 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1368def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1369 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1370def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1371 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1372def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), 1373 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 1374 1375def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1376 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1377def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1378 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1379 1380def : MipsPat<(brcond RC:$cond, bb:$dst), 1381 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1382} 1383 1384defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1385 1386def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), 1387 (BLEZ i32:$lhs, bb:$dst)>; 1388def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), 1389 (BGEZ i32:$lhs, bb:$dst)>; 1390 1391// setcc patterns 1392multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1393 Instruction SLTuOp, Register ZEROReg> { 1394 def : MipsPat<(seteq RC:$lhs, 0), 1395 (SLTiuOp RC:$lhs, 1)>; 1396 def : MipsPat<(setne RC:$lhs, 0), 1397 (SLTuOp ZEROReg, RC:$lhs)>; 1398 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1399 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1400 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1401 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1402} 1403 1404multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1405 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1406 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1407 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1408 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1409} 1410 1411multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1412 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1413 (SLTOp RC:$rhs, RC:$lhs)>; 1414 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1415 (SLTuOp RC:$rhs, RC:$lhs)>; 1416} 1417 1418multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1419 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1420 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1421 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1422 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1423} 1424 1425multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1426 Instruction SLTiuOp> { 1427 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1428 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1429 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1430 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1431} 1432 1433defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>; 1434defm : SetlePats<GPR32, SLT, SLTu>; 1435defm : SetgtPats<GPR32, SLT, SLTu>; 1436defm : SetgePats<GPR32, SLT, SLTu>; 1437defm : SetgeImmPats<GPR32, SLTi, SLTiu>; 1438 1439// bswap pattern 1440def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>; 1441 1442// Load halfword/word patterns. 1443let AddedComplexity = 40 in { 1444 let Predicates = [HasStdEnc] in { 1445 def : LoadRegImmPat<LBu, i32, zextloadi8>; 1446 def : LoadRegImmPat<LH, i32, sextloadi16>; 1447 def : LoadRegImmPat<LW, i32, load>; 1448 } 1449} 1450 1451//===----------------------------------------------------------------------===// 1452// Floating Point Support 1453//===----------------------------------------------------------------------===// 1454 1455include "MipsInstrFPU.td" 1456include "Mips64InstrInfo.td" 1457include "MipsCondMov.td" 1458 1459// 1460// Mips16 1461 1462include "Mips16InstrFormats.td" 1463include "Mips16InstrInfo.td" 1464 1465// DSP 1466include "MipsDSPInstrFormats.td" 1467include "MipsDSPInstrInfo.td" 1468 1469// MSA 1470include "MipsMSAInstrFormats.td" 1471include "MipsMSAInstrInfo.td" 1472 1473// Micromips 1474include "MicroMipsInstrFormats.td" 1475include "MicroMipsInstrInfo.td" 1476include "MicroMipsInstrFPU.td" 1477